GB2536589A

GB2536589A - Inverter device and air conditioner using inverter device

Info

Publication number: GB2536589A
Application number: GB1610810.2A
Authority: GB
Inventors: Nasu Motoshi; Tsumura Akihiro; Yuasa Kenta; Kusube Shinsaku
Original assignee: Mitsubishi Electric Corp
Current assignee: Mitsubishi Electric Corp
Priority date: 2014-01-15
Filing date: 2014-01-15
Publication date: 2016-09-21
Also published as: WO2015107639A1; JPWO2015107639A1; JP6173488B2; GB201610810D0

Abstract

The present invention is provided with a DC inductor (13), a smoothing capacitor (17), an inrush current prevention circuit (15), an inverter (19), and an inverter substrate (45). The inrush current prevention circuit (15) is provided with: the DC inductor (13); relays (23, 27, 29) that open/close to the smoothing capacitor (17); and an inrush current prevention resistor (25) connected to the relay in parallel. The inverter substrate (45) performs an operation that decelerates a motor (7) that is driven by the inverter (19) and an operation that closes the relays (23, 27, 29) when the inverter (19) is abnormal.

Description

DESCRIPTION Title of Invention INVERTER DEVICE AND AIR-CONDITIONING APPARATUS USING THE INVERTER DEVICE

Technical Field

[0001] The present invention relates to an inverter device and an air-conditioning apparatus using the inverter device.

Background Art

[0002] A related-art air-conditioning apparatus includes an inverter device, and is configured to variably control a speed of a compressor or other components by an operation of the inverter device (for example, see Patent Literature 1).

Citation List Patent Literature [0003] Patent Literature 1: Japanese Unexamined Patent Application Publication No. 2013-162719 (paragraph [0003])

Summary of Invention

Technical Problem [0004] However, when the inverter device suddenly stops its operation, a surge voltage is generated by magnetic energy stored in a DC reactor. As a result, a switching element is damaged.

[0005] The present invention has been made to solve the above-mentioned problem, and has an object to provide an inverter device capable of preventing the switching element from being damaged due to the magnetic energy stored in the DC reactor, which is generated when the inverter device suddenly stops, and to provide an air-conditioning apparatus using the inverter device.

Solution to Problem [0006] An inverter device according to the present invention includes a rectifier, a DC reactor connected to an anode side of the rectifier and configured to smooth a DC current of the rectifier, a smoothing capacitor connected between an output side of the DC reactor and a cathode side of the rectifier and configured to smooth a DC voltage of the rectifier, an inrush current preventing circuit connected between the DC reactor and the smoothing capacitor and configured to prevent an inrush current to the smoothing capacitor, an inverter configured to convert the DC voltage smoothed by the smoothing capacitor into an AC voltage, and an inverter board configured to control the inrush current preventing circuit and the inverter. The inrush current preventing circuit includes one or a plurality of relays connected between the DC reactor and the smoothing capacitor, and an inrush current preventing resistor connected in parallel to the one or the plurality of relays. Of the one or the plurality of relays, the plurality of relays are connected in parallel to each other. When the inverter is abnormal, the inverter board is configured to set at least any one relay of the one or the plurality of relays to a closed state until the inverter is stopped.

Advantageous Effects of Invention [0007] According to the present invention, a path for causing the magnetic energy stored in the DC reactor, which is generated when the inverter suddenly stops, to flow into the smoothing capacitor is formed. Thus, the present invention has such an effect capable of suppressing the surge voltage generated by the magnetic energy, and an effect capable of preventing the switching element from being damaged.

Brief Description of Drawings

[0008] [Fig. 1] Fig. 1 is a diagram for illustrating an example of an electrical configuration of an inverter device 1 according to Embodiment 1 of the present invention.

[Fig. 2] Fig. 2 is a diagram for illustrating an example of a functional configuration of an inverter board 45 according to Embodiment 1 of the present invention.

[Fig. 3] Fig. 3 is a flow chart for illustrating a control example of the inverter device 1 according to Embodiment 1 of the present invention.

[Fig. 4] Fig. 4 is a diagram for illustrating an example of an electrical configuration of an inverter device 1 according to the related art.

[Fig. 5] Fig. 5 is a timing chart for illustrating an operation in a normal state of the inverter device 1 according to the related art.

[Fig. 6] Fig. 6 is a timing chart for illustrating an operation in an abnormal state of the inverter device 1 according to the related art.

[Fig. 7] Fig. 7 is a timing chart for illustrating an operation of a case where a first relay 27 and a second relay 23 included in the inverter device 1 according to Embodiment 1 of the present invention are both out of order.

[Fig. 8] Fig. 8 is a timing chart for illustrating an operation of a case where a power supply voltage is decreased in the inverter device 1 according to Embodiment 1 of the present invention.

[Fig. 9] Fig. 9 is a diagram for illustrating an example of an electrical configuration of an inverter device 1 according to Embodiment 2 of the present invention.

[Fig. 10] Fig. 10 is a diagram for illustrating an example of a functional configuration of a signal operation device 47 included in the inverter device 1 according to Embodiment 2 of the present invention.

[Fig. 11] Fig. 11 is a flow chart for illustrating a control example of the signal operation device 47 included in the inverter device 1 according to Embodiment 2 of the present invention.

[Fig. 12] Fig. 12 is a diagram for illustrating a configuration example of an electrical component box 9 according to Embodiment 3 of the present invention. [Fig. 13] Fig. 13 is a diagram for illustrating an example of an electrical configuration of a signal operation device 47 according to Embodiment 3 of the present invention.

[Fig. 14] Fig. 14 is a diagram for illustrating an example of an electrical configuration of a signal operation device 47 according to Embodiment 4 of the present invention.

[Fig. 15] Fig. 15 is a diagram for illustrating an example of an electrical configuration of an inverter device 1 according to Embodiment 5 of the present invention.

[Fig. 16] Fig. 16 is a diagram for illustrating another example of an electrical configuration of the inverter device 1 according to Embodiment 5 of the present invention.

[Fig. 17] Fig. 17 is a diagram for illustrating an example of an air-conditioning apparatus 110 using the inverter device 1 according to Embodiment 6 of the present invention.

Description of Embodiments

[0009] Embodiments of the present invention are described below in detail with reference to the drawings. Steps describing a program for performing operations of the embodiments of the present invention are pieces of processing to be performed in time series along the described order. However, the steps may not necessarily be processed in time series, and the steps may include processing to be performed in parallel or individually.

[0010] Further, each function described in the embodiments of the present invention is achieved by hardware or software. In other words, each block diagram to be described in the embodiments of the present invention may be regarded as a block diagram of hardware or a functional block diagram of software. For example, each block diagram may be achieved by hardware such as a circuit device, or may be achieved by software to be run on an arithmetic unit such as a processor (not shown).

[0011] Further, the function in each block of the block diagrams described in the embodiments of the present invention is only required to be performed, and the configuration is not required to be separated by those respective blocks. In each of Embodiments 1 to 6 of the present invention, items not particularly described are similar to those in Embodiments 1 to 6, and the same functions and configurations are described with use of the same reference signs. Further, each of Embodiments 1 to 6 of the present invention may be implemented alone or may be implemented in combination. In any of the cases, advantageous effects to be described below are produced. Further, various specific setting examples described in the embodiments of the present invention are merely examples, and the present invention is not particularly limited to the examples.

[0012] Embodiment 1 [0013] (Configuration of Embodiment 1) Fig. 1 is a diagram for illustrating an example of an electrical configuration of an inverter device 1 according to Embodiment 1 of the present invention. As illustrated in Fig. 1, the inverter device 1 is connected between a motor 7 and a switch 5 configured to control supply and interruption of power from a commercial power source 3, and is configured to convert the power of the commercial power source 3 into power appropriate to the motor 7 to supply the converted power. Details of the inverter device 1 are described later, but the inverter device 1 is configured to prevent resistance voltage breakdown of a switching element 87 formed of, for example, a semiconductor element that is a main component of an inverter 19. For example, the inverter device 1 roughly includes three parts. The first part is a rectifier circuit unit, the second part is a smoothing circuit unit, and the third part is an inverter circuit unit. Of those, the second smoothing circuit unit or the third inverter circuit unit operates to prevent the resistance voltage breakdown of the switching element 87 of the inverter circuit unit.

[0014] The inverter device 1 includes, for example, as main circuit elements, a rectifier 11, a DC reactor 13, an inrush current preventing circuit 15, a smoothing capacitor 17, and the inverter 19. The rectifier circuit unit is made up of the rectifier 11. The smoothing circuit unit is made up of the DC reactor 13, the inrush current preventing circuit 15, and the smoothing capacitor 17. The inverter circuit unit is made up of the inverter 19. The inverter device 1 includes, for example, as detection units, a first voltage detection unit 31 and a second voltage detection unit 33. The inverter device 1 includes, for example, as main controllers, a control board 43 and an inverter board 45.

[0015] In this case, the first voltage detection unit 31 has a connection configuration to detect a voltage applied to the inrush current preventing circuit 15 and to transmit the detection result to the inverter board 45. Further, the second voltage detection unit 33 has a connection configuration to detect a voltage applied to the inverter 19 and to transmit the detection result to the inverter board 45.

[0016] The inverter 19 includes, for example, the switching element 87 as described later, and, in addition, the switching element 87 may be provided with a feedback diode (not shown). For example, when the inverter 19 is a voltage-type inverter configured to output a square-wave voltage, the feedback diode may be provided in parallel to the switching element 87. Further, for example, when the inverter 19 is a current-type inverter configured to output a square-wave current, the feedback diode may be provided in series to the switching element 87.

[0017] The rectifier circuit unit is configured to convert AC into DC. The rectifier 11, which is a component of the rectifier circuit unit, includes, for example, a three-phase full-bridge rectifier circuit, and is configured to form a three-phase full-wave rectified waveform from three-phase AC power supplied from the commercial power source 3 via the switch 5. In the description above, the rectifier 11 configured to form the three-phase full-wave rectified waveform is described as an example of the rectifier circuit unit, but the present invention is not particularly limited to the example. For example, when the power supplied to the rectifier 11 is single-phase AC power, the rectifier 11 may have a circuit configuration that forms a single-phase full-wave rectified waveform. In other words, the rectifier circuit unit is not particularly limited as long as the circuit is configured to convert AC into DC.

[0018] The smoothing circuit unit is configured to, for example, smooth the three-phase full-wave rectified waveform output from the rectifier circuit unit. In the smoothing circuit unit, the DC reactor 13 is connected to the anode side of the rectifier 11, and is configured to smooth the DC current output from the rectifier circuit unit. In the smoothing circuit unit, the inrush current preventing circuit 15 and the smoothing capacitor 17 are connected between the output side of the DC reactor 13 and the cathode side of the rectifier 11. In the smoothing circuit unit, the smoothing capacitor 17 is a polarized capacitor. The smoothing capacitor 17 has an anode side connected to the inrush current preventing circuit 15, and a cathode side connected to the cathode side of the rectifier 11. The smoothing capacitor 17 is configured to smooth the DC current.

[0019] In the smoothing circuit unit, the inrush current preventing circuit 15 is connected between the DC reactor 13 and the smoothing capacitor 17. The inrush current preventing circuit 15 includes a first relay 27, a second relay 23, and an inrush current preventing resistor 25, and is arranged on a path through which a charge current and discharge current of the smoothing capacitor 17 flow. With such a configuration, the inrush current preventing circuit 15 suppresses the inrush current flowing into the smoothing capacitor 17 at the time of power-on or other times, and also prevents the application of an overvoltage to the inverter circuit unit when an abnormal state occurs while the inverter 19 is in operation.

[0020] Specifically, the inrush current preventing circuit 15 includes, for example, the first relay 27, the second relay 23, and the inrush current preventing resistor 25, which are connected in parallel. The inrush current preventing circuit 15 is described in detail later. While the inverter 19 is in operation, any one of the first relay 27 and the second relay 23 connected in parallel to the inrush current preventing resistor 25 is closed to form a low-impedance closed circuit. Thus, application of an overvoltage to the inverter 19 is prevented.

[0021] Even under a state in which the first relay 27 and the second relay 23 are both out of control, the inverter board 45 to be described in detail later subjects the inverter 19 to deceleration control to consume the magnetic energy supplied from the DC reactor 13 to the inverter 19. Thus, the resistance voltage breakdown of the switching element 87 included in the inverter 19 is prevented.

[0022] In other words, the inverter device 1 is configured to form a path for causing the magnetic energy stored in the DC reactor 13 to flow into the smoothing capacitor 17 by performing at least one of control of an open-closed state of the first relay 27 included in the inrush current preventing circuit 15, and control of an open-closed state of the second relay 23 included in the inrush current preventing circuit 15. Further, the inverter device 1 is configured to subject the inverter 19 to deceleration control, to thereby form a load for consuming the magnetic energy stored in the DC reactor 13.

[0023] The inverter circuit unit is supplied with the smoothed DC power output from the smoothing circuit unit, and is configured to convert the supplied DC power into AC power to drive the motor 7. The motor 7 is a load of the inverter 19, and serves as, for example, a drive source for a compressor 131, an indoor fan 143, an outdoor fan 141, or other components of an air-conditioning apparatus 110 to be described later. In other words, the inverter circuit unit is a circuit configuration for converting the DC power into the AC power, and is configured to arbitrarily change the AC power and the frequency of the AC power to variably control the speed of the motor 7.

[0024] The control board 43 is mounted, for example, in an electrical component box 9 of an outdoor unit 111 to be described later, and is configured to control the air-conditioning apparatus 110 to be described later. The inverter board 45 is also mounted in the electrical component box 9 of the outdoor unit 111 to be described later. Board-to-board mutual communication information is transmitted or received between the control board 43 and the inverter board 45. The control board 43 controls, for example, the inverter board 45 to control the air-conditioning apparatus 110 to be described later. The inverter board 45 controls the inverter 19. In other words, the control board 43 controls the inverter 19 via the inverter board 45.

[0025] Specifically, for example, the control board 43 controls the open-closed state of the first relay 27 by a first control signal. For example, the inverter board 45 controls the open-closed state of the second relay 23 by a second control signal. For example, the inverter board 45 controls the drive of the inverter 19 by an inverter drive signal.

[0026] In this case, the inverter board 45 is configured to be input with two pieces of voltage information. Specifically, the inverter board 45 is configured to be input with voltage information relating to a voltage across each of the inrush current preventing resistor 25, the first relay 27, and the second relay 23, and voltage information relating to a voltage of DC power input to the inverter 19. Of those, the first voltage across each of the inrush current preventing resistor 25, the first relay 27, and the second relay 23 corresponds to the detection result of the first voltage detection unit 31. The detection result of the first voltage detection unit 31 is input to the inverter board 45 as first voltage information. Further, the second voltage of the DC power input to the inverter 19 is the detection result of the second voltage detection unit 33. The detection result of the second voltage detection unit 33 is input to the inverter board 45 as second voltage information. The inverter board 45 performs control of the open-closed state of the second relay 23 and the deceleration control of the inverter 19 based on such two pieces of voltage information.

[0027] Fig. 2 is a diagram for illustrating an example of a functional configuration of the inverter board 45 according to Embodiment 1 of the present invention. The inverter board 45 includes, for example, an abnormality determining unit 51, a deceleration control unit 53, a relay control unit 55, and an inverter control unit 57.

The abnormality determining unit 51 is configured to determine an abnormal state of the inverter device 1 based on the first voltage information and the second voltage information. The abnormality determining unit 51 includes, for example, a relay failure determining unit 71 and a DC voltage abnormality determining unit 73. In this case, a relay failure determining voltage level refers to a threshold value at which the first relay 27 or the second relay 23 is assumed to be out of order, and a DC voltage abnormal level refers to a threshold value at which the inverter 19 is assumed to suddenly stop due to reduction in power supply voltage caused by power outage or other factors.

[0028] Specifically, when the inverter 19 suddenly stops, it is assumed that, as a result, magnetic energy is generated in the DC reactor 13 to cause abrupt increase of the DC voltage. Thus, a load for consuming the magnetic energy is required to be formed. Details are described later, but the inverter device 1 closes the second relay 23 to cause the smoothing capacitor 17 to consume the magnetic energy, or subjects the inverter 19 to deceleration control to cause the inverter 19 and the motor 7 to consume the magnetic energy. In other words, the magnetic energy generated in the DC reactor 13 is converted into electrical energy and thermal energy in the smoothing capacitor 17, converted into electrical energy and thermal energy in the inverter 19, and converted into kinetic energy in the motor 7.

[0029] When the first voltage information reaches the relay failure determining voltage level, the relay failure determining unit 71 determines that the inverter device 1 is in an abnormal state, and transmits the determination result to the relay control unit 55, the inverter control unit 57, and the deceleration control unit 53. When the second voltage information reaches the DC voltage abnormal level, the DC voltage abnormality determining unit 73 determines that the inverter device 1 is in an abnormal state, and transmits the determination result to the relay control unit 55, the inverter control unit 57, and the deceleration control unit 53.

[0030] When the inverter device 1 is in the abnormal state, the deceleration control unit 53 transmits, for example, various pieces of information for subjecting the inverter 19 to deceleration control to the inverter 19. The deceleration control unit 53 includes, for example, an operation-state rotation speed acquiring unit 75, a deceleration-state rotation speed acquiring unit 77, and a deceleration time calculating unit 79.

[0031] The operation-state rotation speed acquiring unit 75 is configured to acquire the rotation speed in the operation state of the motor 7 whose drive is controlled by the inverter 19. In this case, the rotation speed in the operation state of the motor 7 refers to an actual rotation speed of the load of the inverter 19, and is, for example, calculated based on the number of pulses detected by a rotary encoder (not shown). The deceleration-state rotation speed acquiring unit 77 is configured to acquire the rotation speed of the motor 7 during the deceleration control of the inverter 19 so that the inverter 19 causes the motor 7 to decelerate. In this case, the rotation speed of the motor 7 during the deceleration control refers to a deceleration rotation speed of the load of the inverter 19, and may be set in advance or obtained each time. The rotation speed in the operation state of the motor 7 may be obtained by a Hall element (not shown).

[0032] The deceleration time calculating unit 79 is configured to obtain the deceleration time required for deceleration based on the rotation speed in the operation state and the rotation speed in the deceleration state. The deceleration control unit 53 is configured to transmit the deceleration time to the inverter 19. For example, when the rotation speed in the operation state is 100 rotations per second (rps) and the rotation speed in the deceleration state is 10 rps, the deceleration time is 10 (s).

[0033] The relay control unit 55 is configured to control the second relay 23 included in the inrush current preventing circuit 15 based on the determination result. The inverter control unit 57 is configured to transmit the inverter drive signal based on the determination result to the inverter 19. In this case, it is assumed that, for example, a high-level inverter drive signal is set as an output state in which the inverter 19 is driven, and a low-level inverter drive signal is set as an interruption state in which the inverter 19 is stopped. Under such assumption, when the inverter device 1 is in the abnormal state, the inverter control unit 57 transmits the low-level inverter drive signal to the inverter 19.

[0034] The inverter 19 includes an inverter drive signal determining unit 83, a gate control unit 85, and the switching element 87. The inverter drive signal determining unit 83 is configured to control the gate control unit 85 based on the inverter drive signal to thereby control the operation of the switching element 87. When the low-level inverter drive signal is assumed to indicate the abnormal state of the inverter device 1, and the low-level inverter drive signal is transmitted to the inverter drive signal determining unit 83, the inverter drive signal determining unit 83 selects the deceleration control of the inverter 19, and causes the gate control unit 85 to generate a signal for causing the motor 7 to decelerate. As a result, the switching element 87 operates based on the signal generated by the gate control unit 85.

[0035] For example, the gate control unit 85 controls a gate drive circuit (not shown) for the switching element 87, to thereby control the on state and the off state of the switching element 87. Specifically, the gate control unit 85 controls a duty ratio, which is a ratio between the interval of the on state of the switching element 87 and the interval of the off state of the switching element 87, to thereby generate a PWM signal. In other words, in the inverter 19, the gate control unit 85 causes the switching element 87 to output the PWM signal, to thereby PWM-control the motor 7 by the PWM signal. The motor 7 is configured to generate a rotating magnetic field by the PWM signal, and to rotate a shaft (not shown) provided to the motor 7, thus serving as a drive source of various devices. The motor 7 is, for example, a brushless DC motor.

[0036] In this case, the gate control unit 85 controls the duty ratio, which is the ratio between the interval of the on state of the switching element 87 and the interval of the off state of the switching element 87, so that the motor 7 decelerates within the deceleration time at the rotation speed in the deceleration state, and generates a PWM signal to increase the interval of the off state of the switching element 87 along with elapse of time, to thereby perform the deceleration control of the inverter 19. In this manner, the load such as the motor 7 is caused to decelerate to be stopped within the deceleration time.

[0037] The switching element 87 is formed of, for example, an IGBT, but is not particularly limited to an IGBT. For example, the switching element 87 may be formed of a wide band-gap semiconductor. The wide band-gap semiconductor has high voltage resistance and also high allowable current density, and hence the switching element 87 can be downsized. Further, the wide band-gap semiconductor also has high heat resistance, and hence a radiation fin (not shown) of a heatsink can be downsized, and air cooling of a water-cooling unit (not shown) can be achieved. Thus, the inverter 19 including the switching element 87 can be further downsized. Further, the wide band-gap semiconductor is low in power loss. Thus, the switching element 87 can be achieved at high efficiency, and the inverter 19 can be achieved at high efficiency.

[0038] In the description above, an example in which the deceleration control unit 53 calculates the deceleration time and transmits the calculation result to the inverter 19 is described, but the present invention is not particularly limited to the example. For example, the inverter control unit 57 may transmit, to the inverter 19, the inverter drive signal including an operation of subjecting the inverter 19 to deceleration control. In short, the inverter board 45 is only required to have a configuration capable of subjecting the inverter 19 to deceleration control when the inverter device 1 is in the abnormal state.

[0039] (Operation of Embodiment 1) Fig. 3 is a flow chart for illustrating a control example of the inverter device 1 according to Embodiment 1 of the present invention. In Fig. 3, as the control example of the inverter device 1, the control example of the first voltage detection unit 31 is described in Step S11 and Step S12, the control example of the second voltage detection unit 33 is described in Step S21 and Step S22, the control example of the inverter board 45 is described in Step S31 to Step S39, and the control example of the inverter 19 is described in Step S51 to Step S53.

[0040] As the premise of the processing, a default value of a flag to be described later is assumed to be set to zero. In this case, the flag refers to an identifier for leading the flow to the processing based on the second voltage information when the flag is 1, and is not particularly limited to the example below. Further, as the premise of the processing, when the inverter 19 is in operation, and the first relay 27 and the second relay 23 are not out of order, the first relay 27 and the second relay 23 are assumed to be held in a short-circuit state.

[0041] (First Voltage Detection Unit Control Processing) (Step S11) The first voltage detection unit 31 detects the first voltage.

[0042] (Step S12) The first voltage detection unit 31 outputs the detection result as the first voltage information.

[0043] (Second Voltage Detection Unit Control Processing) (Step S21) The second voltage detection unit 33 detects the second voltage.

[0044] (Step S22) The second voltage detection unit 33 outputs the detection result as the second voltage information.

[0045] (Inverter Board Control Processing) (Step S31) The inverter board 45 identifies the type of the voltage information. When the type of the voltage information is the first voltage information, the inverter board 45 proceeds to Step S32. On the other hand, when the type of the voltage information is the second voltage information, the inverter board 45 proceeds to Step S33.

[0046] (Step S32) When the first voltage information reaches the relay failure determining voltage level, the inverter board 45 proceeds to Step S35. On the other hand, when the first voltage information does not reach the relay failure determining voltage level, the inverter board 45 returns to Step S31.

[0047] In this case, a situation where the first voltage information reaches the relay failure determining voltage level is assumed to be a case where the first relay 27 and the second relay 23 are out of order to be in an open state. Further, even in a case where the second voltage information reaches the DC voltage abnormal level, when the first voltage information does not reach the relay failure determining voltage level, at least one of the first relay 27 and the second relay 23 is assumed to be held in the short-circuit state.

[0048] (Step S33) When the second voltage information reaches the DC voltage abnormal level, the inverter board 45 proceeds to Step S34. On the other hand, when the second voltage information does not reach the DC voltage abnormal level, the inverter board returns to Step S31.

[0049] (Step S34) The inverter board 45 sets the flag to 1, and then proceeds to Step S35.

[0050] (Step S35) The inverter board 45 transmits the inverter drive signal for stopping the inverter 19 to the inverter 19.

[0051] (Step S36) The inverter board 45 transmits the deceleration time information for causing the inverter 19 to decelerate to the inverter 19. As described above, when the inverter drive signal includes a command for causing the inverter 19 to decelerate within the deceleration time, the processing of Step S36 is unnecessary.

[0052] (Step S37) When a time set in advance has elapsed after elapse of the deceleration time, the inverter board 45 proceeds to Step S38. On the other hand, when the time set in advance has not elapsed after the elapse of the deceleration time, the inverter board 45 returns to Step S37. In this case, a state where the time set in advance has elapsed after the elapse of the deceleration time is assumed to be a state where the inverter 19 is stopped, and the operation of the motor 7 along with the moment of inertia is also stopped.

[0053] (Step S38) When the flag is 1, the inverter board 45 proceeds to Step S39. On the other hand, when the flag is not 1, the inverter board 45 ends the processing.

[0054] (Step S39) The inverter board 45 controls the second relay 23 to the open state, and then ends the processing.

[0055] (Inverter Control Processing) (Step S51) The inverter 19 starts the deceleration of the motor 7 at a constant speed so that the motor 7 is stopped when the deceleration time elapses.

[0056] (Step S52) The inverter 19 determines whether or not the deceleration time has elapsed.

When the deceleration time has elapsed, the inverter 19 proceeds to Step S53. On the other hand, when the deceleration time has not elapsed, the inverter 19 returns to Step S52.

[0057] (Step S53) The inverter 19 stops the motor 7, and then ends the processing.

[0058] (Effect of Embodiment 1) Next, with reference to comparison of a configuration and an operation of a related-ad inverter device 1 to the configuration and the operation of the inverter device 1 according to Embodiment 1 of the present invention, the effect of the inverter device 1 according to Embodiment 1 of the present invention is described.

[0059] Fig. 4 is a diagram for illustrating an example of an electrical configuration of an inverter device 1 according to the related art. As illustrated in Fig. 4, the related-art inverter device 1 does not include the first voltage detection unit 31 and the second relay 23.

[0060] A case where the control board 43 is assumed to be turned on. In this case, the control board 43 transmits or receives the board-to-board mutual communication information to or from the inverter board 45 to transmit various control signals, and also closes the switch 5 to supply power supplied from the commercial power source 3 to the inverter device 1. Subsequently, the inverter board 45 controls the inverter 19 based on the various control signals included in the board-to-board mutual communication information from the control board 43, but depending on situations, the inverter board 45 may control the inverter 19 without relying on the various control signals from the control board 43.

[0061] For example, in the inverter device 1, the first relay 27 or the second relay 23 may enter the open state due to a mechanical life or disturbance such as noise while the inverter 19 is in operation. In this case, the charge current or discharge current of the smoothing capacitor 17 flows via the inrush current preventing resistor 25. Thus, the charge current or discharge current is suppressed by the inrush current preventing resistor 25, the smoothing function of the smoothing capacitor 17 is reduced, and the DC voltage input to the inverter circuit unit fluctuates.

Subsequently, when the operation of the inverter device 1 stops, the magnetic energy generated by the current flowing through the DC reactor 13 increases the DC voltage. Thus, an overvoltage is applied to the semiconductor element forming the switching element 87 of the inverter circuit unit, and thus may exceed an allowable voltage of the semiconductor element to cause damage on the semiconductor element.

[0062] To solve the above-mentioned problem, even in a case where the first relay 27 of the inrush current preventing circuit 15 enters the open state while the inverter device 1 is in operation, as described above with reference to Fig. 1, when the second relay 23 is provided to the inrush current preventing circuit 15 to monitor the contact voltage of the first relay 27 and the second relay 23 and the DC voltage input to the inverter 19, and the monitored information is fed back to the inverter board 45, the magnetic energy generated in the DC reactor 13 can be consumed.

[0063] In other words, the second relay 23 is controlled in association with the inverter 19 to obtain an effect of preventing damage on the semiconductor element forming the switching element 87. For example, even in a case where the first relay 27 and the second relay 23 enter the open state, when the inverter 19 decelerates in stages to stop, the inverter 19 consumes the magnetic energy generated in the DC reactor 13. Thus, the magnetic energy generated in the DC reactor 13 can be suppressed, and abrupt increase of the DC voltage applied to the inverter 19 can be prevented.

[0064] Further, in the circuit configuration including the second relay 23 separately from the first relay 27, that is, in the circuit configuration including a plurality of relays, when the short-circuit state of at least one of the relays is maintained until the inverter 19 stops, the smoothing capacitor 17 absorbs and consumes the magnetic energy generated in the DC reactor 13. Thus, the magnetic energy generated in the DC reactor 13 can be suppressed, and abrupt increase of the DC voltage applied to the inverter 19 can be prevented.

[0065] In other words, the inverter device 1 forms a path for causing the magnetic energy stored in the DC reactor 13 to flow into the smoothing capacitor 17. In this manner, a surge voltage to be generated by the magnetic energy stored in the DC reactor 13, which is generated when the inverter device 1 suddenly stops, can be suppressed, and the damage on the switching element 87 can be prevented.

[0066] Next, the effect caused by the difference in operation between the related-art inverter device 1 and the inverter device 1 according to Embodiment 1 of the present invention is specifically described with reference to timing charts.

[0067] Fig. 5 is a timing chart for illustrating an operation in a normal state of the inverter device 1 according to the related art. As illustrated in Fig. 5, the timing chart represents transitions of various states over time of, in order from the top, the first voltage being the detection result of the first voltage detection unit 31, the second voltage being the detection result of the second voltage detection unit 33, the first control signal of the first relay 27, the second control signal of the second relay 23, the contact portion of the first relay 27, the contact portion of the second relay 23, the inverter drive signal, and the actual rotation speed of the load of the inverter 19. [0068] First, although the first voltage detection unit 31 is not included in the related-art inverter device 1, in this case, the first voltage represents a state transition over time of a voltage applied to the first relay 27, which is a position corresponding to the first voltage. For example, the voltage is generated by the contact resistance of the first relay 27 and the conduction current of the first relay 27. Further, the related-art inverter device 1 does not include the second relay 23, and hence the second control signal of the second relay 23 is not generated, and the state of the contact portion of the second relay 23 does not transition as well.

[0069] Next, the transitions of the various states are described along the time axis.

At the timing of tO, the switch 5 enters the closed state, and power is supplied from the commercial power source 3 to the inverter device 1. Next, from tO to t1, the smoothing capacitor 17 is charged, and the charging completes at t1. Thus, the DC voltage being the second voltage becomes stable. Further, from tO to t1, the charge current of the smoothing capacitor 17 flows through the inrush current preventing resistor 25, and hence the first voltage is decreased as the charging of the smoothing capacitor 17 progresses. At the timing of t2, the control board 43 transmits the first control signal in a high-level state to the first relay 27, and the first relay 27 transitions from the open state to the short-circuit state.

[0070] Along with the transition of the state of the first control signal from the low-level to the high-level, the contact portion of the first relay 27 transitions from the open state to the short-circuit state. At the timing of t3, the inverter board 45 outputs the inverter drive signal in the high-level state to the inverter 19, and the drive of the motor 7, which is the load of the inverter 19, is started. The actual rotation speed of the load of the inverter 19 starts to increase from t3, and ramp up-down control is performed. Further, at the timing of t3, the first relay 27 is in the short-circuit state, and hence, for example, a voltage of several volts is detected from the contact resistance of the first relay 27 and the conduction current of the first relay 27. [0071] At the timing of t5, the inverter board 45 outputs the inverter drive signal in the low-level state to the inverter 19, and the drive of the motor 7, which is the load of the inverter 19, is stopped. The actual rotation speed of the load of the inverter 19 starts to decelerate from t5, and the ramp up-down control is performed.

[0072] Fig. 6 is a timing chart for illustrating an operation in an abnormal state of the inverter device 1 according to the related art. As illustrated in Fig. 6, the timing chart represents transitions of various states over time of, in order from the top, the first voltage being the detection result of the first voltage detection unit 31, the second voltage being the detection result of the second voltage detection unit 33, the first control signal of the first relay 27, the second control signal of the second relay 23, the contact portion of the first relay 27, the contact portion of the second relay 23, the inverter drive signal, and the actual rotation speed of the load of the inverter 19. [0073] First, although the first voltage detection unit 31 is not included in the related-art inverter device 1, in this case, the first voltage represents a state transition over time of a voltage applied to the first relay 27, which is the position corresponding to the first voltage. For example, the voltage is generated by the contact resistance of the first relay 27 and the conduction current of the first relay 27. Further, the related-art inverter device 1 does not include the second relay 23, and hence the second control signal of the second relay 23 is not generated, and the state of the contact portion of the second relay 23 does not transition as well.

[0074] Next, the transitions of the various states are described along the time axis. At the timing of tO, the switch 5 enters the closed state, and power is supplied from the commercial power source 3 to the inverter device 1. Next, from tO to t1, the smoothing capacitor 17 is charged, and the charging completes at t1. Thus, the DC voltage being the second voltage becomes stable. Further, from tO to t1, the charge current of the smoothing capacitor 17 flows through the inrush current preventing resistor 25, and hence the first voltage is decreased as the charging of the smoothing capacitor 17 progresses. At the timing of t2, the control board 43 transmits the first control signal in a high-level state to the first relay 27, and the first relay 27 transitions from the open state to the short-circuit state.

[0075] Along with the transition of the state of the first control signal from the low-level to the high-level, the contact portion of the first relay 27 transitions from the open state to the short-circuit state. At the timing of t3, the inverter board 45 outputs the inverter drive signal in the high-level state to the inverter 19, and the drive of the motor 7, which is the load of the inverter 19, is started. The actual rotation speed of the load of the inverter 19 starts to increase from t3, and ramp up-down control is performed. Further, at the timing of t3, the first relay 27 is in the short-circuit state, and hence, for example, a voltage of several volts is detected from the contact resistance of the first relay 27 and the conduction current of the first relay 27. [0076] When open failure is assumed to occur in the first relay 27 at the timing of t4, the charge current or discharge current of the smoothing capacitor 17 flows via the inrush current preventing resistor 25, and hence the first voltage is abruptly increased. Such an abruptly increased first voltage reaches the relay failure determining voltage level. Further, at the timing of t4, the DC voltage fluctuates and the voltage decreases, and hence the second voltage reaches the DC voltage abnormal level. The second voltage reaches the DC voltage abnormal level at the timing of t5, and hence at the timing of t5, the inverter drive signal is output in the low-level state. In this manner, the inverter 19 is immediately stopped.

[0077] As a result of the sudden stop of the inverter 19 at the timing of t5, the magnetic energy is generated in the DC reactor 13. Thus, the DC voltage is abruptly increased, and hence the second voltage is abruptly increased. In other words, the related-art inverter device 1 is in a state in which, even when the inverter device 1 enters the abnormal state, the path for causing the magnetic energy stored in the DC reactor 13 to flow into the smoothing capacitor 17 is not formed.

[0078] Fig. 7 is a timing chart for illustrating an operation of a case where the first relay 27 and the second relay 23 included in the inverter device 1 according to Embodiment 1 of the present invention are both out of order. As illustrated in Fig. 7, the timing chart represents transitions of various states over time of, in order from the top, the first voltage being the detection result of the first voltage detection unit 31, the second voltage being the detection result of the second voltage detection unit 33, the first control signal of the first relay 27, the second control signal of the second relay 23, the contact portion of the first relay 27, the contact portion of the second relay 23, the inverter drive signal, and the actual rotation speed of the load of the inverter 19.

[0079] Next, the transitions of the various states are described along the time axis. At the timing of tO, the switch 5 enters the closed state, and power is supplied from the commercial power source 3 to the inverter device 1. Next, from tO to t1, the smoothing capacitor 17 is charged, and the charging completes at t1. Thus, the DC voltage being the second voltage becomes stable. Further, from tO to t1, the charge current of the smoothing capacitor 17 flows through the inrush current preventing resistor 25, and hence the first voltage is decreased as the charging of the smoothing capacitor 17 progresses. At the timing of t2, the control board 43 transmits the first control signal in a high-level state to the first relay 27, and the first relay 27 transitions from the open state to the short-circuit state.

[0080] Further, at the timing of t2, the inverter board 45 transmits the second control signal in a high-level state to the second relay 23, and the second relay 23 transitions from the open state to the short-circuit state. In the example illustrated in Fig. 7, the first control signal transmitted to the first relay 27 and the second control signal transmitted to the second relay 23 are at the same timing, but the present invention is not particularly limited to the example, and the timings may be different.

[0081] Along with the transition of the state of the first control signal from the low-level to the high-level, the contact portion of the first relay 27 transitions from the open state to the short-circuit state. Similarly, along with the transition of the state of the second control signal from the low-level to the high-level, the contact portion of the second relay 23 transitions from the open state to the short-circuit state. Next, at the timing of t3, the inverter board 45 outputs the inverter drive signal in the high-level state to the inverter 19, and the drive of the motor 7, which is the load of the inverter 19, is started. The actual rotation speed of the load of the inverter 19 starts to increase from t3, and ramp up-down control is performed. Further, at the timing of t3, the first relay 27 is in the short-circuit state, and hence, for example, a voltage of several volts is detected from the contact resistance of the first relay 27 and the conduction current of the first relay 27.

[0082] Open failure is assumed to occur in both of the first relay 27 and the second relay 23 at the timing of t4. In this case, each of the contact portion of the first relay 27 and the contact portion of the second relay 23 transitions from the short-circuit state to the open state. Thus, the charge current or discharge current of the smoothing capacitor 17 flows via the inrush current preventing resistor 25, and hence the first voltage is abruptly increased, and the abruptly increased first voltage reaches the relay failure determining voltage level. Next, at the timing of t5, the inverter board 45 outputs the inverter drive signal in the low-level state to the inverter 19.

Thus, the actual rotation speed of the load of the inverter 19 starts to decelerate from t5, and the ramp up-down control is performed.

[0083] Next, power supplied to the inverter 19 is decreased, and hence the charge current or discharge current of the smoothing capacitor 17 flowing via the inrush current preventing resistor 25 is decreased. Thus, the level of the first voltage is also decreased. At the timing of t6, after the inverter 19 is stopped, the second control signal for controlling the second relay 23 to the open state is transmitted from the inverter board 45 to the second relay 23 in the low-level state, but the second relay 23 is in the open failure state. Thus, the second relay 23 is uncontrollable by the second control signal.

[0084] At the timing of t7, the first control signal for controlling the first relay 27 to the open state is transmitted from the control board 43 to the first relay 27 in the low-level state, but the first relay 27 is in the open failure state. Thus, the first relay 27 is uncontrollable by the first control signal.

[0085] In short, when the first relay 27 and the second relay 23 are both out of order, the inverter 19 is immediately subjected to deceleration control, and hence the magnetic energy of the DC reactor 13 can be consumed gradually. Thus, abrupt increase of the DC voltage can be prevented, and the damage on the switching element 87 can be avoided.

[0086] Fig. 8 is a timing chart for illustrating an operation of a case where a power supply voltage is decreased in the inverter device 1 according to Embodiment 1 of the present invention. As illustrated in Fig. 8, the timing chart represents transitions of various states over time of, in order from the top, the first voltage being the detection result of the first voltage detection unit 31, the second voltage being the detection result of the second voltage detection unit 33, the first control signal of the first relay 27, the second control signal of the second relay 23, the contact portion of the first relay 27, the contact portion of the second relay 23, the inverter drive signal, and the actual rotation speed of the load of the inverter 19.

[0087] Next, the transitions of the various states are described along the time axis.

[0088] Further, at the timing of t2, the inverter board 45 transmits the second control signal in a high-level state to the second relay 23, and the second relay 23 transitions from the open state to the short-circuit state. In the example illustrated in Fig. 7, the first control signal transmitted to the first relay 27 and the second control signal transmitted to the second relay 23 are at the same timing, but the present invention is not particularly limited to the example, and the timings may be different.

[0089] Along with the transition of the state of the first control signal from the low-level to the high-level, the contact portion of the first relay 27 transitions from the open state to the short-circuit state. Similarly, along with the transition of the state of the second control signal from the low-level to the high-level, the contact portion of the second relay 23 transitions from the open state to the short-circuit state. Next, at the timing of t3, the inverter board 45 outputs the inverter drive signal in the high-level state to the inverter 19, and the drive of the motor 7, which is the load of the inverter 19, is started. The actual rotation speed of the load of the inverter 19 starts to increase from t3, and ramp up-down control is performed. Further, at the timing of t3, the first relay 27 is in the short-circuit state, and hence, for example, a voltage of several volts is detected from the contact resistance of the first relay 27 and the conduction current of the first relay 27.

[0090] When the commercial power source 3 is assumed to be affected by power outage or other cases and stop the power supply to the inverter device 1 at the timing of t4, the second voltage starts to decrease. Next, when, at the timing of t5, the DC voltage is decreased and the second voltage reaches the DC voltage abnormal level, the second voltage detection unit 33 outputs the second voltage information to the inverter board 45, and the inverter board 45 detects that the DC voltage is abnormal.

Next, the inverter board 45 outputs the inverter drive signal in the low-level state to the inverter 19. Further, at the timing of t5, the inverter board 45 outputs the inverter drive signal in the low-level state to the inverter 19, the actual rotation speed of the load of the inverter 19 starts to decelerate from t5, and the ramp up-down control is performed.

[0091] At the timing of t6, after the inverter 19 is stopped, the second control signal for controlling the second relay 23 to the open state is transmitted from the inverter board 45 to the second relay 23 in the low-level state, and thus the contact portion of the second relay 23 enters the open state.

[0092] At the timing of t7, the first control signal for controlling the first relay 27 to the open state is transmitted from the control board 43 to the first relay 27 in the low-level state, and thus the contact portion of the first relay 27 enters the open state.

[0093] In short, when the power supply voltage is decreased in the inverter device 1, the inverter 19 is immediately subjected to deceleration control. Thus, the magnetic energy of the DC reactor 13 is decreased gradually. Further, while the inverter 19 is controlled, the short-circuit state of the second relay 23 is held. Thus, abrupt increase of the DC voltage is prevented, and hence the damage on the switching element 87 can be avoided.

[0094] From the description above, even when the inverter device 1 enters an abnormal state, the inverter device 1 forms a load for consuming the magnetic energy of the DC reactor 13. Thus, the switching element 87 can be prevented from being damaged by the magnetic energy of the DC reactor 13 while the inverter device 1 is in operation.

[0095] Specifically, even when the inverter device 1 detects an abnormality such as voltage fluctuation while the inverter 19 is in operation, the inverter device 1 causes the inverter 19 to decelerate in stages, to thereby cause the inverter 19 and the load of the inverter 19, for example, the motor 7 to consume power. Thus, the increase of the DC voltage can be prevented. Thus, the inverter device 1 can prevent the switching element 87 from being damaged by the magnetic energy due to the abnormal state.

[0096] Further, when the open failure does not occur in the second relay 23, the inverter device 1 maintains the shod-circuit state of the second relay 23 until the inverter 19 is stopped, and hence can form the path for causing the current flowing through the DC reactor 13 to flow into the smoothing capacitor 17. Thus, the magnetic energy can be consumed by the smoothing capacitor 17, and the increase of the DC voltage can be prevented. Thus, the inverter device 1 can prevent the switching element 87 from being damaged by the magnetic energy due to the abnormal state. In other words, when the inverter 19 is abnormal, the inverter board 45 sets at least any one relay of one or a plurality of relays to the closed state until the inverter 19 is stopped. As a result, the inverter board 45 can reduce the magnetic energy stored in the DC reactor 13, which is generated when the inverter device 1 suddenly stops. Thus, the damage on the switching element 87 can be prevented.

[0097] In other words, the inverter device 1 can avoid the resistance voltage breakdown of the switching element 87 of the inverter 19. A period between tO and t1 described above is, for example, 3 (s), a period between t1 and t2 is, for example, 3 (s), a period between t2 and t3 is, for example, 1 (s), a period between t3 and t4 is, for example, 30 (s), a period between t4 and t5 is, for example, 10 (ms), and a period between t5 and t6 is, for example, 10 (s). However, the present invention is not particularly limited to the example.

[0098] When the abnormality is detected while the inverter 19 is in operation and the inverter board 45 can control the opening or closing of the second relay 23, the inverter board 45 achieves to maintain the short-circuit state of the second relay 23 until the inverter 19 is stopped. Further, when the abnormality is detected while the inverter 19 is in operation, the inverter board 45 may immediately proceed to the deceleration control of the inverter 19. For example, when the abnormality is detected while the inverter 19 is in operation, even when the inverter board 45 cannot control the opening or closing of the second relay 23, the inverter board 45 is only required to perform deceleration control of the inverter 19. Further, when the abnormality is detected while the inverter 19 is in operation, the inverter board 45 may set the second relay 23 to the short-circuit state, that is, to the closed state, and may also subject the inverter 19 to deceleration control. As a result of the operation as described above, the inverter device 1 can prevent the switching element 87 from being damaged by the magnetic energy due to the abnormal state.

[0099] As described above, according to Embodiment 1 of the present invention, the inverter device 1 includes the rectifier 11, the DC reactor 13 connected to the anode side of the rectifier 11 and configured to smooth the DC current of the rectifier 11, the smoothing capacitor 17 connected between the output side of the DC reactor 13 and the cathode side of the rectifier 11 and configured to smooth the DC voltage of the rectifier 11, the inrush current preventing circuit 15 connected between the DC reactor 13 and the smoothing capacitor 17 and configured to prevent the inrush current to the smoothing capacitor 17, the inverter 19 configured to convert the DC voltage smoothed by the smoothing capacitor 17 into the AC voltage, and the inverter board 45 configured to control the inrush current preventing circuit 15 and the inverter 19. The inrush current preventing circuit 15 includes the one or the plurality of relays connected between the DC reactor 13 and the smoothing capacitor 17, and the inrush current preventing resistor 25 connected in parallel to the one or the plurality of relays. Of the one or the plurality of relays, the plurality of relays are connected in parallel to each other. When the inverter 19 is abnormal, the inverter board 45 is configured to set at least any one relay of the one or the plurality of relays to the closed state until the inverter 19 is stopped.

[0100] As a result, the path for causing the magnetic energy stored in the DC reactor 13 to flow into the smoothing capacitor 17 is formed. Thus, the surge voltage generated by the magnetic energy stored in the DC reactor 13, which is generated when the inverter device 1 suddenly stops, can be suppressed, and the damage on the switching element 87 can be prevented.

[0101] Further, according to Embodiment 1 of the present invention, the inverter 19 includes the switching element 87, and the gate control unit 85 configured to control the switching element 87. The inverter board 45 is configured to control the gate control unit 85 to decrease the operation time of the switching element 87 in stages, to thereby stop the inverter 19.

[0102] Further, according to Embodiment 1 of the present invention, the inverter board 45 is configured to obtain the deceleration time of the motor 7 based on a current rotation speed of the motor 7 driven by the inverter 19.

[0103] Further, according to Embodiment 1 of the present invention, the inverter device 1 further includes the control board 43 configured to control the inrush current preventing circuit 15 and the inverter board 45, the first relay 27 controlled by the control board 43 as the one or the plurality of relays, and the second relay 23 controlled by the inverter board 45 as the one or the plurality of relays. The inverter board 45 includes, as the unit configured to determine stop of the inverter 19, the first voltage detection unit 31 configured to detect the first voltage relating to the first relay 27 and the second relay 23, and the second voltage detection unit 33 configured to detect the second voltage supplied to the inverter 19. The inverter board is configured to output a stop operation command of the inverter 19 in at least one of the case where the first voltage reaches the relay failure determining voltage level and the case where the second voltage reaches the DC voltage abnormal level.

[0104] Thus, by forming the path for causing the magnetic energy stored in the DC reactor 13 to flow into the smoothing capacitor 17 particularly remarkably, the surge voltage to be generated by the magnetic energy stored in the DC reactor 13, which is generated when the inverter device 1 suddenly stops, can be suppressed, and the damage on the switching element 87 can be prevented.

[0105] Embodiment 2 (Difference) The difference from other embodiments resides in that the first control signal and the second control signal are transmitted to a third relay 29 to be described later [0106] (Configuration of Embodiment 2) Fig. 9 is a diagram for illustrating an example of an electrical configuration of an inverter device 1 according to Embodiment 2 of the present invention. As illustrated in Fig. 9, the inrush current preventing circuit 15 includes the inrush current preventing resistor 25 and the third relay 29, and the inrush current preventing resistor 25 and the third relay 29 are connected in parallel to each other. In other words, the inrush current preventing circuit 15 illustrated in Fig. 9 has a single relay configuration.

[0107] The inverter device 1 includes a signal operation device 47. The signal operation device 47 is configured to transmit a third control signal to the third relay 29 based on the first control signal transmitted from the control board 43 and the second control signal transmitted from the inverter board 45.

[0108] Fig. 10 is a diagram for illustrating an example of a functional configuration of the signal operation device 47 included in the inverter device 1 according to Embodiment 2 of the present invention. As illustrated in Fig. 10, the signal operation device 47 includes an OR operation unit 91. The OR operation unit 91 is configured to output the result of OR operation between the first control signal and the second control signal as the third control signal, and to transmit the third control signal to the inrush current preventing circuit 15.

[0109] Specifically, the OR operation unit 91 outputs logical OR of the input signals.

For example, when any one of the first control signal and the second control signal is in a high-level state, the OR operation unit 91 sets the third control signal to the high-level state.

[0110] (Operation of Embodiment 2) Fig. 11 is a flow chart for illustrating a control example of the signal operation device 47 included in the inverter device 1 according to Embodiment 2 of the present invention.

[0111] (Step S71) The signal operation device 47 determines whether or not the first control signal or the second control signal has arrived. When the first control signal or the second control signal has arrived, the signal operation device 47 proceeds to Step S72. On the other hand, when neither the first control signal nor the second control signal has arrived, the signal operation device 47 returns to Step S71.

[0112] (Step S72) The signal operation device 47 executes the OR operation between the first control signal and the second control signal.

[0113] (Step S73) The signal operation device 47 transmits the execution result of the OR operation to the inrush current preventing circuit 15, and then ends the processing. [0114] (Effect of Embodiment 2) From the description above, the third relay 29 is controlled by any one of the first control signal and the second control signal. Further, the inrush current preventing circuit 15 only requires a single relay configuration. Thus, the cost can be suppressed, and the space can be saved.

[0115] As described above, according to Embodiment 2 of the present invention, the inverter device 1 further includes the control board 43 configured to control the inrush current preventing circuit 15 and the inverter board 45, the third relay 29 controlled by the control board 43 or the inverter board 45 as the one or the plurality of relays, and the signal operation device 47 configured to control the third relay 29. The signal operation device 47 is configured to set the third relay 29 to the closed state based on at least one of the first control signal transmitted from the control board 43 and the second control signal transmitted from the inverter board 45.

[0116] Thus, for the inverter device 1, the cost can be suppressed, and the space can be saved.

[0117] Embodiment 3 (Difference) In Embodiment 3 of the present invention, a detailed example of the signal operation device 47 is described.

[0118] (Configuration of Embodiment 3) Fig. 12 is a diagram for illustrating a configuration example of an electrical component box 9 according to Embodiment 3 of the present invention. As illustrated in Fig. 12, the electrical component box 9 includes, for example, a power supply board 41, the control board 43, the inverter board 45, the rectifier 11, the DC reactor 13, the smoothing capacitor 17, the inverter 19, the first voltage detection unit 31, and the second voltage detection unit 33.

[0119] In this case, a heatsink (not shown) is mounted to the back surface side of each of the power supply board 41, the control board 43, and the inverter board 45. Further, the electrical component box 9 is mounted on the outdoor unit 111 to be described later.

[0120] Fig. 13 is a diagram for illustrating an example of an electrical configuration of the signal operation device 47 according to Embodiment 3 of the present invention. In this case, it is assumed that the reference potential of the control board 43 and the reference potential of the inverter board 45 are the same. In other words, the control board 43 and the inverter board 45 have the same potential, and hence a short-circuit state between the control board 43 and the inverter board 45 cannot occur. [0121] As illustrated in Fig. 13, the signal operation device 47 includes a first semiconductor switch 93 and a second semiconductor switch 95. Specifically, the signal operation device 47 includes the first semiconductor switch 93 having a gate to which the first control signal is input, the second semiconductor switch 95 having a gate to which the second control signal is input, and the OR operation unit 91. A first power supply 101 and a second power supply 102 are power supplies used for driving the third relay 29.

[0122] The first semiconductor switch 93 is connected between the first power supply 101 and the OR operation unit 91, and the second semiconductor switch 95 is connected between the second power supply 102 and the OR operation unit 91.

Through use of two semiconductor switches in this manner, the signal operation device 47 is downsized and reduced in cost.

[0123] (Operation of Embodiment 3) When the first control signal is input to the first semiconductor switch 93, the first semiconductor switch 93 supplies the voltage supplied from the first power supply 101 to the OR operation unit 91. The OR operation unit 91 outputs the logical OR of the inputs, and hence the voltage supplied from the first power supply 101 is applied to the third relay 29 so that the third relay 29 transitions from the open state to the short-circuit state.

[0124] When the second control signal is input to the second semiconductor switch 95, the second semiconductor switch 95 supplies the voltage supplied from the second power supply 102 to the OR operation unit 91. The OR operation unit 91 outputs the logical OR of the inputs, and hence the voltage supplied from the second power supply 102 is applied to the third relay 29 so that the third relay 29 transitions from the open state to the short-circuit state.

[0125] When the first control signal is input to the first semiconductor switch 93, and the second control signal is input to the second semiconductor switch 95, the first semiconductor switch 93 supplies the voltage supplied from the first power supply 101 to the OR operation unit 91, and the second semiconductor switch 95 supplies the voltage supplied from the second power supply 102 to the OR operation unit 91. The OR operation unit 91 outputs the logical OR of the inputs, and hence the voltage supplied from the first power supply 101 or the voltage supplied from the second power supply 102 is applied to the third relay 29 so that the third relay 29 transitions from the open state to the short-circuit state.

[0126] When the first control signal is not input to the first semiconductor switch 93, and the second control signal is not input to the second semiconductor switch 95, the first semiconductor switch 93 does not supply the voltage supplied from the first power supply 101 to the OR operation unit 91, and the second semiconductor switch 95 does not supply the voltage supplied from the second power supply 102 to the OR operation unit 91. The OR operation unit 91 outputs the logical OR of the inputs, nothing is output to the third relay 29, and the third relay 29 is maintained to the open state.

[0127] (Effect of Embodiment 3) From the description above, in the inverter device 1, through use of two semiconductor switches, the signal operation device 47 can be downsized, and also achieved in low cost.

[0128] The OR operation unit 91 is only required to execute the logical OR operation, and its configuration is not particularly limited. The OR operation unit 91 may be constructed of, for example, an OR circuit, or may be constructed by providing a NOT circuit to each input of a NAND circuit. Further, the OR operation unit 91 may be constructed of an analog circuit instead of a digital circuit.

[0129] As described above, according to Embodiment 3 of the present invention, the inverter board 45 and the control board 43 have the same reference potential. The signal operation device 47 includes the second semiconductor switch 95 configured to open or close based on the second control signal, and the first semiconductor switch 93 being non-insulated to the second semiconductor switch 95 and configured to open or close based on the first control signal. The signal operation device 47 is configured to set the third relay 29 to the closed state based on the result of the logical OR operation between the output of the first semiconductor switch 93 and the output of the second semiconductor switch 95.

[0130] Thus, in the inverter device 1, the signal operation device 47 can be downsized, and also achieved in low cost.

[0131] Embodiment 4 (Difference) In Embodiment 4 of the present invention, a detailed example of the signal operation device 47 is described.

[0132] (Configuration of Embodiment 4) Fig. 14 is a diagram for illustrating an example of an electrical configuration of a signal operation device 47 according to Embodiment 4 of the present invention. In this case, it is assumed that the reference potential of the control board 43 and the reference potential of the inverter board 45 are different. In other words, the control board 43 and the inverter board 45 do not have the same potential, and hence a shod-circuit state between the control board 43 and the inverter board 45 can occur [0133] As illustrated in Fig. 14, the signal operation device 47 includes the second semiconductor switch 95 and a third semiconductor switch 97. Specifically, the signal operation device 47 includes the third semiconductor switch 97 having a gate to which the first control signal is input, the second semiconductor switch 95 having the gate to which the second control signal is input, and the OR operation unit 91.

The first power supply 101 and the second power supply 102 are power supplies used for driving the third relay 29.

[0134] The third semiconductor switch 97 is connected between the first power supply 101 and the OR operation unit 91, and the second semiconductor switch 95 is connected between the second power supply 102 and the OR operation unit 91. Through use of two semiconductor switches in this manner, the signal operation device 47 is downsized and reduced in cost.

[0135] Further, the third semiconductor switch 97 is constructed of, for example, a semiconductor switch having insulating specifications, such as a photocoupler. With this configuration, the potential on the control board 43 side is insulated and isolated from the potential on the inverter board 45 side.

[0136] (Operation of Embodiment 4) When the first control signal is input to the third semiconductor switch 97, the third semiconductor switch 97 supplies the voltage is supplied from the first power supply 101 to the OR operation unit 91. The OR operation unit 91 outputs the logical OR of the inputs, and hence the voltage supplied from the first power supply 101 is applied to the third relay 29 so that the third relay 29 transitions from the open state to the short-circuit state.

[0137] When the second control signal is input to the second semiconductor switch 95, the second semiconductor switch 95 supplies the voltage supplied from the second power supply 102 to the OR operation unit 91. The OR operation unit 91 outputs the logical OR of the inputs, and hence the voltage supplied from the second power supply 102 is applied to the third relay 29 so that the third relay 29 transitions from the open state to the short-circuit state.

[0138] When the first control signal is input to the third semiconductor switch 97, and the second control signal is input to the second semiconductor switch 95, the third semiconductor switch 97 supplies the voltage supplied from the first power supply 101 to the OR operation unit 91, and the second semiconductor switch 95 supplies the voltage supplied from the second power supply 102 to the OR operation unit 91.

The OR operation unit 91 outputs the logical OR of the inputs, and hence the voltage supplied from the first power supply 101 or the voltage supplied from the second power supply 102 is applied to the third relay 29 so that the third relay 29 transitions from the open state to the short-circuit state.

[0139] When the first control signal is not input to the third semiconductor switch 97, and the second control signal is not input to the second semiconductor switch 95, the third semiconductor switch 97 does not supply the voltage supplied from the first power supply 101 to the OR operation unit 91, and the second semiconductor switch 95 does not supply the voltage supplied from the second power supply 102 to the OR operation unit 91. The OR operation unit 91 outputs the logical OR of the inputs, nothing is output to the third relay 29, and the third relay 29 is maintained to the open state. [0140] (Effect of Embodiment 4) From the description above, in the inverter device 1, through use of two semiconductor switches, the signal operation device 47 can be downsized, and also achieved in low cost.

[0141] The OR operation unit 91 is only required to execute the logical OR operation, and its configuration is not particularly limited. The OR operation unit 91 may be constructed of, for example, an OR circuit, or may be constructed by providing a NOT circuit to each input of a NAND circuit. Further, the OR operation unit 91 may be constructed of an analog circuit instead of a digital circuit.

[0142] Further, the third semiconductor switch 97 is only required to have a configuration capable of being electrically insulated, and is not particularly limited to the photocoupler described above. For example, a set of a light emitting element and a light receiving element may be used to configure a unit corresponding to the third semiconductor switch 97. In this case, the following configuration is only required. The light emitting element emits light in response to input of the first control signal, and the light receiving element receives the light emitted from the light emitting element, thereby establishing conduction between the first power supply 101 and the OR operation unit 91 by the light receiving element.

[0143] Further, the potential on the control board 43 side is insulated and isolated from the potential on the inverter board 45 side. Thus, when the contact side of the third relay 29 and the reference potential of the inverter board 45 have the same potential, the insulating distance between the coil portion of the third relay 29 and the contact portion of the third relay 29 can be shortened. With such a circuit configuration, the wiring length of each element can be shortened, and accordingly the board pattern can be increased in size relatively. Thus, the inverter device 1 can be increased in current, and also can suppress in temperature of the board.

[0144] As described above, according to Embodiment 4 of the present invention, the inverter board 45 and the control board 43 have different reference potentials. The signal operation device 47 includes the second semiconductor switch 95 configured to open or close based on the second control signal, and the third semiconductor switch 97 insulated from the second semiconductor switch 95 and configured to open or close based on the first control signal. The signal operation device 47 is configured to set the third relay 29 to the closed state based on the result of the logical OR operation between the output of the second semiconductor switch 95 and the output of the third semiconductor switch 97.

[0145] Thus, in the inverter device 1, the signal operation device 47 can be downsized, and also achieved in low cost. Further, in the inverter device 1, the board pattern can be increased in size. Thus, the current can be increased, and also the board temperature can be suppressed.

[0146] Embodiment 5 (Difference) The difference from other embodiments resides in that, as the rectifier 11, a chopper circuit 12 or a switching converter 14 is used.

[0147] (Configuration of Embodiment 5) In Embodiments 1 to 4, on the premise of a case where the commercial power source 3 is a three-phase AC power source, the rectifier 11 configured to form a three-phase full-wave rectified waveform is described, but as described in the paragraph above, the chopper circuit 12 or the switching converter 14 may be used. [0148] Fig. 15 is a diagram for illustrating an example of an electrical configuration of an inverter device 1 according to Embodiment 5 of the present invention. As illustrated in Fig. 15, the DC current output from the chopper circuit 12 is supplied to the DC reactor 13, and the DC voltage output from the chopper circuit 12 is supplied to the smoothing capacitor 17. In other words, the chopper circuit 12 is configured to convert the power supplied from the outside into DC power to supply the DC power, and hence an effect similar to the effects described above in Embodiments 1 to 4 can be obtained.

[0149] Fig. 16 is a diagram for illustrating another example of an electrical configuration of the inverter device 1 according to Embodiment 5 of the present invention. As illustrated in Fig. 16, the DC current output from the switching converter 14 is supplied to the DC reactor 13, and the DC voltage output from the switching converter 14 is supplied to the smoothing capacitor 17. In other words, the switching converter 14 is configured to convert the power supplied from the outside into DC power to supply the DC power, and hence an effect similar to the effects described above in Embodiments 1 to 4 can be obtained.

[0150] In other words, the circuit configuration for rectification is not particularly limited as long as the circuit configuration achieves conversion into DC power. The commercial power source 3 may be a single-phase AC power source.

[0151] (Effect of Embodiment 5) As long as the circuit configuration for rectification achieves conversion into DC power, an effect similar to the effects described above in Embodiments 1 to 4 can be obtained.

[0152] As described above, according to Embodiment 5 of the present invention, as the rectifier 11, one of the chopper circuit 12 and the switching converter 14 is used. [0153] Thus, in the inverter device 1, as long as the circuit configuration for rectification achieves conversion into DC power, an effect similar to the effects described above in Embodiments 1 to 4 can be obtained.

[0154] Embodiment 6 (Difference) In Embodiment 6 of the present invention, the air-conditioning apparatus 110 including the compressor 131 including the motor 7 driven by the inverter device 1 is described.

[0155] (Configuration of Embodiment 6) Fig. 17 is a diagram for illustrating an example of the air-conditioning apparatus using the inverter device 1 according to Embodiment 6 of the present invention. As illustrated in Fig. 17, the air-conditioning apparatus 110 includes the outdoor unit 111, and an indoor unit 112_1 to an indoor unit 112_N. Reference sign 112 is used to describe the indoor unit unless otherwise required to particularly distinguish the indoor unit 112 1 to the indoor unit 112_N.

[0156] The outdoor unit 111 and the indoor unit 112 are connected to each other by a gas-side refrigerant pipe 121 and a liquid-side refrigerant pipe 122. Further, in the gas-side refrigerant pipe 121, the outdoor unit 111 and the indoor unit 112 are connected via a gas-side valve 123. In the liquid-side refrigerant pipe 122, the outdoor unit 111 and the indoor unit 112 are connected via a liquid-side valve 124. In other words, by connecting the outdoor unit 111 and the indoor unit 112 to each other by the gas-side refrigerant pipe 121 and the liquid-side refrigerant pipe 122, a refrigerant circuit to be described later is constructed. Reference sign 120 is used to describe the refrigerant pipe unless otherwise required to particularly distinguish the gas-side refrigerant pipe 121 and the liquid-side refrigerant pipe 122.

[0157] The outdoor unit 111 includes the compressor 131, a four-way valve 132, an outdoor heat exchanger 133, an accumulator 134, a second expansion device 137, and the outdoor fan 141. The indoor unit 112_1 includes an indoor heat exchanger 135_1, a first expansion device 136_1, and an indoor fan 143_1. The outdoor unit 111 includes the electrical component box 9 described above, but illustration of the electrical component box 9 is omitted herein because Fig. 17 is a refrigerant system diagram.

[0158] Each of the indoor unit 112_2 to the indoor unit 112_N has a configuration similar to that of the indoor unit 112_1, and hence description thereof is omitted. Further, reference sign 135 is used to describe the indoor heat exchanger unless otherwise required to particularly distinguish the indoor heat exchanger 135_1 to the indoor heat exchanger 135_N. Reference sign 136 is used to describe the first expansion device unless otherwise required to particularly distinguish the first expansion device 136_1 to the first expansion device 136_N. Reference sign 143 is used to describe the indoor fan unless otherwise required to particularly distinguish the indoor fan 143 1 to the indoor fan 143_N.

[0159] The compressor 131, the four-way valve 132, the outdoor heat exchanger 133, the accumulator 134, the indoor heat exchanger 135, the first expansion device 136, and the second expansion device 137 are connected in order by the refrigerant pipe 120, to thereby construct the refrigerant circuit. The refrigerant circuit is configured to circulate the refrigerant while causing the refrigerant to be compressed and expanded. For example, the compressor 131 includes the motor 7, and is configured to compress and discharge the refrigerant along with the drive of the motor 7. The four-way valve 132 is configured to switch the path of the refrigerant depending on cooling or heating. The outdoor heat exchanger 133 is configured to exchange heat between the refrigerant and outside air, to thereby condense or evaporate the refrigerant. The accumulator 134 is configured to store surplus refrigerant. The indoor heat exchanger 135 is configured to exchange heat between the refrigerant and indoor air, to thereby evaporate or condense the refrigerant.

[0160] (Operation of Embodiment 6) In the air-conditioning apparatus 110, the inverter device 1 drives the motor 7 to drive the compressor 131. At this time, even when an abnormality occurs in the inverter 19 of the inverter device 1, as described above, the resistance voltage breakdown of the switching element 87 of the inverter 19 is prevented.

[0161] (Effect of Embodiment 6) Even in the abnormal state, the inverter device 1 can prevent the switching element 87 from being damaged. Thus, the air-conditioning apparatus 110 can be stably operated.

[0162] As described above, according to Embodiment 6 of the present invention, the air-conditioning apparatus 110 includes the outdoor unit 111, and the indoor unit 112 connected to the outdoor unit 111 by the gas-side refrigerant pipe 121 and the liquid-side refrigerant pipe 122, to thereby construct the refrigerant circuit. The outdoor unit 111 includes the compressor 131 configured to compress and discharge the refrigerant. The compressor 131 includes the motor 7. The motor 7 is controlled by the inverter device 1.

[0163] Thus, even in the abnormal state, the inverter device 1 can prevent the switching element 87 from being damaged. Thus, the air-conditioning apparatus 110 can be stably operated.

Reference Signs List [0164] 1 inverter device 3 commercial power source 5 switch 7 motor 9 electrical component box 11 rectifier 12 chopper circuit 13 DC reactor 14 switching converter 15 inrush current preventing circuit 17 smoothing capacitor 19 inverter 23 second relay 25 inrush current preventing resistor 27 first relay 29 third relay 31 first voltage detection unit 33 second voltage detection unit 41 power supply board 43 control board 45 inverter board 47 signal operation device 51 abnormality determining unit 53 deceleration control unit 55 relay control unit 57 inverter control unit 71 relay failure determining unit 73 DC voltage abnormality determining unit 75 operation-state rotation speed acquiring unit 77 deceleration-state rotation speed acquiring unit 79 deceleration time calculating unit 83 inverter drive signal determining unit 85 gate control unit 87 switching element 91 OR operation unit 93 first semiconductor switch 95 second semiconductor switch 97 third semiconductor switch 101 first power supply 102 second power supply 110 air-conditioning apparatus 111 outdoor unit 112, 112_1 to 112_N indoor unit 120 refrigerant pipe 121 gas-side refrigerant pipe 122 liquid-side refrigerant pipe 123 gas-side valve 124 liquid-side valve 131 compressor 132 four-way valve 133 outdoor heat exchanger 134 accumulator 135, 135_1 to 135_N indoor heat exchanger 136, 136_1 to 136_N first expansion device 137 second expansion device 141 outdoor fan 143, 143_1 to 143_N indoor fan