JP6155282B2 - Power semiconductor module and power converter using the same - Google Patents

Power semiconductor module and power converter using the same Download PDF

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JP6155282B2
JP6155282B2 JP2014551810A JP2014551810A JP6155282B2 JP 6155282 B2 JP6155282 B2 JP 6155282B2 JP 2014551810 A JP2014551810 A JP 2014551810A JP 2014551810 A JP2014551810 A JP 2014551810A JP 6155282 B2 JP6155282 B2 JP 6155282B2
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semiconductor element
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electrode side
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真実 国広
真実 国広
石川　勝美
勝美 石川
歩 畑中
歩 畑中
徹 増田
徹 増田
景山　寛
景山　　寛
和俊 小川
和俊 小川
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Description

本発明は、パワー半導体モジュール及びこれを用いた電力変換装置に係わり、特に、多層の回路基板に適用したパワー半導体モジュールの構成に関する。   The present invention relates to a power semiconductor module and a power converter using the same, and more particularly to a configuration of a power semiconductor module applied to a multilayer circuit board.

一般に、電流経路を対向させることによって、発生する磁束を相殺させ、回路基板のインダクタンスを低減させることは、従来から知られている。そして、回路基板を多層化し、表層配線と内層配線の電流を対向させて、回路基板のインダクタンスを低減する従来技術は、例えば特許文献１に開示されている。この特許文献１に記載された半導体装置では、グランドと電源の２層の配線が積層された配線基板において、電源（＋電流）とグランドライン（−電流）とに対向電流を流すことでインダクタンスを低減する構成が用いられている。   In general, it has been conventionally known that the generated magnetic flux is canceled by opposing the current paths to reduce the inductance of the circuit board. A conventional technique for reducing the inductance of a circuit board by multilayering the circuit board and causing the currents of the surface layer wiring and the inner layer wiring to face each other is disclosed in Patent Document 1, for example. In the semiconductor device described in Patent Document 1, in a wiring board in which two layers of wiring of a ground and a power supply are stacked, an inductance is generated by causing a counter current to flow through a power supply (+ current) and a ground line (−current). A reducing configuration is used.

また、特許文献２に記載されたパワー半導体モジュールには、多層の配線基板において内層配線をグランド配線とする構成が示されている（特許文献２の図６を参照）。   Further, the power semiconductor module described in Patent Document 2 shows a configuration in which an inner layer wiring is a ground wiring in a multilayer wiring board (see FIG. 6 of Patent Document 2).

特開２００１−１４４４４０号公報JP 2001-144440 A 特開２００７−２３４６９０号公報JP 2007-234690 A

ところで、電力変換器で発生するスイッチングに伴う電力損失を低減するには、絶縁ゲートバイポーラトランジスタ（ＩＧＢＴ）におけるスイッチングの高速化による高速駆動と、半導体モジュールへのワイドギャップ半導体素子（例．ＩＧＢＴとショットキーバリアダイオード）の搭載によるリカバリー電流の減少と、が有効である。   By the way, in order to reduce the power loss accompanying the switching generated in the power converter, high-speed driving by increasing the switching speed in the insulated gate bipolar transistor (IGBT) and wide gap semiconductor elements (eg, IGBT and shot) to the semiconductor module. Reduction of recovery current by mounting a key barrier diode) is effective.

ここで、半導体素子の高速駆動時には高周波の電流振動が発生するが、これに対してはインダクタンスを低減することによって、電流振動を抑制することができる。また、ワイドギャップ半導体素子を搭載した大容量半導体モジュールを形成するには、当該ワイドギャップ半導体素子（ＳｉＣ、ＧａＮ）が歩留まりの点から小容量のものしか製造でき難い実情からすると、ワイドギャップ半導体素子を多数並列に実装することが必要である。   Here, high-frequency current vibration is generated when the semiconductor element is driven at high speed. However, current vibration can be suppressed by reducing the inductance. In addition, in order to form a large capacity semiconductor module equipped with a wide gap semiconductor element, it is difficult to manufacture only a small capacity wide gap semiconductor element (SiC, GaN) from the viewpoint of yield. Must be implemented in parallel.

その際、搭載すべき半導体素子の数を一定とすると、一の回路基板に比較的少ない数の半導体素子を搭載した場合には回路基板の数を増加せざると得ず、この回路基板の数の増加は装置の大型化や駆動信号のばらつきにつながるおそれがある。そのため、回路基板あたりの半導体素子を多数搭載する（すなわち、回路基板の数を少なくする）ことの方が望ましい。   At that time, if the number of semiconductor elements to be mounted is constant, when a relatively small number of semiconductor elements are mounted on one circuit board, the number of circuit boards cannot be increased. There is a possibility that the increase in the size of the apparatus will lead to an increase in the size of the device and variations in drive signals. Therefore, it is desirable to mount a large number of semiconductor elements per circuit board (that is, to reduce the number of circuit boards).

ところで、上記の特許文献１には、多層配線基板の積層構造において、電源ラインとグランドライン間の電流の大きさを略等しくし且つ電流の向きを逆とすることでインダクタンスの低減を図ることが開示されてはいるが、多層の配線基板上における半導体素子と接続端子との位置関係については特段の記載はない。特に、半導体素子の多並列実装時においては、配線基板のインダクタンスが低減する一方で、半導体素子間のインダクタンスのばらつきが大きくなり、わずかなインダクタンスばらつきが各半導体素子の負荷、発熱のばらつきに発展するおそれがある。また、半導体素子と接続端子の位置次第によっては、形成される電流ループが大きくなり、相殺する磁束数が少なくなってインダクタンスの低減にむすびつかないこととなる。   By the way, in the above-mentioned Patent Document 1, in the multilayer structure of the multilayer wiring board, the inductance is reduced by making the magnitude of the current between the power supply line and the ground line substantially equal and reversing the direction of the current. Although disclosed, there is no particular description about the positional relationship between the semiconductor element and the connection terminal on the multilayer wiring board. In particular, when multiple semiconductor elements are mounted in parallel, while the inductance of the wiring board is reduced, the variation in inductance between the semiconductor elements increases, and the slight inductance variation develops into the variation of the load and heat generation of each semiconductor element. There is a fear. Further, depending on the position of the semiconductor element and the connection terminal, the formed current loop becomes large, and the number of magnetic fluxes to be canceled decreases, so that it is difficult to reduce the inductance.

また、上記の特許文献２に示す構成においては、電源パタンから半導体素子を経由して形成される電流ループの大きさが不均一であるため、等価的にインダクタンスがばらついて電流ループの電流バランスがくずれることとなり、ループ毎の半導体素子の動作不安定と故障に結び付くこととなる。このように、特許文献２に開示の構成では、低インダクタンス基板において半導体素子を多数並列に実装した場合の課題である、半導体素子間のインダクタンスばらつき、電流アンバランスの影響を受けることとなる。   Further, in the configuration shown in Patent Document 2 above, since the size of the current loop formed from the power supply pattern via the semiconductor element is non-uniform, the inductance is equivalently varied and the current balance of the current loop is balanced. As a result, the operation of the semiconductor element in each loop is unstable and a failure occurs. As described above, the configuration disclosed in Patent Document 2 is affected by inductance variation between semiconductor elements and current imbalance, which are problems when a large number of semiconductor elements are mounted in parallel on a low-inductance substrate.

本発明の目的は、パワー半導体モジュールのインダクタンスを低減でき、且つ、多数並列に実装した半導体素子間の電流バランスを改善するパワー半導体モジュールを提供することにある。   An object of the present invention is to provide a power semiconductor module capable of reducing the inductance of the power semiconductor module and improving the current balance between a plurality of semiconductor elements mounted in parallel.

上記目的を達成するために、本発明は主として以下のような構成を採用する。
少なくとも２層の絶縁層と２層の金属層とを有し、当該金属層間に当該絶縁層を介在させて積層構造とした矩形状の回路基板と、正極電流を流す正極側端子と、負極電流を流す負極側端子と、前記金属層の内で上層の金属層に載置された半導体素子と、を備えたパワー半導体モジュールであって、前記上層の金属層は、前記半導体素子に加えて前記正極側端子と電気的に接続されると共に、当該上層の金属層の下に配置された下層の金属層と電気的に接続され、前記下層の金属層は、前記負極側端子と電気的に接続され、前記正極側端子と前記負極側端子とは、前記回路基板上で近接した位置で対として前記回路基板の長辺方向に沿って複数設置され、前記上層の金属層は、前記回路基板の長辺方向の一端部から他端部に亘って延びる矩形状の金属箔を前記回路基板の短辺方向に複数並列して形成されており、前記半導体素子は、スイッチング素子とダイオードとから成ると共に、複数の前記金属箔のうち少なくともいずれかにおいて、その長辺方向に沿って複数並列して配置され、前記正極側端子及び前記負極側端子の対と当該対に対応する前記半導体素子とは、前記回路基板の短辺方向に沿ったパターンを形成して前記回路基板の長辺方向に沿って複数並列実装され、前記パターンは、前記回路基板の短辺方向に沿って複数並列配置された前記半導体素子によって成る列を２列含み、かつ前記正極側端子及び前記負極側端子の対が前記列同士の中間位置に対応する位置に設けられており、前記複数設置された前記正極側端子及び前記負極側端子の対のそれぞれと当該対に対応する前記半導体素子とを通る電流経路は、前記回路基板の短辺方向に沿って形成され、かつ互いに略同一の長さを有する構成とする。 In order to achieve the above object, the present invention mainly adopts the following configuration.
A rectangular circuit board having a laminated structure having at least two insulating layers and two metal layers, with the insulating layer interposed between the metal layers, a positive terminal for passing a positive current, and a negative current A power semiconductor module comprising: a negative electrode side terminal through which a current flows; and a semiconductor element mounted on an upper metal layer in the metal layer, wherein the upper metal layer includes the semiconductor element in addition to the semiconductor element. It is electrically connected to the positive electrode side terminal and is electrically connected to the lower metal layer disposed under the upper metal layer, and the lower metal layer is electrically connected to the negative electrode terminal. A plurality of the positive electrode side terminals and the negative electrode side terminals are installed along the long side direction of the circuit board as a pair at a position close to each other on the circuit board, and the upper metal layer is formed on the circuit board. A rectangular shape extending from one end of the long side to the other end A plurality of metal foils are formed in parallel in the short side direction of the circuit board, and the semiconductor element is composed of a switching element and a diode, and in at least one of the plurality of metal foils, the long side direction A plurality of the positive electrode side terminals and the negative electrode side terminal pairs, and the semiconductor elements corresponding to the pairs form a pattern along the short side direction of the circuit board to form the circuit. A plurality of parallel mounting is performed along the long side direction of the substrate, and the pattern includes two columns of the semiconductor elements arranged in parallel along the short side direction of the circuit board, and the positive terminal and the a pair of negative terminal is provided at a position corresponding to the intermediate position of the column between, to respond to each and the pair of pairs of said plurality installed said positive terminal and said negative terminal The current path through the semiconductor element is formed along the short side direction of the circuit board, and configured to have substantially the same lengths.

本発明によれば、パワー半導体モジュールにおける低インダクタンス化と多数並列に実装した半導体素子間の電流バランスの改善を両立することができる。これによって、半導体素子に流れる電流振動を抑制することができるとともに、パワー半導体モジュールのスイッチングに伴う電力損失を低減することができる。   According to the present invention, it is possible to achieve both a reduction in inductance in a power semiconductor module and an improvement in current balance between a plurality of semiconductor elements mounted in parallel. As a result, it is possible to suppress the vibration of the current flowing through the semiconductor element and reduce the power loss associated with the switching of the power semiconductor module.

また、回路基板あたりの半導体素子の搭載数を増加することができ、小型かつ大容量の半導体モジュールを構成することができる。   In addition, the number of semiconductor elements mounted on a circuit board can be increased, and a small and large capacity semiconductor module can be configured.

本発明の実施形態に係るパワー半導体モジュールを構成する多数並列実装された半導体素子、正極側端子、負極側端子、回路基板の配置構成と、電流の流れと、を示す図である。It is a figure which shows the arrangement configuration of the semiconductor element, the positive electrode side terminal, the negative electrode side terminal, and circuit board which are comprised in parallel and which comprises the power semiconductor module which concerns on embodiment of this invention, and the flow of an electric current. 本実施形態に係るパワー半導体モジュールを構成する多数並列実装された半導体素子と、正極側端子及び負極側端子と、における等価回路を示す図である。It is a figure which shows the equivalent circuit in the semiconductor element and the positive electrode side terminal and negative electrode side terminal which were comprised in parallel and comprised many power semiconductor modules which concern on this embodiment. 本実施形態に係るパワー半導体モジュールを構成する回路基板における対向する金属箔の長さ、幅、厚みと、インダクタンスとの関係を示す説明図である。It is explanatory drawing which shows the relationship between the length of the metal foil which opposes in the circuit board which comprises the power semiconductor module which concerns on this embodiment, width | variety, thickness, and an inductance. 本実施形態に関する多数並列実装された半導体素子と、正極側端子及び負極側端子と、の位置関係を示す図である。It is a figure which shows the positional relationship of the semiconductor element mounted in parallel regarding this embodiment, and the positive electrode side terminal and the negative electrode side terminal. 本実施形態に関する回路基板における金属箔の配置パターンの形状を示す図である。It is a figure which shows the shape of the arrangement pattern of metal foil in the circuit board regarding this embodiment. 本実施形態に係るパワー半導体モジュールの全体構成を示す図である。It is a figure which shows the whole structure of the power semiconductor module which concerns on this embodiment. 本実施形態に係るパワー半導体モジュールに冷却機構を備えた電力変換装置を示す図である。It is a figure which shows the power converter device provided with the cooling mechanism in the power semiconductor module which concerns on this embodiment. 本実施形態に係るパワー半導体モジュールに他の冷却機構を備えた電力変換装置を示す図である。It is a figure which shows the power converter device provided with the other cooling mechanism in the power semiconductor module which concerns on this embodiment.

本発明の実施形態に係るパワー半導体モジュールについて、図面を参照しながら以下説明する。図１は本発明の実施形態に係るパワー半導体モジュールを構成する多数並列実装された半導体素子、正極側端子、負極側端子、回路基板の配置構成と、電流の流れと、を示す図である。図１において、１は回路基板、２は正極側端子、３は半導体素子、４は半導体素子及び正極側端子と電気的接続する金属箔、５は負極側端子、６は金属箔４及び負極側端子と電気的接続する金属箔、７は回路基板と放熱ベース１５を接続する金属箔、８は金属箔４と金属箔６を絶縁する絶縁材、９は金属箔６と金属箔７を絶縁する絶縁材、をそれぞれ表す。   A power semiconductor module according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing an arrangement configuration of a large number of semiconductor elements, positive electrode side terminals, negative electrode side terminals, and circuit boards that constitute a power semiconductor module according to an embodiment of the present invention, and a current flow. In FIG. 1, 1 is a circuit board, 2 is a positive terminal, 3 is a semiconductor element, 4 is a metal foil electrically connected to the semiconductor element and the positive terminal, 5 is a negative terminal, and 6 is a metal foil 4 and a negative side. A metal foil that is electrically connected to the terminal, 7 is a metal foil that connects the circuit board and the heat dissipation base 15, 8 is an insulating material that insulates the metal foil 4 and the metal foil 6, and 9 is that that insulates the metal foil 6 and the metal foil 7. Each of the insulating materials is represented.

図１において、回路基板１は、半導体素子３を戴置する金属箔４と、金属箔４と電気的に接続する金属箔６と、金属箔４と金属箔６を積層する絶縁材８と、放熱板１５（図６を参照）と接続する金属箔７と、金属箔６と金属箔７を積層する絶縁材９と、から成り立っていて、これらの各構成要素を積層接着させたものである。図１（１）には、回路基板１上の各構成要素の載置状態を平面図及び側面図として示し、図１（２）には、回路基板１上の各構成要素の載置状態を分解図として示している。   In FIG. 1, a circuit board 1 includes a metal foil 4 on which a semiconductor element 3 is placed, a metal foil 6 that is electrically connected to the metal foil 4, an insulating material 8 that laminates the metal foil 4 and the metal foil 6, It consists of a metal foil 7 connected to a heat sink 15 (see FIG. 6), and an insulating material 9 that laminates the metal foil 6 and the metal foil 7, and these components are laminated and bonded together. . FIG. 1 (1) shows a mounting state of each component on the circuit board 1 as a plan view and a side view, and FIG. 1 (2) shows a mounting state of each component on the circuit board 1. It is shown as an exploded view.

本実施形態に係るパワー半導体モジュールは、半導体素子３と、回路基板１と、正極電流を供給する正極側端子２と、負極電流を供給する負極側端子５と、放熱ベース１５（図６を参照）と、を基本的な構成としている。正極側端子２と負極側端子５とは、金属箔４，６上においてそれぞれ近接して配置され、回路基板１の長辺方向に２対以上設けられている（図示例では３対の端子２，５が長辺方向に並列実装されている）。図１において、半導体素子３は、ＩＧＢＴとダイオードから成り立って１つのアーム（スイッチ部）を形成しており、図１では上下に半導体素子３，３が図示されていて、いわゆる上下アーム直列回路が図示されている。そして、図示例ではこの上下アーム直列回路が６個並列に実装されている。   The power semiconductor module according to the present embodiment includes a semiconductor element 3, a circuit board 1, a positive terminal 2 that supplies a positive current, a negative terminal 5 that supplies a negative current, and a heat dissipation base 15 (see FIG. 6). ) And the basic configuration. The positive electrode side terminal 2 and the negative electrode side terminal 5 are arranged close to each other on the metal foils 4 and 6, and two or more pairs are provided in the long side direction of the circuit board 1 (three pairs of terminals 2 in the illustrated example). , 5 are mounted in parallel in the long side direction). In FIG. 1, a semiconductor element 3 is composed of an IGBT and a diode to form a single arm (switch unit). In FIG. It is shown in the figure. In the illustrated example, six upper and lower arm series circuits are mounted in parallel.

正極側端子２と負極側端子５との間に流れる電流は、回路基板１内において回路基板１の短辺方向の流れである。ここで、端子２，５間を流れる電流は、例えば、上アームのＩＧＢＴがオフ状態で且つ下アームのＩＧＢＴがオンになった時に流れるリカバリー電流である。そして、下アームには、インバータ回路として正常動作時の電流がリカバリー電流に重畳されている。   The current flowing between the positive electrode side terminal 2 and the negative electrode side terminal 5 is a flow in the short side direction of the circuit board 1 in the circuit board 1. Here, the current flowing between the terminals 2 and 5 is, for example, a recovery current that flows when the IGBT of the upper arm is off and the IGBT of the lower arm is on. In the lower arm, the current during normal operation as an inverter circuit is superimposed on the recovery current.

ここで、後述する図４（１）に示すように、正極側及び負極側端子２，５は、金属箔４上に戴置された半導体素子３の間に対応する位置に配置してもよく、また、図４（２）に示すように、各半導体素子３に対向する位置に配置してもよい。また、正極側及び負極側端子２，５の設置位置は回路基板１の基板端部に限定されず、回路基板１の長辺方向であればどこで並列実装してもよい。また、半導体素子３と金属箔４の接続については、ワイヤボンドだけでなく、リボンボンドやフリップチップ実装によってもよい。   Here, as shown in FIG. 4A described later, the positive and negative terminals 2 and 5 may be arranged at corresponding positions between the semiconductor elements 3 placed on the metal foil 4. Further, as shown in FIG. 4B, the semiconductor elements 3 may be arranged at positions facing each other. Further, the installation positions of the positive electrode side and negative electrode side terminals 2 and 5 are not limited to the end portions of the circuit board 1 and may be mounted in parallel anywhere in the long side direction of the circuit board 1. Further, the connection between the semiconductor element 3 and the metal foil 4 may be not only wire bonding but also ribbon bonding or flip chip mounting.

図２は、本実施形態に係るパワー半導体モジュールを構成する多数並列実装された半導体素子と、正極側端子及び負極側端子と、における等価回路を示す図であり、図１に示す構成に対応する等価回路である。半導体素子は、そのスイッチのオフ時に、半導体素子の接合容量と寄生のインダクタンスにより、高周波の共振電流が発生し、この共振電流により電圧も振動する。ここで、高周波とは、パワー半導体モジュールを用いた電力変換器の出力周波数の最大値より１００倍以上大きい周波数のことである。   FIG. 2 is a diagram showing an equivalent circuit of a large number of semiconductor elements mounted in parallel constituting the power semiconductor module according to the present embodiment, and a positive electrode side terminal and a negative electrode side terminal, and corresponds to the configuration shown in FIG. It is an equivalent circuit. When the switch is turned off, the semiconductor element generates a high-frequency resonance current due to the junction capacitance and parasitic inductance of the semiconductor element, and the voltage also vibrates due to this resonance current. Here, the high frequency is a frequency 100 times or more larger than the maximum value of the output frequency of the power converter using the power semiconductor module.

この共振電流はスイッチの遮断速度が大きいほど顕著になる。このため、シリコンを使用した半導体素子よりも、シリコンカーバイドやガリウムナイトライドのようなワイドギャップ半導体の方が電流の振動は大きくなり、電磁ノイズを引き起こすおそれがある。   This resonance current becomes more significant as the cutoff speed of the switch increases. For this reason, current vibration is larger in a wide gap semiconductor such as silicon carbide or gallium nitride than in a semiconductor element using silicon, which may cause electromagnetic noise.

そこで、電流振動の抑制には寄生インダクタンスの低減が有効であるが、図２に示すように、特に、一つの基板に半導体素子３を多数並列実装する場合においては（大容量の半導体モジュールを形成するために）、基板に戴置される半導体素子３間のインダクタンスのばらつきが、各半導体素子のスイッチのタイミングに影響を及ぼすという不都合が生じる。   Therefore, reduction of parasitic inductance is effective in suppressing current oscillation. However, as shown in FIG. 2, particularly when a large number of semiconductor elements 3 are mounted in parallel on one substrate (a large capacity semiconductor module is formed). Therefore, there arises a disadvantage that the variation in inductance between the semiconductor elements 3 placed on the substrate affects the switch timing of each semiconductor element.

本発明の実施形態によれば、金属箔４と金属箔６において、回路基板１の短辺方向（図１の図示例で紙面上下方向）に電流を流すことによって、回路基板１の長辺方向に電流を流した場合と対比すると、電流経路の長さが短く且つ電流経路の幅が広くなるため、金属箔４，６からなる導体に電流が流れる際に発生するインダクタンスを低減することができる（その理由は後述の図３で説明する）。   According to the embodiment of the present invention, in the metal foil 4 and the metal foil 6, by passing a current in the short side direction of the circuit board 1 (vertical direction on the paper surface in the illustrated example of FIG. 1), the long side direction of the circuit board 1. As compared with the case where a current is passed through, the length of the current path is short and the width of the current path is wide, so that the inductance generated when the current flows through the conductor made of the metal foils 4 and 6 can be reduced. (The reason is explained in FIG. 3 described later).

さらに、回路基板１上に電流を流す金属箔４と金属箔６が絶縁材８を介した積層構造となっているために、積層された金属箔４，６の表面のうち、他方の金属箔と対向する面において電流が集中（積層する金属箔では対向する金属面の側に電流が集中）し、対向して流れる電流の空隙が狭くなって、発生する磁束をより多く相殺することで、回路基板のインダクタンスを低減することができる（その理由は後述の図３で説明する）。   Furthermore, since the metal foil 4 and the metal foil 6 that flow current on the circuit board 1 have a laminated structure with the insulating material 8 interposed therebetween, the other metal foil of the surfaces of the laminated metal foils 4 and 6 is used. The current is concentrated on the surface facing the surface (current is concentrated on the side of the facing metal surface in the laminated metal foil), the gap of the current flowing in the opposite direction is narrowed, and the generated magnetic flux is offset more, The inductance of the circuit board can be reduced (the reason for this will be described later with reference to FIG. 3).

また、正極側端子２と負極側端子５の対を２つ以上設けることで（図１の図示例で３つ）、端子２，５から半導体素子３を経て形成される電流ループの大きさが均一化され、半導体素子３の間で発生するインダクタンスのばらつきを低減する効果がある。換言すると、半導体素子３を回路基板１に多数並列実装する場合に、図４に示すように、並列実装した半導体素子３毎に、又は２つの半導体素子毎に、端子２，５を設けることによって、それぞれの端子２，５からみた半導体素子の電流ループは、その大きさが均一化されていることになる（図１の例で、例えば左端の一対の端子のみで、６個の上下アームのリカバリー電流通路を形成するものと対比すると、電流ループの大きさが均一化される）。   Further, by providing two or more pairs of the positive electrode side terminal 2 and the negative electrode side terminal 5 (three in the illustrated example of FIG. 1), the size of the current loop formed from the terminals 2 and 5 through the semiconductor element 3 is reduced. This is uniform and has the effect of reducing the variation in inductance that occurs between the semiconductor elements 3. In other words, when many semiconductor elements 3 are mounted in parallel on the circuit board 1, as shown in FIG. 4, by providing the terminals 2 and 5 for each semiconductor element 3 mounted in parallel or for every two semiconductor elements. Thus, the current loops of the semiconductor elements viewed from the respective terminals 2 and 5 are uniform in size (in the example of FIG. 1, for example, only the pair of terminals at the left end includes six upper and lower arms. The size of the current loop is made uniform when compared with the one that forms the recovery current path).

以上説明したように、本実施形態によれば、低インダクタンス化と半導体素子間インダクタンスばらつき（電流アンバランスに結び付く）の低減を両立でき、スイッチングに伴う電力損失の低減、インダクタンス低減による共振周波数のずれがもたらすノイズの低減、跳ね上がり電圧の抑制だけでなく、各半導体素子のスイッチばらつきの抑制が可能となり、基板あたりに実装できる半導体素子の数を増加でき、かつ電力変換器を安全に駆動することができる。すなわち、電力変換器の安全駆動の意味は、各半導体素子への電流ループが不均一になると、一の半導体素子への過度のリカバリー電流の偏りによる当該半導体素子の故障確率が高くなることに比べて、多数並列実装時のそれぞれの半導体素子の電流ループを均一にすることで故障確率を低くして、長持ちさせることである。   As described above, according to the present embodiment, it is possible to achieve both a reduction in inductance and a reduction in inductance variation between semiconductor elements (which leads to current imbalance), a reduction in power loss due to switching, and a shift in resonance frequency due to inductance reduction. In addition to the reduction of noise and suppression of jumping voltage, it is possible to suppress switch variation of each semiconductor element, increase the number of semiconductor elements that can be mounted per board, and drive the power converter safely. it can. That is, the meaning of safe driving of the power converter is that when the current loop to each semiconductor element becomes uneven, the failure probability of the semiconductor element increases due to excessive recovery current bias to one semiconductor element. Thus, by making uniform the current loop of each semiconductor element when multiple semiconductor devices are mounted in parallel, the failure probability is lowered and long-lasting.

特に、ＳｉＣ（炭化ケイ素）やＧａＮ（窒化ガリウム）のようなデバイスを用いて大容量半導体モジュールを構成する場合、小容量のチップを多並列で基板に実装する必要があるが、半導体素子間のインダクタンスのばらつき低減によって半導体素子毎の負荷や発熱の差を抑制できる。また、高速駆動のデバイスは、従来用いられていたＳｉよりも高速で遮断可能であるため、高速駆動に伴うｄＶ／ｄｔの増大によって電流の振動及び跳ね上がり電圧の増大が課題となっていたので、半導体素子間のインダクタンスのばらつき低減の効果は大きい。   In particular, when a large-capacity semiconductor module is configured using a device such as SiC (silicon carbide) or GaN (gallium nitride), it is necessary to mount small-capacity chips on a substrate in multiple parallels. By reducing the variation in inductance, a difference in load and heat generation for each semiconductor element can be suppressed. In addition, since the high-speed drive device can be cut off at a higher speed than the conventionally used Si, the increase in dV / dt associated with the high-speed drive has caused problems such as current oscillation and increase in jump voltage. The effect of reducing the variation in inductance between semiconductor elements is great.

図３は本実施形態に係るパワー半導体モジュールを構成する回路基板における対向する金属箔の長さ、幅、厚みと、インダクタンスとの関係を示す説明図である。図３において、金属箔４に電流が流れた場合、電流による磁束の変化に伴い、磁束の変化を打ち消すように誘導電力が発生する。自己誘導の起こしやすさを自己インダクタンスと呼び、次式にて求めることができる。   FIG. 3 is an explanatory diagram showing the relationship between the length, width and thickness of opposing metal foils on the circuit board constituting the power semiconductor module according to the present embodiment, and the inductance. In FIG. 3, when a current flows through the metal foil 4, inductive power is generated so as to cancel the change in the magnetic flux as the magnetic flux changes due to the current. The ease with which self-induction occurs is called self-inductance and can be calculated by the following equation.

Ｌ＝μｏ×ｌ／２π［ｌｎ｛２ｌ／（ａ＋ｗ）｝＋１／２］ （Ｈ）
ここで、μｏは金属箔の透磁率、ｌは金属箔長、ａは金属箔厚み、ｗは金属箔幅を示す。L = μo × l / 2π [ln {2l / (a + w)} + 1/2] (H)
Here, μo represents the permeability of the metal foil, l represents the metal foil length, a represents the metal foil thickness, and w represents the metal foil width.

また、金属箔４と対向する金属箔６に電流が流れた場合、電流による磁束の変化に伴い、誘導電力が発生する。誘導の起こしやすさを相互インダクタンスと呼び、次式にて求めることができる。   In addition, when a current flows through the metal foil 6 facing the metal foil 4, inductive power is generated as the magnetic flux changes due to the current. The ease of induction is called mutual inductance, and can be calculated by the following equation.

Ｍ＝μｏ×ｌ／２π［ｌｎ｛２ｌ／ｆ（ｗ，ｄ）｝−１］ （Ｈ）
ここで、ｄは絶縁材の厚みを示す。M = [mu] o * l / 2 [pi] [ln {2l / f (w, d)}-1] (H)
Here, d indicates the thickness of the insulating material.

一般に、電流経路を対向させることによって、発生する磁束を相殺してインダクタンスを低減することは、従来から知られている。ここでは、金属箔４の電流経路と金属箔６の電流経路を対向させることで、金属箔４で発生する磁束と金属箔６で発生する磁束の一部が相殺される。金属箔４と金属箔６によって発生するインダクタンスは、次式にて求めることができる。   In general, it has been conventionally known that an inductance is reduced by canceling a generated magnetic flux by making current paths face each other. Here, by making the current path of the metal foil 4 and the current path of the metal foil 6 face each other, the magnetic flux generated in the metal foil 4 and a part of the magnetic flux generated in the metal foil 6 are offset. The inductance generated by the metal foil 4 and the metal foil 6 can be obtained by the following equation.

Ｌ（ｔ）＝２Ｌ−２Ｍ
図３には、回路基板における金属箔４と金属箔６によって発生するインダクタンスＬ（ｔ）の値が、配線長（ｌ）、配線幅（ｗ）、空隙（ｄ）によって変化する特性を表している。L (t) = 2L-2M
FIG. 3 shows a characteristic in which the value of the inductance L (t) generated by the metal foil 4 and the metal foil 6 in the circuit board varies depending on the wiring length (l), the wiring width (w), and the air gap (d). Yes.

図示の説明によると、金属箔の長さ（ｌ）を短く、その幅（ｗ）を広く、絶縁材の厚みを狭め金属箔間の距離（ｄ）を短くして磁束相殺作用を大きくすることによって、回路基板のインダクタンスを低減することができ、インダクタンスに蓄えられるエネルギーが小さくなるため、跳ね上がり電圧抑制の効果が得られる。   According to the illustrated explanation, the length (l) of the metal foil is shortened, the width (w) is widened, the thickness of the insulating material is narrowed, and the distance (d) between the metal foils is shortened to increase the magnetic flux canceling action. Thus, the inductance of the circuit board can be reduced, and the energy stored in the inductance is reduced, so that the effect of suppressing the jumping voltage is obtained.

図４は本実施形態に関する多数並列実装された半導体素子と、正極側端子及び負極側端子と、の位置関係を示す図である。図４に示す回路基板では、金属箔４と接着する端子２，５の対が回路基板の長辺方向に２つ以上設けられており、回路基板上に同じパターンを繰り返すことで、端子２，５から半導体素子３と金属箔４，６を経て形成される電流ループの大きさを均一化できる。   FIG. 4 is a diagram showing the positional relationship between a number of semiconductor elements mounted in parallel and the positive terminal and the negative terminal according to this embodiment. In the circuit board shown in FIG. 4, two or more pairs of terminals 2 and 5 to be bonded to the metal foil 4 are provided in the long side direction of the circuit board. By repeating the same pattern on the circuit board, the terminals 2 and 2 5, the size of the current loop formed through the semiconductor element 3 and the metal foils 4 and 6 can be made uniform.

ここで、図４（１）に示すように、端子２，５は金属箔４上に戴置された半導体素子３の間の対応位置に配置する構成となっている。その際、図４（１）において点線で示すように、回路基板上に同じパターンを繰り返すことで、回路基板上に形成される電流ループの大きさを均一化できる。また、図４（２）に示すように、端子２，５は金属箔４上に戴置された半導体素子３毎に配置する構成であっても良い。その際、図４（１）と同様に、図４（２）において点線で示すように、回路基板１上に同じパターンを繰り返すことで、回路基板上に形成される電流ループの大きさを均一化できる。   Here, as shown in FIG. 4 (1), the terminals 2 and 5 are arranged at corresponding positions between the semiconductor elements 3 placed on the metal foil 4. At that time, as indicated by a dotted line in FIG. 4A, the same pattern is repeated on the circuit board, whereby the size of the current loop formed on the circuit board can be made uniform. Further, as shown in FIG. 4B, the terminals 2 and 5 may be arranged for each semiconductor element 3 placed on the metal foil 4. At that time, as shown in FIG. 4 (1), as shown by a dotted line in FIG. 4 (2), by repeating the same pattern on the circuit board 1, the size of the current loop formed on the circuit board is made uniform. Can be

このように、電流ループを複数設け且つ電流ループの大きさを均一化することで、回路基板１のインダクタンスと半導体素子３間のインダクタンスばらつきの低減を両立できる。これにより、跳ね上がり電圧による素子破壊の防止、半導体素子間の発熱や駆動速度のばらつき低減を実現でき、回路基板あたりに搭載できる半導体素子数を増加することができる。   In this way, by providing a plurality of current loops and making the size of the current loop uniform, it is possible to reduce both the inductance of the circuit board 1 and the inductance variation between the semiconductor elements 3. Accordingly, it is possible to prevent element destruction due to the jumping voltage, reduce heat generation between semiconductor elements and drive speed variation, and increase the number of semiconductor elements that can be mounted per circuit board.

図５は本実施形態に関する回路基板における金属箔の配置パターンの形状を示す図である。図５に示す構成例は、正極側端子２と負極側端子５毎に金属箔４の短辺方向にスリット３０を設け、スリット３０で区分けされた各金属箔上を流れる電流経路の形状を均一化させ、正極側端子２から金属箔上に流れる電流の形状を指定するものである。この構成例においては、電流経路の幅が狭まるためインダクタンスがやや増加するものの、スリット３０による区分け形状により、電流ループの大きさを均一にするとともに、電流ループの大きさを任意に変更することが可能となる。   FIG. 5 is a diagram showing the shape of the arrangement pattern of the metal foil on the circuit board according to this embodiment. In the configuration example shown in FIG. 5, slits 30 are provided in the short side direction of the metal foil 4 for each of the positive electrode side terminal 2 and the negative electrode side terminal 5, and the shape of the current path flowing on each metal foil divided by the slit 30 is uniform. The shape of the current flowing from the positive electrode side terminal 2 onto the metal foil is designated. In this configuration example, although the inductance is slightly increased because the width of the current path is narrowed, the size of the current loop can be made uniform and the size of the current loop can be arbitrarily changed by the partitioning shape by the slit 30. It becomes possible.

図６は本実施形態に係るパワー半導体モジュールの全体構成を示す図である。図６に示すように、パワー半導体モジュールは、回路基板１、回路基板１に戴置された半導体素子３、正極側端子２、負極側端子５、金属箔４，６，７、絶縁材８，９、モジュールケース１４、金属箔７に固設された放熱ベース１５、絶縁用ゲル１６、表面に絶縁処理を施した排熱用バスバー１７、から構成される。図６において、回路基板１の金属箔の積層数増加ともに増大する熱抵抗による発熱を低減するために、排熱用バスバー１７は半導体素子３の表面から外部に放熱するものである。   FIG. 6 is a diagram showing an overall configuration of the power semiconductor module according to the present embodiment. As shown in FIG. 6, the power semiconductor module includes a circuit board 1, a semiconductor element 3 placed on the circuit board 1, a positive terminal 2, a negative terminal 5, metal foils 4, 6, 7, an insulating material 8, 9, a module case 14, a heat dissipation base 15 fixed to the metal foil 7, an insulating gel 16, and an exhaust heat bus bar 17 whose surface is insulated. In FIG. 6, the exhaust heat bus bar 17 radiates heat from the surface of the semiconductor element 3 to reduce heat generation due to thermal resistance that increases with an increase in the number of laminated metal foils on the circuit board 1.

ここで、排熱用バスバー１７は直線状でなくて、波形や穴あき等のように表面積を増やす形状であってもよい。また、排熱用バスバー１７内に冷媒を封入し、冷媒の状態変化により冷却する構成であってもよい。その際、気化した冷媒は、半導体モジュール外部のバスバー表面で冷却し再度液化してもよい。   Here, the exhaust heat bus bar 17 is not linear, and may have a shape that increases the surface area, such as corrugated or perforated. Moreover, the structure which encloses a refrigerant | coolant in the bus bar 17 for waste heat, and cools by the state change of a refrigerant | coolant may be sufficient. At that time, the vaporized refrigerant may be cooled on the surface of the bus bar outside the semiconductor module and liquefied again.

図６においては、排熱用バスバー１７と半導体素子３を接続し排熱させる構成としたが、排熱用バスバー１７は、半導体素子３を直接冷却するだけでなく、半導体素子の上方で絶縁用ゲル１６を冷却することで半導体素子３を冷却する構成であってもよい。また、モジュールケース１４の内部に接着し、モジュールケース１４から半導体モジュール全体を冷却する構成であってもよい。   In FIG. 6, the exhaust heat bus bar 17 and the semiconductor element 3 are connected to exhaust heat. However, the exhaust heat bus bar 17 not only directly cools the semiconductor element 3, but also insulates above the semiconductor element. The structure which cools the semiconductor element 3 by cooling the gel 16 may be sufficient. Moreover, the structure which adhere | attaches inside the module case 14 and cools the whole semiconductor module from the module case 14 may be sufficient.

図７は本実施形態に係るパワー半導体モジュールに冷却機構を備えた電力変換装置を示す図である。図７に示す構成例は、図６に示すパワー半導体モジュールの放熱ベース１５に冷却用フィン１８を取り付けた電力変換装置である。図７の構成例では、冷却用フィン１８にヒートパイプ状の放熱器１９を取り付け、放熱器１９の内部に冷媒を封入することで、冷媒の状態変化により半導体モジュールを冷却するものである。ヒートパイプ内の冷媒は、冷却用フィン１８で暖められて上昇し、外気で冷却されて下降する。この冷却によって、金属箔と絶縁材を積層させた構成である回路基板１の発熱を低減することができる。また、ヒートパイプ状の放熱器１９は、凹凸を設けて冷却性能を向上させた構成であっても良い。   FIG. 7 is a diagram showing a power conversion device provided with a cooling mechanism in the power semiconductor module according to the present embodiment. The configuration example shown in FIG. 7 is a power conversion device in which cooling fins 18 are attached to the heat dissipation base 15 of the power semiconductor module shown in FIG. In the configuration example of FIG. 7, a heat pipe-like radiator 19 is attached to the cooling fin 18, and the refrigerant is sealed inside the radiator 19, thereby cooling the semiconductor module due to a change in the state of the refrigerant. The refrigerant in the heat pipe is warmed and raised by the cooling fins 18 and cooled by the outside air and lowered. By this cooling, the heat generation of the circuit board 1 having a configuration in which the metal foil and the insulating material are laminated can be reduced. Further, the heat pipe-shaped radiator 19 may have a configuration in which the cooling performance is improved by providing irregularities.

図７においては、冷却用フィン１８に対して、冷媒を封入したヒートパイプ状放熱器１９を設ける構成としたが、冷却用フィン１８自体を冷媒に浸ける構成であっても良い。その際、フィンによって暖められ気化した冷媒は、フィンと冷媒を収めるケースの表面で液化し、再度フィンを冷却することで冷却性能を向上させることができる。   In FIG. 7, the cooling fin 18 is provided with the heat pipe-shaped radiator 19 enclosing the refrigerant, but the cooling fin 18 itself may be immersed in the refrigerant. At that time, the refrigerant heated and vaporized by the fins can be liquefied on the surface of the case containing the fins and the refrigerant, and the cooling performance can be improved by cooling the fins again.

図８は本実施形態に係るパワー半導体モジュールに他の冷却機構を備えた電力変換装置を示す図である。図８に示す構成例は、図７に示す電力変換装置の冷却用フィン１８を接続パイプ２１を介して外部冷却器２０（冷却器としてそれ自体で独立した冷却機能を有したものである）を取り付けた電力変換装置である。図８の構成例では、冷却用フィン１８と外部冷却器２０を直接接続することによって、半導体モジュールの冷却性能を向上させ、金属箔と絶縁材を積層させた回路基板１の熱を除熱させることができる。なお、図８において、ヒートパイプ状放熱器９は必須の構成要素でなくてもよい。   FIG. 8 is a diagram showing a power conversion device provided with another cooling mechanism in the power semiconductor module according to the present embodiment. In the configuration example shown in FIG. 8, the cooling fin 18 of the power conversion device shown in FIG. 7 is connected to the external cooler 20 (with a cooling function independent of itself as a cooler) via the connection pipe 21. It is the attached power converter. In the configuration example of FIG. 8, the cooling performance of the semiconductor module is improved by directly connecting the cooling fins 18 and the external cooler 20, and the heat of the circuit board 1 in which the metal foil and the insulating material are laminated is removed. be able to. In FIG. 8, the heat pipe radiator 9 may not be an essential component.

ここで、接続パイプ２１は一つではなく複数設ける構成であってもよく、さらに、その形状は円筒状に限らず、凹凸を設け冷却性能を向上させた構成であっても良い。また、接続パイプ２１内に空気だけでなく冷媒を含ませることによって、冷媒の状態変化で半導体モジュールを冷却する構成であってもよく、その際、気化した冷媒は、接続パイプ表面で冷却し再度液化することで冷却を実現する。さらに、冷却用フィン１８と外部冷却器２０との間に、接続パイプ２１を設けなくても、両者間の空間を覆って外部冷却器２０による冷却機能を外部に漏らすこと無く冷却用フィン１８に伝える構造であってもよい。   Here, a configuration in which a plurality of connection pipes 21 are provided instead of one may be provided, and the shape is not limited to a cylindrical shape, and a configuration in which unevenness is provided and cooling performance is improved may be employed. In addition, the semiconductor module may be cooled by changing the state of the refrigerant by including not only air but also a refrigerant in the connection pipe 21, and in this case, the vaporized refrigerant is cooled on the surface of the connection pipe and then again. Cooling is realized by liquefying. Further, even if the connection pipe 21 is not provided between the cooling fin 18 and the external cooler 20, the cooling fin 18 is covered without covering the space between the two without leaking the cooling function of the external cooler 20 to the outside. It may be a structure to convey.

以上のように、本発明の実施形態では、図１に示すような、２ｉｎ１の構成のモジュール（１つのモジュール内に上下アーム直列回路を含む構成）を例に説明したが、１モジュール内に１個のスイッチ部を搭載した１ｉｎ１の構成のモジュールや、１モジュール内に６個のスイッチ部を搭載した６ｉｎ１の構成のモジュールであっても良い。さらに、本発明は、上述した実施形態に限定されるものではなく、本発明の技術的思想の範囲内に属する種々の構成例が含まれることは言うまでもない。   As described above, in the embodiment of the present invention, a module having a 2 in 1 configuration (a configuration including an upper and lower arm series circuit in one module) as illustrated in FIG. 1 has been described as an example. A module having a 1 in 1 configuration in which a single switch unit is mounted, or a module having a 6 in 1 configuration in which six switch units are mounted in one module may be used. Furthermore, the present invention is not limited to the above-described embodiments, and it goes without saying that various configuration examples belonging to the scope of the technical idea of the present invention are included.

１ 回路基板
２ 正極側端子
３ 半導体素子
４ 半導体素子及び正極側端子と電気的接続する金属箔
５ 負極側端子
６ 金属箔４及び負極側端子と電気的接続する金属箔
７ 回路基板と放熱ベースを接続する金属箔
８ 金属箔４と金属箔６を絶縁する絶縁材
９ 金属箔６と金属箔７を絶縁する絶縁材
１４ モジュールケース
１５ 放熱ベース
１６ 絶縁用ゲル
１７ 排熱用バスバー
１８ 冷却用フィン
１９ ヒートパイプ状放熱器
２０ 外部冷却器
２１ 冷却用フィンと外部冷却器の接続パイプ
３０ スリットDESCRIPTION OF SYMBOLS 1 Circuit board 2 Positive electrode side terminal 3 Semiconductor element 4 Metal foil electrically connected with a semiconductor element and a positive electrode side terminal 5 Negative electrode side terminal 6 Metal foil 4 and metal foil electrically connected with a negative electrode side terminal 7 Circuit board and heat dissipation base Metal foil to be connected 8 Insulating material for insulating the metal foil 4 and the metal foil 6 9 Insulating material for insulating the metal foil 6 and the metal foil 7 14 Module case 15 Radiation base 16 Insulating gel 17 Waste heat bus bar 18 Cooling fin 19 Heat pipe radiator 20 External cooler 21 Connection pipe for cooling fin and external cooler 30 Slit

Claims (6)

少なくとも２層の絶縁層と２層の金属層とを有し、当該金属層間に当該絶縁層を介在させて積層構造とした矩形状の回路基板と、正極電流を流す正極側端子と、負極電流を流す負極側端子と、前記金属層の内で上層の金属層に載置された半導体素子と、を備えたパワー半導体モジュールであって、
前記上層の金属層は、前記半導体素子に加えて前記正極側端子と電気的に接続されると共に、当該上層の金属層の下に配置された下層の金属層と電気的に接続され、
前記下層の金属層は、前記負極側端子と電気的に接続され、
前記正極側端子と前記負極側端子とは、前記回路基板上で近接した位置で対として前記回路基板の長辺方向に沿って複数設置され、
前記上層の金属層は、前記回路基板の長辺方向の一端部から他端部に亘って延びる矩形状の金属箔を前記回路基板の短辺方向に複数並列して形成されており、
前記半導体素子は、スイッチング素子とダイオードとから成ると共に、複数の前記金属箔のうち少なくともいずれかにおいて、その長辺方向に沿って複数並列して配置され、
前記正極側端子及び前記負極側端子の対と当該対に対応する前記半導体素子とは、前記回路基板の短辺方向に沿ったパターンを形成して前記回路基板の長辺方向に沿って複数並列実装され、
前記パターンは、前記回路基板の短辺方向に沿って複数並列配置された前記半導体素子によって成る列を２列含み、かつ前記正極側端子及び前記負極側端子の対が前記列同士の中間位置に対応する位置に設けられており、
前記複数設置された前記正極側端子及び前記負極側端子の対のそれぞれと当該対に対応する前記半導体素子とを通る電流経路は、前記回路基板の短辺方向に沿って形成され、かつ互いに略同一の長さを有する
ことを特徴とするパワー半導体モジュール。 A rectangular circuit board having a laminated structure having at least two insulating layers and two metal layers, with the insulating layer interposed between the metal layers, a positive terminal for passing a positive current, and a negative current A power semiconductor module comprising: a negative electrode side terminal through which a current flows; and a semiconductor element mounted on an upper metal layer among the metal layers,
The upper metal layer is electrically connected to the positive terminal in addition to the semiconductor element, and is electrically connected to a lower metal layer disposed below the upper metal layer,
The lower metal layer is electrically connected to the negative terminal,
A plurality of the positive electrode side terminals and the negative electrode side terminals are installed along the long side direction of the circuit board as a pair at a position close to each other on the circuit board,
The upper metal layer is formed by paralleling a plurality of rectangular metal foils extending in the short side direction of the circuit board from one end part in the long side direction to the other end part of the circuit board,
The semiconductor element comprises a switching element and a diode, and in at least one of the plurality of metal foils, a plurality of the semiconductor elements are arranged in parallel along the long side direction,
A pair of the positive electrode side terminal and the negative electrode side terminal and the semiconductor element corresponding to the pair form a pattern along the short side direction of the circuit board, and a plurality of parallel arrangements along the long side direction of the circuit board Implemented,
The pattern includes two rows of the semiconductor elements arranged in parallel along the short side direction of the circuit board, and the pair of the positive terminal and the negative terminal is located at an intermediate position between the rows. It is provided at the corresponding position,
Current paths passing through each of the plurality of positive electrode side terminal and negative electrode side terminal pairs and the semiconductor element corresponding to the pair are formed along the short side direction of the circuit board and are substantially mutually A power semiconductor module having the same length. 請求項１記載のパワー半導体モジュールにおいて、
前記半導体素子は、シリコンカーバイト又はガリウムナイトライドを含むワイドギャップ半導体であり、シリコンよりも高速に遮断可能なデバイスである
ことを特徴とするパワー半導体モジュール。 The power semiconductor module according to claim 1,
The semiconductor element is a wide gap semiconductor containing silicon carbide or gallium nitride, and is a device that can be cut off at a higher speed than silicon. 請求項１又は２記載のパワー半導体モジュールにおいて、
前記半導体素子を載置した前記上層の金属層とは逆側の最下層の金属層に放熱ベースを取り付け、当該上層の金属層に載置された複数の当該半導体素子に接続された高熱伝導導体の排熱用バスバーを設けた
ことを特徴とするパワー半導体モジュール。 The power semiconductor module according to claim 1 or 2 ,
A heat-dissipating base is attached to the lowermost metal layer opposite to the upper metal layer on which the semiconductor element is placed, and a high thermal conductive conductor connected to the semiconductor elements placed on the upper metal layer A power semiconductor module provided with a waste heat bus bar. 請求項３記載のパワー半導体モジュールの前記放熱ベースに冷却用フィンを取り付けて成る
ことを特徴とする電力変換装置。 A power conversion device comprising a cooling fin attached to the heat dissipation base of the power semiconductor module according to claim 3 . 請求項４記載の電力変換装置において、
前記冷却用フィンに対して、冷媒を封入したヒートパイプ状放熱器を設置した
ことを特徴とする電力変換装置。 The power conversion device according to claim 4 , wherein
A power conversion device characterized in that a heat pipe-like radiator in which a refrigerant is sealed is installed for the cooling fin. 請求項５記載の電力変換装置において、
前記冷却用フィンに対して、独自に冷却機能を有した外部の冷却器を直接接続した
ことを特徴とする電力変換装置。 The power conversion device according to claim 5 , wherein
An electric power converter characterized by directly connecting an external cooler having a cooling function to the cooling fin.
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Publication number Priority date Publication date Assignee Title
JP6288301B2 (en) * 2014-11-28 2018-03-14 日産自動車株式会社 Half-bridge power semiconductor module and manufacturing method thereof
US10811329B2 (en) 2015-02-17 2020-10-20 Koninklijke Philips N.V. Ceramic substrate and method for producing a ceramic substrate
WO2017090281A1 (en) * 2015-11-25 2017-06-01 シャープ株式会社 Module substrate
US10008411B2 (en) 2016-12-15 2018-06-26 Infineon Technologies Ag Parallel plate waveguide for power circuits
US10410952B2 (en) 2016-12-15 2019-09-10 Infineon Technologies Ag Power semiconductor packages having a substrate with two or more metal layers and one or more polymer-based insulating layers for separating the metal layers
JP2019091804A (en) * 2017-11-15 2019-06-13 シャープ株式会社 Power semiconductor module and electronic equipment
WO2021117227A1 (en) * 2019-12-13 2021-06-17 三菱電機株式会社 Semiconductor device, semiconductor system, moving body, and method for manufacturing semiconductor device
JP2021177676A (en) * 2020-05-08 2021-11-11 株式会社日立製作所 Power conversion device

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11354955A (en) * 1998-06-11 1999-12-24 Mitsubishi Electric Corp Cooling structure for electronic equipment
JP3521757B2 (en) * 1998-09-08 2004-04-19 株式会社豊田自動織機 Semiconductor module electrode structure
JP3723869B2 (en) * 2001-03-30 2005-12-07 株式会社日立製作所 Semiconductor device
JP2004186504A (en) * 2002-12-04 2004-07-02 Hitachi Unisia Automotive Ltd Semiconductor device
JP4479365B2 (en) * 2004-06-14 2010-06-09 日産自動車株式会社 Semiconductor device
JP4946845B2 (en) * 2007-12-13 2012-06-06 株式会社豊田自動織機 Semiconductor device
JP5136343B2 (en) * 2008-10-02 2013-02-06 三菱電機株式会社 Semiconductor device
JP2011036015A (en) * 2009-07-31 2011-02-17 Daikin Industries Ltd Power converter
JP2011222707A (en) * 2010-04-08 2011-11-04 Mitsubishi Electric Corp Power semiconductor device
FR2974969B1 (en) * 2011-05-03 2014-03-14 Alstom Transport Sa DEVICE FOR ELECTRICALLY INTERCONNECTING AT LEAST ONE ELECTRONIC COMPONENT WITH AN ELECTRIC POWER SUPPLY COMPRISING MEANS FOR REDUCING AN LOOP INDUCTANCE BETWEEN THE FIRST AND SECOND TERMINALS
JP2013033812A (en) * 2011-08-01 2013-02-14 Fuji Electric Co Ltd Power semiconductor module

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7165072B2 (en) 2019-02-19 2022-11-02 トーヨーエイテック株式会社 Honing machine

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