JP6105720B2 - チップ間メモリインターフェース構造 - Google Patents

チップ間メモリインターフェース構造 Download PDF

Info

Publication number
JP6105720B2
JP6105720B2 JP2015515261A JP2015515261A JP6105720B2 JP 6105720 B2 JP6105720 B2 JP 6105720B2 JP 2015515261 A JP2015515261 A JP 2015515261A JP 2015515261 A JP2015515261 A JP 2015515261A JP 6105720 B2 JP6105720 B2 JP 6105720B2
Authority
JP
Japan
Prior art keywords
memory
physical address
address space
semiconductor die
die
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2015515261A
Other languages
English (en)
Japanese (ja)
Other versions
JP2015525398A (ja
JP2015525398A5 (enExample
Inventor
ジュンウォン・スー
デクスター・ティー・チュン
Original Assignee
クアルコム，インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by クアルコム，インコーポレイテッド filed Critical クアルコム，インコーポレイテッド
Publication of JP2015525398A publication Critical patent/JP2015525398A/ja
Publication of JP2015525398A5 publication Critical patent/JP2015525398A5/ja
Application granted granted Critical
Publication of JP6105720B2 publication Critical patent/JP6105720B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H10W90/00—
    • H10W70/60—
    • H10W74/00—
    • H10W90/722—
    • H10W90/724—
    • H10W90/754—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Semiconductor Memories (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP2015515261A 2012-06-01 2013-05-31 チップ間メモリインターフェース構造 Active JP6105720B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201261654156P 2012-06-01 2012-06-01
US61/654,156 2012-06-01
US13/752,427 2013-01-29
US13/752,427 US9448947B2 (en) 2012-06-01 2013-01-29 Inter-chip memory interface structure
PCT/US2013/043714 WO2013181603A2 (en) 2012-06-01 2013-05-31 Inter-chip memory interface structure

Publications (3)

Publication Number Publication Date
JP2015525398A JP2015525398A (ja) 2015-09-03
JP2015525398A5 JP2015525398A5 (enExample) 2016-12-08
JP6105720B2 true JP6105720B2 (ja) 2017-03-29

Family

ID=49671774

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015515261A Active JP6105720B2 (ja) 2012-06-01 2013-05-31 チップ間メモリインターフェース構造

Country Status (7)

Country Link
US (1) US9448947B2 (enExample)
EP (1) EP2856466B1 (enExample)
JP (1) JP6105720B2 (enExample)
KR (1) KR101748329B1 (enExample)
CN (1) CN104335279B (enExample)
IN (1) IN2014MN02115A (enExample)
WO (1) WO2013181603A2 (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102107147B1 (ko) * 2013-02-01 2020-05-26 삼성전자주식회사 패키지 온 패키지 장치
KR102144367B1 (ko) * 2013-10-22 2020-08-14 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
US9570142B2 (en) * 2015-05-18 2017-02-14 Micron Technology, Inc. Apparatus having dice to perorm refresh operations
US20170118140A1 (en) * 2015-10-21 2017-04-27 Mediatek Inc. Network switch having identical dies and interconnection network packaged in same package
KR102755934B1 (ko) 2016-10-04 2025-01-17 삼성전자 주식회사 무선 통신 장치 및 그 제어 방법
KR102400101B1 (ko) 2017-11-03 2022-05-19 삼성전자주식회사 Pop 반도체 패키지 및 그를 포함하는 전자 시스템
US10579557B2 (en) * 2018-01-16 2020-03-03 Advanced Micro Devices, Inc. Near-memory hardened compute blocks for configurable computing substrates
KR20190087893A (ko) * 2018-01-17 2019-07-25 삼성전자주식회사 클럭을 공유하는 반도체 패키지 및 전자 시스템
KR102674550B1 (ko) 2019-10-07 2024-06-13 삼성전자주식회사 온-다이 미러링 기능을 갖는 메모리 칩 및 그것을 테스트하는 방법
US11797229B2 (en) * 2020-07-02 2023-10-24 Micron Technology, Inc. Multiple register clock driver loaded memory subsystem

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5945886A (en) * 1996-09-20 1999-08-31 Sldram, Inc. High-speed bus structure for printed circuit boards
US7352602B2 (en) * 2005-12-30 2008-04-01 Micron Technology, Inc. Configurable inputs and outputs for memory stacking system and method
JP2008140220A (ja) 2006-12-04 2008-06-19 Nec Corp 半導体装置
US8120958B2 (en) * 2007-12-24 2012-02-21 Qimonda Ag Multi-die memory, apparatus and multi-die memory stack
US7701251B1 (en) 2008-03-06 2010-04-20 Xilinx, Inc. Methods and apparatus for implementing a stacked memory programmable integrated circuit system in package
US7944726B2 (en) 2008-09-30 2011-05-17 Intel Corporation Low power termination for memory modules
US20100174858A1 (en) 2009-01-05 2010-07-08 Taiwan Semiconductor Manufacturing Co., Ltd. Extra high bandwidth memory die stack
US8683164B2 (en) 2009-02-04 2014-03-25 Micron Technology, Inc. Stacked-die memory systems and methods for training stacked-die memory systems
US8713248B2 (en) * 2009-06-02 2014-04-29 Nokia Corporation Memory device and method for dynamic random access memory having serial interface and integral instruction buffer
US8296526B2 (en) * 2009-06-17 2012-10-23 Mediatek, Inc. Shared memory having multiple access configurations
US8604593B2 (en) * 2009-10-19 2013-12-10 Mosaid Technologies Incorporated Reconfiguring through silicon vias in stacked multi-die packages
US8472279B2 (en) * 2010-08-31 2013-06-25 Micron Technology, Inc. Channel skewing
US20120137090A1 (en) * 2010-11-29 2012-05-31 Sukalpa Biswas Programmable Interleave Select in Memory Controller
US8400808B2 (en) * 2010-12-16 2013-03-19 Micron Technology, Inc. Phase interpolators and push-pull buffers
JP2013058277A (ja) * 2011-09-07 2013-03-28 Renesas Electronics Corp 半導体装置
US20130159587A1 (en) * 2011-12-15 2013-06-20 Aaron Nygren Interconnect Redundancy for Multi-Interconnect Device

Also Published As

Publication number Publication date
US20130326188A1 (en) 2013-12-05
CN104335279A (zh) 2015-02-04
KR20150016605A (ko) 2015-02-12
IN2014MN02115A (enExample) 2015-09-11
EP2856466B1 (en) 2018-10-24
JP2015525398A (ja) 2015-09-03
CN104335279B (zh) 2017-08-15
WO2013181603A2 (en) 2013-12-05
US9448947B2 (en) 2016-09-20
KR101748329B1 (ko) 2017-06-16
WO2013181603A3 (en) 2014-02-27
EP2856466A2 (en) 2015-04-08

Similar Documents

Publication Publication Date Title
JP6105720B2 (ja) チップ間メモリインターフェース構造
CN104885212B (zh) 利用分区多跳网络的裸片堆叠装置
US10964682B2 (en) Data storage system using wafer-level packaging
US20220092016A1 (en) Off-package high density, high bandwidth memory access using optical links
US20100121994A1 (en) Stacked memory array
EP3901778B1 (en) Stacked memory device with end to end data bus inversion
US7639037B1 (en) Method and system for sizing flow control buffers
US11422887B2 (en) Techniques for non-deterministic operation of a stacked memory system
US7761668B2 (en) Processor architecture having multi-ported memory
US20190115058A1 (en) Apparatus and method of clock shaping for memory
CN118679520A (zh) 具有存储体之间的复用的存储器电路架构
US20150121000A1 (en) Independently selective tile group access with data structuring
US20250322876A1 (en) Split block array for 3d nand memory
US20240162189A1 (en) Active Interposers For Migration Of Packages
US20240321670A1 (en) Techniques For Transferring Heat From Electronic Devices Using Heatsinks
US20250130943A1 (en) Circuits And Methods For Exchanging Data Coherency Traffic Through Multiple Interfaces
US20230305708A1 (en) Interface for different internal and external memory io paths
US20240386102A1 (en) Circuits And Methods For Preventing Row Hammer Attacks To Memory Circuits
US12520495B2 (en) 3D NAND with IO contacts in isolation trench
US20250370621A2 (en) Interface layout for stacked memory architectures
US20240120302A1 (en) Techniques For Arranging Conductive Pads In Electronic Devices
US20240111703A1 (en) Techniques For Configuring Repeater Circuits In Active Interconnection Devices
KR20250026757A (ko) 동시 스위칭 출력을 위한 채널 라우팅
CN119181396A (zh) 用于具有裸片到裸片接口的半导体装置的系统及方法
CN121349910A (zh) 数据处理装置、方法以及电子设备

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20160509

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20160509

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20161019

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20161019

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20161117

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20161121

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20161219

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20170206

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20170302

R150 Certificate of patent or registration of utility model

Ref document number: 6105720

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250