JP6042424B2 - 集積回路用の応力認識設計 - Google Patents
集積回路用の応力認識設計 Download PDFInfo
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Description
本明細書に開示されている1つ以上の実施の形態は、集積回路(IC)に関する。より特定的には、1つ以上の実施の形態は、IC用の応力認識設計およびIC内での回路設計の応力認識実現に関する。
回路設計の規模は大きくなり続け、実施するためにより大規模な集積回路(IC)を必要とする。場合によっては、単一の大きなダイを用いて実施できる回路設計は、2つ以上のより小さいダイを含むICを用いて実現することができる。2つ以上のより小さいダイを含むICは「マルチダイIC」と呼ぶことができる。マルチダイICは一般に、互いに結合される2つ以上のダイを含み、単一のICパッケージ内に配置されることを特徴とする。回路設計は、単一のより大きいダイを用いる代わりに、複数のダイにわたって実施される。
本明細書に開示されている1つ以上の実施の形態は集積回路(IC)に関し、より特定的にはIC用の応力認識設計およびIC内の回路設計の応力認識実現に関する。
一部の実施の形態において、第2の区域は外側境界を包含することができる。
Claims (11)
- インターポーザおよび前記インターポーザ上に取付けられる第1のダイを含む集積回路(IC)に係わる回路設計の方法であって、前記方法は
前記インターポーザ(605)の応力誘起体をプロセッサを用いて特定することを備え、
前記応力誘起体は、前記インターポーザ上に取付けられる第1のダイの外縁によって規定されるダイ取付境界(605)であり、
前記ダイ取付境界内の内側境界(530)と前記ダイ取付境界の外にある外側境界(525)とによって規定される、インターポーザ内の立入り禁止区域(535)を前記プロセッサを用いて規定することと、
前記プロセッサを用いて、前記インターポーザ内の前記立入り禁止区域以外の少なくとも1つの区域(610、615、620)内にあるアクティブリソースを見つけることと、
前記アクティブリソースが前記ダイ取付境界から所定の距離内にあると判断したことに応答して、前記プロセッサを用いて、前記アクティブリソースと前記ダイ取付境界との間の距離を関数として前記アクティブリソースの動作特性を定めることとを備える、方法。 - 前記アクティブリソース用に応力認識タイミングモデルを用いることをさらに備える、請求項1に記載の方法。
- 前記プロセッサを用いて、前記アクティブリソース用の前記応力認識タイミングモデルに従い、IC内に実現されるプログラム可能回路設計のエレメントを、前記アクティブリソースに選択的に割当てることをさらに備える、請求項2に記載の方法。
- 選択的に割当てることは、前記プロセッサによって行なわれるプログラム可能回路設計のための配置動作または経路付け動作の際に行なわれる、請求項3に記載の方法。
- 前記アクティブリソースを用いる場合の前記回路設計のタイミングは臨界ではないとの前記プロセッサを用いた判断に応答して、回路設計のエレメントを実現するためにだけアクティブリソースを用いることをさらに備える、請求項4に記載の方法。
- 集積回路(IC)であって、
応力誘起構造(605)を含むインターポーザ(205、505)と、
前記インターポーザの表面上に取付けられる第1のダイ(210、510)とを備え、
前記応力誘起構造は、前記インターポーザ上の第1のダイの外縁によって規定されるダイ取付境界(605)であり、
前記インターポーザは
如何なるアクティブデバイスも含まない立入り禁止区域(535)を含み、前記立入り禁止区域は、前記インターポーザの外縁から所定の距離である前記ダイ取付境界外の外側境界(525)と、前記外側境界から所定の距離である前記ダイ取付境界内の内側境界(530)との間の領域を有する矩形のリングを含み、前記インターポーザはさらに
第1の領域(620)を含み、第1の領域内で前記立入り禁止区域によって囲まれた、正規化された量の応力によって特徴付けられ、さらに
第2の領域(610)を含み、前記第2の領域は前記立入り禁止区域および前記第1の領域に接し、前記第2の領域内で前記応力誘起構造によって誘起される、正規化されたよりも大きい量の応力によって特徴付けられ、前記インターポーザはさらに
前記インターポーザ内の前記第2の領域内に配置されるアクティブデバイスをさらに含み、
前記アクティブデバイスの動作特性は、前記アクティブデバイスと前記ダイ取付境界との間の距離を関数として、劣化する、集積回路(IC)。 - 前記第2の領域は、前記内側境界に接する、請求項6に記載のIC。
- 前記インターポーザはさらに、
前記立入り禁止区域の前記外側境界に接する前記インターポーザ内の第3の領域(615)を含み、前記第3の領域は、前記第3の領域内で前記応力誘起構造によって誘起される、正規化されたよりも大きい量の応力によって特徴付けられ、前記インターポーザはさらに、
前記インターポーザ内の前記第3の領域内に配置される、さらなるアクティブデバイスを含み、
前記さらなるアクティブデバイスの動作特性は、前記さらなるアクティブデバイスと前記ダイ取付境界との間の距離を関数として、劣化する、請求項6に記載のIC。 - 前記インターポーザの表面上の第2のダイ(215、515)をさらに備え、
前記第1のダイおよび第2のダイは所定の距離で隔離されて、前記第1のダイと前記第2のダイとの間で、インターポーザのチャネル(540)を露出させ、
前記立入り禁止区域は、前記第1のダイと前記第2のダイとの間の前記インターポーザの前記チャネルを含む、請求項6に記載のIC。 - 前記インターポーザ表面上の第2のダイ(215、515)をさらに備え、
前記ダイ取付境界(605)は、前記インターポーザ上の前記第1のダイおよび前記第2のダイの各々の外縁によって規定される、請求項6に記載のIC。 - 前記インターポーザの表面上に複数のダイを形成するインターポーザの表面上に少なくとも第2のダイをさらに備え、
前記立入り禁止区域の前記内側境界および前記外側境界の間の距離は、前記インターポーザの表面上の複数のダイの数に依存する、請求項6に記載のIC。
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US13/162,541 US8779553B2 (en) | 2011-06-16 | 2011-06-16 | Stress-aware design for integrated circuits comprising a stress inducing structure and keep out zone |
PCT/US2012/031299 WO2012173683A1 (en) | 2011-06-16 | 2012-03-29 | Stress-aware design for integrated circuits |
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US20120319248A1 (en) | 2012-12-20 |
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