JP6018773B2 - Semiconductor device manufacturing method and manufacturing apparatus - Google Patents

Description

  The present invention relates to a method and apparatus for manufacturing a semiconductor element using CMP processing.

  Chemical mechanical polishing (CMP) is used to realize a shallow trench isolation (STI) structure in a semiconductor element and to planarize an insulating film as an upper layer of a gate wiring or a metal wiring in the semiconductor element. This is a necessary technique (for example, see Patent Document 1).

In the CMP process for realizing the STI structure, as shown in FIG. 1A, the groove 103 is formed by etching leaving the element portion 102 on the main surface of the Si substrate 101, and then chemical vapor deposition ( A SiO ₂ film 104 which is an insulating film is formed by a CVD method or the like, and thereafter, the SiO ₂ film 104 having a step on the surface is polished by a CMP process. By such a process, an STI structure having a flat surface as shown in FIG. 1B is obtained.

Further, in the CMP process of the insulating film on the metal wiring layer, as shown in FIG. 2A, a wiring pattern made of the metal wiring layer 112 is formed on the substrate 111, and the groove 113 where the metal wiring layer 112 does not exist is formed. An SiO ₂ film 114 that is an insulating film is formed so as to fill the surface, and thereafter, the SiO ₂ 114 having a step on the surface is polished by CMP treatment. By such a process, a wiring pattern structure having a flat surface as shown in FIG. 2B is obtained.

  However, the polishing characteristics (for example, the polishing amount per unit time, that is, the thickness of the portion polished per unit time) of the CMP processing by the CMP apparatus is, for example, the ratio of the area of the region where the groove portion exists in the semiconductor element (the groove portion) Density) or an area ratio (active (AC) portion density) of a region where the element portion 102 (or the metal wiring layer 112 constituting the wiring pattern) exists. In general, as shown in FIG. 3A, a pattern ratio (also referred to as “local ratio”), which is a ratio of an area occupied by the element part (AC part) 102 to the area of the substrate 101 of the semiconductor element. 3 is high (that is, when the ratio of the area occupied by the STI portion (filled portion) that is the trench portion 103 in which the insulating film is embedded is low), as shown in FIG. Therefore, the amount of polishing by CMP processing for a predetermined time is reduced. On the other hand, as shown in FIG. 3C, when the pattern ratio of the semiconductor element is low (that is, when the ratio of the area occupied by the groove 103a is high), as shown in FIG. Polishing is facilitated, and the amount of polishing by CMP processing for a predetermined time increases. Note that the length D is the polishing in the processes of FIGS. 3A and 3B and the processes of FIGS. 3C and 3D when the CMP process is performed for the same time under the same conditions by the same CMP apparatus. Indicates the difference in quantity. Therefore, in order to make the film thickness of the insulating films 104 and 104a remaining on the AC portions 102 and 102a the same for each of the manufactured semiconductor elements (that is, the value of D is made close to 0), it depends on the pattern ratio. Therefore, it is necessary to adjust the CMP processing time.

  FIG. 4 shows the relationship between the pattern ratio and the amount of polishing by CMP treatment for a predetermined time, that is, the CMP polishing amount required to align the pattern ratio [%] and the predetermined film thickness in an actual product group. It is a figure which shows the result which showed the value. In FIG. 4, the result of the actual measurement value is shown by 14 points. In FIG. 4, a straight line 120 indicated by a solid line rising to the right is a straight line indicating a linear function that approximates the relationship between the pattern ratio and the polishing amount by the CMP process. In addition, the area between the straight lines 121 and 122 indicated by the broken lines rising to the right in FIG. 4 is an area showing the relationship between the pattern ratio and the polishing amount by the CMP process in consideration of variation. Therefore, if the pattern ratio calculated in advance, the straight line 120 in FIG. 4 and the predetermined time for performing the CMP process are used, it is possible to estimate the CMP process time required to obtain the target amount of polishing by the CMP process. it can.

JP2004-200580

  However, a dedicated analysis tool is required to calculate the pattern ratio of the semiconductor element to be polished, and it takes a long time to calculate the pattern ratio using the dedicated analysis tool. For this reason, there is a problem that the method of estimating the CMP processing time using the pattern ratio calculated in advance is not suitable for manufacturing a semiconductor device that allows only a short product development period.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor element manufacturing method and a manufacturing apparatus capable of easily and quickly determining the CMP processing time.

According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: determining a time for performing a CMP process using a CMP apparatus on a semiconductor element chip formed on a semiconductor substrate; and providing the CMP apparatus for the semiconductor element chip. Performing the CMP process used for the determined time for performing the CMP process. In the process for determining the time for performing the CMP process, the length of the long side of the semiconductor element chip and When the length of the short side is represented by L ₁ and L ₂ , the CMP value increases as the value of (L ₁ / L ₂ ) increases so that the polishing amount of the semiconductor element chip becomes a predetermined target value. The time for performing the processing is determined to be a long time.

In addition, a semiconductor device manufacturing apparatus according to the present invention includes a CMP apparatus that performs a CMP process and a control unit that causes the CMP apparatus to execute the CMP process, and the control unit is formed on a semiconductor substrate. A time for performing the CMP process using the CMP apparatus is determined for a semiconductor element chip, and the CMP process using the CMP apparatus for the semiconductor element chip is performed for the determined time for performing the CMP process. is executed, the time for performing the CMP process, the long side of the semiconductor element chip length and short length, respectively, when represented by L ₁ and L _2, the polishing amount of the semiconductor element chip is given As the value of (L ₁ / L ₂ ) increases, it is determined that the time is longer.

  According to the method for manufacturing a semiconductor element according to the present invention, it is possible to easily and quickly calculate the CMP processing time for setting the polishing amount to a predetermined target value, so that the time required for manufacturing the semiconductor element can be shortened. There is an effect that can be done.

  The semiconductor device manufacturing apparatus according to the present invention can easily and quickly calculate the CMP processing time for setting the polishing amount to a predetermined target value, thereby reducing the time required for manufacturing the semiconductor device. There is an effect that can be done.

(A) And (b) is a schematic longitudinal cross-sectional view which shows an example of CMP process. (A) And (b) is a schematic longitudinal cross-sectional view which shows the other example of CMP process. (A) And (b) is a schematic sectional drawing which shows the CMP process with respect to a semiconductor element with a high pattern ratio, (c) And (d) is a schematic with a CMP process with respect to a semiconductor element with a low pattern ratio. FIG. It is a figure which shows the relationship between a pattern ratio and the grinding | polishing amount by CMP process of predetermined time. 1 is a perspective view schematically showing a configuration of a CMP apparatus of a semiconductor device manufacturing apparatus according to an embodiment of the present invention. 3 is a flowchart schematically showing a method for manufacturing a semiconductor element according to an embodiment. 1 is a plan view schematically showing a plurality of semiconductor element chips to be polished. It is a figure which shows the relationship between chip size ratio and the grinding | polishing amount by CMP processing of predetermined time. 3 is a flowchart schematically showing a method for manufacturing a semiconductor element according to an embodiment.

  FIG. 5 is a perspective view schematically showing a configuration of a CMP apparatus 130 which is a part of the semiconductor element manufacturing apparatus according to the embodiment of the present invention. The CMP apparatus 130 shown in FIG. 5 repairs unevenness on the surface of the pad 132, a head 131 that holds the semiconductor wafer 10, a platen 133 that includes a polishing pad 132, a slurry supply unit 134 that supplies the slurry, and the pad 132. The pad conditioner 135 is provided.

  For example, “MIRRA (trade name)” manufactured by Applied Materials can be used as the CMP apparatus 130. The rotation speed of the platen 133 is, for example, 38 rpm, the rotation speed of the head 131 is, for example, 58 rpm, and the head portion pressure (force that presses the wafer stuck to the head 131 against the pad 132) is, for example, 3 psi. The slurry flow rate is, for example, 120 ml / min. The type of slurry is, for example, a silica-based material, the conditioner is, for example, with diamond abrasive grains, and the polishing rate is 200 to 300 nm / min (equivalent to an oxide film).

FIG. 6 is a block diagram schematically showing the configuration of the semiconductor device manufacturing apparatus according to the embodiment of the present invention. The semiconductor device manufacturing apparatus shown in FIG. 6 includes a CMP apparatus 130, a control section 140 that controls the CMP apparatus 130, and an input section 150 into which instructions and data are input by a user. For example, the control unit 140 determines the CMP processing time required to obtain a predetermined polishing amount from the chip sizes L ₁ and L ₂ input from the input unit 150, and only the time determined by the CMP apparatus 130. A CMP process is executed.

FIG. 7 is a plan view schematically showing a plurality of semiconductor element chips to be polished. As shown in FIG. 7, a plurality of semiconductor element chips (product chips) 11 to be polished are formed on a semiconductor wafer as a semiconductor substrate. For example, the chip size of the long side _{L 1} is, 18.55Mm, the chip size of the short side _{L 2} may be a 1.24 mm. Incidentally, the long sides _{L 1} is about 15 to 20 mm, a short side _{L 2} is, if the semiconductor element chip of about 0.8 to 2 mm, can be applied. FIG. 8 shows the chip size ratio (L ₁ / L ₂ ) in FIG. 7 and the polishing amount [時間] (CMP polishing time) required to align the film thickness of the insulating film on the AC portion with the target value. It is a plot of the measured values of the relationship. As can be seen from the solid line 160 indicating the tendency of the plot in FIG. 8, the polishing amount [Å] (this is necessary to align the chip size ratio (L ₁ / L ₂ ) and the film thickness of the insulating film to the target values. It can be seen that the value is proportional to the polishing time).

  For example, a semiconductor wafer is a Si substrate, and a semiconductor element chip to be subjected to a CMP process using a CMP apparatus includes an active (AC) portion made of Si, a groove portion that separates the AC portion, an AC portion, And an insulating film covering the groove. The surface shape of the semiconductor element chip 11 before the CMP process is, for example, a shape as shown in FIG. 1A, and the surface shape of the semiconductor element chip 11 after the CMP process is, for example, as shown in FIG. Shape.

  Further, the semiconductor element chip to be subjected to the CMP process using the CMP apparatus may be a structure including a wiring pattern and an insulating film covering the wiring pattern. The surface shape of the semiconductor element chip (11 in FIG. 7) before the CMP process is, for example, the shape as shown in FIG. 2A, and the surface shape of the semiconductor element chip (11 in FIG. 7) after the CMP process is For example, the shape is as shown in FIG.

FIG. 8 is a diagram showing the relationship between the chip size ratio and the amount of processing (polishing amount) in CMP necessary to achieve a predetermined film thickness. FIG. 8 shows a chip of a liquid crystal driver, in which the chip size ratio (L ₁ / L ₂ ) and the AC part when the long side chip size is L ₁ and the short side chip size is L _2. The measured values of the relationship between the polishing amount [Å] of the upper insulating film thickness (which is proportional to the CMP processing time when the same CMP apparatus is used under the same conditions) are plotted. As can be seen from the solid line 160 indicating the tendency of the plot in FIG. 8, the polishing amount [Å] (this is necessary to align the chip size ratio (L ₁ / L ₂ ) and the film thickness of the insulating film to the target values. It can be seen that the value is proportional to the polishing time). As a straight line indicating the proportional relationship, another straight line passing through the area between the broken straight lines 161 and 162 in FIG. 8 may be employed.

  FIG. 9 is a flowchart schematically showing a method for manufacturing a semiconductor device according to the embodiment. As shown in FIG. 9, a semiconductor device is manufactured by a wafer manufacturing process (step S1) for manufacturing a wafer by slicing from silicon, a process for forming a circuit pattern, an insulating film, or the like using a photolithography technique (step S2). ), A CMP process (step S3) which is a characteristic part of the present invention, and a device manufacturing process (step S4) such as cutting a wafer into chips.

The CMP step (step S3) includes a step of determining a time for performing the CMP process using the CMP apparatus on the semiconductor element chip formed on the semiconductor substrate, and a CMP process using the CMP apparatus for the semiconductor element chip. And a step of performing only for a determined time. In the step of determining the time for performing the CMP process, as shown in FIG. 7, when the length of the long side and the length of the short side of the semiconductor element chip are respectively represented by L ₁ and L ₂ , FIG. As indicated by the straight line 160, the polishing time (reference polishing amount) required for the CMP process increases as the value of the chip size ratio (L ₁ / L ₂ ) increases. Therefore, in order to align the polishing amount to a predetermined target value, it is effective to determine the CMP processing time as a longer time as the value of the chip size ratio (L ₁ / L ₂ ) increases.

Specifically, in the step of determining the time for performing the CMP process, the chip size ratio (L ₁ / L ₂ ) is X, and the estimated value of the polishing amount of the semiconductor element chip by the CMP process using the CMP apparatus is calculated. When Y (Å)
Y = a ₁ X + a ₂ (a ₁ and a ₂ are positive values)
The time T [second] for performing the CMP process is obtained by dividing the estimated value Y [Å] by the polishing amount Z [Å / second] per unit time in CMP.

  As described above, according to the method for manufacturing a semiconductor device according to the present embodiment, it is not necessary to calculate the pattern ratio, and the time for the CMP process for setting the polishing amount to a predetermined target value can be calculated easily and quickly. Therefore, the time required for manufacturing the semiconductor element can be shortened.

  Further, if the semiconductor element manufacturing apparatus according to the present embodiment is used, the calculation of the pattern ratio becomes unnecessary, and the time for the CMP process for setting the polishing amount to the predetermined target value can be easily and quickly calculated. The period required for manufacturing the semiconductor element can be shortened.

  Furthermore, since the chip size is determined at the mask ordering stage necessary for the trial production, it is possible to predict the polishing time before the trial production, which is the biggest concern.

DESCRIPTION OF SYMBOLS 10 Semiconductor wafer, 11 Semiconductor element chip, 130 CMP apparatus, 131 head, 132 pad, 133 platen, 134 Slurry supply part, 135 Pad conditioner, 140 Control part, 150 Input part

Claims (6)

Determining a time for performing a CMP process using a CMP apparatus on a semiconductor element chip formed on a semiconductor substrate;
Performing the CMP process using the CMP apparatus on the semiconductor element chip for the determined time for performing the CMP process.
In said step of determining the time for the CMP process, the long side of the semiconductor element chip length and short length, respectively, when represented by L ₁ and L _2, the polishing amount of the semiconductor element chip The semiconductor device manufacturing method is characterized in that, as the value of the chip size ratio (L ₁ / L ₂ ) is increased, the time for performing the CMP process is determined to be a longer time so that becomes a predetermined target value. In the step of determining the time for performing the CMP process,
Let the chip size ratio (L ₁ / L ₂ ) be X,
When the estimated value of the polishing amount required for the semiconductor element chip by the CMP process using the CMP apparatus is Y,
Y = a ₁ X + a ₂ (a ₁ and a ₂ are positive values)
age,
The semiconductor element according to claim 1, wherein the time for performing the CMP process is obtained by dividing the estimated value Y by a polishing amount Z [Ｚ / sec] per unit time in CMP. Manufacturing method. The semiconductor substrate is a Si substrate;
The semiconductor element chip to be subjected to the CMP process using the CMP apparatus includes an active portion made of Si, a groove portion that separates the active portion, and an insulating film that covers the active portion and the groove portion. The method for manufacturing a semiconductor device according to claim 1, wherein: The semiconductor substrate is a Si substrate;
The method of manufacturing a semiconductor element according to claim 1, wherein the semiconductor element chip on which the CMP process using the CMP apparatus is performed includes a wiring pattern and an insulating film covering the wiring pattern. . A CMP apparatus for performing a CMP process;
A control unit that causes the CMP apparatus to execute the CMP process;
The controller is
Determining a time for performing the CMP process using the CMP apparatus on the semiconductor element chip formed on the semiconductor substrate;
The CMP process using the CMP apparatus for the semiconductor element chip is executed for the determined time to perform the CMP process,
The time for the CMP process, the long side of the semiconductor element chip length and short length, respectively, when represented by L ₁ and L _2, the semiconductor device chip polishing amount is a predetermined target value of so that the chip size ratio _(L 1 _/ L ₂₎ values of the increases, apparatus for manufacturing a semiconductor device characterized by being determined to have long time. The controller is
Let the chip size ratio (L ₁ / L ₂ ) be X,
When the estimated value of the polishing amount required for the semiconductor element chip by the CMP process using the CMP apparatus is Y,
Y = a ₁ X + a ₂ (a ₁ and a ₂ are positive values)
age,
The semiconductor element according to claim 5, wherein the time for performing the CMP process is obtained by dividing the estimated value Y by a polishing amount Z [Å / second] per unit time in CMP. Manufacturing equipment.

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