CN108875098B - Modeling method and device for chemical mechanical polishing process of high-k metal gate - Google Patents
Modeling method and device for chemical mechanical polishing process of high-k metal gate Download PDFInfo
- Publication number
- CN108875098B CN108875098B CN201710325974.0A CN201710325974A CN108875098B CN 108875098 B CN108875098 B CN 108875098B CN 201710325974 A CN201710325974 A CN 201710325974A CN 108875098 B CN108875098 B CN 108875098B
- Authority
- CN
- China
- Prior art keywords
- grinding
- stage
- polishing
- chemical mechanical
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/20—Design optimisation, verification or simulation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The application discloses a modeling method and a device for a chemical mechanical polishing process of a high-k metal gate. The modeling method and device comprise the following steps: and fusing the surface appearance of the interlayer dielectric layer after grinding into a metal gate modeling process, and establishing a chemical mechanical grinding process simulation model of the metal gate. Therefore, the modeling method considers the influence of the surface topography of the lower layer structure (namely the interlayer dielectric layer) of the high-k metal gate device on the surface topography of the upper layer structure (namely the metal gate) so as to more accurately and reliably simulate the chemical mechanical polishing process of the high-k metal gate.
Description
Technical Field
The application relates to the technical field of integrated circuit manufacturing processes, in particular to a modeling method and device for a chemical mechanical polishing process of a high-k metal gate.
Background
Entering a 28 nanometer technology node, a high-k metal gate (HKMG) is taken as a main process technology to continue the Moore's law. Although the 14 nm node industry widely adopts a three-dimensional FinFET device structure to reduce power consumption and area, so as to replace a planar device structure, HKMG still plays different roles at different nodes and different stages.
At present, the HKMG device structure of the "gate last" process is mainly adopted in the industry, mainly because the "gate last" process does not need to be subjected to a high temperature step, and the work function value of the gate electrode material can be set and adjusted more freely, so that the stability and reliability of the chip are higher. However, the "gate last" process faces more process difficulties and design limitations, the flatness of the metal surface is very difficult to reach, and incomplete polishing in the Chemical Mechanical Polishing (CMP) step will result in the metal not being removed cleanly, thereby causing short circuit; while over-polishing can result in a thinner gate electrode, resulting in an excessively high gate resistance and potential contact over-etching. In addition, severe overpolishing can result in exposure of adjacent source/drain regions, which can be attacked during subsequent dummy gate etch removal.
Therefore, in the manufacturing process of the HKMG device structure, the process control of CMP is vital, and a scientific, reasonable, accurate and reliable CMP process model can help a process engineer to strictly control process conditions, reduce the difficulty of parameter optimization, and reduce dishing and erosion after grinding as much as possible, so that the flatness of the surface of the metal gate meets the requirement of the photoetching focusing depth level. Meanwhile, the manufacturability design of different graph structures can lead the layout designer to predict hot spot areas possibly appearing in the actual process manufacturing process in advance, and provide modification suggestions for the designer, thereby reducing the flow sheet risk and improving the success rate of the primary flow sheet.
Disclosure of Invention
In view of the above, the present application provides a modeling method and apparatus for a chemical mechanical polishing process of a high-k metal gate to establish an accurate CMP process simulation model of the high-k metal gate.
In order to achieve the purpose of the invention, the following technical scheme is adopted in the application:
a modeling method for a high-k metal gate chemical mechanical polishing process is characterized in that the high-k metal gate chemical mechanical polishing process comprises the following steps: an interlayer dielectric layer chemical mechanical grinding process and a metal gate chemical mechanical grinding process;
the modeling method comprises the following steps:
modeling the chemical mechanical polishing process of the interlayer dielectric layer to obtain a chemical mechanical polishing process simulation model of the interlayer dielectric layer;
calculating the surface morphology of the interlayer dielectric layer after grinding by utilizing the chemical mechanical grinding process simulation model of the interlayer dielectric layer;
and fusing the surface appearance of the interlayer dielectric layer after grinding into a metal gate modeling process, and establishing a chemical mechanical grinding process simulation model of the metal gate.
Optionally, the interlayer dielectric layer grinding process comprises a first grinding stage and a second grinding stage, wherein the first grinding stage grinds the oxide layer and the silicon nitride layer, and the second grinding stage grinds the oxide layer, the silicon nitride layer, the barrier layer and the polysilicon layer;
the modeling of the chemical mechanical polishing process of the interlayer dielectric layer to obtain the chemical mechanical polishing process simulation model of the interlayer dielectric layer specifically comprises the following steps:
modeling the chemical mechanical polishing process in the first polishing stage to obtain a chemical mechanical polishing process simulation model in the first polishing stage;
calculating the appearance of the ending surface of the first grinding stage by utilizing the chemical mechanical grinding process simulation model of the first grinding stage;
and establishing a chemical mechanical polishing process simulation model of the second polishing stage by taking the finishing surface topography of the first polishing stage as the initial surface topography of the second polishing stage.
Optionally, calculating a finish surface morphology of the interlayer dielectric layer after polishing by using the interlayer dielectric layer chemical mechanical polishing process simulation model, specifically including:
and calculating the finishing surface morphology of the second grinding stage by using the chemical mechanical grinding process simulation model of the second grinding stage, wherein the finishing surface morphology of the second grinding stage is the finishing surface morphology of the interlayer dielectric layer after grinding.
Optionally, the step of establishing a chemical mechanical polishing process simulation model of the second polishing stage by using the ending surface topography of the first polishing stage as the initial surface topography of the second polishing stage specifically includes:
and taking the silicon nitride layer, the barrier layer and the polycrystalline silicon layer which are ground in the second grinding stage as the same material layer, taking the oxide layer which is ground in the second grinding stage as another material layer, taking the finishing surface appearance of the first grinding stage as the initial surface appearance of the second grinding stage, and establishing a chemical mechanical grinding process simulation model of the second grinding stage.
Optionally, the chemical mechanical polishing process simulation model of the first polishing stage and the chemical mechanical polishing process simulation model of the second polishing stage respectively include a dish model and an erosion model.
Optionally, the disc model of the first grinding stage specifically includes:
the surface erosion model of the first grinding stage is specifically:
wherein, KOxIs the Priston factor, K, of the oxide layer of the first polishing stageNiIs the Priston factor, P, of the silicon nitride layer of the first polishing stage0The initial pressure of the polishing pad on the chip at the beginning of the first polishing stage, k is the hardness of the polishing pad, α is the deformation factor of the polishing pad, w is the line width corresponding to the oxide layer of the first polishing stage, s is the distance corresponding to the silicon nitride layer of the first polishing stage, L is the pitch of the first polishing stage, L is w + s, Y isNi(0) Is the initial height of the silicon nitride layer in the first polishing stage, YOx(0) The initial height of the oxide layer in the first polishing stage, v is the relative sliding speed of the polishing pad to the wafer, and t is the polishing time in the first polishing stage.
Optionally, the calculating the final surface morphology of the second polishing stage by using the chemical mechanical polishing process simulation model of the second polishing stage specifically includes:
calculating the final surface dishing ILD2 after the second polishing stage polishing using the surface dishing model for the second polishing stagedishing；
Calculating the final surface erosion ILD2 after the second grinding stage grinding using the surface erosion model of the second grinding stageero；
Dishing of ILD2 according to the polished termination surface of the second polishing stagedishingAnd the ILD for stopping surface erosion after the second grinding stage grinding2eroAnd calculating the surface disc curve R after the second grinding stage grinding by a pre-established coordinate systemdishing(ii) a The dish-shaped curve of the surface ground in the second grinding stage is the appearance of the finishing surface of the second grinding stage;
the direction of the X axis of the pre-established coordinate system is the direction of measuring the line width of the oxide layer, and the direction of the Y axis is the direction perpendicular to the line width of the measured oxide layer.
Optionally, the post-polishing stop surface dishing ILD2 according to the second polishing stagedishingAnd the etch stop surface ILD2 after the second grinding stage grindingeroAnd calculating the surface disc curve R after the second grinding stage grinding by a pre-established coordinate systemdishingThe method specifically comprises the following steps:
calculating the surface disc curve R after the second grinding stage grinding according to the following formuladishing：
Wherein L is a pitch, L is w + s, w is a line width corresponding to the oxide layer, and s is a distance corresponding to the silicon nitride layer; x0 is the abscissa of the line width starting point of the oxide layer, and ρ is the pattern density.
A modeling device for a chemical mechanical polishing process of a high-k metal gate comprises the following steps: an interlayer dielectric layer chemical mechanical grinding process and a metal gate chemical mechanical grinding process;
the modeling apparatus includes:
the interlayer dielectric layer modeling unit is used for modeling the interlayer dielectric layer chemical mechanical polishing process to obtain a chemical mechanical polishing process simulation model of the interlayer dielectric layer;
the calculation unit is used for calculating the surface morphology of the polished interlayer dielectric layer after the interlayer dielectric layer is polished by utilizing the chemical mechanical polishing process simulation model of the interlayer dielectric layer;
and the metal gate modeling unit is used for integrating the surface morphology of the interlayer dielectric layer after grinding into the metal gate modeling process and establishing a chemical mechanical grinding process simulation model of the metal gate.
Optionally, the interlayer dielectric layer grinding process comprises a first grinding stage and a second grinding stage, wherein the first grinding stage grinds the oxide layer and the silicon nitride layer, and the second grinding stage grinds the oxide layer, the silicon nitride layer, the barrier layer and the polysilicon layer;
the interlayer dielectric layer modeling unit specifically comprises:
the first modeling subunit is used for modeling the chemical mechanical polishing process in the first polishing stage to obtain a chemical mechanical polishing process simulation model in the first polishing stage;
the calculation subunit is used for calculating the appearance of the ending surface of the first grinding stage by using the chemical mechanical grinding process simulation model of the first grinding stage;
and the second modeling subunit is used for establishing a chemical mechanical polishing process simulation model of the second polishing stage by taking the finishing surface topography of the first polishing stage as the initial surface topography of the second polishing stage.
Optionally, the computing unit specifically includes:
and calculating the finishing surface morphology of the second grinding stage by using the chemical mechanical grinding process simulation model of the second grinding stage, wherein the finishing surface morphology of the second grinding stage is the finishing surface morphology of the interlayer dielectric layer after grinding.
Compared with the prior art, the method has the following beneficial effects:
according to the modeling method of the chemical mechanical polishing process of the high-k metal gate, the surface appearance of the termination surface after the interlayer dielectric layer is polished is integrated into the metal gate modeling process, and the chemical mechanical polishing process of the metal gate is modeled. Therefore, the modeling method considers the influence of the surface topography of the lower layer structure (namely the interlayer dielectric layer) of the high-k metal gate device on the surface topography of the upper layer structure (namely the metal gate) so as to more accurately and reliably simulate the chemical mechanical polishing process of the high-k metal gate, therefore, the modeling method considers the lamination effect of the surface topography of the high-k metal gate, and the simulation model of the chemical mechanical polishing process of the high-k metal gate obtained by the modeling method can more accurately reflect the real process of the chemical mechanical polishing of the high-k metal gate, can more accurately simulate the real-time change of the surface topography of a chip and the surface defect of graph dependence, and has guiding significance for the optimization of the chemical mechanical polishing process of the high-k metal gate and the layout design optimization.
Drawings
In order that the detailed description of the present application may be clearly understood, a brief description of the drawings that will be used when describing the detailed description of the present application will be provided.
FIG. 1 is a schematic diagram of a wafer structure to be ground after an interlevel dielectric layer deposition process;
FIG. 2 is a schematic diagram of a chip structure after CMP of an interlayer dielectric layer under ideal conditions;
FIG. 3 is a schematic diagram of a chip structure before polishing in a metal gate CMP process;
FIG. 4 is a schematic flow chart of a modeling method of the HKMG chemical mechanical polishing process provided by the embodiment of the application;
FIG. 5 is a flowchart illustrating an embodiment of the step S41 according to the present invention;
FIG. 6 is a schematic diagram of a corresponding disc-shaped curved surface after a chemical mechanical polishing process for an interlayer dielectric layer according to an embodiment of the present disclosure;
FIG. 7 is a flow chart illustrating a method for calculating a dishing curve of a polished interlayer dielectric layer;
fig. 8 is a schematic structural diagram of a HKMG chemical mechanical polishing process modeling apparatus provided in an embodiment of the present application.
Detailed Description
The following detailed description of specific embodiments of the present application is provided in conjunction with the accompanying drawings.
In the manufacturing process of the HKMG device structure, the manufacturing process comprises two CMP process steps, wherein one CMP process step is an interlayer dielectric (ILD) process step, and the other CMP process step is a metal gate CMP process step.
The structure of a chip requiring polishing in the interlayer dielectric layer CMP process is shown in fig. 1. As shown in fig. 1, the chip structure includes a dummy gate (the material of the dummy gate is generally polysilicon)11, an oxide layer 12, and a silicon nitride layer 13.
In an ideal situation, if the interlayer dielectric layer CMP process is set to have no defects such as surface dishing and erosion, the chip structure after the interlayer dielectric layer CMP process is terminated is as shown in fig. 2, and the corresponding chip surface is a flat surface.
However, under the actual CMP process conditions, due to the different materials of the dummy gate 11, the oxide layer 12 and the silicon nitride layer 13, the corresponding CMP polishing rates are also different, and thus, the surface topography of the chip is fluctuated greatly due to the defect generated by the CMP polishing of the interlayer dielectric layer. After the planarization of the interlayer dielectric layer is completed and before the metal gate CMP process is performed, the dummy gate 11 needs to be etched away, then a thin barrier layer 14 is deposited at the position of the original dummy gate 11, and then a metal 15 (the metal 15 is generally metal aluminum) is deposited on the barrier layer 14 and the planarized oxide layer 12, where the structural diagram of the chip formed at this time is shown in fig. 3. The chip structure shown in fig. 3 is the chip structure before the metal gate CMP process is performed.
As shown in fig. 3, since the metal 15 is deposited on the surface of the interlayer dielectric layer after the CMP process, the unevenness of the interlayer dielectric layer is transferred to the deposition process of the metal 15, and meanwhile, in the CMP process of the metal gate, the metal 15 on the oxide layer 12 needs to be completely ground and removed, so the unevenness of the surface of the interlayer dielectric layer after the CMP process also affects the surface topography of the metal gate, and therefore, the surface topography of the termination layer after the CMP process of the interlayer dielectric layer has a great effect on the deposition of the metal gate and the subsequent CMP process of the metal gate.
Therefore, in the process of metal gate CMP, the influence of the surface topography of the chip after the interlayer dielectric layer CMP on the surface topography of the chip after the metal gate CMP needs to be considered. Based on this, the present application provides a specific embodiment of a modeling method for HKMG chemical mechanical polishing process.
Fig. 4 is a schematic flow chart of a modeling method of the HKMG chemical mechanical polishing process according to an embodiment of the present application. As shown in fig. 4, the modeling method includes the steps of:
s41, modeling the chemical mechanical polishing process of the interlayer dielectric layer to obtain a chemical mechanical polishing process simulation model of the interlayer dielectric layer:
as shown in the chip structure of fig. 1, the first material ground by the interlayer dielectric layer CMP process only includes the oxide layer 12, and as the CMP grinding is performed, the thickness of the oxide layer 12 is gradually reduced until the oxide layer 12 located above the silicon nitride layer 13 is completely ground to expose the silicon nitride layer 13, at this time, the interlayer dielectric layer CMP process not only grinds the oxide layer 12 but also grinds the exposed silicon nitride layer 13, and then as the CMP grinding is performed, the silicon nitride layer 13 located above the dummy gate 11 is completely ground to expose the dummy gate 11, at this time, the CMP process of the interlayer dielectric layer not only grinds the oxide layer 12, the silicon nitride layer 13, and the dummy gate 11, and since the dummy gate 11 is made of polysilicon material, polysilicon needs to be ground at this stage.
The surface unevenness after CMP is caused by different polishing rates of different polishing materials. Therefore, in order to improve the precision of the interlayer dielectric layer CMP process model, the interlayer dielectric layer CMP grinding process is divided into different grinding stages according to different material layers ground in the interlayer dielectric layer CMP grinding process, and then CMP modeling is respectively carried out on the CMP processes in the different grinding stages.
However, when the CMP polished surface comprises only one material, the end surface can be approximated as a flat surface. However, since the initial stage of the inter-layer dielectric layer CMP only grinds one material of the oxide layer, the terminating surface is a flat surface which has no stack effect on the subsequent planarization process of the CMP process, the embodiment of the present application does not model the CMP at this stage alone. In order to improve the precision of a CMP process model, the interlayer lamination effect of the unevenness of the surface appearance of a plurality of layers is considered, the CMP grinding process of the interlayer dielectric layer is divided into a first grinding stage and a second grinding stage according to different material layers ground in the CMP grinding process of the interlayer dielectric layer, the oxide layer and the silicon nitride layer are ground in the first grinding stage, the oxide layer, the silicon nitride layer, the barrier layer and the polysilicon layer are ground in the second grinding stage, the CMP processes of the two grinding stages are respectively modeled, and when the CMP process of the second grinding stage is modeled, the initial surface appearance is the finishing surface appearance after the CMP process of the first grinding stage.
According to the above concept, as an embodiment of the present application, as shown in fig. 5, the step S41 may specifically include:
s411, modeling the chemical mechanical polishing process in the first polishing stage to obtain a chemical mechanical polishing process simulation model in the first polishing stage:
it should be noted that, since the CMP polished surface of the oxide layer before the first polishing stage is approximately a flat surface, which has no influence on the unevenness of the subsequent surface, in the embodiment of the present application, the initial surface of the CMP polishing process in the first polishing stage is considered to be a flat surface.
The step may specifically be: by combining the removal mechanism of the grinding materials (mainly comprising oxides and silicon nitride) in the first grinding stage and the experience of test chip design, data extraction and the like, modeling is performed on the chemical mechanical grinding process of the interlayer dielectric layer in the first grinding stage based on means such as contact mechanics theory, experimental verification and the like, so as to obtain a chemical mechanical grinding process simulation model in the first grinding stage.
It should be noted that, in the embodiment of the present application, the simulation model of the cmp process in the first polishing stage may include a dishing model, an erosion model, a silicon nitride layer thickness model, and an oxide layer thickness model.
In addition, since the polishing rate of silicon nitride is low and the polishing rate of oxide is high, as an example, the disk model of the first polishing stage can be shown by the following formula (1):
the erosion model for the first grinding stage can be shown as equation (2):
the formula for calculating the thickness of the silicon nitride layer in the first polishing stage can be shown as formula (3):
the calculation formula of the oxide layer thickness in the first polishing stage can be shown as formula (4):
wherein, KOxIs the Priston factor, K, of the oxide layer of the first polishing stageNiIs the Priston factor, P, of the silicon nitride layer of the first polishing stage0The initial pressure of the polishing pad on the wafer at the beginning of the first polishing stage, k is the hardness of the polishing pad, α is the deformation factor of the polishing pad, w is the line width corresponding to the oxide layer of the first polishing stage, s is the distance corresponding to the silicon nitride layer of the first polishing stage, L is the pitch, L is w + s, Y isNi(0) Is the initial height of the silicon nitride layer at the beginning of the first polishing stage, YOx(0) Is the initial height of the oxide layer at the beginning of the first polishing stage, v is the relative sliding velocity of the polishing pad to the wafer, and t is the polishing time of the first polishing stage.
S412, calculating the final surface topography of the first grinding stage by using the chemical mechanical grinding process simulation model of the first grinding stage:
as an example, this step may calculate the dishing, erosion, silicon nitride layer thickness, and oxide layer thickness of the termination surface of the first polishing stage using a dishing model, an erosion model, a silicon nitride layer thickness model, and an oxide layer thickness model, respectively.
S413, establishing a chemical mechanical polishing process simulation model of the second polishing stage by taking the ending surface topography of the first polishing stage as the initial surface topography of the second polishing stage:
in the second grinding stage of the interlayer dielectric layer, the ground materials of the interlayer dielectric layer comprise oxide, silicon nitride, a barrier layer and polysilicon, and the grinding rates of the silicon nitride, the barrier layer and the polysilicon are greatly different from the grinding rate of the oxide, so that in order to simplify the modeling process of the chemical mechanical grinding process in the second grinding stage and simplify the simulation model of the chemical mechanical grinding process in the second grinding stage, the oxide can be used as one material when the chemical mechanical grinding process model in the second grinding stage is established, the other three materials, namely the silicon nitride, the barrier layer and the polysilicon, are used as another material, and for convenience of recording, the three materials, namely the silicon nitride, the barrier layer and the polysilicon, are collectively recorded as the polysilicon in the embodiment of the application.
It should be noted that, because the two materials are polished in the first polishing stage, the terminating surface of the first polishing stage is an uneven surface due to the difference in polishing rates of the two materials, and the uneven surface has an effect on the planarization of the interlayer dielectric layer in the second polishing stage, so that the terminating surface topography of the first polishing stage is used as the initial surface topography of the second polishing stage when the chemical mechanical polishing process simulation model of the second polishing stage is established.
Similar to the establishment process of the simulation model of the chemical mechanical polishing process in the first polishing stage, the steps may specifically be: and modeling the chemical mechanical polishing process of the interlayer dielectric layer in the second polishing stage by taking the final surface topography of the first polishing stage as the initial surface topography of the second polishing stage and combining the removal mechanism of the materials (mainly comprising oxide, silicon nitride, a barrier layer and polysilicon) polished in the stage and the experiences of test chip design, data extraction and the like based on means such as a contact mechanics theory, experimental verification and the like to obtain a chemical mechanical polishing process simulation model of the second polishing stage.
It should be noted that, in the embodiment of the present application, the simulation model of the cmp process in the second polishing stage may include a dishing model, an erosion model, a silicon nitride layer, a barrier layer and polysilicon thickness model, and an oxide layer thickness model.
Further, as an example, the disc model of the second grinding stage may be shown as the following formula (5):
the erosion model for the second grinding stage can be as shown in equation (6):
the calculation formula of the thicknesses of the silicon nitride layer, the barrier layer and the polysilicon in the second polishing stage can be shown as formula (7):
the calculation formula of the oxide layer thickness in the second polishing stage can be shown as formula (8):
wherein, KOxIs the Priston factor, K, of the oxide layer of the second polishing stagePolyIs the Prusson factor, P, of the polysilicon layer (the polysilicon layer is a general term for the silicon nitride layer, the barrier layer and the polysilicon layer) in the second polishing stage0The initial pressure of the polishing pad on the wafer at the beginning of the second polishing stage, k is the hardness of the polishing pad, α is the deformation factor of the polishing pad, w is the line width corresponding to the oxide layer of the second polishing stage, s is the distance corresponding to the polysilicon layer (the polysilicon layer is the general name of the silicon nitride layer, the barrier layer and the polysilicon) of the second polishing stage, L is the pitch, L is w + s, and Y isPoly(0) Is the initial height, Y, of the polysilicon layer (polysilicon is referred to herein as silicon nitride layer, barrier layer and polysilicon collectively) at the beginning of the second polishing stageOx(0) Is the initial height of the oxide layer at the beginning of the second polishing stage, v is the relative sliding velocity of the polishing pad to the wafer, and t is the polishing time of the second polishing stage.
It should be noted that, in the embodiment of the present application, the simulation model of the chemical mechanical polishing process in the second polishing stage is substantially the same as the simulation model of the chemical mechanical polishing process in the first polishing stage, and replacing silicon nitride in each model in the first polishing stage with polysilicon becomes each corresponding model in the second polishing stage.
It should be noted that, in the simulation model of the chemical mechanical polishing process in the second polishing stage, the polishing time t needs to be calculated again, instead of accumulating the polishing time in the first polishing stage to the second polishing stage.
S42, calculating the surface morphology of the polished interlayer dielectric layer by using the chemical mechanical polishing process simulation model of the interlayer dielectric layer:
since in step S41, when the CMP process simulation model of the second polishing stage is created, the ending surface topography of the first polishing stage is taken as the initial surface topography of the second polishing stage, that is, the CMP process simulation model of the second polishing stage considers the influence of the post-CMP surface topography unevenness factor of the first polishing stage on the surface flatness of the second polishing stage, as an example, step S42 may specifically be: and calculating the surface morphology of the end surface of the second grinding stage after the chemical mechanical grinding by using the chemical mechanical grinding process simulation model of the second grinding stage.
As an example, the post-chemical mechanical polishing stop surface topography of the second polishing stage can include at least one of dishing, erosion, oxide layer thickness, silicon nitride layer thickness, barrier layer thickness, and polysilicon layer thickness.
As a specific embodiment of the present application, since the line width and the pitch of the HKMG device structure are generally very small, the characteristic of the disc-shaped curved surface after the chemical mechanical polishing process of the interlayer dielectric layer is very prominent, and for the sake of convenience, in the embodiment of the present application, it is assumed that the disc-shaped surface is a cylindrical surface perpendicular to the paper surface, and fig. 6 shows a schematic diagram of the disc-shaped curved surface after the chemical mechanical polishing process of the interlayer dielectric layer. Therefore, in order to describe the surface appearance of the interlayer dielectric layer after grinding,the disc-shaped curve R of the terminating surface can be useddishingTo describe.
As an example, the dish-shaped curve R of the termination surface is shown in FIG. 7dishingThe calculation method of (a) may include the steps of:
s421, calculating the final surface dishing ILD2 after the second grinding stage grinding by using the surface dishing model of the second grinding stagedishing；
S422, calculating the etch stop ILD2 after grinding in the second grinding stage by using the surface etch model in the second grinding stageero；
S423, forming a disc-shaped ILD2 according to the final surface shape after the second grinding stagedishingAnd the etch stop surface ILD2 after the second grinding stage grindingeroAnd calculating the surface disc curve R after the second grinding stage grinding by a pre-established coordinate systemdishingAnd the surface disc-shaped curve R after the second grinding stage grindingdishingEnd surface topography for the second grinding stage:
as shown in fig. 6, the pre-established coordinate system has an X axis in a direction of the line width of the measured oxide layer, and a Y axis in a direction perpendicular to the line width of the measured oxide layer.
As an example, the dishing curve R of the surface after the second polishing stage polishing can be calculated according to the following formula (9)dishing：
Wherein L is a pitch, L is w + s, w is a line width corresponding to the oxide layer, and s is a distance corresponding to the silicon nitride layer; x0 is the abscissa of the line width starting point of the oxide layer, and ρ is the pattern density.
And S43, fusing the surface appearance of the ground interlayer dielectric layer into the metal gate modeling process, and establishing a chemical mechanical grinding process simulation model of the metal gate.
In the embodiment of the application, in order to enable the established model of the chemical mechanical polishing process of the metal gate to be more accurate and reliable, the surface appearance of the polished interlayer dielectric layer is integrated into the modeling process of the metal gate, and the simulation model of the chemical mechanical polishing process of the metal gate is established.
As an example, the formula (9) of the dishing curve is introduced into the CMP modeling of the metal gate Al, the CMP process of the metal gate influenced by the dishing curve is studied, the real surface contact and the stress deformation are strictly analyzed, the fluid mechanics and chemical dynamics mechanisms are applied, the nano size and the surface effect are considered, and the accurate CMP process simulation model of the high-k metal gate is established. By investigating the chemical reaction process in which various grinding fluid components participate, the chemical and mechanical synergistic effect can be integrated into a model, and the influence of design patterns (equivalent line width, equivalent density), technological processes (empty wafer grinding rate, external pressure, relative sliding rate, grinding time and the like) and chemical and physical parameters (chemical reaction parameters, grinding fluid component concentration, material properties, elastic modulus, Poisson's ratio, flattening length and the like) on the precision of a CMP model is comprehensively investigated.
The above is a specific implementation of the modeling method of the chemical mechanical polishing process of HKMG provided in the embodiments of the present application. In the specific embodiment, the surface morphology of the interlayer dielectric layer after grinding is integrated into the metal gate modeling process, and the chemical mechanical grinding process of the metal gate is modeled. Therefore, the modeling method considers the influence of the surface topography of the lower layer structure (namely the interlayer dielectric layer) of the high-k metal gate device on the surface topography of the upper layer structure (namely the metal gate) so as to more accurately simulate the chemical mechanical polishing process of the high-k metal gate, therefore, the modeling method considers the lamination effect of the surface topography of the high-k metal gate, the chemical mechanical polishing process simulation model of the high-k metal gate obtained by the modeling method can accurately reflect the real chemical mechanical polishing process of the high-k metal gate, accurately and quickly simulate the real-time change of the surface topography of a chip and the surface defects depending on graphs, and has guiding significance for the optimization of the chemical mechanical polishing process and layout design of the high-k metal gate.
The CMP process model of the HKMG obtained by the modeling method can assist a process engineer in strictly controlling process conditions, reduce the difficulty of parameter optimization, and reduce the dishing and erosion after grinding as much as possible, so that the surface flatness of the metal gate meets the requirement of the photoetching focusing depth level. Meanwhile, due to the grinding design of different graph structures, a layout designer can predict hot spot regions possibly occurring in the actual process manufacturing process of the design layout in advance, and a modification suggestion is provided for the designer, so that the tape-out risk is reduced, and the success rate of primary tape-out is improved.
Based on the specific implementation of the HKMG chemical mechanical polishing modeling method provided in the foregoing embodiment, the embodiment of the present application also provides a specific implementation of the HKMG chemical mechanical polishing modeling apparatus, which is specifically referred to in the following embodiments.
Fig. 8 is a schematic structural diagram of an HKMG chemical mechanical polishing modeling apparatus provided in an embodiment of the present application. As shown in fig. 8, the modeling apparatus includes the following units:
the interlayer dielectric layer modeling unit 81 is used for modeling the interlayer dielectric layer chemical mechanical polishing process to obtain a chemical mechanical polishing process simulation model of the interlayer dielectric layer;
the calculating unit 82 is used for calculating the surface morphology of the polished interlayer dielectric layer after the interlayer dielectric layer is polished by using the chemical mechanical polishing process simulation model of the interlayer dielectric layer;
and the metal gate modeling unit 83 is used for integrating the surface appearance of the ground interlayer dielectric layer into the metal gate modeling process and establishing a chemical mechanical grinding process simulation model of the metal gate.
As a specific embodiment of the present application, in order to improve the precision of an interlayer dielectric layer CMP process simulation model, according to the difference of polishing material layers in the interlayer dielectric layer polishing process, the interlayer dielectric layer polishing process includes a first polishing stage and a second polishing stage, the first polishing stage polishes an oxide layer and a silicon nitride layer, and the second polishing stage polishes the oxide layer, the silicon nitride layer, a barrier layer, and a polysilicon layer;
the interlayer dielectric layer modeling unit 81 may specifically include:
a first modeling subunit 811, configured to model the chemical mechanical polishing process in the first polishing stage to obtain a simulation model of the chemical mechanical polishing process in the first polishing stage;
a calculating subunit 812, configured to calculate a final surface morphology of the first polishing stage by using the cmp process simulation model of the first polishing stage;
the second modeling subunit 813 is configured to establish a simulation model of the chemical mechanical polishing process in the second polishing stage by using the ending surface topography of the first polishing stage as the initial surface topography of the second polishing stage.
As an embodiment of the present application, since the surface unevenness factor of the first polishing stage is fully considered when modeling the CMP process of the second polishing stage of the interlayer dielectric layer, the calculating unit 82 may specifically include: and calculating the finishing surface morphology of the second grinding stage by using the chemical mechanical grinding process simulation model of the second grinding stage, wherein the finishing surface morphology of the second grinding stage is the finishing surface morphology of the interlayer dielectric layer after grinding.
The above is a specific implementation of the modeling apparatus for HKMG chemical mechanical polishing process provided in the embodiments of the present application. In the specific embodiment, the lamination effect of the surface topography of the high-k metal gate is considered, the chemical mechanical polishing process simulation model of the high-k metal gate obtained by the modeling method can accurately reflect the real process of the chemical mechanical polishing of the high-k metal gate, accurately and quickly simulate the real-time change of the surface topography of a chip and the surface defects depending on graphs, and has guiding significance for the optimization of the chemical mechanical polishing process of the high-k metal gate and the layout design optimization.
The foregoing is a detailed description of the present application. These embodiments are merely examples of the embodiments of the present application, and modifications and substitutions of the above embodiments are within the scope of the present application.
Claims (8)
1. A modeling method for a high-k metal gate chemical mechanical polishing process is characterized in that the high-k metal gate chemical mechanical polishing process comprises the following steps: an interlayer dielectric layer chemical mechanical grinding process and a metal gate chemical mechanical grinding process; the chemical mechanical grinding process of the interlayer dielectric layer comprises a first grinding stage and a second grinding stage, wherein the first grinding stage is used for grinding the oxide layer and the silicon nitride layer, and the second grinding stage is used for grinding the oxide layer, the silicon nitride layer, the barrier layer and the polycrystalline silicon layer;
the modeling method comprises the following steps:
modeling the chemical mechanical polishing process in the first polishing stage to obtain a chemical mechanical polishing process simulation model in the first polishing stage;
calculating the appearance of the ending surface of the first grinding stage by utilizing the chemical mechanical grinding process simulation model of the first grinding stage;
taking the final surface topography of the first grinding stage as the initial surface topography of the second grinding stage, and establishing a chemical mechanical grinding process simulation model of the second grinding stage;
calculating the surface morphology of the interlayer dielectric layer after grinding by utilizing the chemical mechanical grinding process simulation model of the interlayer dielectric layer;
and fusing the surface appearance of the interlayer dielectric layer after grinding into a metal gate modeling process, and establishing a chemical mechanical grinding process simulation model of the metal gate.
2. The modeling method according to claim 1, wherein calculating the surface morphology of the interlayer dielectric layer after polishing by using the interlayer dielectric layer chemical mechanical polishing process simulation model specifically comprises:
and calculating the finishing surface morphology of the second grinding stage by using the chemical mechanical grinding process simulation model of the second grinding stage, wherein the finishing surface morphology of the second grinding stage is the finishing surface morphology of the interlayer dielectric layer after grinding.
3. The modeling method of claim 1, wherein the end surface topography of the first polishing stage is used as an initial surface topography of the second polishing stage, and the establishing of the chemical mechanical polishing process simulation model of the second polishing stage specifically comprises:
and taking the silicon nitride layer, the barrier layer and the polycrystalline silicon layer which are ground in the second grinding stage as the same material layer, taking the oxide layer which is ground in the second grinding stage as another material layer, taking the finishing surface appearance of the first grinding stage as the initial surface appearance of the second grinding stage, and establishing a chemical mechanical grinding process simulation model of the second grinding stage.
4. The modeling method of claim 2, wherein the CMP process simulation model of the first polishing stage and the CMP process simulation model of the second polishing stage each include a dishing model and an erosion model, respectively.
5. Modeling method according to claim 4, characterized in that the disk model of the first grinding phase is in particular:
the surface erosion model of the first grinding stage is specifically:
wherein, KOxIs the Priston factor, K, of the oxide layer of the first polishing stageNiIs the Priston factor, P, of the silicon nitride layer of the first polishing stage0The initial pressure of the polishing pad on the chip at the beginning of the first polishing stage, k is the hardness of the polishing pad, α is the deformation factor of the polishing pad, w is the line width corresponding to the oxide layer of the first polishing stage, s is the distance corresponding to the silicon nitride layer of the first polishing stage, L is the pitch of the first polishing stage, L is w + s, Y isNi(0) Is the initial height of the silicon nitride layer in the first polishing stage, YOx(0) Is the initial height of the oxide layer in the first polishing stage, v is the relative sliding speed of the polishing pad to the wafer, and t isThe polishing time of the first polishing stage, ILD1_ polishing (t), is the dishing of the termination surface of the first polishing stage, and ILD1_ ero (t), is the erosion of the termination surface of the first polishing stage.
6. The modeling method of claim 4, wherein the calculating the end surface topography of the second polishing stage using the CMP process simulation model of the second polishing stage comprises:
calculating the final surface dishing ILD2 after the second polishing stage polishing using the surface dishing model for the second polishing stagedishing；
Calculating the final surface erosion ILD2 after the second grinding stage grinding using the surface erosion model of the second grinding stageero；
Dishing of ILD2 according to the polished termination surface of the second polishing stagedishingAnd the etch stop surface ILD2 after the second grinding stage grindingeroAnd calculating the surface disc curve R after the second grinding stage grinding by a pre-established coordinate systemdishing(ii) a The dish-shaped curve of the surface ground in the second grinding stage is the appearance of the finishing surface of the second grinding stage;
the direction of the X axis of the pre-established coordinate system is the direction of measuring the line width of the oxide layer, and the direction of the Y axis is the direction perpendicular to the line width of the measured oxide layer.
7. The modeling method of claim 6, wherein the post-grinding termination surface dishing ILD2 according to the second grinding stagedishingAnd the etch stop surface ILD2 after the second grinding stage grindingeroAnd calculating the surface disc curve R after the second grinding stage grinding by a pre-established coordinate systemdishingThe method specifically comprises the following steps:
calculating the surface disc curve R after the second grinding stage grinding according to the following formuladishing：
Wherein L 'is a pitch of the second polishing stage, L' is w '+ s', w 'is a line width corresponding to the oxide layer of the second polishing stage, and s' is a distance corresponding to the silicon nitride layer of the second polishing stage; x0 is the abscissa of the line width starting point of the oxide layer, and ρ is the pattern density.
8. A modeling device for a chemical mechanical polishing process of a high-k metal gate is characterized in that the chemical mechanical polishing process of the high-k metal gate comprises the following steps: an interlayer dielectric layer chemical mechanical grinding process and a metal gate chemical mechanical grinding process; the chemical mechanical grinding process of the interlayer dielectric layer comprises a first grinding stage and a second grinding stage, wherein the first grinding stage is used for grinding the oxide layer and the silicon nitride layer, and the second grinding stage is used for grinding the oxide layer, the silicon nitride layer, the barrier layer and the polycrystalline silicon layer;
the modeling apparatus includes:
the first modeling subunit is used for modeling the chemical mechanical polishing process in the first polishing stage to obtain a chemical mechanical polishing process simulation model in the first polishing stage;
the calculation subunit is used for calculating the appearance of the ending surface of the first grinding stage by using the chemical mechanical grinding process simulation model of the first grinding stage;
the second modeling subunit is used for establishing a chemical mechanical polishing process simulation model of the second polishing stage by taking the finishing surface topography of the first polishing stage as the initial surface topography of the second polishing stage;
the calculation unit is used for calculating the surface morphology of the polished interlayer dielectric layer after the interlayer dielectric layer is polished by utilizing the chemical mechanical polishing process simulation model of the interlayer dielectric layer;
and the metal gate modeling unit is used for integrating the surface morphology of the interlayer dielectric layer after grinding into the metal gate modeling process and establishing a chemical mechanical grinding process simulation model of the metal gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710325974.0A CN108875098B (en) | 2017-05-10 | 2017-05-10 | Modeling method and device for chemical mechanical polishing process of high-k metal gate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710325974.0A CN108875098B (en) | 2017-05-10 | 2017-05-10 | Modeling method and device for chemical mechanical polishing process of high-k metal gate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108875098A CN108875098A (en) | 2018-11-23 |
| CN108875098B true CN108875098B (en) | 2022-01-04 |
Family
ID=64287600
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710325974.0A Active CN108875098B (en) | 2017-05-10 | 2017-05-10 | Modeling method and device for chemical mechanical polishing process of high-k metal gate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108875098B (en) |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102820328A (en) * | 2011-06-09 | 2012-12-12 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
| US8546209B1 (en) * | 2012-06-15 | 2013-10-01 | International Business Machines Corporation | Replacement metal gate processing with reduced interlevel dielectric layer etch rate |
| US8921150B2 (en) * | 2012-12-06 | 2014-12-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Process to achieve contact protrusion for single damascene via |
| CN104637797A (en) * | 2013-11-12 | 2015-05-20 | 中国科学院微电子研究所 | Method for treating ILD (injection laser diode) layer in gate-last technology |
| CN105390447B (en) * | 2015-10-26 | 2018-09-04 | 上海华力微电子有限公司 | A kind of nitridation silicon preparation method for dummy gate |
| CN106206441A (en) * | 2016-08-30 | 2016-12-07 | 上海华力微电子有限公司 | The preparation method of metal gates |
-
2017
- 2017-05-10 CN CN201710325974.0A patent/CN108875098B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN108875098A (en) | 2018-11-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10971370B2 (en) | Hard mask removal method | |
| CN109545790A (en) | The forming method in the channel hole of three-dimensional storage | |
| CN103985668A (en) | Copper interconnection manufacturing method | |
| Lee | Modeling of chemical mechanical polishing for shallow trench isolation | |
| US9165880B2 (en) | Process control methods for CMP (chemical mechanical polishing) and other polishing methods used to form semiconductor devices | |
| CN108875098B (en) | Modeling method and device for chemical mechanical polishing process of high-k metal gate | |
| CN107195561A (en) | A kind of cmp defect inspection method | |
| JP2008226935A (en) | Manufacturing method of semiconductor device | |
| US6809031B1 (en) | Method for manufacturing a reclaimable test pattern wafer for CMP applications | |
| WO2007000823A1 (en) | Semiconductor device and production method therefor | |
| JP2004532510A (en) | Chemical mechanical polishing method for copper-oxide damascene structure | |
| CN108228943B (en) | CMP (chemical mechanical polishing) process modeling method of FinFET (Fin field effect transistor) device | |
| US20130241075A1 (en) | Contact or via critical dimension control with novel closed loop control system in chemical mechanical planarization process | |
| CN104576539B (en) | Method for forming semiconductor structure | |
| CN109545676A (en) | Grating of semiconductor element high planarization method | |
| CN102371534B (en) | Chemical mechanical polishing method for surface of wafer | |
| CN105448684B (en) | The method for forming grid | |
| CN110867377A (en) | Planarization method of dummy gate | |
| JP3933619B2 (en) | Method for determining remaining film thickness in polishing process and method for manufacturing semiconductor device | |
| CN109767987A (en) | A kind of post tensioned unbonded prestressed concrete forming method | |
| TW200400596A (en) | Surface-smoothing conductive layer for semiconductor devices with magnetic material layers | |
| CN103928310B (en) | The method for opening polysilicon gate | |
| US10606170B2 (en) | Template for imprint lithography and methods of making and using the same | |
| TWI689081B (en) | Method for manufacturing non-volatile memory device | |
| CN102592993B (en) | Method for improving uniformity of chemical and mechanical planarization process for metal plug in post-gate engineering |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |