JP6007524B2 - Solid-state imaging device - Google Patents

Description

  The present invention relates to a solid-state imaging device.

  As a solid-state imaging device used as an image sensor, a threshold modulation type solid-state imaging device has been proposed in place of a CCD (Charge Coupled Device) type or CMOS (Complementary Metal Oxide Semiconductor) type solid-state imaging device. The threshold modulation type solid-state imaging device includes a plurality of pixels arranged in a matrix on a semiconductor substrate, and each pixel includes one photodiode and one transistor.

  In each pixel of the threshold modulation type solid-state imaging device, the photodiode generates photogenerated charges (holes or electrons) according to the intensity of incident light. The generated charge changes the threshold voltage of the transistor. The change in the threshold voltage of the transistor is read as the source voltage when the transistor is in the saturation region. Thereby, a source voltage corresponding to the intensity of incident light, that is, pixel data is obtained. By using a plurality of pixel data corresponding to a plurality of pixels, one piece of image data is generated (for example, see Patent Document 1).

Japanese Patent No. 3313683

  However, in a conventional solid-state imaging device such as Patent Document 1, a potential for element selection is applied to the gate of a transistor among a plurality of solid-state imaging devices that share a source line connected to the source of the transistor. When strong light is incident on an unselected element that is not selected, a phenomenon (black smear) in which the light intensity is apparently reduced and output may occur.

  One cause of the occurrence of this black smear is that the N-type well region formed in the semiconductor substrate is connected to the drain (N-type) of the transistor, and this N-type well region and the source region of the transistor This is considered to be because a leakage current is generated between the (N-type) and the P-type region.

  The present invention has been made in view of the above technical problems. Some aspects of the present invention relate to suppressing the occurrence of black smear in a solid-state imaging device.

In some embodiments of the present invention, a solid-state imaging device includes: a photodiode that is located on a semiconductor substrate and generates a photo-generated charge according to incident light; and a detection transistor that detects the photo-generated charge generated by the photodiode. A photodiode includes a first diffusion layer of a first conductivity type located on a semiconductor substrate, and a second conductivity type of a second conductivity type located closer to the first surface of the semiconductor substrate than the first diffusion layer. A detection transistor including a gate electrode located in the second diffusion layer in plan view, and a source part and a drain part of a first conductivity type located across the gate electrode in plan view, A gate insulating film positioned between the gate electrode and the first surface of the semiconductor substrate, the source portion and the drain portion include a region in contact with the first surface of the semiconductor substrate, and a second diffusion of the second conductivity type Layer or second Located at a distance from the first diffusion layer through the third layer of the conductivity type.
According to this aspect, both the source part and the drain part of the first conductivity type are located apart from the first diffusion layer of the first conductivity type via the second conductivity type layer. Thereby, generation | occurrence | production of the leakage current through the 1st diffused layer between a source part and a drain part can be suppressed, and generation | occurrence | production of a black smear can be suppressed.

In the above-described aspect, the first diffusion layer includes the first region containing the first conductivity type impurity having a lower concentration than the impurity concentration of the source portion and the impurity concentration of the drain portion, and a lower concentration than the impurity concentration of the first region. And a second region located between the first region and the second diffusion layer.
According to this, by making the potential curve from the first region to the second diffusion layer gentle and making the depletion layer easily spread, the generation of leakage current can be suppressed and the occurrence of black smear can be suppressed. .

In the above-described aspect, the carrier is located in the second diffusion layer and overlaps at least a part of the gate electrode in plan view and includes the second conductivity type impurity having a concentration higher than the impurity concentration of the second diffusion layer. It is desirable that a pocket is further included and a part of the second diffusion layer is also located between the carrier pocket and the first diffusion layer.
According to this, the carrier pocket and the first diffusion layer can be separated from each other, and the potential increase of the carrier pocket can be suppressed. As a result, it is possible to suppress the formation of an unintended channel between the carrier pocket and the surface of the semiconductor substrate, which electrically connects the source portion and the drain portion, thereby suppressing the occurrence of black smear.

  In the above-described aspect, the planar shape of the carrier pocket and the gate electrode is a ring shape, and one of the source part and the drain part is located inside the gate electrode in a plan view, and the other is located outside the gate electrode in a plan view. It is desirable to do. Further, it is desirable that the first conductivity type is an N type and the second conductivity type is a P type.

The top view of the solid-state image sensor which constitutes one embodiment. Sectional drawing in the II-II line of the solid-state image sensor of FIG. Sectional drawing which shows the manufacturing process of the solid-state image sensor of FIG. Sectional drawing which shows the manufacturing process of the solid-state image sensor of FIG. Sectional drawing which shows the manufacturing process of the solid-state image sensor of FIG.

  Hereinafter, embodiments of the present invention will be described in detail. In addition, this embodiment demonstrated below does not unduly limit the content of this invention described in the claim. Further, not all of the configurations described in the present embodiment are essential as a solution means of the present invention. The same constituent elements are denoted by the same reference numerals, and description thereof is omitted.

<1. Configuration>
FIG. 1 is a plan view conceptually showing a solid-state imaging device constituting a solid-state imaging device according to one embodiment of the present invention. 2 is a cross-sectional view taken along line II-II of the solid-state imaging device shown in FIG. The solid-state imaging device is configured by regularly arranging a plurality of solid-state imaging devices 1. One solid-state imaging device 1 includes one photodiode 10, one detection transistor 20, and a reset transistor 32 common to a plurality of (for example, two) solid-state imaging devices 1.

  The photodiode 10, the detection transistor 20, and the reset transistor 32 are formed on the front surface (first surface) side of the semiconductor substrate 110. The semiconductor substrate 110 is a substrate of a second conductivity type (for example, P type). The substrate itself is not limited to the second conductivity type, and a second conductivity type well may be formed on the surface side of the first conductivity type (for example, N type) semiconductor substrate.

<1-1. Photodiode>
A first conductivity type first diffusion layer 11 is formed in the semiconductor substrate 110. A second conductivity type second diffusion layer 12 is formed at a position closer to the surface of the semiconductor substrate 110 than the first diffusion layer 11. The first conductivity type first diffusion layer 11 and the second conductivity type second diffusion layer 12 constitute a photodiode 10. The first diffusion layer 11 includes a first region 11a containing a first conductivity type impurity, and a second region 11b and a third region 11c containing a first conductivity type impurity having a lower concentration than the first region 11a. . The second region 11 b is located between the first region 11 a and the second diffusion layer 12.

  A first conductivity type pinning layer 13 is formed on the outermost surface of the semiconductor substrate 110. The pinning layer 13 prevents generation of dark current on the substrate surface. In addition, the subscripts + and − to N and P in each figure indicate a portion with a high impurity concentration (subscript +) and a thin portion (subscript −), respectively.

<1-2. Detection transistor>
The detection transistor 20 includes a gate electrode 26 formed on the semiconductor substrate 110 via a gate insulating film 25. The gate electrode 26 is formed in a ring shape in plan view. A drain region 27 of the first conductivity type is formed on the surface of the semiconductor substrate 110 in a part of the region surrounding the outside of the gate electrode 26 in plan view. The drain region 27 of the first conductivity type is located away from the first diffusion layer 11 of the first conductivity type via the second conductivity type layer 22.

  The surface of the semiconductor substrate 110 in a region surrounded by the gate electrode 26 in plan view is a first conductivity type source region 28, and the source region 28 is connected via a source contact 28 a on the semiconductor substrate 110. It is connected to the signal output line 28b. The source region 28 of the first conductivity type is located away from the first diffusion layer 11 of the first conductivity type via the second diffusion layer 12 of the second conductivity type. In this embodiment, the drain region 27 is formed in a part of the region surrounding the outside of the gate electrode 26 in plan view, and the source region 28 is formed on the surface of the semiconductor substrate 110 in the region surrounded by the gate electrode 26 in plan view. However, it is not limited to this. The source region 28 may be formed in a part of the region surrounding the outside of the gate electrode 26 in plan view, and the drain region 27 may be formed on the surface of the semiconductor substrate 110 in the region surrounded by the gate electrode 26 in plan view.

  In a region immediately below the detection transistor 20 of the semiconductor substrate 110, a first conductivity type first diffusion layer 11 constituting the photodiode 10 and a second conductivity type second diffusion layer 12 constituting the photodiode 10 extend. Exist. Charges (for example, holes) generated in the photodiode 10 that has received the light are high-concentration second conductivity type semiconductor regions formed in the second conductivity type second diffusion layer 12 immediately below the detection transistor 20. It is transferred to the carrier pocket 24 and stored. Due to this charge accumulation, a substrate bias is applied to the detection transistor 20 and the threshold voltage of the detection transistor 20 changes. Therefore, the amount of change in the threshold voltage (the amount of change in the source voltage during the saturation region operation) is detected as the amount of incident light.

<1-3. Reset transistor>
The reset transistor 32 includes a gate electrode 36 (FIG. 1) formed on the semiconductor substrate 110 via an insulating film (not shown). The gate electrodes 36 extend on the gate electrodes 26 of the two detection transistors 20 on both end sides of the reset transistor 32 via insulating films (not shown). A through hole 36a is formed in the central portion of the gate electrode 36, and immediately below the through hole 36a, a discharge portion (not shown) which is a high-concentration second conductivity type semiconductor region on the surface of the semiconductor substrate 110 ) Is formed. This discharge part is connected to a wiring (not shown).

  After detecting the amount of incident light by the detection transistor 20 and applying a voltage higher than the threshold value to the gate electrode 36, a channel is formed between the second conductivity type carrier pocket 24 and the second conductivity type discharge portion. Thereby, the above-mentioned electric charges transferred to and accumulated in the carrier pocket 24 are discharged through the discharge unit. Therefore, the charges accumulated in the carrier pocket 24 do not have to be discharged through the first diffusion layer 11.

<2. Manufacturing method>
3 and 4 are cross-sectional views showing manufacturing steps of the solid-state imaging device shown in FIG. In FIGS. 3 and 4, illustration of a photoresist, a sacrificial oxide film, and the like is omitted. First, as shown in FIG. 3A, impurity ions of the first conductivity type are implanted into a semiconductor substrate 110 such as silicon (Si) through a predetermined pattern of photoresist to thereby form the first diffusion layer 11. Form.

  For example, the first region 11a containing the first conductivity type impurity having a relatively high concentration is first formed at a predetermined depth position of the semiconductor substrate 110, and then the semiconductor substrate 110 is heat treated to diffuse the first conductivity type impurity. By doing so, the second region 11b and the third region 11c containing the first conductivity type impurity having a lower concentration than the first region 11a are formed.

  Alternatively, the first region 11a containing the first conductivity type impurity is first formed at a predetermined depth position of the semiconductor substrate 110, and then the first conductivity having a lower concentration than the first region 11a is changed by changing the ion implantation conditions. The second region 11b containing the type impurity may be formed in a shallow position of the semiconductor substrate 110.

  Next, as shown in FIG. 3B, ions of the second conductivity type impurity are implanted into the shallower position on the surface side than the first diffusion layer 11 through a predetermined pattern of photoresist, thereby The diffusion layer 12 is formed. Thereby, the photodiode 10 is formed.

  Next, as shown in FIG. 3C, the drain region 27 is formed by implanting ions of the first conductivity type impurity into the semiconductor substrate 110 through a predetermined pattern of photoresist. The drain region 27 is formed at a shallow position on the surface side of the semiconductor substrate 110 so as not to reach the first diffusion layer 11. The second conductivity type layer 22 remains between the drain region 27 and the first diffusion layer 11.

  Next, as shown in FIG. 4D, ions of a second conductivity type impurity are implanted into the semiconductor substrate 110 through a photoresist having a predetermined pattern, whereby the second conductivity type second diffusion layer 12 is implanted. A carrier pocket 24 is formed. Further, the first conductivity type pinning layer 13 is formed by implanting ions of the first conductivity type impurity into the semiconductor substrate 110 through a predetermined pattern of photoresist.

Next, as illustrated in FIG. 4E, after forming a silicon oxide (SiO ₂ ) film 29 to be the gate insulating film 25 over the semiconductor substrate 110, the gate electrode 26 is formed over the silicon oxide film 29. The gate electrode 26 is formed of, for example, polycrystalline silicon doped to the first conductivity type.

  Next, as illustrated in FIG. 5F, an oxide film 30 serving as a sidewall is deposited over the silicon oxide film 29 and the gate electrode 26. Further, an interlayer insulating film 31 is deposited on the oxide film 30.

  Next, as shown in FIG. 5G, a part of each of the interlayer insulating film 31, the oxide film 30, and the silicon oxide film 29 is etched to expose the surface of the semiconductor substrate 110. Next, as shown in FIG. Then, ion implantation is performed using the interlayer insulating film 31, the oxide film 30 and the silicon oxide film 29 as a mask, thereby forming the first conductivity type source region. Thereafter, a solid-state imaging device having the solid-state imaging device 1 and the plurality of solid-state imaging devices 1 is manufactured through wiring processes such as the source contact 28a and the signal output line 28b (see FIG. 2).

<3. Effects of this embodiment>
According to the embodiment described above, the source region 28 of the first conductivity type is located away from the first diffusion layer 11 of the first conductivity type via the second diffusion layer 12 of the second conductivity type. The drain region 27 of the first conductivity type is located away from the first diffusion layer 11 of the first conductivity type via the second conductivity type layer 22. Thereby, generation | occurrence | production of the leakage current through the 1st diffused layer between a source region and a drain region can be suppressed, and generation | occurrence | production of a black smear can be suppressed.

  The first conductivity type first diffusion layer 11 includes a first region 11a and a second region 11b containing a first conductivity type impurity having a lower concentration than the first region 11a, and the second region 11b includes: It is located between the first region 11 a and the second conductivity type second diffusion layer 12. As a result, the potential curve from the first region 11a to the second conductivity type second diffusion layer 12 is moderated, and the depletion layer is likely to spread, thereby suppressing the occurrence of leakage current and the generation of black smear. Can be suppressed.

  In addition, since a part of the second diffusion layer 12 constituting the photodiode 10 is also located between the carrier pocket 24 and the first diffusion layer 11, it is between the carrier pocket 24 and the first diffusion layer 11. , So that the potential rise of the carrier pocket 24 can be suppressed. As a result, it is possible to suppress the formation of an unintended channel that connects the source region and the drain region between the carrier pocket 24 and the surface of the semiconductor substrate 110, thereby suppressing the occurrence of black smear.

  Further, according to the above embodiment, it is possible to avoid complication such as adding a transistor separately as a measure against black smear. Further, since the deep photodiode 10 is formed, an increase in red sensitivity is expected.

  DESCRIPTION OF SYMBOLS 1 ... Solid-state image sensor, 10 ... Photodiode, 11 ... 1st conductivity type 1st diffused layer, 11a ... 1st area | region, 11b ... 2nd area | region, 11c ... 3rd area | region, 12 ... 2nd conductivity type 2nd Diffusion layer, 13 ... pinning layer, 20 ... detection transistor, 22 ... second conductivity type layer, 24 ... carrier pocket, 25 ... gate insulating film, 26 ... gate electrode, 27 ... drain region, 28 ... source region, 28a ... Source contact, 28b ... signal output line, 29 ... silicon oxide film, 30 ... oxide film, 31 ... interlayer insulating film, 32 ... reset transistor, 36 ... gate electrode, 36a ... through hole, 110 ... semiconductor substrate.

Claims (6)

A solid-state imaging device comprising a photodiode that is located on a semiconductor substrate and generates a photo-generated charge according to incident light, and a detection transistor that detects the photo-generated charge generated by the photodiode,
The photodiode is
A first diffusion layer of a first conductivity type located on the semiconductor substrate;
A second diffusion layer of a second conductivity type located closer to the first surface of the semiconductor substrate than the first diffusion layer;
Including
The detection transistor is
A gate electrode located in the second diffusion layer in plan view;
A source part and a drain part of a first conductivity type located across the gate electrode in plan view;
A gate insulating film located between the gate electrode and the first surface of the semiconductor substrate;
Including
The source part and the drain part include a region in contact with the first surface of the semiconductor substrate, and the source part is located away from the first diffusion layer through the second diffusion layer of the second conductivity type. And the drain portion is spaced apart from the first diffusion layer via a second conductive type third layer, and the third layer has a lower concentration than the impurity concentration of the second diffusion layer. A solid-state imaging device comprising a second conductivity type impurity . In claim 1,
The solid-state imaging device, wherein the drain portion is located outside the second diffusion layer in plan view. In claim 1 or 2 ,
The first diffusion layer includes
A first region containing a first conductivity type impurity having a lower concentration than the impurity concentration of the source portion and the impurity concentration of the drain portion;
A second region containing a first conductivity type impurity at a lower concentration than the impurity concentration of the first region, and located between the first region and the second diffusion layer;
A solid-state imaging device. In any one of Claims 1 thru | or 3 ,
A carrier pocket which is located in the second diffusion layer and overlaps at least a part of the gate electrode in plan view and contains a second conductivity type impurity having a concentration higher than the impurity concentration of the second diffusion layer; In addition,
The solid-state imaging device, wherein a part of the second diffusion layer is also located between the carrier pocket and the first diffusion layer. In claim 4 ,
The planar shapes of the carrier pocket and the gate electrode are respectively ring-shaped, and one of the source part and the drain part is located inside the gate electrode in a plan view, and the other is located outside the gate electrode in a plan view. A solid-state imaging device located. In any one of Claims 1 to 5 ,
The solid-state imaging device, wherein the first conductivity type is an N type and the second conductivity type is a P type.

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