JP5971728B2 - Wiring substrate manufacturing method and semiconductor device manufacturing method - Google Patents

Description

  FIELD Embodiments described herein relate generally to a wiring board manufacturing method and a semiconductor device manufacturing method.

  Some semiconductor devices are obtained by laminating a plurality of semiconductor chips with a die attachment film (DAF) on a wiring substrate containing glass epoxy resin as a main component and sealing with a mold resin. In recent years, semiconductor devices are becoming smaller and thinner. When a semiconductor device is thinned, the semiconductor device is warped due to a difference in thermal expansion coefficient, elastic modulus, and the like of a wiring board, a semiconductor chip, a DAF, and a mold resin that constitute the semiconductor device.

  When a large warp occurs in the semiconductor device, connection becomes difficult when soldering to a mounting board (for example, a mother board) on which the semiconductor device is mounted. Further, the thickness including the warp of the semiconductor device may be out of the standard due to the warp. In order to reduce the warpage of the semiconductor device, it has been proposed to increase the rigidity of the wiring board. In this wiring board, it has been proposed to increase the rigidity of the wiring board by using a highly rigid solder resist layer laminated on the surface.

  However, when the rigidity of the solder resist layer is high, it becomes difficult to form an opening that exposes the wiring pattern in the solder resist layer. Specifically, when the opening is formed in the solder resist layer, the wiring pattern is excessively etched, and the bonding strength with the bonding wire or the solder ball may be insufficient. Moreover, there is a possibility that the time required for forming the opening becomes long, and variation in the opening shape and size may occur. Furthermore, if the opening shape and dimensions vary, the size (diameter), position, and height of solder balls formed on the back surface (side on which the semiconductor chip is not mounted) of the wiring board may vary.

JP 2013-21374 A

  The problem to be solved by the present invention is to provide a method for manufacturing a wiring board and a method for manufacturing a semiconductor device, in which an opening can be easily formed in a solder resist layer.

A method of manufacturing a wiring board according to an embodiment includes a step of forming a wiring layer having a connection terminal and a wiring on an insulating layer, a step of laminating a first mask layer on the connection terminal of the wiring layer, and the wiring Laminating a solder resist layer on the layer and on the first mask layer, etching the solder resist layer until the surface of the first mask layer is exposed, and the first exposed by the etching. And a step of laminating a second mask layer on the solder resist layer before the step of etching the solder resist layer, and the step of removing the mask layer of the second mask layer. Forming an opening in a region located on one mask layer, and etching the solder resist layer using the second mask layer having the opening as a mask.

Sectional drawing of the semiconductor device which concerns on embodiment The figure which shows the wiring board which concerns on embodiment Manufacturing process diagram of wiring board according to the embodiment Manufacturing process diagram of wiring board according to the embodiment Manufacturing process diagram of wiring board according to the embodiment Manufacturing process diagram of wiring board according to the embodiment Manufacturing process diagram of wiring board according to the embodiment Manufacturing process diagram of wiring board according to the embodiment Manufacturing process diagram of wiring board according to the embodiment Manufacturing process diagram of wiring board according to modification of embodiment Manufacturing process diagram of wiring board according to modification of embodiment

  A semiconductor device manufacturing method and a semiconductor manufacturing apparatus according to an embodiment will be described below with reference to FIGS. In each embodiment, substantially the same components are assigned the same reference numerals, and description thereof is omitted. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. The term indicating the direction such as up and down in the description indicates the relative direction when the semiconductor chip mounting side described later is up, and may be different from the actual direction based on the gravitational acceleration direction.

(Embodiment)
FIG. 1 is a cross-sectional view of a semiconductor device 600 according to the embodiment. The semiconductor device 600 includes a wiring substrate 100, a plurality of semiconductor chips 200, a die attachment film (DAF) 300 that bonds the semiconductor chips 200, a bonding wire 400 that connects the wiring substrate 100 and the semiconductor chip 200, the wiring substrate 100, and the semiconductor chip. A sealing resin 500 that seals 200 and the like is provided.

  On the back side of the wiring substrate 100, solder balls B are provided on connection terminals (not shown) with a substrate (for example, a mother board or the like) on which the semiconductor device 600 is mounted. When the semiconductor device 600 is mounted on a mother board or the like, the solder balls B of the wiring board 100 are reflowed so that the wiring board 100 is electrically connected to connection terminals of a board (for example, a mother board) on which the semiconductor device 600 is mounted. Is done.

  FIG. 2 is a diagram illustrating the wiring board 100 according to the embodiment. 2A is a plan view (front surface) of the wiring substrate 100, FIG. 2B is a plan view (back surface) of the wiring substrate 100, and FIG. 2C is a cross-sectional view of the wiring substrate 100.

  The wiring substrate 100 includes a core substrate 110, wiring layers 120 and 130, and solder resist layers 140 and 150. The core substrate 110 is made of a highly rigid insulating material such as glass epoxy resin. The wiring layer 120 is a wiring pattern, and includes a connection terminal 120a to the semiconductor chip 200 and a wiring (not shown) connected to the connection terminal 120a.

  The wiring layer 130 is a wiring pattern, and includes a connection terminal (connection pad) 130a to the substrate on which the semiconductor device 600 is mounted, and a wiring (not shown) connected to the connection terminal 130a. For the wiring layers 120 and 130, a material having excellent electrical conductivity, for example, copper or aluminum is used.

  The solder resist layer 140 is formed by laminating a film-like solder resist on the surface of the wiring layer 120. The solder resist layer 140 has an opening 140a that covers the wiring of the wiring layer 120 and exposes the connection terminal 120a. The opening 140a of the solder resist layer 140 has an NSMD (non-solder mask defined) shape in which a plurality of connection terminals 120a are arranged in the same opening.

  The solder resist layer 150 is formed by laminating a film-like solder resist on the surface of the wiring layer 130. The solder resist layer 150 has an opening 150a that covers the wiring of the wiring layer 130 and exposes the connection terminal 130a. The opening 150a of the solder resist layer 150 has an SMD (solder mask defined) shape in which one connection terminal 130a is disposed in the same opening.

  3 to 9 are manufacturing process diagrams of the wiring board 100. Hereinafter, the manufacturing process of the wiring board 100 will be described with reference to FIGS. 3 to 9, but the same components as those described in FIGS. To do.

  First, the wiring layers 120 and 130 are formed on the core substrate 110. A wiring layer 120 having a connection terminal 120a and a wiring 120b connected to the connection terminal 120a is formed on the surface side (side on which the semiconductor chip is mounted) of the core substrate 110 (see FIG. 3A). ). Further, a wiring layer 130 having a connection terminal 130a and a wiring 130b connected to the connection terminal 130a is formed on the back surface side (side to which a mother board or the like is connected) of the core substrate 110 (FIG. 3B). )reference).

  Next, a resin layer M11 (first mask layer) is laminated on the connection terminal 120a of the wiring layer 120 on the front surface side (see FIG. 4A). Further, a resin layer M12 (first mask layer) is laminated on the connection terminal 130a (expected area to be exposed) of the wiring layer 130 on the back side (see FIG. 4B). The resin layers M11 and M12 are preferably made of a material that can be easily removed by washing with a chemical solution. The resin layers M11 and M12 are, for example, photosensitive resists. In this embodiment, the resin layers M11 and M12 are laminated on the connection terminals 120a and 130a. However, if the solder resist layers 140 and 150 are to be opened later, the resin layers M11 and M12 are formed in other regions. You may laminate.

  Next, the solder resist layer 140 is laminated on the wiring layer 120 and the resin layer M11 on the front side (see FIG. 5A). Further, a solder resist layer 150 is laminated on the wiring layer 130 and the resin layer M12 on the back side (see FIG. 5B). For the solder resist layers 140 and 150, a film-like solder resist may be applied, or a liquid solder resist may be applied by a roll coating method.

  The solder resist layers 140 and 150 are preferably thicker than the resin layers M11 and M12, respectively. Further, the thermal expansion coefficient and the elastic modulus of the solder resist layers 140 and 150 also affect the warp generated in the semiconductor device 600. For this reason, it is preferable to use a solder resist made of a material having as high rigidity as possible for the solder resist layers 140 and 150.

  FIG. 6 shows a cross section taken along line XX in FIG. In this embodiment, the resin layers M11 and M12 are stacked on the connection terminals 120a and 130a, and then the solder resist layers 140 and 150 are stacked on the wiring layers 120 and 130. Since the solder resist is not yet cured when applied or pasted, the solder resist absorbs the irregularities caused by the wiring layers 120 and 130 and the resin layers M11 and M12, and the resin layers M11 and M12, as shown in FIG. The surface on the opposite side (exposed surface) is flatter than the back surface on the resin layer M11, M12 side.

  For this reason, as shown in FIG. 6, the solder resist layers 140 and 150 on the connection terminals 120a and 130a are thinner than other regions by the thickness of the resin layers M11 and M12. Since the amount of etching of the solder resist layers 140 and 150 is reduced by the thinning, openings can be easily formed in the solder resist layers 140 and 150.

  Next, the resin layer M21 (second mask layer) is laminated on the solder resist layer 140 laminated on the surface, and an opening A1 exposing the solder resist layer 140 is formed in a region located on the resin layer M11 ( FIG. 7 (a)). Further, a resin layer M22 (second mask layer) is laminated on the solder resist layer 150 laminated on the back surface, and an opening A2 exposing the solder resist layer 150 is formed in a region located on the resin layer M12 (FIG. 7 (b)).

  Considering the positional deviation between the resin layers M11 and M12 and the openings A1 and A2 formed in the resin layers M21 and 22, the openings A1 and A2 formed in the resin layers M21 and M22 are more than the corresponding resin layers M11 and M12. It is preferable to form it one size larger (for example, about several μm to several tens of μm). Furthermore, if the openings A1 and A2 formed in the resin layers M21 and M22 are smaller than the corresponding resin layers M11 and M12, the cross-sectional shapes of the solder resist layers 140 and 150 in the openings 140a and 150a are below the openings 140a and 150a. It becomes the reverse taper shape which the upper side protruded from the side. For this reason, when the solder balls B are provided in the openings 140a and 150a, considering the possibility that air bubbles remain in the openings 140a and 150a, the openings A1 and A2 formed in the resin layers M21 and M22 are the corresponding resin layers. It is more preferable to form it slightly larger than M11 and M12.

  Similarly to the resin layers M11 and M12, the resin layers M21 and M22 are preferably made of a material that can be easily removed by cleaning with a chemical solution. The resin layers M21 and M22 are more preferably made of the same material as the resin layers M11 and M12. This is because the resin layers M11 and M12 and the resin layers M21 and M22 can be removed in the same process.

  Next, the solder resist layer 140 is etched until the surface of the resin layer M11 is exposed using the resin layer M21 in which the opening A1 is formed as a mask (see FIG. 8A). Further, using the resin layer M22 in which the opening A2 is formed as a mask, the solder resist layer 150 is etched until the surface of the resin layer M12 is exposed (see FIG. 8B).

  For example, wet blasting can be used for etching the solder resist layers 140 and 150. Wet blasting is a processing method in which slurry mixed with abrasive grains and liquid is sprayed onto an object at high speed to etch the object. By using the wet blast process, the etching process of the solder resist layers 140 and 150 having high rigidity becomes easy.

  Next, the resin layer M21 laminated on the solder resist layer 140 and the resin layer M11 covering the connection terminal 120a are removed using a release agent or the like (see FIG. 9A). Similarly, the resin layer M22 laminated on the solder resist layer 150 and the resin layer M21 covering the connection terminal 130a are removed using a release agent or the like (see FIG. 9B). In addition, after peeling off the resin layers M11 and 12, the connection terminals 120a and 130a may be plated with a corrosion-resistant film using gold, nickel, palladium, or the like.

  As described above, in the method for manufacturing the wiring substrate 100 according to the embodiment, after the resin layers M11 and M12 (first resin layer) are stacked on the connection terminals 120a and 130a of the wiring layers 120 and 130, the solder resist layer is formed. Since 140 and 150 are laminated, the thickness of the solder resist layers 140 and 150 can be selectively reduced by the amount of the resin layers M11 and M12. For this reason, the etching amount required for forming the openings 140a and 150a exposing the connection terminals 120a and 130a in the solder resist layers 140 and 150 is reduced.

  Therefore, the openings 140a and 150a can be easily formed in the solder resist layers 140 and 150. As a result, when the openings 140a and 150a are formed in the solder resist layers 140 and 150, the connection terminals 120a and 130a of the wiring layers 120 and 130 are excessively etched, and the bonding strength between the bonding wires and the solder balls may be insufficient. Can be reduced. The time required for forming the openings 140a and 150a of the solder resist layers 140 and 150 can be shortened. It is possible to reduce the possibility of variations in the shapes and dimensions of the openings 140a and 150a of the solder resist layers 140 and 150. For this reason, it is possible to reduce the possibility of variations in the size (diameter), position, and height of the solder balls formed on the connection terminals 130a.

(Modification of the embodiment)
Next, a method for manufacturing a wiring board according to a modification of the embodiment will be described. Since the manufacturing process up to FIG. 5 is the same as the manufacturing method of the wiring board according to the embodiment, the manufacturing process up to FIG. 5 has been described. Further, the same components as those described with reference to FIGS. 1 to 9 are denoted by the same reference numerals, and redundant description is omitted.

  Next, the solder resist layer 140 laminated on the surface side is etched until the surface of the resin layer M11 is exposed (see FIG. 10A). Further, the solder resist layer 150 laminated on the back surface is etched until the surface of the resin layer M12 is exposed (see FIG. 10B). In the etching of the solder resist layers 140 and 150, wet blasting can be used as in the above embodiment.

  Next, the resin layer M11 covering the connection terminal 120a is removed using a release agent or the like (see FIG. 11A). Similarly, the resin layer M21 covering the connection terminal 130a is removed using a release agent or the like (see FIG. 11B). In addition, after peeling off the resin layers M11 and 12, the connection terminals 120a and 130a may be plated with gold.

  As described above, in the method for manufacturing a wiring board according to the modification of the embodiment, etching is performed without providing the resin layers M21 and M22 on the solder resist layers 140 and 150. For this reason, the process of providing the resin layers M21 and M22 serving as masks on the solder resist layers 140 and 150 can be omitted, and the productivity of the wiring board is improved. Other effects are the same as those of the method for manufacturing the wiring board 100 according to the embodiment.

  Although some embodiments of the present invention have been described, the present invention is not limited to the configurations and various conditions shown in each embodiment, and these embodiments are presented as examples and limit the scope of the invention. Not intended to do. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 100 ... Wiring board, 110 ... Core board, 120, 130 ... Wiring layer, 120a, 130a ... Connection terminal, 120b, 130b ... Wiring, 140, 150 ... Solder resist layer, 140a, 150a ... Opening, 200 ... Semiconductor chip, 300 Die attachment film (DAF), 400 Bonding wire, 500 Sealing resin, 600 Semiconductor device, A1, A2 Open, B Solder ball, M11, M12 Resin layer, M21, M22 Resin layer

Claims (4)

Forming a wiring layer having connection terminals and wiring on the insulating layer;
Laminating a first mask layer on the connection terminal of the wiring layer;
Laminating a solder resist layer on the wiring layer and on the first mask layer;
Etching the solder resist layer until the surface of the first mask layer is exposed;
Removing the first mask layer exposed by the etching;
Comprising
Before the step of etching the solder resist layer,
Laminating a second mask layer on the solder resist layer;
Forming an opening in a region located on the first mask layer of the second mask layer,
Opening etching the solder resist layer using the second mask layer formed as a mask, the manufacturing method of the wiring substrate. The method for manufacturing a wiring board according to claim 1, wherein an opening formed in the second mask layer is larger than the first mask layer. The wiring board manufacturing method according to claim 1, wherein the solder resist layer is thicker than the first mask layer. Forming a wiring layer having connection terminals and wiring on the insulating layer;
Laminating a first mask layer on the connection terminal of the wiring layer;
Laminating a solder resist layer on the wiring layer and on the first mask layer;
Etching the solder resist layer until the surface of the first mask layer is exposed;
Removing the first mask layer exposed by the etching;
Providing a semiconductor chip on the solder resist layer;
Connecting the semiconductor chip and the connection terminal exposed by removing the first mask layer using a bonding wire;
Sealing the semiconductor chip, the connection terminal and the bonding wire using a sealing resin ,
Before the step of etching the solder resist layer,
Laminating a second mask layer on the solder resist layer;
Forming an opening in a region of the second mask layer located on the first mask layer;
Have
A method of manufacturing a semiconductor device , wherein the solder resist layer is etched using the second mask layer having an opening as a mask .

Images