JP4451874B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP4451874B2
JP4451874B2 JP2006317988A JP2006317988A JP4451874B2 JP 4451874 B2 JP4451874 B2 JP 4451874B2 JP 2006317988 A JP2006317988 A JP 2006317988A JP 2006317988 A JP2006317988 A JP 2006317988A JP 4451874 B2 JP4451874 B2 JP 4451874B2
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semiconductor device
base substrate
film
manufacturing
resin
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JP2007081425A (en
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敦 藤沢
貴史 今野
慎悟 大坂
亮 春田
昌弘 一谷
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Hitachi Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To prevent the occurrence of deformation such as warp and distortion of a base substrate, when an insulating layer is disposed over the whole region on the base substrate made of a flexible film. <P>SOLUTION: In the semiconductor device, wiring conductors (electrode pads 2 for bump connection, wiring 3, electrode pads 4 for wire connection, and wiring 5 for plating) is arranged on one surface of the base substrate 1 made of the flexible film, and a semiconductor chip 10 is mounted on the surface of the flexible film through an adhesive 12, wherein the insulating layer 9 is divided into a plurality of portions to locate them on each wiring conductor. <P>COPYRIGHT: (C)2007,JPO&amp;INPIT

Description

本発明は、半導体装置に関し、特に、可撓性フィルムからなるベース基板を有する半導体装置に適用して有効な技術に関するものである。   The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device having a base substrate made of a flexible film.

多ピン化に好適な半導体装置として、ＢＧＡ(Ｂall Ｇrid Ａrray)構造の半導体装置が開発されている。このＢＧＡ構造の半導体装置は、ベース基板の一表面のチップ搭載領域上に接着材を介在して半導体チップを搭載し、ベース基板の一表面と対向するその裏面側に複数のバンプ電極を格子状に配置した構成になっている。   A semiconductor device having a BGA (Ball Grid Array) structure has been developed as a semiconductor device suitable for increasing the number of pins. In this BGA semiconductor device, a semiconductor chip is mounted on a chip mounting region on one surface of a base substrate with an adhesive interposed therebetween, and a plurality of bump electrodes are formed in a lattice pattern on the back surface side facing the surface of the base substrate. It has a configuration arranged in.

前記ベース基板は、例えば、ガラス繊維にエポキシ樹脂、ポリイミド樹脂、マレイミド樹脂等を含浸させた硬質の樹脂基板(リジット基板)で形成されている。ベース基板の一表面のチップ搭載領域の周囲を囲むその周辺領域には複数のワイヤ接続用電極パッドが配置されている。また、ベース基板の裏面には複数のバンプ接続用電極パッドが配置されている。このバンプ接続用電極パッドには、例えばＰｂ−Ｓｎ組成の半田材からなるバンプ電極が固着され、電気的にかつ機械的に接続されている。   The base substrate is formed of, for example, a hard resin substrate (rigid substrate) in which glass fiber is impregnated with epoxy resin, polyimide resin, maleimide resin, or the like. A plurality of wire connection electrode pads are disposed in a peripheral region surrounding the periphery of the chip mounting region on one surface of the base substrate. A plurality of bump connection electrode pads are disposed on the back surface of the base substrate. For example, a bump electrode made of a solder material having a Pb—Sn composition is fixed to the bump connection electrode pad, and is electrically and mechanically connected.

前記半導体チップは、例えば単結晶珪素からなる半導体基板を主体とする構成になっている。半導体チップには、論理回路システム、記憶回路システム、或はそれらの混合回路システムが搭載されている。また、半導体チップの主面（素子形成面）には複数の外部端子(ボンディングパッド)が配置されている。この外部端子は、ベース基板の一表面に配置されたワイヤ接続用電極パッドにワイヤを介して電気的に接続されている。   The semiconductor chip is mainly composed of a semiconductor substrate made of, for example, single crystal silicon. A semiconductor circuit is equipped with a logic circuit system, a memory circuit system, or a mixed circuit system thereof. A plurality of external terminals (bonding pads) are disposed on the main surface (element formation surface) of the semiconductor chip. The external terminal is electrically connected to a wire connecting electrode pad disposed on one surface of the base substrate via a wire.

前記半導体チップ、ワイヤ及びワイヤ接続用電極パッド等は、ベース基板の一表面上に形成された樹脂封止体で封止されている。樹脂封止体は、大量生産に好適なトランスファモールド法で形成される。   The semiconductor chip, wires, wire connection electrode pads, and the like are sealed with a resin sealing body formed on one surface of the base substrate. The resin sealing body is formed by a transfer mold method suitable for mass production.

このように構成されたＢＧＡ構造の半導体装置は、実装基板の実装面に形成された電極パッドにそのバンプ電極を溶融接続することにより、実装基板の実装面上に実装される。   The semiconductor device having the BGA structure configured as described above is mounted on the mounting surface of the mounting substrate by melting and connecting the bump electrodes to the electrode pads formed on the mounting surface of the mounting substrate.

なお、前記ＢＧＡ構造の半導体装置については、例えば、日経ＢＰ社発行の日経エレクトロニクス〔１９９４年、２月２８日号、第１１１頁乃至第１１７頁〕に記載されている。
日経ＢＰ社発行の日経エレクトロニクス〔１９９４年、２月２８日号、第１１１頁乃至第１１７頁〕 The semiconductor device having the BGA structure is described in, for example, Nikkei Electronics (February 28, 1994, pages 111 to 117) issued by Nikkei BP.
Nikkei Electronics, published by Nikkei BP (February 28, 1994, pages 111 to 117)

近年、ベース基板として可撓性フィルムを用いたＢＧＡ構造の半導体装置が開発されている。このＢＧＡ構造の半導体装置は、ベース基板として硬質の樹脂基板を用いた半導体装置に比べて、薄型化、多ピン化及び小型化を図ることができる。しかしながら、本発明者等は、ベース基板として可撓性フィルムを用いた半導体装置の開発中に以下の問題点を見出した。   In recent years, semiconductor devices having a BGA structure using a flexible film as a base substrate have been developed. This BGA structure semiconductor device can be made thinner, more pins, and smaller than a semiconductor device using a hard resin substrate as a base substrate. However, the present inventors have found the following problems during development of a semiconductor device using a flexible film as a base substrate.

可撓性フィルムからなるベース基板は、一般的に、可撓性フィルムのバンプ接続領域に接続孔を形成し、その後、可撓性フィルムの片面側に接着材を介在して例えば銅(Ｃｕ)からなる金属箔を貼り付け、その後、金属箔にパターンニングを施し、パンプ接続用電極パッド、配線、ワイヤ接続用電極パッド及びメッキ用配線等からなる配線導体を形成し、その後、配線導体を保護する絶縁膜を形成し、その後、バンプ接続用電極パッド及びワイヤ接続用電極パッドにメッキ層を形成するためのメッキ処理を施すことによって形成される。メッキ処理は電解メッキ法で行なわれる。このメッキ処理は、絶縁膜を形成する前の段階において行う場合もある。メッキ層は、例えば、金(Ａｕ)／ニッケル(Ｎｉ)膜、又はＡｕ／パラジウム(Ｐｄ)／Ｎｉ膜で形成される。   A base substrate made of a flexible film generally forms a connection hole in a bump connection region of the flexible film, and then, for example, copper (Cu) with an adhesive interposed on one side of the flexible film. A metal foil made of is attached, and then patterning is applied to the metal foil to form a wiring conductor made up of bump connection electrode pads, wiring, wire connection electrode pads, plating wiring, etc., and then the wiring conductor is protected. An insulating film to be formed is formed, and thereafter, a plating process for forming a plating layer is performed on the bump connection electrode pad and the wire connection electrode pad. The plating process is performed by an electrolytic plating method. This plating process may be performed before the insulating film is formed. The plating layer is formed of, for example, a gold (Au) / nickel (Ni) film or an Au / palladium (Pd) / Ni film.

前記絶縁膜は、例えば、可撓性フィルムの片面側に感光性樹脂膜を形成し、ベーク処理を施した後、写真印刷技術を使用し、感光処理、現像処理、洗浄処理を施すことにより形成される。絶縁膜は、ワイヤ接続用電極パッドを除いた配線導体上を含む可撓性フィルムの片面側のほぼ全域に形成されている。即ち、可撓性フィルムの片面側のほぼ全域に絶縁膜が形成されるため、ベース基板に反り、歪み等の変形が生じる。このベース基板の変形は、半導体装置の製造プロセス（組立プロセス）中における搬送トラブルの原因となったり、半導体チップを搭載する工程において、接着材の濡れ性を悪くする原因となる。   The insulating film is formed by, for example, forming a photosensitive resin film on one side of a flexible film, performing a baking process, and then performing a photosensitive process, a developing process, and a cleaning process using a photographic printing technique. Is done. The insulating film is formed over almost the entire area of one side of the flexible film including the wiring conductor excluding the electrode pad for wire connection. That is, since the insulating film is formed on almost the entire area on one side of the flexible film, the base substrate is warped and deformation such as distortion occurs. The deformation of the base substrate may cause a conveyance trouble during the manufacturing process (assembly process) of the semiconductor device, and may deteriorate the wettability of the adhesive in the process of mounting the semiconductor chip.

前記ベース基板の変形は、絶縁膜の熱膨張係数及び硬化収縮率が大きいことが主要因であるが、絶縁膜を形成しない場合は以下の問題が生じる。   The deformation of the base substrate is mainly due to the large thermal expansion coefficient and cure shrinkage rate of the insulating film, but the following problems arise when the insulating film is not formed.

（１）ベース基板の一表面のチップ搭載領域にはバンプ接続用電極パッドが配置されている。このため、ベース基板の一表面のチップ搭載領域に絶縁性の接着材を塗布して半導体チップを搭載する際、接着材の厚さの制御が難しく、バンプ接続用電極パッドに半導体チップが接触し、両者間において短絡が生じる。 (1) Bump connection electrode pads are arranged in a chip mounting region on one surface of the base substrate. Therefore, when mounting a semiconductor chip by applying an insulating adhesive to the chip mounting area on one surface of the base substrate, it is difficult to control the thickness of the adhesive, and the semiconductor chip comes into contact with the bump connection electrode pads. A short circuit occurs between the two.

（２）ベース基板の一表面のチップ搭載領域にはバンプ接続用電極パッドが配置され、このバンプ接続用電極パッドには、ベース基板のチップ搭載領域に形成された接続孔を通して、ベース基板の裏面側に配置されたバンプ電極が接続されている。即ち、半導体チップの下部にはバンプ電極が配置されている。 (2) A bump connection electrode pad is disposed on the chip mounting region on one surface of the base substrate, and the back surface of the base substrate is connected to the bump connection electrode pad through a connection hole formed in the chip mounting region of the base substrate. Bump electrodes arranged on the side are connected. That is, the bump electrode is disposed below the semiconductor chip.

前記ベース基板のチップ搭載領域に配置されたバンプ接続用電極パッドは、ベース基板の一表面のチップ搭載領域の周囲を囲むその周辺領域に配置されたワイヤ接続用電極パッドに配線を介して一体化され、電気的に接続されている。即ち、ベース基板の一表面の周辺領域において、半導体チップとワイヤ接続用電極パッドとの間の領域には配線が配置されている。このため、半導体チップの外部端子とワイヤ接続用パッドとをワイヤで接続する際、ワイヤとこのワイヤに電気的に接続された配線に隣接する他の配線とが交差する場合がある。ワイヤの高さが充分ある場合は問題ないが、特に、半導体チップの角部において、ワイヤと他の配線とが平行になっていない場合や、ワイヤ接続用電極パッド側でワイヤと他の配線とが交差する場合は、ワイヤと他の配線との短絡が生じる可能性がある。   The bump connection electrode pad arranged in the chip mounting area of the base substrate is integrated with the wire connection electrode pad arranged in the peripheral area surrounding the chip mounting area on one surface of the base substrate through wiring. Are electrically connected. That is, in the peripheral region on the one surface of the base substrate, the wiring is arranged in a region between the semiconductor chip and the wire connection electrode pad. For this reason, when the external terminal of the semiconductor chip and the wire connection pad are connected by a wire, the wire and another wiring adjacent to the wiring electrically connected to the wire may intersect each other. There is no problem if the height of the wire is sufficient, but in particular, when the wire and other wiring are not parallel at the corner of the semiconductor chip, or when the wire and other wiring are If the crosses, a short circuit between the wire and other wiring may occur.

本発明の目的は、可撓性フィルムからなるベース基板を有する半導体装置において、ベース基板の変形(反り、歪み)を抑制することが可能な技術を提供することにある。   An object of the present invention is to provide a technology capable of suppressing deformation (warpage, distortion) of a base substrate in a semiconductor device having a base substrate made of a flexible film.

本発明の他の目的は、可撓性フィルムからなるベース基板を有する半導体装置において、ベース基板の変形を抑制すると共に、ベース基板の配線導電体と半導体チップとの短絡を防止することが可能な技術を提供することにある。   Another object of the present invention is to suppress deformation of the base substrate and prevent a short circuit between the wiring conductor of the base substrate and the semiconductor chip in a semiconductor device having a base substrate made of a flexible film. To provide technology.

本発明の他の目的は、可撓性フィルムからなるベース基板を有する半導体装置において、ベース基板の変形を抑制すると共に、ベース基板の配線導体とワイヤとの短絡を防止することが可能な技術を提供することにある。   Another object of the present invention is to provide a technology capable of suppressing deformation of a base substrate and preventing a short circuit between a wiring conductor and a wire of the base substrate in a semiconductor device having a base substrate made of a flexible film. It is to provide.

本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述及び添付図面によって明らかになるであろう。   The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、下記のとおりである。   Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

（１）可撓性フィルムからなるベース基板の一表面に配線導体が配置され、前記ベース基板の一表面上に接着材を介在して半導体チップが搭載される半導体装置であって、前記ベース基板の一表面上において絶縁膜を複数個に分割し、この絶縁膜を前記配線導体上に配置する。絶縁膜の分割は、例えば配線導体毎に行う。 (1) A semiconductor device in which a wiring conductor is disposed on one surface of a base substrate made of a flexible film, and a semiconductor chip is mounted on one surface of the base substrate with an adhesive interposed therebetween, wherein the base substrate An insulating film is divided into a plurality on one surface, and this insulating film is disposed on the wiring conductor. The insulating film is divided for each wiring conductor, for example.

（２）可撓性フィルムからなるベース基板の一表面のチップ搭載領域に配線導体が配置され、前記ベース基板の一表面のチップ搭載領域上に接着材を介在して半導体チップが搭載される半導体装置であって、前記ベース基板上において絶縁膜を複数個に分割し、この絶縁膜を前記配線導体上に配置する。絶縁膜の分割は、例えば配線導体毎に行う。 (2) A semiconductor in which a wiring conductor is disposed on a chip mounting region on one surface of a base substrate made of a flexible film, and a semiconductor chip is mounted on the chip mounting region on one surface of the base substrate via an adhesive material In the apparatus, an insulating film is divided into a plurality of parts on the base substrate, and the insulating film is disposed on the wiring conductor. The insulating film is divided for each wiring conductor, for example.

（３）可撓性フィルムからなるベース基板の一表面のチップ搭載領域に接着材を介在して半導体チップが搭載され、前記ベース基板の一表面のチップ搭載領域を囲むその周辺領域にワイヤ接続用電極パッドが配置され、前記ベース基板の一表面の周辺領域において前記半導体チップと前記ワイヤ接続用電極パッドとの間の領域に配線が配置され、前記半導体チップの外部端子と前記ワイヤ接続用電極パッドとがワイヤを介して電気的に接続される半導体装置であって、前記ベース基板の一表面上において絶縁膜を複数個に分割し、この絶縁膜を前記配線上に配置する。 (3) A semiconductor chip is mounted on a chip mounting region on one surface of a base substrate made of a flexible film with an adhesive interposed therebetween, and a wire connection is made in a peripheral region surrounding the chip mounting region on one surface of the base substrate. An electrode pad is disposed, and a wiring is disposed in a region between the semiconductor chip and the wire connection electrode pad in a peripheral region on one surface of the base substrate, and the external terminal of the semiconductor chip and the wire connection electrode pad Are electrically connected via wires, and an insulating film is divided into a plurality on one surface of the base substrate, and the insulating film is disposed on the wiring.

上述した手段（１）によれば、絶縁膜の膨張及び硬化収縮による応力が緩和されるので、ベース基板の変形(反り、歪み)を抑制できる。   According to the means (1) described above, stress due to expansion and cure shrinkage of the insulating film is relieved, so that deformation (warpage, distortion) of the base substrate can be suppressed.

上述した手段（２）によれば、ベース基板の一表面のチップ搭載領域に接着材を塗布して半導体チップを搭載する際、配線導体に半導体チップが接触しないので、配線導体と半導体チップとの短絡を防止できる。   According to the means (2) described above, when the semiconductor chip is mounted by applying an adhesive to the chip mounting area on one surface of the base substrate, the semiconductor chip does not contact the wiring conductor. Short circuit can be prevented.

上述した手段（３）によれば、配線にワイヤが接触しないので、ベース基板の配線導体とワイヤとの短絡を防止できる。   According to the means (3) described above, since the wire does not contact the wiring, a short circuit between the wiring conductor of the base substrate and the wire can be prevented.

本願において開示される発明のうち代表的なものによって得られる効果を簡単に説明すれば、下記のとおりである。   The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

可撓性フィルムからなるベース基板を有する半導体装置において、ベース基板の変形(反り、歪み)を抑制できる。   In a semiconductor device having a base substrate made of a flexible film, deformation (warpage or distortion) of the base substrate can be suppressed.

可撓性フィルムからなるベース基板を有する半導体装置において、ベース基板の変形を抑制できる共に、ベース基板の配線導電体と半導体チップとの短絡を防止できる。   In a semiconductor device having a base substrate made of a flexible film, deformation of the base substrate can be suppressed and a short circuit between the wiring conductor of the base substrate and the semiconductor chip can be prevented.

可撓性フィルムからなるベース基板を有する半導体装置において、ベース基板の変形を抑制できる共に、ベース基板の配線導体とワイヤとの短絡を防止できる。   In a semiconductor device having a base substrate made of a flexible film, deformation of the base substrate can be suppressed and a short circuit between a wiring conductor and a wire of the base substrate can be prevented.

以下、本発明の構成について、ＢＧＡ構造の半導体装置に本発明を適用した実施の形態とともに説明する。なお、実施の形態を説明するための図面において、同一機能を有するものは同一符号を付け、その繰り返しの説明は省略する。   The configuration of the present invention will be described below together with an embodiment in which the present invention is applied to a BGA structure semiconductor device. Note that components having the same function are denoted by the same reference symbols in the drawings for describing the embodiments, and the repetitive description thereof is omitted.

図１は本発明の一実施形態である半導体装置の平面図であり、図２は図１に示すＡ−Ａ線の位置で切った拡大断面図であり、図３は図２の要部拡大断面図であり、図４は樹脂封止体を除去した状態の平面図であり、図５はベース基板の平面図であり、図６は前記半導体装置の要部拡大断面図である。   FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is an enlarged cross-sectional view taken along the line AA shown in FIG. 1, and FIG. 4 is a plan view showing a state where a resin sealing body is removed, FIG. 5 is a plan view of a base substrate, and FIG. 6 is an enlarged cross-sectional view of a main part of the semiconductor device.

図１、図２及び図３に示すように、半導体装置は、ベース基板１の一表面のチップ搭載領域上に接着材１２を介在して半導体チップ１０を搭載し、ベース基板１の一表面と対向するその裏面側に複数のバンプ電極１５を格子状に配置した構成になっている。バンプ電極１５は例えば６３［重量％］Ｐｂ−３７［重量％］Ｓｎ組成の半田材で形成されている。本実施形態の半導体装置は、ＣＳＰ（Ｃhip Ｓize Ｐackage)構造で構成されている。   As shown in FIGS. 1, 2, and 3, the semiconductor device has a semiconductor chip 10 mounted on a chip mounting region on one surface of the base substrate 1 with an adhesive 12 interposed therebetween, A plurality of bump electrodes 15 are arranged in a grid pattern on the opposite back side. The bump electrode 15 is made of, for example, a solder material having a composition of 63 [wt%] Pb-37 [wt%] Sn. The semiconductor device according to the present embodiment has a CSP (Chip Size Package) structure.

前記ベース基板１の平面形状は方形状で形成されている。このベース基板１は、例えばエポキシ系の絶縁樹脂若しくはポリイミド系の絶縁樹脂からなる可撓性フィルムで形成されている。ベース基板１は、例えば５０［μｍ］程度の厚さに設定されている。   The planar shape of the base substrate 1 is a square shape. The base substrate 1 is formed of a flexible film made of, for example, an epoxy insulating resin or a polyimide insulating resin. The base substrate 1 is set to a thickness of about 50 [μm], for example.

前記ベース基板１の一表面には、バンプ接続用電極パッド２、配線３、ワイヤ接続用電極パッド４及びメッキ用配線５等からなる配線導電体が配置されている。バンプ接続用電極パッド２及びワイヤ接続用電極パッド４は複数個設けられ、配線３及びメッキ用配線５は複数本設けられている。即ち、ベース基板１の一表面には複数本の配線導体が配置されている。バンプ接続用電極パッド２は配線３を介してワイヤ接続用電極パッド４と一体化され、互いに電気的に接続されている。メッキ用配線５はワイヤ接続用電極パッド４と一体化され、互いに電気的に接続されている。バンプ接続用電極パッド２、配線３、ワイヤ接続用電極パッド４及びメッキ用配線５等は、可撓性フィルムの一表面に接着材を介在して例えばＣｕ箔からなる金属箔を貼り付けた後、この金属箔にエッチング処理を施すことによって形成される。これらのバンプ接続用電極パッド２、配線３、ワイヤ接続用電極パッド４及びメッキ用配線５は、例えば１８［μｍ］程度の厚さに設定されている。   On one surface of the base substrate 1, a wiring conductor including a bump connection electrode pad 2, a wiring 3, a wire connection electrode pad 4, a plating wiring 5 and the like is disposed. A plurality of bump connection electrode pads 2 and wire connection electrode pads 4 are provided, and a plurality of wirings 3 and plating wirings 5 are provided. That is, a plurality of wiring conductors are disposed on one surface of the base substrate 1. The bump connection electrode pad 2 is integrated with the wire connection electrode pad 4 via the wiring 3 and is electrically connected to each other. The plating wiring 5 is integrated with the wire connection electrode pad 4 and is electrically connected to each other. The bump connection electrode pad 2, the wiring 3, the wire connection electrode pad 4, the plating wiring 5, and the like are bonded to one surface of a flexible film with a metal foil made of Cu foil, for example, with an adhesive interposed therebetween. The metal foil is formed by performing an etching process. The bump connecting electrode pad 2, the wiring 3, the wire connecting electrode pad 4, and the plating wiring 5 are set to a thickness of, for example, about 18 [μm].

前記半導体チップ１０の平面形状は方形状で形成されている。この半導体チップ１０は、例えば単結晶珪素からなる半導体基板を主体とする構成になっている。半導体チップ１０には、論理回路システム、記憶回路システム、或いはそれらの混合回路システムが搭載されている。これらの回路システムは、半導体チップ１０の主面(素子形成面)１０Ａ側に形成された複数の半導体素子を配線で接続することによって形成される。   The planar shape of the semiconductor chip 10 is a square shape. The semiconductor chip 10 is configured mainly with a semiconductor substrate made of, for example, single crystal silicon. The semiconductor chip 10 is mounted with a logic circuit system, a memory circuit system, or a mixed circuit system thereof. These circuit systems are formed by connecting a plurality of semiconductor elements formed on the main surface (element forming surface) 10A side of the semiconductor chip 10 by wiring.

前記半導体チップ１０の主面１０Ａには、半導体チップ１０の各辺に沿って配列された複数の外部端子(ボンディングパッド)１１が配置されている。この複数の外部端子１１の夫々は、半導体基板の主面上に形成された配線層のうち、最上層の配線層に形成され、例えばアルミニウム(Ａｌ)膜若しくはアルミニウム合金膜で形成されている。また、複数の外部端子１１の夫々は、半導体チップ１０に搭載された回路システムに電気的に接続されている。   A plurality of external terminals (bonding pads) 11 arranged along each side of the semiconductor chip 10 are arranged on the main surface 10A of the semiconductor chip 10. Each of the plurality of external terminals 11 is formed in the uppermost wiring layer among the wiring layers formed on the main surface of the semiconductor substrate, and is formed of, for example, an aluminum (Al) film or an aluminum alloy film. Each of the plurality of external terminals 11 is electrically connected to a circuit system mounted on the semiconductor chip 10.

前記複数のバンプ接続用電極パッド２のうち、大部分のバンプ接続用電極パッド２はベース基板１の一表面のチップ搭載領域に配置され、その他(残り)のバンプ接続用電極パッド２は、ベース基板１の一表面のチップ搭載領域の周囲を囲むその周辺領域に配置されている。この複数のバンプ接続用電極パッド２の夫々の裏面には、ベース基板１に形成された接続孔６を通して、ベース基板１の裏面側に配置された複数のバンプ電極１５の夫々が固着され、電気的にかつ機械的に接続されている。なお、本実施形態において、バンプ接続用電極パッド２の平面形状は円形状で形成されている。   Among the plurality of bump connection electrode pads 2, most of the bump connection electrode pads 2 are arranged in the chip mounting region on one surface of the base substrate 1, and the other (remaining) bump connection electrode pads 2 are formed on the base. The substrate 1 is disposed in a peripheral region surrounding the periphery of the chip mounting region on one surface. The plurality of bump electrodes 15 disposed on the back surface side of the base substrate 1 are fixed to the back surfaces of the plurality of bump connection electrode pads 2 through the connection holes 6 formed in the base substrate 1. Connected mechanically and mechanically. In the present embodiment, the planar shape of the bump connection electrode pad 2 is circular.

前記複数のワイヤ接続用電極パッド４の夫々は、図２、図３及び図４に示すように、ベース基板１の一表面の周辺領域に配置され、半導体チップ１０の各辺に沿って配列されている。複数のワイヤ接続用電極パッド４の夫々は、半導体チップ１０の主面１０Ａに配置された複数の外部端子１１の夫々にワイヤ１３を介して電気的に接続されている。ワイヤ１３としては例えばＡｕワイヤが用いられている。ワイヤ１３は、例えば熱圧着に超音波振動を併用したボンディング法で接続される。   As shown in FIGS. 2, 3, and 4, each of the plurality of wire connection electrode pads 4 is disposed in a peripheral region on one surface of the base substrate 1 and arranged along each side of the semiconductor chip 10. ing. Each of the plurality of wire connection electrode pads 4 is electrically connected to each of the plurality of external terminals 11 disposed on the main surface 10 </ b> A of the semiconductor chip 10 via wires 13. For example, an Au wire is used as the wire 13. For example, the wire 13 is connected by a bonding method in which ultrasonic vibration is used in combination with thermocompression bonding.

前記複数本の配線３のうち、ベース基板１の一表面のチップ搭載領域に配置されたバンプ接続用電極パッド２と一体化された配線３はベース基板１の一表面のチップ搭載領域及び周辺領域を延在し、ベース基板１の一表面の周辺領域に配置されたバンプ接続用電極パッド２と一体化された配線３はベース基板１の一表面の周辺領域に延在している。即ち、ベース基板１の一表面の周辺領域において、半導体チップ１とワイヤ接続用電極パッド４との間の領域には配線３が配置されている。   Among the plurality of wirings 3, the wiring 3 integrated with the bump connection electrode pad 2 disposed in the chip mounting region on one surface of the base substrate 1 is a chip mounting region and a peripheral region on one surface of the base substrate 1. The wiring 3 integrated with the bump connection electrode pad 2 arranged in the peripheral region on one surface of the base substrate 1 extends in the peripheral region on one surface of the base substrate 1. That is, in the peripheral region on one surface of the base substrate 1, the wiring 3 is arranged in the region between the semiconductor chip 1 and the wire connection electrode pad 4.

前記半導体チップ１０、配線３、ワイヤ接続用電極パッド４及びワイヤ１３等は樹脂封止体１４で封止されている。樹脂封止体１４は、低応力化を図る目的として、例えばフェノール系硬化剤、シリコーンゴム及びフィラーが添加されたエポキシ系の樹脂で形成されている。樹脂封止体１４は、大量生産に好適なトランスファモールド法で形成されている。トランスファモールド法は、ポット、ランナー、ゲート及びキャビティ等を備えたモールド金型を使用し、ポットからランナー及びゲートを通してキャビティ内に樹脂を加圧注入して樹脂封止体を形成する方法である。   The semiconductor chip 10, the wiring 3, the wire connection electrode pad 4, the wire 13 and the like are sealed with a resin sealing body 14. For the purpose of reducing the stress, the resin sealing body 14 is formed of, for example, an epoxy resin to which a phenolic curing agent, silicone rubber, and a filler are added. The resin sealing body 14 is formed by a transfer mold method suitable for mass production. The transfer mold method is a method of forming a resin sealing body by using a mold die provided with a pot, a runner, a gate, a cavity, and the like, and pressure-injecting resin into the cavity from the pot through the runner and the gate.

前記複数のメッキ用配線５の夫々は、ベース基板１の一表面の周辺領域において、ワイヤ接続用電極パッド４の外側に配置されている。この複数のメッキ用配線５の夫々は、半導体チップ１０の各辺に沿って配列されている。メッキ用配線５の一部分は樹脂封止体１４の内部に配置され、他の部分は樹脂封止体樹脂封止体の外側に配置されている。   Each of the plurality of plating wirings 5 is disposed outside the wire connection electrode pad 4 in the peripheral region of one surface of the base substrate 1. Each of the plurality of plating wirings 5 is arranged along each side of the semiconductor chip 10. A part of the plating wiring 5 is disposed inside the resin sealing body 14, and the other part is disposed outside the resin sealing body resin sealing body.

前記ベース基板１の一表面のチップ搭載領域に配置された複数のバンプ接続用電極パッド２の夫々の上面上には、図２、図３及び図５に示すように、絶縁膜９が配置されている。この絶縁膜９は、ベース基板１の一表面のチップ搭載領域において、バンプ接続用電極パッド２毎に分割されている。絶縁膜９は、ベース基板１の一表面のチップ搭載領域において点在するように複数個に分割されている。即ち、本実施形態の半導体装置は、ベース基板１の一表面のチップ搭載領域において絶縁膜９を複数個に分割し、この絶縁膜９をバンプ接続用電極パッド２上に配置している。なお、本実施形態において、バンプ接続用電極パッド２上に配置された絶縁膜９の平面形状は円形状で形成されている。   As shown in FIGS. 2, 3, and 5, an insulating film 9 is disposed on the upper surface of each of the plurality of bump connection electrode pads 2 disposed in the chip mounting region on one surface of the base substrate 1. ing. The insulating film 9 is divided for each bump connection electrode pad 2 in the chip mounting region on one surface of the base substrate 1. The insulating film 9 is divided into a plurality of parts so as to be scattered in the chip mounting region on one surface of the base substrate 1. That is, in the semiconductor device of this embodiment, the insulating film 9 is divided into a plurality of parts in the chip mounting region on the one surface of the base substrate 1, and the insulating film 9 is disposed on the bump connection electrode pad 2. In the present embodiment, the planar shape of the insulating film 9 disposed on the bump connection electrode pad 2 is circular.

前記ベース基板１の一表面の周辺領域に配置された複数のメッキ用配線５の夫々の上面上には、絶縁膜９が配置されている。この絶縁膜９は、ベース基板１の各辺に沿って延在し、ベース基板１の各辺毎に分割されている。絶縁膜９は、ベース基板１の周辺領域において点在するように複数個に分割されている。即ち、本実施形態の半導体装置は、ベース基板１の一表面の周辺領域において絶縁膜９を複数個に分割し、この絶縁膜９をメッキ用配線５上に配置している。   An insulating film 9 is disposed on the upper surface of each of the plurality of plating wirings 5 disposed in the peripheral region of one surface of the base substrate 1. The insulating film 9 extends along each side of the base substrate 1 and is divided for each side of the base substrate 1. The insulating film 9 is divided into a plurality of portions so as to be scattered in the peripheral region of the base substrate 1. That is, in the semiconductor device according to the present embodiment, the insulating film 9 is divided into a plurality of parts in the peripheral region on one surface of the base substrate 1, and the insulating film 9 is arranged on the plating wiring 5.

前記メッキ用配線５上に配置された絶縁膜９の一部分は樹脂封止体１４の内部に配置され、他の部分は樹脂封止体１４の外側に配置されている。即ち、メッキ用配線５と樹脂封止体１４との間には絶縁膜９が介在されている。   A part of the insulating film 9 disposed on the plating wiring 5 is disposed inside the resin sealing body 14, and the other part is disposed outside the resin sealing body 14. That is, the insulating film 9 is interposed between the plating wiring 5 and the resin sealing body 14.

前記ベース基板１のチップ搭載領域には、図５及び図６に示すように、ベントホール７が設けられている。このように、ベース基板１のチップ搭載領域にベントホール７を設けることにより、ベース基板１の一表面のチップ搭載領域上に接着材１２を塗布して半導体チップ１０を搭載する際、接着材１２の硬化時に発生するアウトガスを外部に放出することができる。また、半導体装置の製品完成後の環境試験である温度サイクル試験時の熱や実装基板の実装面上に半導体装置を実装する実装時の熱によって接着材１２に発生した水蒸気を外部に放出することができる。   As shown in FIGS. 5 and 6, a vent hole 7 is provided in the chip mounting region of the base substrate 1. Thus, by providing the vent hole 7 in the chip mounting area of the base substrate 1, the adhesive 12 is applied when the semiconductor chip 10 is mounted by applying the adhesive 12 on the chip mounting area on one surface of the base substrate 1. The outgas generated during the curing of can be released to the outside. Also, the water vapor generated in the adhesive 12 due to heat during a temperature cycle test, which is an environmental test after completion of the product of the semiconductor device, and heat during mounting for mounting the semiconductor device on the mounting surface of the mounting substrate is released to the outside. Can do.

前記ベース基板１の一表面のチップ搭載領域上には、ベントホール７の周囲を囲むダム８が設けられている。本実施形態のダム８は、導電膜８Ａ及びこの導電膜８Ａ上に配置された絶縁膜９で構成されている。   On the chip mounting area on one surface of the base substrate 1, a dam 8 surrounding the vent hole 7 is provided. The dam 8 of the present embodiment is composed of a conductive film 8A and an insulating film 9 disposed on the conductive film 8A.

前記ベントホール７は、図５に示すように、ベース基板１のＸ方向（図中、横方向）の中心線Ｐ１及びベース基板１のＹ方向（図中、縦方向）の中心線Ｐ２からずれた位置に配置されている。即ち、ベントホール７は、ベース基板１の中心からずれた位置に配置されている。このように、ベントホール７をベース基板１の中心からずれた位置に配置することにより、ベース基板１の裏面側から半導体装置を見た場合、インデックスとして方向を明確化できる。また、インデックスとして方向を明確化できるので、ベントホール７をインデックスとして兼用できる。   As shown in FIG. 5, the vent hole 7 is displaced from the center line P1 of the base substrate 1 in the X direction (horizontal direction in the figure) and the center line P2 of the base substrate 1 in the Y direction (vertical direction in the figure). It is arranged at the position. That is, the vent hole 7 is arranged at a position shifted from the center of the base substrate 1. Thus, by arranging the vent hole 7 at a position shifted from the center of the base substrate 1, the direction can be clarified as an index when the semiconductor device is viewed from the back side of the base substrate 1. Further, since the direction can be clarified as an index, the vent hole 7 can also be used as an index.

次に、前記半導体装置の製造プロセスで使用されるフレーム構造体について説明する。   Next, a frame structure used in the semiconductor device manufacturing process will be described.

図７(要部平面図)に示すように、フレーム構造体２０は、これに限定されないが、例えば枠体２１で規定された領域を一方向に複数個配置した多連フレーム構造で構成されている。枠体２１で規定された各領域内にはフィルム基材１Ａが配置されている。本実施形態のフィルム基材１Ａは四つの樹脂封止領域２２を備えている。即ち、枠体２１で規定された各領域内には四つの製品を形成するためのフィルム基材１Ａが配置されている。なお、樹脂封止領域２２には、図５に示す配線導体パターンが形成されている。   As shown in FIG. 7 (principal plan view), the frame structure 20 is not limited to this. For example, the frame structure 20 has a multiple frame structure in which a plurality of regions defined by the frame 21 are arranged in one direction. Yes. A film substrate 1 </ b> A is disposed in each region defined by the frame body 21. The film base 1 </ b> A of the present embodiment includes four resin sealing regions 22. That is, the film base 1 </ b> A for forming four products is arranged in each region defined by the frame body 21. Note that a wiring conductor pattern shown in FIG. 5 is formed in the resin sealing region 22.

前記枠体２１は、板材にエッチング加工又はプレス打抜き加工を施すことにより形成される。板材としては、例えばＣｕ系合金材からなるものを用いる。   The frame body 21 is formed by subjecting a plate material to etching processing or press punching processing. As the plate material, for example, a material made of a Cu-based alloy material is used.

前記フィルム基材１Ａは、図７及び図８（図７に示すＢ−Ｂ線の位置で切った断面図）に示すように、枠体２１の互いに対向する２個所の接着領域に接着材２４を介在して固定されている。枠体２１の夫々の接着領域にはスリット２３が設けられている。このスリット２３は、フレーム構造体２０の長手方向に所定の間隔を置いて複数個配置されている。このように、枠体２１の接着領域にスリット２３を設けることにより、枠体２１とフィルム基材１Ａとの材料の違いによる応力を緩和できるので、フィルム基材１Ａの反り、歪み等の変形を抑制できる。   As shown in FIGS. 7 and 8 (cross-sectional view taken along the line BB shown in FIG. 7), the film base material 1A has an adhesive 24 in two adhesive regions facing each other on the frame body 21. Is fixed. A slit 23 is provided in each bonding region of the frame body 21. A plurality of the slits 23 are arranged at predetermined intervals in the longitudinal direction of the frame structure 20. As described above, by providing the slits 23 in the adhesion region of the frame body 21, stress due to the difference in material between the frame body 21 and the film base material 1A can be relieved, so that deformation such as warping and distortion of the film base material 1A can be achieved. Can be suppressed.

次に、前記フレーム構造体２０の製造方法について、図９及び図１０（製造方法を説明するための要部断面図）を用いて説明する。   Next, a method for manufacturing the frame structure 20 will be described with reference to FIGS. 9 and 10 (main-part cross-sectional views for explaining the manufacturing method).

まず、図９−(Ａ)に示すように、フィルム基材１Ａを準備する。フィルム基材１Ａは、例えばエポキシ系の絶縁樹脂若しくはポリイミド系の絶縁樹脂で形成される。次に、図９−(Ｂ)に示すように、前記フィルム基材１Ａの一表面側に接着材３０を貼り付ける。接着材３０を使用せず、熱加圧によっても製造できる。   First, as shown to FIG. 9- (A), 1 A of film base materials are prepared. The film base 1A is formed of, for example, an epoxy insulating resin or a polyimide insulating resin. Next, as shown in FIG. 9- (B), the adhesive material 30 is affixed on the one surface side of the said film base material 1A. It can also be manufactured by heat and pressure without using the adhesive 30.

次に、図９−(Ｃ)に示すように、前記フィルム基材１Ａのバンプ接続領域に接続孔６を形成すると共に、図示していないが、フィルム基材１Ａのチップ搭載領域にベントホール７を形成する。接続孔６及びベントホール７の形成は、例えば金型若しくはレーザ加工等により行う。次に、図９−(Ｄ)に示すように、前記フィルム基材１Ａの一表面側に接着材３０を介在して金属箔(例えばＣｕ箔)３１を貼り付ける。フィルム基材１Ａに金属箔３１を貼り付けた後、金型若しくはレーザ加工等により接続孔６及びベントホール７を形成することもできる。   Next, as shown in FIG. 9- (C), the connection holes 6 are formed in the bump connection region of the film base 1A, and the vent hole 7 is formed in the chip mounting region of the film base 1A. Form. The connection hole 6 and the vent hole 7 are formed by, for example, a mold or laser processing. Next, as shown in FIG. 9- (D), a metal foil (for example, Cu foil) 31 is attached to one surface side of the film base 1A with an adhesive 30 interposed therebetween. After the metal foil 31 is attached to the film base 1A, the connection hole 6 and the vent hole 7 can be formed by a mold or laser processing.

次に、前記金属箔３１にパターンニングを施し、図９−(Ｅ)に示すように、フィルム基材１Ａの一表面にバンプ接続用電極パッド２を形成すると共に、図示していないが、配線３、ワイヤ接続用電極パッド４及びメッキ用配線５等を形成する。即ち、この工程において配線導体パターンが形成される。また、この工程において、図示していないが、フィルム基材１Ａの一表面のチップ搭載領域に、ベントホール７の周囲を囲む導電膜８Ａも形成される。   Next, patterning is performed on the metal foil 31, and as shown in FIG. 9- (E), a bump connection electrode pad 2 is formed on one surface of the film base 1A. 3. Wire connection electrode pads 4 and plating wirings 5 are formed. That is, a wiring conductor pattern is formed in this step. In this step, although not shown, a conductive film 8A surrounding the periphery of the vent hole 7 is also formed in the chip mounting region on one surface of the film base 1A.

次に、図１０−(Ｆ)に示すように、前記配線導体パターン上を含むフィルム基材１Ａ上の全面に均一な膜厚の感光性樹脂膜３２を形成する。感光性樹脂膜３２の形成は、感光性樹脂を塗布した後、スクリーン印刷法によって行う。次に、ベーク処理を施した後、写真印刷技術を使用し、感光処理、現像処理、洗浄処理等を施して、図１０−(Ｇ)に示すように、所定のパターンの絶縁膜９を形成する。この工程において、図５に示すように、複数個に分割された絶縁膜９が配線導体上に配置される。また、この工程において、導電膜８Ａ及びこの導電膜８Ａ上に配置された絶縁膜９からなるダム８も形成される。フィルム基材１Ａ上の全面に絶縁膜９を配置した場合、フィルム基材１Ａ、配線導体、絶縁膜９等の材料特性の違いにより、ベース基板１に反り、歪み等の変形が生じるが、本実施形態のように、絶縁膜９を分割して配置することにより、絶縁膜９の膨張及び硬化収縮による応力が緩和されるので、ベース基板１の変形を抑制できる。   Next, as shown in FIG. 10- (F), a photosensitive resin film 32 having a uniform film thickness is formed on the entire surface of the film substrate 1A including the wiring conductor pattern. The photosensitive resin film 32 is formed by a screen printing method after applying a photosensitive resin. Next, after baking, a photo printing technique is used to perform photosensitive processing, development processing, cleaning processing, and the like, thereby forming an insulating film 9 having a predetermined pattern as shown in FIG. To do. In this step, as shown in FIG. 5, the insulating film 9 divided into a plurality of parts is disposed on the wiring conductor. In this step, a dam 8 including the conductive film 8A and the insulating film 9 disposed on the conductive film 8A is also formed. When the insulating film 9 is disposed on the entire surface of the film substrate 1A, the base substrate 1 is warped and deformed, such as distortion, due to the difference in material characteristics of the film substrate 1A, the wiring conductor, the insulating film 9, etc. Since the insulating film 9 is divided and disposed as in the embodiment, stress due to expansion and curing shrinkage of the insulating film 9 is relieved, so that deformation of the base substrate 1 can be suppressed.

次に、電解メッキ法でメッキ処理を施し、ワイヤボンディングが可能なメッキ層（例えば、Ａｕ／Ｎｉ層、Ａｕ／Ｐｄ／Ｎｉ層、Ｐｄ／Ｎｉ層、Ｓｎ／Ｎｉ層等）を形成する。この後、フィルム基材１Ａを個片化し、枠体２１の接着領域に接着材２４を用いて貼り付けることにより、図７に示すフレーム構造体が形成される。このように、フィルム基材１Ａを枠体２１の接着領域に貼り付け、枠体２１で規定された領域にフィルム基材１Ａを有するフレーム構造体２０を形成することにより、半導体装置の製造プロセス(組立プロセス)におけるフィルム基材１Ａの搬送性が向上すると共に、ハンドリング性が向上する。   Next, a plating process is performed by an electrolytic plating method to form a plating layer (for example, an Au / Ni layer, an Au / Pd / Ni layer, a Pd / Ni layer, a Sn / Ni layer, etc.) capable of wire bonding. Thereafter, the film base 1 </ b> A is separated into pieces and attached to the bonding region of the frame 21 using the adhesive 24, thereby forming the frame structure shown in FIG. 7. In this way, the film substrate 1A is attached to the adhesion region of the frame body 21, and the frame structure 20 having the film substrate 1A in the region defined by the frame body 21 is formed. The transportability of the film base 1A in the assembly process) is improved and the handling properties are improved.

次に、前記半導体装置の製造方法について説明する。   Next, a method for manufacturing the semiconductor device will be described.

まず、図７に示すフレーム構造体２０を準備する。フレーム構造体２０は、枠体２１で規定された領域内にフィルム基材１Ａを有している。フィルム基材１Ａには樹脂封止領域２２が配置され、この樹脂封止領域２２には、図５に示す配線導体パターンが形成されている。   First, the frame structure 20 shown in FIG. 7 is prepared. The frame structure 20 has a film substrate 1 </ b> A in a region defined by the frame body 21. A resin sealing region 22 is disposed on the film base 1A, and a wiring conductor pattern shown in FIG. 5 is formed in the resin sealing region 22.

次に、図１１(要部断面図)に示すように、前記フィルム基材１Ａの一表面のチップ搭載領域上に接着材１２を介在して半導体チップ１０を搭載する。接着材１２は、フィルム基材１Ａの一表面のチップ搭載領域に多点塗布法で供給される。接着材１２としては、例えば、エポキシ系又はポリイミド系の熱硬化性絶縁樹脂を用いる。また、接着材１２としては、例えば、エポキシ系又はポリイミド系の熱可塑性絶縁樹脂を用いてもよい。この工程において、フィルム基材１Ａのチップ搭載領域には図６に示すベントホール７が設けられているので、接着材１２の硬化時に発生するアウトガスを外部に逃すことができる。また、フィルム基材１Ａの一表面のチップ搭載領域上には図６に示すベントホール７の周囲を囲むダム８が設けられているので、接着材１２がベントホール７に流れ込むのを堰き止めることができる。この結果、接着材１２によるベントホール７の塞ぎを防止できると共に、接着材１２がフィルム基材１Ａの裏面側に回り込むのを防止できる。また、バンプ接続用電極パッド２上に絶縁膜９が配置されているので、半導体チップ１０が傾いた状態で搭載されたり、接着材１２の膜厚が薄くなっても、半導体チップ１０がバンプ接続用電極パッド２に接触することはない。また、半導体チップ１０が傾いた状態で搭載されたり、接着材１２の膜厚が薄くなっても、半導体チップ１０は絶縁膜９に接触し、この絶縁膜９によって支持されるので、半導体チップ１０が配線３に接触することはない。   Next, as shown in FIG. 11 (main cross-sectional view), the semiconductor chip 10 is mounted on the chip mounting region on one surface of the film base 1A with an adhesive 12 interposed. The adhesive 12 is supplied to the chip mounting area on one surface of the film base 1A by a multipoint coating method. As the adhesive 12, for example, an epoxy-based or polyimide-based thermosetting insulating resin is used. Moreover, as the adhesive material 12, for example, an epoxy-based or polyimide-based thermoplastic insulating resin may be used. In this step, since the vent hole 7 shown in FIG. 6 is provided in the chip mounting region of the film base 1A, outgas generated when the adhesive 12 is cured can be released to the outside. Moreover, since the dam 8 surrounding the periphery of the vent hole 7 shown in FIG. 6 is provided on the chip mounting region on one surface of the film base 1A, the adhesive material 12 is blocked from flowing into the vent hole 7. Can do. As a result, the vent hole 7 can be prevented from being blocked by the adhesive material 12, and the adhesive material 12 can be prevented from wrapping around the back side of the film base 1A. Further, since the insulating film 9 is disposed on the bump connection electrode pad 2, the semiconductor chip 10 is bump-connected even when the semiconductor chip 10 is mounted in an inclined state or the thickness of the adhesive 12 is reduced. There is no contact with the electrode pad 2 for use. Even if the semiconductor chip 10 is mounted in an inclined state or the thickness of the adhesive 12 is reduced, the semiconductor chip 10 contacts the insulating film 9 and is supported by the insulating film 9. Does not contact the wiring 3.

次に、図１２(要部断面図)に示すように、前記半導体チップ１０の外部端子１１とフィルム基材１Ａのワイヤ接続用電極パッド４とをワイヤ１３で電気的に接続する。ワイヤ１３としてはＡｕワイヤを用いる。   Next, as shown in FIG. 12 (essential cross-sectional view), the external terminals 11 of the semiconductor chip 10 and the wire connection electrode pads 4 of the film base 1A are electrically connected by wires 13. An Au wire is used as the wire 13.

次に、前記フレーム構造体２０を成形金型にセットし、図１３(要部断面図)に示すように、成形金型の上型３５Ａと下型３５Ｂとで形成されるキャビティ３６内に、フィルム基材１Ａの樹脂封止領域２２、半導体チップ１０及びワイヤ１３等を配置する。成形金型は、図１４（要部断面図）に示すように、サブランナー(幹ランナー)３７及び突起３８を備え、更に、図示していないが、流入ゲート、メインランナー(主ランナー)、ポットの夫々を備えている。ポットは、メインランナー、サブランナー３７、流入ゲートの夫々を通してキャビティ３６に連結される。   Next, the frame structure 20 is set in a molding die, and as shown in FIG. 13 (main part sectional view), in the cavity 36 formed by the upper die 35A and the lower die 35B of the molding die, The resin sealing region 22, the semiconductor chip 10, the wire 13, and the like of the film base 1A are disposed. As shown in FIG. 14 (main part cross-sectional view), the molding die includes a sub-runner (stem runner) 37 and a projection 38, and although not shown, an inflow gate, a main runner (main runner), a pot Each of them. The pot is connected to the cavity 36 through the main runner, the sub runner 37, and the inflow gate.

前記成形金型の下型３５Ｂは、フレーム構造体２０の枠体２１が装着される段差部３９及びフィルム基材１Ａが装着される段差部４０を有している。即ち、フレーム構造体２０の枠体２１は下型３５Ｂの段差部３９に装着され、フレーム構造体２０のフィルム基材１Ａは下型３５Ｂの段差部４０に装着される。上型３５Ａと下型３５Ｂの縦方向の合わせ吸収は、枠体２１−接着材２４−フィルム基材１Ａの構造で行う。   The lower mold 35B of the molding die has a step portion 39 to which the frame body 21 of the frame structure 20 is mounted and a step portion 40 to which the film base 1A is mounted. That is, the frame body 21 of the frame structure 20 is attached to the step portion 39 of the lower mold 35B, and the film base 1A of the frame structure 20 is attached to the step portion 40 of the lower mold 35B. The vertical absorption of the upper mold 35A and the lower mold 35B is performed by the structure of the frame 21-the adhesive 24-the film base 1A.

前記サブランナー３７は、詳細に図示していないが、フレーム構造体２０の枠体２１が装着される段差部３９及びフィルム基材１Ａが装着される段差部４０を横切るように、フレーム構造体２０の外側からその内側に向かって延在し、流入ゲートを通してキャビティ３６に連結されている。前記メインランナーは、フレーム構造体２０の外側において、フレーム構造体２０の長手方向に沿って延在し、フレーム構造体２０の外側に引き出されたサブランナー３７の一端側に連結されている。なお、突起３８は、サブランナー３７内にて硬化した樹脂を切断し易くするために設けられている。この突起３８は、フレーム構造体２０の枠体２１とフィルム基材１Ａとで形成される段差部の領域上に位置している。   Although not shown in detail, the sub-runner 37 crosses the step portion 39 to which the frame body 21 of the frame structure 20 is mounted and the step portion 40 to which the film base 1A is mounted so as to cross the frame structure 20. Extends from the outside to the inside and is connected to the cavity 36 through the inflow gate. The main runner extends along the longitudinal direction of the frame structure 20 on the outside of the frame structure 20 and is connected to one end side of the sub-runner 37 drawn to the outside of the frame structure 20. The protrusion 38 is provided to facilitate cutting of the resin cured in the sub runner 37. The protrusion 38 is located on a stepped region formed by the frame body 21 of the frame structure 20 and the film substrate 1A.

次に、前記ポットに樹脂タブレットを投入し、この樹脂タブレットをトランスファモールド装置のプランジャで加圧し、ポットからメインランナー、サブランナー３７、流入ゲートの夫々を通してキャビティ３６内に樹脂を供給し、樹脂封止体１４を形成する。この後、成形金型からフレーム構造体２０を取り出す。成型金型から取り出したフレーム構造体２０の状態を図１５(要部平面図)に示す。図１５において、符号４１は成形金型のサブランー３７内において硬化したサブランナー樹脂であり、符号４２は成形金型のメインナランナー内にて硬化したメインナランナー樹脂４２である。メインナランナー樹脂４２は、フレーム構造体２０の長手方向に沿って延在している。サブランナー樹脂４１は、枠体２１の外側からその内側に向かって延在している。なお、図１４は図１５に示すＣ−Ｃ線の位置での断面図である。   Next, a resin tablet is put into the pot, and the resin tablet is pressurized with a plunger of a transfer mold device, and the resin is supplied from the pot into the cavity 36 through the main runner, the sub runner 37, and the inflow gate. A stop 14 is formed. Thereafter, the frame structure 20 is taken out from the molding die. A state of the frame structure 20 taken out from the molding die is shown in FIG. In FIG. 15, reference numeral 41 denotes a sub runner resin cured in the sub run 37 of the molding die, and reference numeral 42 denotes a main runner resin 42 cured in the main runner of the molding die. The main runner resin 42 extends along the longitudinal direction of the frame structure 20. The sub runner resin 41 extends from the outside of the frame body 21 toward the inside thereof. FIG. 14 is a cross-sectional view taken along the line CC shown in FIG.

次に、前記枠体２１の内側に位置するサブランナー樹脂４１を残し、それ以外のサブランナー樹脂４１及びメインランナー樹脂４２を除去する。この状態を図１６(要部平面図)に示す。   Next, the sub runner resin 41 located inside the frame body 21 is left, and the other sub runner resin 41 and the main runner resin 42 are removed. This state is shown in FIG. 16 (plan view of relevant parts).

次に、図１７に示すように、バンプ接続用電極パッド２の裏面に、フィルム基材１Ａに形成された接続孔６を通してバンプ電極１５を接続する。バンプ電極１５は、例えばボール供給法で供給され、赤外線リフロー炉等で溶融することにより接続される。バンプ電極１５を形成した後の搬送状態を図１８(概略構成図)に示す。フレーム構造体２０を多段に積み重ねた場合、上段のフレーム構造体２０と下段のフレーム構造体２０との間の隙間を上段のフレーム構造体２０に設けられたサブランナー樹脂４１で確保することができ、下段のフレーム構造体２０で製造された半導体装置のバンプ電極１５を保護できる。従って、フレーム構造体２０を多段に積み重ねた状態で搬送することができるので、フレーム構造体２０の搬送性が向上する。また、半導体装置の製造プロセスにおける生産合理性が向上する。   Next, as shown in FIG. 17, the bump electrode 15 is connected to the back surface of the bump connection electrode pad 2 through the connection hole 6 formed in the film base 1 </ b> A. The bump electrode 15 is supplied by, for example, a ball supply method and is connected by melting in an infrared reflow furnace or the like. A transport state after the bump electrode 15 is formed is shown in FIG. When the frame structure 20 is stacked in multiple stages, a gap between the upper frame structure 20 and the lower frame structure 20 can be secured by the sub-runner resin 41 provided in the upper frame structure 20. The bump electrode 15 of the semiconductor device manufactured by the lower frame structure 20 can be protected. Therefore, since the frame structure 20 can be transported in a stacked state, the transportability of the frame structure 20 is improved. Also, the production rationality in the semiconductor device manufacturing process is improved.

次に、フィルム基材１Ａを所定の形状(ベース基板形状)に切断することにより、フィルム基材１Ａからなるベース基板１を有する半導体装置がほぼ完成する。この後、半導体装置は製品として出荷される。製品として出荷された半導体装置は実装基板の実装面上に実装される。   Next, by cutting the film base 1A into a predetermined shape (base substrate shape), a semiconductor device having the base substrate 1 made of the film base 1A is almost completed. Thereafter, the semiconductor device is shipped as a product. A semiconductor device shipped as a product is mounted on a mounting surface of a mounting board.

なお、樹脂封止体１４を形成した後、フィルム基材１Ａを切断し、個片にした状態にてバンプ電極１５の接続を行ってもよい。   In addition, after forming the resin sealing body 14, you may connect the bump electrode 15 in the state which cut | disconnected the film base material 1A and was made into the piece.

また、メッキ処理は、絶縁膜９を形成する前の段階において行ってもよい。本実施形態のように、絶縁膜９を形成した後の段階においてメッキ処理を行った場合、図１９(要部断面図)に示すように、メッキ層３３は、ベース基板（フィルム基材１Ａ）１の一表面の周辺領域に配置されたバンプ接続用電極パッド２、配線３、ワイヤ接続用電極パッド４及びバンプ接続用電極パッド２の裏面に形成される。即ち、配線導体と絶縁膜９との間にはメッキ層３３が形成されない。絶縁膜９を形成する前の段階においてメッキ処理を行った場合、図２０(要部断面図)に示すように、メッキ層３３は、ベース基板（フィルム基材１Ａ）１の一表面のチップ搭載領域及び周辺領域に配置されたバンプ接続用電極パッド２、配線３、ワイヤ接続用電極パッド４、メッキ用配線５及びバンプ接続用電極パッド２の裏面に形成される。即ち、配線導体と絶縁膜９との間にメッキ層３３が形成される。   The plating process may be performed before the insulating film 9 is formed. When plating is performed at a stage after the insulating film 9 is formed as in the present embodiment, the plating layer 33 is formed on the base substrate (film base 1A) as shown in FIG. The bump connection electrode pad 2, the wiring 3, the wire connection electrode pad 4, and the bump connection electrode pad 2 are formed on the back surface of the peripheral area of the one surface. That is, the plating layer 33 is not formed between the wiring conductor and the insulating film 9. When the plating process is performed in the stage before the insulating film 9 is formed, the plating layer 33 is mounted on the chip on one surface of the base substrate (film substrate 1A) 1 as shown in FIG. The bump connection electrode pad 2, the wiring 3, the wire connection electrode pad 4, the plating wiring 5, and the bump connection electrode pad 2 are formed on the back surface of the bump connection electrode pad 2, the wiring 3, and the bump connection electrode pad 2. That is, the plating layer 33 is formed between the wiring conductor and the insulating film 9.

以上説明したように、本実施形態によれば、以下の効果が得られる。   As described above, according to the present embodiment, the following effects can be obtained.

（１）配線導体上に絶縁膜９を分割して配置することにより、絶縁膜９の膨張及び硬化収縮による応力が緩和されるので、ベース基板(フィルム基材１Ａ)１の反り、歪み等の変形を抑制できる。 (1) Since the insulating film 9 is divided and disposed on the wiring conductor, stress due to expansion and curing shrinkage of the insulating film 9 is relieved, so that warping, distortion, etc. of the base substrate (film substrate 1A) 1 are reduced. Deformation can be suppressed.

また、ベース基板１の変形を抑制できるので、半導体装置の製造プロセスにおける歩留まりが向上する。   Further, since the deformation of the base substrate 1 can be suppressed, the yield in the semiconductor device manufacturing process is improved.

（２）ベントホール７の周囲を囲むダム８を設けることにより、接着材１２がベントホール７に流れ込むのを堰き止めることができるので、接着材１２によるベントホール７の塞ぎを防止できると共に、接着材１２がフィルム基材１Ａの裏面側に回り込むのを防止できる。 (2) By providing the dam 8 surrounding the periphery of the vent hole 7, the adhesive material 12 can be blocked from flowing into the vent hole 7, so that the vent hole 7 can be prevented from being blocked by the adhesive material 12 and bonded. It can prevent that the material 12 wraps around to the back surface side of 1 A of film base materials.

（３）ベントホール７をベース基板１の中心からずれた位置に配置することにより、ベース基板１の裏面側から半導体装置を見た場合、インデックスとして方向を明確化できる。 (3) By arranging the vent hole 7 at a position shifted from the center of the base substrate 1, the direction can be clarified as an index when the semiconductor device is viewed from the back side of the base substrate 1.

（４）絶縁膜９を印刷法で形成することにより、シート状に形成された絶縁膜９を貼り付けて形成する場合に比べて、半導体装置の低コスト化が図れる。 (4) By forming the insulating film 9 by a printing method, the cost of the semiconductor device can be reduced as compared with the case where the insulating film 9 formed in a sheet shape is attached.

また、絶縁膜９のパターン形状を自由に設定できるので、半導体装置の生産合理性が向上する。   Moreover, since the pattern shape of the insulating film 9 can be freely set, the production rationality of the semiconductor device is improved.

（５）枠体２１で規定された領域内にフィルム基材１Ａが配置されたフレーム構造体２０を用いて半導体装置の製造を行うことにより、半導体装置の製造プロセスにおけるフィルム基材１Ａの搬送性が向上すると共に、ハンドリング性が向上する。 (5) By carrying out the manufacture of a semiconductor device using the frame structure 20 in which the film base 1A is disposed in the region defined by the frame 21, the transportability of the film base 1A in the semiconductor device manufacturing process As a result, handling is improved.

（６）サブランナー部に、フレーム構造体２０の枠体２１が装着される段差部３９及びフレーム構造体２０のフィルム基材１Ａが装着される段差部４０を有する成形金型を用いたトランスファモールド法で樹脂封止体１４を形成することにより、フィルム基材１Ａ及び枠体２１に付着する樹脂バリを防止できるので、封止及び切断時に発生する異物を低減できる。 (6) Transfer mold using a molding die having a stepped portion 39 to which the frame body 21 of the frame structure 20 is attached and a stepped portion 40 to which the film base 1A of the frame structure 20 is attached to the sub-runner portion. By forming the resin sealing body 14 by this method, resin burrs that adhere to the film base material 1A and the frame body 21 can be prevented, and foreign matters generated during sealing and cutting can be reduced.

（７）フレーム構造体２０の枠体２１内にランナー樹脂４１を残した状態で、バンプ電極１５の接続を行うことにより、フレーム構造体２０を多段に積み重ねた場合、上段のフレーム構造体２０と下段のフレーム構造体２０との間の隙間を上段のフレーム構造体２０に設けられたサブランナー樹脂４１で確保することができ、下段のフレーム構造体２０で製造された半導体装置のバンプ電極１５を保護できる。従って、フレーム構造体２０を多段に積み重ねた状態で搬送することができるので、フレーム構造体２０の搬送性が向上する。また、半導体装置の製造プロセスにおける生産合理性が向上する。 (7) When the bump electrode 15 is connected in a state where the runner resin 41 is left in the frame body 21 of the frame structure 20, when the frame structure 20 is stacked in multiple stages, the upper frame structure 20 and A gap between the lower frame structure 20 and the lower runner resin 41 provided in the upper frame structure 20 can be secured, and the bump electrode 15 of the semiconductor device manufactured by the lower frame structure 20 can be secured. Can protect. Therefore, since the frame structure 20 can be transported in a stacked state, the transportability of the frame structure 20 is improved. Also, the production rationality in the semiconductor device manufacturing process is improved.

（８）バンプ接続用電極パッド２上に絶縁膜９が配置されているので、ベース基板(フィルム基材１Ａ)１の一表面のチップ搭載領域上に接着材１２を介在して半導体チップ１０を搭載する際、半導体チップ１０が傾いた状態で搭載されたり、接着材１２の膜厚が薄くなっても、半導体チップ１０がバンプ接続用電極パッド２に接触しないので、バンプ接続用電極パッド２と半導体チップ１０との短絡、即ち、配線導体と半導体チップ１０との短絡を防止できる。 (8) Since the insulating film 9 is disposed on the bump connection electrode pad 2, the semiconductor chip 10 is mounted on the chip mounting region on one surface of the base substrate (film base 1 </ b> A) 1 with the adhesive 12 interposed. When mounting, even if the semiconductor chip 10 is mounted in an inclined state or the thickness of the adhesive 12 is reduced, the semiconductor chip 10 does not contact the bump connection electrode pad 2. A short circuit with the semiconductor chip 10, that is, a short circuit between the wiring conductor and the semiconductor chip 10 can be prevented.

また、半導体チップ１０が傾いた状態で搭載されたり、接着材１２の膜厚が薄くなっても、半導体チップ１０は絶縁膜９に接触し、この絶縁膜９によって支持されるので、配線３と半導体チップ１０との短絡、即ち、配線導体と半導体チップ１０との短絡を防止できる。   Even if the semiconductor chip 10 is mounted in an inclined state or the thickness of the adhesive 12 is reduced, the semiconductor chip 10 contacts the insulating film 9 and is supported by the insulating film 9. A short circuit with the semiconductor chip 10, that is, a short circuit between the wiring conductor and the semiconductor chip 10 can be prevented.

（９）枠体２１の接着領域にスリット２３を設けることにより、枠体２１とフィルム基材１Ａとの材料の違いによる応力を低減できるので、フィルム基材１Ａの反り、歪み等の変形を抑制できる。 (9) By providing the slits 23 in the bonding region of the frame body 21, stress due to the difference in material between the frame body 21 and the film base material 1A can be reduced, so that deformation of the film base material 1A such as warpage and distortion is suppressed. it can.

なお、前述の実施形態では、ベース基板１のチップ搭載領域において、バンプ接続用電極パッド２上に絶縁膜９を形成した例について説明したが、絶縁膜９は配線３上に形成してもよい。また、絶縁膜９はバンプ接続用電極パッド２上及び配線３上に形成してもよい。これらの場合、ベース基板（フィルム基材１Ａ）１の一表面のチップ搭載領域上に接着材１２を介在して半導体チップ１０を搭載する際、半導体チップ１０が傾いた状態で搭載されたり、接着材１２の膜厚が薄くなっても、前述の実施形態と同様に、バンプ接続用電極パッド２及び配線３と半導体チップ１０との短絡、即ち、配線導体と半導体チップ１０との短絡を防止できる。   In the above-described embodiment, the example in which the insulating film 9 is formed on the bump connection electrode pad 2 in the chip mounting region of the base substrate 1 has been described. However, the insulating film 9 may be formed on the wiring 3. . Further, the insulating film 9 may be formed on the bump connection electrode pad 2 and the wiring 3. In these cases, when the semiconductor chip 10 is mounted on the chip mounting region on one surface of the base substrate (film base 1A) 1 with the adhesive 12 interposed, the semiconductor chip 10 is mounted in an inclined state or bonded. Even when the film thickness of the material 12 is reduced, the short circuit between the bump connection electrode pad 2 and the wiring 3 and the semiconductor chip 10, that is, the short circuit between the wiring conductor and the semiconductor chip 10 can be prevented as in the above-described embodiment. .

また、図２１(半導体装置の要部断面図)及び図２２(ベース基板の平面図)に示すように、ベース基板１の一表面の周辺領域であって、半導体チップ１０とワイヤ接続用電極パッド４との間の領域に形成された配線３上に絶縁膜９が配置されるように、ベース基板１上において絶縁膜９を複数個に分割してもよい。この場合、配線３にワイヤ１３が接触しないので、ワイヤ１３とこのワイヤ１３に電気的に接続された配線３に隣接する他の配線３との短絡、即ち配線導体とワイヤ１３との短絡を防止できる。   Further, as shown in FIG. 21 (sectional view of the principal part of the semiconductor device) and FIG. 22 (plan view of the base substrate), it is a peripheral region on one surface of the base substrate 1 and includes the semiconductor chip 10 and the electrode pad for wire connection. The insulating film 9 may be divided into a plurality of parts on the base substrate 1 so that the insulating film 9 is disposed on the wiring 3 formed in a region between the insulating film 9 and the wiring 4. In this case, since the wire 13 does not come into contact with the wiring 3, a short circuit between the wire 13 and another wiring 3 adjacent to the wiring 3 electrically connected to the wire 13, that is, a short circuit between the wiring conductor and the wire 13 is prevented. it can.

また、図２３(ベース基板の平面図)及び図２４(半導体装置の要部断面図)に示すように、ベース基板１上において絶縁膜９を配線導体毎に分割し、ワイヤ接続用電極パッド４を除いた配線導体（バンプ接続用電極パッド２、配線３、メッキ用配線５）の全域に絶縁膜９を形成してもよい。この場合、半導体装置の製造プロセスにおいて、配線導体間に導電性異物が付着しても、配線導体に導電性異物が接触しないので、配線導体間の短絡を防止できる。   Further, as shown in FIG. 23 (plan view of the base substrate) and FIG. 24 (cross-sectional view of the main part of the semiconductor device), the insulating film 9 is divided into wiring conductors on the base substrate 1, and the wire connection electrode pads 4 are formed. The insulating film 9 may be formed over the entire area of the wiring conductor (the bump connection electrode pad 2, the wiring 3, and the plating wiring 5) except for. In this case, even if conductive foreign matter adheres between the wiring conductors in the manufacturing process of the semiconductor device, the conductive foreign matter does not contact the wiring conductor, so that a short circuit between the wiring conductors can be prevented.

また、図２５(ベース基板の平面図)に示すように、ベース基板１上において絶縁膜９を複数個に分割し、この絶縁膜９を配線導体上に配置してもよい。複数の絶縁膜９の夫々は、平面が方形状で形成され、所定の間隔を置いて行列状に配置される。   Further, as shown in FIG. 25 (plan view of the base substrate), the insulating film 9 may be divided into a plurality of parts on the base substrate 1, and the insulating film 9 may be disposed on the wiring conductor. Each of the plurality of insulating films 9 has a rectangular plane and is arranged in a matrix at a predetermined interval.

また、図２６(ベース基板の平面図)に示すように、ベース基板１上において絶縁膜９を複数個に分割し、この絶縁膜９を配線導体上に配置してもよい。複数の絶縁膜９の夫々は、長尺状に形成され、所定の間隔を置いた状態にて放射状に配置される。   Further, as shown in FIG. 26 (plan view of the base substrate), the insulating film 9 may be divided into a plurality of parts on the base substrate 1, and the insulating film 9 may be disposed on the wiring conductor. Each of the plurality of insulating films 9 is formed in a long shape, and is arranged radially with a predetermined interval.

また、前述の実施形態では、ベース基板１の裏面側に配置される電極として、球状のバンプ電極１５を用いた例について説明したが、電極としては、ボールボンディング法で形成されるスタッドバンプのような突起電極又は平坦な電極を用いてもよい。   In the above-described embodiment, the example in which the spherical bump electrode 15 is used as the electrode disposed on the back surface side of the base substrate 1 has been described. However, the electrode may be a stud bump formed by a ball bonding method. Simple protruding electrodes or flat electrodes may be used.

以上、本発明者によってなされた発明を、前記実施形態に基づき具体的に説明したが、本発明は、前記実施形態に限定されるものではなく、その要旨を逸脱しない範囲において種々変更可能であることは勿論である。   As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Of course.

本発明の一実施形態である半導体装置の平面図である。It is a top view of the semiconductor device which is one embodiment of the present invention. 図１に示すＡ−Ａ線の位置で切った拡大断面図である。It is the expanded sectional view cut in the position of the AA line shown in FIG. 図２の要部拡大断面図である。It is a principal part expanded sectional view of FIG. 前記半導体装置の樹脂封止体を除去した状態の平面図である。It is a top view of the state which removed the resin sealing body of the said semiconductor device. ベース基板の平面図である。It is a top view of a base substrate. 前記半導体装置の要部拡大断面図である。It is a principal part expanded sectional view of the said semiconductor device. 前記半導体装置の製造プロセスで使用されるフレーム構造体の要部平面図である。It is a principal part top view of the frame structure used in the manufacturing process of the said semiconductor device. 図７に示すＢ−Ｂ線の位置で切った拡大断面図である。It is the expanded sectional view cut in the position of the BB line shown in FIG. 前記フレーム構造体の製造方法を説明するための要部断面図である。It is principal part sectional drawing for demonstrating the manufacturing method of the said frame structure. 前記フレーム構造体の製造方法を説明するための要部断面図である。It is principal part sectional drawing for demonstrating the manufacturing method of the said frame structure. 前記半導体装置の製造方法を説明するための要部断面図である。It is principal part sectional drawing for demonstrating the manufacturing method of the said semiconductor device. 前記半導体装置の製造方法を説明するための要部断面図である。It is principal part sectional drawing for demonstrating the manufacturing method of the said semiconductor device. 前記半導体装置の製造方法を説明するための要部断面図である。It is principal part sectional drawing for demonstrating the manufacturing method of the said semiconductor device. 前記半導体装置の製造方法を説明するための要部断面図である。It is principal part sectional drawing for demonstrating the manufacturing method of the said semiconductor device. 前記半導体装置の製造方法を説明するための要部平面図である。It is a principal part top view for demonstrating the manufacturing method of the said semiconductor device. 前記半導体装置の製造方法を説明するための要部平面図である。It is a principal part top view for demonstrating the manufacturing method of the said semiconductor device. 前記半導体装置の製造方法を説明するための要部断面図である。It is principal part sectional drawing for demonstrating the manufacturing method of the said semiconductor device. 前記フレーム構造体を多段に積み重ねた状態を示す概略構成図である。It is a schematic block diagram which shows the state which accumulated the said frame structure in multistage. 前記フレーム構造体の製造方法を説明するための要部断面図である。It is principal part sectional drawing for demonstrating the manufacturing method of the said frame structure. 前記フレーム構造体の製造方法を説明するための要部断面図である。It is principal part sectional drawing for demonstrating the manufacturing method of the said frame structure. 本発明の一実施形態である半導体装置の第１変形例を示す要部断面図である。It is principal part sectional drawing which shows the 1st modification of the semiconductor device which is one Embodiment of this invention. 本発明の一実施形態である半導体装置の第１変形例を示すベース基板の平面図である。It is a top view of the base substrate which shows the 1st modification of the semiconductor device which is one Embodiment of this invention. 本発明の一実施形態である半導体装置の第２変形例を示すベース基板の平面図である。It is a top view of the base substrate which shows the 2nd modification of the semiconductor device which is one Embodiment of this invention. 図２３に示すベース基板を用いた半導体装置の要部断面図である。FIG. 24 is a main-portion cross-sectional view of the semiconductor device using the base substrate shown in FIG. 本発明の一実施形態である半導体装置の第３変形例を示すベース基板の平面図である。It is a top view of the base substrate which shows the 3rd modification of the semiconductor device which is one Embodiment of this invention. 本発明の一実施形態である半導体装置の第４変形例を示すベース基板の平面図である。It is a top view of the base substrate which shows the 4th modification of the semiconductor device which is one Embodiment of this invention.

符号の説明Explanation of symbols

１…ベース基板、１Ａ…フィルム基材、２…バン接続用電極パッド、３…配線、４…ワイヤ接続用電極パッド、５…メッキ用配線、６…接続孔、７…ベントホール、８…ダム、９…絶縁膜、１０…半導体チップ、１１…外部端子、１２…接着材、１３…ワイヤ、１４…樹脂封止体、２０…フレーム構造体、２１…枠体、２２…樹脂封止領域、２３…スリット、２４…接着材、３７…サブランナー、３９，４０…段差部、４１…サブランナー樹脂、４２…メインランナー樹脂。   DESCRIPTION OF SYMBOLS 1 ... Base substrate, 1A ... Film base material, 2 ... Electrode pad for van connection, 3 ... Wiring, 4 ... Electrode pad for wire connection, 5 ... Wiring for plating, 6 ... Connection hole, 7 ... Vent hole, 8 ... Dam , 9 ... Insulating film, 10 ... Semiconductor chip, 11 ... External terminal, 12 ... Adhesive, 13 ... Wire, 14 ... Resin sealing body, 20 ... Frame structure, 21 ... Frame body, 22 ... Resin sealing region, 23 ... Slit, 24 ... Adhesive, 37 ... Sub runner, 39, 40 ... Step portion, 41 ... Sub runner resin, 42 ... Main runner resin.

Claims (8)

（ａ）金属で構成される枠体と、前記枠体に形成され、かつスリットが設けられた接着領域と、前記枠体の内側に位置するように前記接着領域に固定されたフィルム基材とを備えたフレーム構造体を準備する工程と、
（ｂ）主面、裏面、及び前記主面に形成された複数の第２電極を有する半導体チップを準備する工程と、
（ｃ）前記半導体チップの裏面を前記フィルム基材の樹脂封止領域に搭載する工程と、
（ｄ）前記（ｃ）工程の後、前記半導体チップの複数の第２電極と前記フィルム基材の前記樹脂封止領域に形成された複数の第１電極とを、複数のワイヤを介してそれぞれ電気的に接続する工程と、
（ｅ）前記（ｄ）工程の後、前記フィルム基材の表面において、前記樹脂封止領域と前記枠体との間の領域が露出するように、前記半導体チップ及び前記複数のワイヤを封止する樹脂封止体を前記樹脂封止領域上に形成する工程と、
（ｆ）前記（ｅ）工程の後、前記フィルム基材において、前記接着領域よりも内側を切断し、個片化する工程と、
を含むことを特徴とする半導体装置の製造方法。 (A) When configured frame body of metal, it is formed on the frame, or One slit an adhesive area provided, which is fixed to the front Symbol bonding region so as to be positioned inside the prior SL frame film Preparing a frame structure including a base material;
(B) preparing a semiconductor chip having a main surface, a back surface, and a plurality of second electrodes formed on the main surface;
(C) mounting the back surface of the semiconductor chip in a resin-sealed region of the film base ;
After; (d) (c) step, a plurality of first electrodes formed on the plurality of second electrodes wherein the resin sealing region of the film substrate of the semiconductor chip, respectively, via a plurality of wires Electrically connecting, and
(E) after step (d), in the front surface of the film substrate, as a region between the frame member and the resin sealing region is exposed, sealing the semiconductor chip and the plurality of wires Forming a resin sealing body to be stopped on the resin sealing region;
(F) After the step (e), in the film substrate, a step of cutting the inside of the adhesive region and dividing into pieces,
A method for manufacturing a semiconductor device, comprising: 請求項１に記載の半導体装置の製造方法において、
前記（ｅ）工程では、さらに前記フィルム基材の前記表面に、サブランナー樹脂の一部が形成されることを特徴とする半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1,
In the step (e), a part of the sub-runner resin is further formed on the surface of the film base material. 請求項２に記載の半導体装置の製造方法において、
前記サブランナー樹脂は、前記樹脂封止体と前記枠体との間に位置することを特徴とする半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 2,
The sub-runner resin is located between the resin sealing body and the frame body. 請求項２に記載の半導体装置の製造方法において、
前記サブランナー樹脂は、前記枠体の外側から内側に向かって延在していることを特徴とする半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 2,
The sub-runner resin extends from the outside to the inside of the frame body. 請求項２に記載の半導体装置の製造方法において、
さらに前記樹脂封止体から前記サブランナー樹脂を分割する工程を有することを特徴とする半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 2,
Furthermore, it has the process of dividing | segmenting the said sub runner resin from the said resin sealing body, The manufacturing method of the semiconductor device characterized by the above-mentioned. 請求項１に記載の半導体装置の製造方法において、
前記フィルム基材は、絶縁樹脂から成ることを特徴とする半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the film base is made of an insulating resin. 請求項１に記載の半導体装置の製造方法において、
前記枠体は、前記フレーム構造体にエッチング加工又はプレス打抜き加工を施すことによって形成されていることを特徴とする半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1,
The frame is formed by subjecting the frame structure to an etching process or a press punching process. 請求項１に記載の半導体装置の製造方法において、
前記フィルム基材は、前記接着領域に接着材を介して固定されていることを特徴とする半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1,
The method for manufacturing a semiconductor device, wherein the film base is fixed to the adhesion region via an adhesive.
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