JP2012178482A - Manufacturing method of wiring board - Google Patents

Manufacturing method of wiring board Download PDF

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JP2012178482A
JP2012178482A JP2011041048A JP2011041048A JP2012178482A JP 2012178482 A JP2012178482 A JP 2012178482A JP 2011041048 A JP2011041048 A JP 2011041048A JP 2011041048 A JP2011041048 A JP 2011041048A JP 2012178482 A JP2012178482 A JP 2012178482A
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connection pad
semiconductor element
solder resist
central portion
exposed
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Seiichi Takami
征一 高見
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Kyocera SLC Technologies Corp
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PROBLEM TO BE SOLVED: To provide a manufacturing method of a wiring board in which a plating metal layer based on electroless plating is attached excellently onto an external connecting pad and a solder is deposited directly to a semiconductor device connecting pad.SOLUTION: While covering a central portion of a semiconductor device connecting pad 2 on an upper surface of an insulated substrate 1 with a thin film 4b of a solder resist resin layer 4, a plating metal layer 6 is attached to an exposed central portion of an external connecting pad 2 on a lower surface of the insulated substrate 1 by electroless plating. Next, the thin film 4b of the solder resist resin layer 4 at an upper surface side of the insulated substrate 1 is removed, the central portion of the semiconductor device connecting pad 2 is exposed and finally, a solder 7 is deposited to the exposed central portion of the semiconductor device connecting pad 2.

Description

本発明は、半導体素子を搭載するために用いられる配線基板の製造方法に関するものである。   The present invention relates to a method for manufacturing a wiring board used for mounting a semiconductor element.

従来、半導体集積回路素子等の半導体素子を搭載するために用いられる配線基板は、例えばガラス−エポキシ板等から成る絶縁板やエポキシ樹脂等から成る絶縁層が複数層積層された絶縁基板の内部および表面に銅箔や銅めっき膜等の銅から成る配線導体が配設されて成る。また絶縁基板の上面中央部には半導体素子の電極が半田バンプを介して電気的に接続される半導体素子接続パッドが複数形成されており、絶縁基板の下面には外部電気回路基板の配線導体に半田ボールを介して電気的に接続される外部接続パッドが形成されている。さらに絶縁基板の上下面には各半導体素子接続パッドの中央部および各外部接続パッドの中央部を露出させる開口部を有するソルダーレジスト層が各半導体素子接続パッドの外周部および各外部接続パッドの外周部を覆うようにして被着されている。またソルダーレジスト層から露出する半導体素子接続パッドおよび外部接続パッドには、ニッケルめっき層と金めっき層とを順次被着させたニッケル−金めっき層やニッケルめっき層とパラジウムめっき層と金めっき層とを順次被着させたニッケル−パラジウム−金めっき層等から成るめっき金属層が被着される。さらに半導体素子接続パッドには半導体素子の電極と接続するための半田バンプが溶着されている。あるいは、半導体素子接続パッドおよび外部接続パッドにめっき金属層を被着させずに、半導体素子接続パッド上に直接半田バンプを溶着させたり、外部接続パッド上に半田層を直接溶着させたりする場合もある。   Conventionally, a wiring board used for mounting a semiconductor element such as a semiconductor integrated circuit element includes, for example, an insulating board made of a glass-epoxy board or the like, and an insulating board in which a plurality of insulating layers made of epoxy resin are laminated and A wiring conductor made of copper such as a copper foil or a copper plating film is disposed on the surface. In addition, a plurality of semiconductor element connection pads are formed in the central portion of the upper surface of the insulating substrate, to which the electrodes of the semiconductor element are electrically connected via solder bumps, and the wiring conductor of the external electric circuit substrate is formed on the lower surface of the insulating substrate. External connection pads that are electrically connected via solder balls are formed. Furthermore, solder resist layers having openings exposing the central part of each semiconductor element connection pad and the central part of each external connection pad are provided on the upper and lower surfaces of the insulating substrate. The outer peripheral part of each semiconductor element connection pad and the outer periphery of each external connection pad It is attached so as to cover the part. The semiconductor element connection pad and the external connection pad exposed from the solder resist layer include a nickel-gold plating layer, a nickel plating layer, a palladium plating layer, and a gold plating layer in which a nickel plating layer and a gold plating layer are sequentially deposited. A plating metal layer composed of a nickel-palladium-gold plating layer or the like on which is sequentially deposited is deposited. Furthermore, solder bumps for connecting to the electrodes of the semiconductor element are welded to the semiconductor element connection pads. Alternatively, solder bumps may be welded directly on the semiconductor element connection pads or solder layers may be welded directly on the external connection pads without depositing the plated metal layer on the semiconductor element connection pads and the external connection pads. is there.

そして、半導体素子の電極を半導体素子接続パッドに溶着された半田バンプ上に当接させるとともに、その半田バンプを加熱溶融させることによって半導体素子の電極と半導体素子接続パッドとが半田バンプを介して電気的に接続され、さらにその半導体素子と配線基板との隙間にアンダーフィルと呼ばれる封止樹脂を注入して硬化させることにより半導体素子が配線基板上に実装される。また、外部接続パッド上に被着されためっき金属層上または半田層上に半田ボールを載置するとともにその半田ボールを加熱溶融させることによって、外部接続パッド上に半田ボールが溶着され、この半田ボールを外部電気回路基板の配線導体上に接触させた状態で加熱溶融させることによって、配線基板が半田ボールを介して外部電気回路基板上に実装されることとなる。   Then, the electrodes of the semiconductor element are brought into contact with the solder bumps welded to the semiconductor element connection pads, and the solder bumps are heated and melted to electrically connect the semiconductor element electrodes and the semiconductor element connection pads via the solder bumps. The semiconductor element is mounted on the wiring board by injecting a sealing resin called underfill into the gap between the semiconductor element and the wiring board and curing it. Also, the solder balls are deposited on the external connection pads by placing the solder balls on the plated metal layer or the solder layer deposited on the external connection pads and heating and melting the solder balls. By heating and melting the ball in contact with the wiring conductor of the external electric circuit board, the wiring board is mounted on the external electric circuit board via the solder balls.

ところで近時、上述したような半導体素子を搭載するための配線基板においては、環境への配慮から、半導体素子接続パッドに溶着される半田バンプや外部接続パッドに溶着される半田ボールとして、鉛を含まない錫−銀合金や錫−銀−銅合金等のいわゆる鉛フリー半田が使用されるようになってきている。ところが、この鉛フリー半田を半導体素子の電極と半導体素子接続パッドとを接続するための半田バンプに使用した場合、半導体素子の電極を半導体素子接続パッドに半田バンプを介して接続した後、半導体素子の電極と半導体素子接続パッドとの間に半導体素子を作動させるための電流が長期間にわたり高い電流密度で流れると、半田バンプ中にエレクトロマイグレーションによるボイドが発生する場合がある。半田バンプにエレクトロマイグレーションによるボイドが発生すると、半導体素子の電極とこれに接続されている半導体素子接続パッドとの間の電気的な抵抗が高くなったり、半導体素子の電極とこれに接続されている半導体素子接続パッドとの間が電気的に断線したりして半導体素子を正常に作動させることができなくなる。このような半田バンプに発生するエレクトロマイグレーションは、銅から成る半導体素子接続パッド上に直接半田バンプを溶着した場合よりも、ニッケルから成るめっき金属層を介して半田バンプを溶着した場合の方が特に顕著に発生する。したがって、銅から成る半導体素子接続パッドに鉛フリー半田から成る半田バンプを溶着する場合、半導体素子接続パッド上に直接半田バンプを溶着する方が好ましい。   Recently, in a wiring board for mounting a semiconductor element as described above, in consideration of the environment, as a solder bump welded to a semiconductor element connection pad or a solder ball welded to an external connection pad, lead is used. So-called lead-free solders such as tin-silver alloys and tin-silver-copper alloys that are not included have come to be used. However, when this lead-free solder is used as a solder bump for connecting the electrode of the semiconductor element and the semiconductor element connection pad, the semiconductor element is connected to the semiconductor element connection pad via the solder bump. When a current for operating the semiconductor element flows between the electrode and the semiconductor element connection pad at a high current density for a long time, a void due to electromigration may occur in the solder bump. When a void due to electromigration occurs in the solder bump, the electrical resistance between the electrode of the semiconductor element and the semiconductor element connection pad connected thereto increases, or the electrode of the semiconductor element is connected to the electrode. The semiconductor element cannot be normally operated due to electrical disconnection between the semiconductor element connection pads and the like. Electromigration that occurs in such solder bumps is particularly the case when solder bumps are welded via a plated metal layer made of nickel, rather than when solder bumps are welded directly onto a semiconductor element connection pad made of copper. It occurs remarkably. Therefore, when solder bumps made of lead-free solder are welded to the semiconductor element connection pads made of copper, it is preferable to weld the solder bumps directly on the semiconductor element connection pads.

他方、外部接続パッドには、半田ボールを溶着するための下地としてニッケルめっき層を含むめっき金属層が被着されている方が好ましい。これは、銅から成る外部接続パッド上に鉛フリー半田から成る半田を直接溶着すると、配線基板を外部電気回路基板上に実装した後、両者の間に外部からの衝撃が加えられた場合に、両者の接合部での破断が発生しやすいものとなるからである。銅から成る外部接続パッドの上にニッケルめっき層を含むめっき金属層が被着されている場合、このような衝撃に良好に耐えるための耐衝撃性が高くなる。なお、外部接続パッドは半導体素子接続パッドと比較してその面積が10〜100倍程度大きく、そのため単位面積当たりに流れる電流密度も半導体素子接続パッドの場合に比較して10〜100分の1とはるかに小さいものとなるため、外部接続パッドと外部電気回路基板との間に長期間にわたり電流が流れたとしても、両者を接続する半田ボール中にエレクトロマイグレーションによるボイドが発生する危険性は極めて小さい。したがって、銅から成る外部接続パッド上に半田を直接溶着する必要は無い。   On the other hand, it is preferable that a plating metal layer including a nickel plating layer is applied to the external connection pads as a base for welding solder balls. This is because when solder made of lead-free solder is directly welded on an external connection pad made of copper, after mounting the wiring board on the external electric circuit board, an external impact is applied between them. This is because breakage at the joint between the two tends to occur. When a plated metal layer including a nickel plating layer is deposited on the external connection pad made of copper, the impact resistance for satisfactorily withstanding such an impact is enhanced. Note that the area of the external connection pad is about 10 to 100 times larger than that of the semiconductor element connection pad. Therefore, the current density per unit area is 10 to 1/100 that of the semiconductor element connection pad. Since the current is much smaller, even if a current flows between the external connection pad and the external electric circuit board for a long time, the risk of voids due to electromigration in the solder balls connecting the two is extremely small. . Therefore, it is not necessary to weld solder directly on the external connection pad made of copper.

ところで、このように半導体素子接続パッドに半田バンプが直接溶着されているとともに、外部接続パッドにニッケル−パラジウム−金めっき等のめっき金属層が被着された配線基板を得るには、以下に述べる方法が考えられる。まず、絶縁基板の上面に半導体素子接続パッドを形成するとともに絶縁基板の下面に外部接続パッドを形成する。次に、絶縁基板の上下面に、感光性を有するソルダーレジスト用樹脂層を、それぞれ半導体素子接続パッドおよび外部接続パッドを覆うようにして被着させる。次に、絶縁基板上下面のソルダーレジスト用樹脂層に露光および現像処理を施した後、それらを紫外線硬化および熱硬化させることにより、絶縁基板の上面に半導体素子接続パッドの中央部を露出させる開口部を有する上面側のソルダーレジスト層を形成するとともに、絶縁基板の下面に外部接続パッドの中央部を露出させる開口部を有する下面側のソルダーレジスト層を形成する。次に上面側のソルダーレジスト層の上のみに半導体素子接続パッドを覆うようにしてめっきレジスト層を積層するとともに、下面側のソルダーレジスト層から露出する外部接続パッドの表面にめっき金属層を無電解めっき法により被着させる。そして最後に上面側のソルダーレジスト層からめっきレジスト層を剥離して除去するとともに、ソルダーレジスト層から露出する半導体素子接続パッド上に半田バンプを溶着する。   By the way, in order to obtain a wiring substrate in which solder bumps are directly welded to the semiconductor element connection pads and a plating metal layer such as nickel-palladium-gold plating is applied to the external connection pads, it will be described below. A method is conceivable. First, a semiconductor element connection pad is formed on the upper surface of the insulating substrate, and an external connection pad is formed on the lower surface of the insulating substrate. Next, a photosensitive solder resist resin layer is deposited on the upper and lower surfaces of the insulating substrate so as to cover the semiconductor element connection pads and the external connection pads, respectively. Next, the solder resist resin layers on the upper and lower surfaces of the insulating substrate are exposed and developed, and then UV-cured and thermally cured to expose the central portion of the semiconductor element connection pad on the upper surface of the insulating substrate. And forming a lower side solder resist layer having an opening exposing the central portion of the external connection pad on the lower surface of the insulating substrate. Next, a plating resist layer is laminated so as to cover the semiconductor element connection pad only on the solder resist layer on the upper surface side, and the plating metal layer is electrolessly formed on the surface of the external connection pad exposed from the solder resist layer on the lower surface side. Deposit by plating. Finally, the plating resist layer is peeled off and removed from the solder resist layer on the upper surface side, and solder bumps are welded onto the semiconductor element connection pads exposed from the solder resist layer.

しかしながら、この方法によると、上面側のソルダーレジスト層の上に半導体素子接続パッドを覆うようにしてめっきレジスト層を積層するとともに、下面側のソルダーレジスト層から露出する外部接続パッドの表面にめっき金属層を無電解めっき法により被着させる際に、めっきレジスト層が無電解めっき液に侵されて無電解めっき液中に溶出して無電解めっき液を分解したり、外部接続パッドの表面に被着されるめっき金属層を良好に被着できなくしたりする。これは無電解めっき液が強いアルカリ性を示すとともに高い温度であり、めっきレジストが被めっき物からの剥離性を確保するためにアルカリ性の剥離液に対して侵されやすい性質を与えられているためである。したがって、このような方法で半導体素子接続パッドに半田バンプが直接溶着されているとともに、外部接続パッドにニッケル−パラジウム−金めっき等のめっき金属層が無電解めっき法により被着された配線基板を得ることは困難である。   However, according to this method, the plating resist layer is laminated so as to cover the semiconductor element connection pad on the solder resist layer on the upper surface side, and the plating metal is exposed on the surface of the external connection pad exposed from the solder resist layer on the lower surface side. When depositing the layer by the electroless plating method, the plating resist layer is attacked by the electroless plating solution and eluted into the electroless plating solution to decompose the electroless plating solution or to cover the surface of the external connection pad. The plated metal layer to be deposited cannot be deposited well. This is because the electroless plating solution exhibits strong alkalinity and is at a high temperature, and the plating resist is given the property of being easily attacked by the alkaline stripping solution in order to ensure the peelability from the object to be plated. is there. Therefore, a wiring board in which a solder bump is directly welded to a semiconductor element connection pad by such a method and a plating metal layer such as nickel-palladium-gold plating is attached to the external connection pad by an electroless plating method. It is difficult to get.

特開2005−191131号公報JP 2005-191131 A

本発明の課題は、絶縁基板の下面に設けた銅から成る外部接続パッドに無電解めっき法によるめっき金属層が良好に被着されているとともに、絶縁基板の上面に設けた銅から成る半導体素子接続パッドに半田が直接溶着された配線基板の製造方法を提供することにある。   SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor element made of copper provided on the upper surface of an insulating substrate, while an external connection pad made of copper provided on the lower surface of the insulating substrate is well coated with a plated metal layer by an electroless plating method. An object of the present invention is to provide a method of manufacturing a wiring board in which solder is directly welded to a connection pad.

本発明の配線基板の製造方法は、絶縁基板の上面に半導体素子の電極が接続される半導体素子接続パッドを形成するとともに該絶縁基板の下面に外部電気回路基板に接続される外部接続パッドを形成する工程と、
感光性を有するソルダーレジスト用樹脂層を、前記絶縁基板の上面および下面に前記半導体素子接続パッドおよび前記外部接続パッドを覆うように被着させる工程と、
感光性を有する前記ソルダーレジスト用樹脂層を、該ソルダーレジスト用樹脂層における前記半導体素子接続パッドの中央部に対応する部位と前記外部接続パッドの中央部に対応する部位とが選択的に未露光部として残り、該未露光部以外の部位が感光されるように露光する工程と、
露光された前記ソルダーレジスト用樹脂層を、前記感光された部位がそのままで残るとともに前記未露光部の一部が前記感光された部位よりも薄い薄膜となって前記半導体素子接続パッドの中央部および前記外部接続パッドの中央部を覆って残るように現像した後、現像されたソルダーレジスト用樹脂層を硬化させる工程と、
硬化した前記ソルダーレジスト用樹脂層における前記薄膜を絶縁基板の下面側のみ除去して前記外部接続パッドの中央部を露出させる工程と、
前記半導体素子接続パッドの中央部を前記薄膜で覆ったままの状態で、前記外部接続パッドの露出した中央部に無電解めっき法によりめっき金属層を被着させる工程と、
絶縁基板の上面側の前記ソルダーレジスト用樹脂層における前記薄膜を除去して前記半導体素子接続パッドの中央部を露出させる工程と、
露出した前記半導体素子接続パッドの中央部に半田を溶着させる工程と、
を行なうことを特徴とするものである。
According to the method for manufacturing a wiring board of the present invention, a semiconductor element connection pad to which an electrode of a semiconductor element is connected is formed on an upper surface of an insulating substrate, and an external connection pad to be connected to an external electric circuit board is formed on the lower surface of the insulating substrate And a process of
Applying a photosensitive solder resist resin layer to the upper and lower surfaces of the insulating substrate so as to cover the semiconductor element connection pads and the external connection pads;
The solder resist resin layer having photosensitivity is selectively unexposed to a portion corresponding to the center portion of the semiconductor element connection pad and a portion corresponding to the center portion of the external connection pad in the solder resist resin layer. A step of exposing so that a portion other than the unexposed portion is exposed;
In the exposed solder resist resin layer, the exposed part remains as it is, and a part of the unexposed part becomes a thin film thinner than the exposed part, and the central part of the semiconductor element connection pad and Step of curing the developed solder resist resin layer after developing so as to cover the central portion of the external connection pad, and
Removing the thin film of the cured resin layer for solder resist only on the lower surface side of the insulating substrate to expose the central portion of the external connection pad; and
A step of depositing a plating metal layer by an electroless plating method on the exposed central portion of the external connection pad while the central portion of the semiconductor element connection pad is covered with the thin film;
Removing the thin film in the solder resist resin layer on the upper surface side of the insulating substrate to expose a central portion of the semiconductor element connection pad;
A step of welding solder to the exposed central portion of the semiconductor element connection pad;
It is characterized by performing.

本発明の配線基板の製造方法によれば、絶縁基板の上面側に形成した半導体素子接続パッドの中央部をソルダーレジスト用樹脂層の硬化した薄膜で覆ったままの状態で、絶縁基板の下面側に形成した外部接続パッドの中央部を露出させ、その露出した外部接続パッドの中央部に無電解めっき法によりめっき金属層を被着させることから、外部接続パッドにめっき金属層を被着させる際には、半導体素子接続パッドはソルダーレジスト用樹脂層が硬化した薄膜で覆われているので、外部接続パッドのみに選択的にめっき金属層を被着させることができる。この場合、半導体素子接続パッドの中央部を覆うソルダーレジスト用樹脂層の薄膜は硬化されて樹脂成分の架橋が進んでいるので、強いアルカリ性を呈する無電解めっき液中であっても、めっき液中に溶出することはなく、したがって、外部接続パッドに無電解めっき法によりめっき金属層を良好に被着させることができる。また、外部接続パッドにめっき金属層を被着させた後に、半導体素子接続パッド上のソルダーレジスト用樹脂層の薄膜を除去し、露出した半導体素子接続パッドの中央部に半田を溶着させることから、銅から成る半導体素子接続パッド上に半田を直接溶着することができる。   According to the method for manufacturing a wiring board of the present invention, the lower surface side of the insulating substrate with the central portion of the semiconductor element connection pad formed on the upper surface side of the insulating substrate covered with the hardened thin film of the solder resist resin layer. When the plated metal layer is deposited on the external connection pad, the central portion of the external connection pad formed on the surface is exposed and the plated metal layer is deposited on the exposed central portion of the external connection pad by electroless plating. Since the semiconductor element connection pad is covered with a thin film obtained by curing the solder resist resin layer, the plated metal layer can be selectively applied only to the external connection pad. In this case, since the thin film of the solder resist resin layer covering the central portion of the semiconductor element connection pad is cured and the crosslinking of the resin component is proceeding, even in the electroless plating solution exhibiting strong alkalinity, Therefore, the plated metal layer can be satisfactorily applied to the external connection pads by the electroless plating method. In addition, after depositing the plating metal layer on the external connection pad, the thin film of the solder resist resin layer on the semiconductor element connection pad is removed, and solder is welded to the exposed central part of the semiconductor element connection pad. Solder can be directly deposited on the semiconductor element connection pad made of copper.

図1は、本発明の配線基板の製造方法を説明するための工程毎の要部拡大概略断面図である。FIG. 1 is an enlarged schematic cross-sectional view of a main part for each process for explaining a method for manufacturing a wiring board according to the present invention.

次に、本発明の配線基板の製造方法の実施形態の一例を添付の図1(a)〜(h)を基に説明する。まず、図1(a)に示すように、絶縁基板1の上面に半導体素子の電極が電気的に接続される半導体素子接続パッド2を形成するとともに絶縁基板1の下面に外部電気回路基板の配線導体に電気的に接続される外部接続パッド3を形成する。   Next, an example of an embodiment of the method for manufacturing a wiring board according to the present invention will be described with reference to FIGS. 1 (a) to 1 (h). First, as shown in FIG. 1A, a semiconductor element connection pad 2 to which an electrode of a semiconductor element is electrically connected is formed on the upper surface of the insulating substrate 1 and wiring of an external electric circuit board is formed on the lower surface of the insulating substrate 1. External connection pads 3 that are electrically connected to the conductor are formed.

絶縁基板1は、例えばガラス−エポキシ板やエポキシ樹脂から成る複数の絶縁層を積層して成る平板であり、その内部には銅箔や無電解および電解銅めっき層から成る内部配線導体(不図示)が形成されている。   The insulating substrate 1 is a flat plate formed by laminating a plurality of insulating layers made of, for example, a glass-epoxy plate or an epoxy resin, and has an internal wiring conductor (not shown) made of a copper foil or an electroless and electrolytic copper plating layer. ) Is formed.

半導体素子接続パッド2および外部接続パッド3は、それぞれ厚みが10〜30μm程度の銅箔や無電解および電解銅めっき層から成り、従来周知のサブトラクティブ法やセミアディティブ法により形成される。なお、半導体素子接続パッド2の大きさは直径が50〜100μm程度、外部接続パッド3の大きさは直径が300〜1000μm程度である。   The semiconductor element connection pad 2 and the external connection pad 3 are each formed of a copper foil or an electroless and electrolytic copper plating layer having a thickness of about 10 to 30 μm, and are formed by a conventionally known subtractive method or semi-additive method. The semiconductor element connection pad 2 has a diameter of about 50 to 100 μm, and the external connection pad 3 has a diameter of about 300 to 1000 μm.

次に、図1(b)に示すように、感光性を有するソルダーレジスト用樹脂層4,5を、絶縁基板1の上面および下面に半導体素子接続パッド2および外部接続パッド3を覆うように被着させる。なお、ソルダーレジスト用樹脂層4,5の厚みは半導体素子接続パッド2上および外部接続パッド3上で10〜20μm程度の厚みとする。   Next, as shown in FIG. 1B, the solder resist resin layers 4 and 5 having photosensitivity are covered so as to cover the semiconductor element connection pads 2 and the external connection pads 3 on the upper and lower surfaces of the insulating substrate 1. Put on. The solder resist resin layers 4 and 5 have a thickness of about 10 to 20 μm on the semiconductor element connection pad 2 and the external connection pad 3.

次に、図1(c)に示すように、感光性を有するソルダーレジスト用樹脂層4,5を、ソルダーレジスト用樹脂層4,5における半導体素子接続パッド2の中央部に対応する部位と外部接続パッドの中央部に対応する部位とが選択的に未露光部4a,5aとして残るとともに、未露光部4a,5a以外の部位が感光されるように露光する。なお、露光の際には、未露光部4a,5aに対応する部分が紫外線を透過せず、それ以外の部分が紫外線を透過するガラス板からなる露光マスクをソルダーレジスト用樹脂層4,5に対向するように配置し、そのマスクを透して未露光部4a,5a以外の部位に紫外線を照射して感光させる方法が採用される。   Next, as shown in FIG. 1C, the solder resist resin layers 4, 5 having photosensitivity are arranged between a portion corresponding to the central portion of the semiconductor element connection pad 2 in the solder resist resin layers 4, 5 and the outside. The part corresponding to the central part of the connection pad remains selectively as unexposed parts 4a and 5a, and exposure is performed so that parts other than the unexposed parts 4a and 5a are exposed. At the time of exposure, the portions corresponding to the unexposed portions 4a and 5a do not transmit ultraviolet rays, and the other portions are exposed to ultraviolet rays on the solder resist resin layers 4 and 5, respectively. A method is adopted in which they are arranged so as to face each other, and the portions other than the unexposed portions 4a and 5a are irradiated with ultraviolet rays through the mask to be exposed.

次に、図1(d)に示すように、露光されたソルダーレジスト用樹脂層4,5を、感光された部位がそのままで残るとともに未露光部4a,5aの一部が感光された部位よりも薄い薄膜4b,5bとなって半導体素子接続パッド2の中央部および外部接続パッド3の中央部を覆って残るように現像する。なお、現像には、炭酸ナトリウムを含有するアルカリ性の現像液が用いられる。半導体素子接続パッド2の中央部および外部接続パッド3の中央部を覆って残る薄膜4b,5bの厚みは0.5〜2.0μm程度である。このような厚みの薄膜4b,5bを残すためには、現像の時間を通常より短くしたり、現像液の温度を通常より下げたり、現像液の濃度を通常よりも下げたりする。これらの操作を単独あるいは組み合わせて現像を行なうことにより、未露光部4a,5aが完全に除去することなく半導体素子接続パッド2の中央部および外部接続パッド3の中央部に0.5〜2.0μmの厚みの薄膜4b,5bを形成することが可能である。   Next, as shown in FIG. 1D, the exposed solder resist resin layers 4 and 5 remain exposed as they are and the unexposed portions 4a and 5a are partially exposed from the exposed portions. The thin films 4b and 5b are developed so as to cover the central portion of the semiconductor element connection pad 2 and the central portion of the external connection pad 3 so as to remain. For development, an alkaline developer containing sodium carbonate is used. The thickness of the thin films 4b and 5b remaining covering the central portion of the semiconductor element connection pad 2 and the central portion of the external connection pad 3 is about 0.5 to 2.0 μm. In order to leave the thin films 4b and 5b having such a thickness, the developing time is shortened from the normal time, the temperature of the developing solution is decreased from the normal level, or the concentration of the developing solution is decreased from the normal level. By developing these operations singly or in combination, the unexposed portions 4a and 5a are not removed completely, and 0.5 to 2.. It is possible to form thin films 4b and 5b having a thickness of 0 μm.

次に、現像されたソルダーレジスト用樹脂層4,5を硬化させる。硬化には紫外線硬化および熱硬化が用いられる。紫外線硬化の場合、ソルダーレジスト用樹脂層4,5の全面に紫外線を照射する。熱硬化の場合、ソルダーレジスト用樹脂層4,5をその熱硬化温度より高い温度に加熱する。紫外線硬化の後に熱硬化を行なってもよいし、熱硬化の後に紫外線硬化を行なってもよい。ソルダーレジスト用樹脂層4,5は、硬化により含有される樹脂成分の架橋が進み、耐アルカリ性が強いものとなる。   Next, the developed solder resist resin layers 4 and 5 are cured. For curing, ultraviolet curing and thermal curing are used. In the case of ultraviolet curing, the entire surface of the solder resist resin layers 4 and 5 is irradiated with ultraviolet rays. In the case of thermosetting, the solder resist resin layers 4 and 5 are heated to a temperature higher than the thermosetting temperature. Thermal curing may be performed after ultraviolet curing, or ultraviolet curing may be performed after thermal curing. The resin layers 4 and 5 for the solder resist have a strong alkali resistance due to the progress of crosslinking of the resin component contained by the curing.

次に、図1(e)に示すように、硬化した下面側のソルダーレジスト用樹脂層5における薄膜5bを除去して外部接続パッド3の中央部を露出させる。薄膜5bの除去には、例えばウェットブラスト法が用いられる。具体的には、外部接続パッド3の中央部を覆う薄膜5bが消失するまで下面側のソルダーレジスト用樹脂層5の全面にアルミナ等から成る砥粒を水とともに高圧で吹き付ける方法が採用される。この吹き付けにより、下面側のソルダーレジスト用樹脂層5の表面が薄く削り取られて薄膜5bを除去できる。このとき、上面側のソルダーレジスト用樹脂層4における薄膜4bは、半導体素子接続パッド2の中央部を覆ったままで残しておく。また、薄膜5bの除去後には、露出した外部接続パッド3の表面を過酸化水素および硫酸を含有するエッチング液で薄くエッチングして清浄化することが好ましい。   Next, as shown in FIG. 1E, the thin film 5 b in the cured solder resist resin layer 5 on the lower surface side is removed to expose the central portion of the external connection pad 3. For removing the thin film 5b, for example, a wet blast method is used. Specifically, a method of spraying abrasive grains made of alumina or the like together with water at high pressure on the entire surface of the solder resist resin layer 5 on the lower surface side until the thin film 5b covering the central portion of the external connection pad 3 disappears is employed. By this spraying, the surface of the solder resist resin layer 5 on the lower surface side is thinly scraped off and the thin film 5b can be removed. At this time, the thin film 4 b in the solder resist resin layer 4 on the upper surface side is left while covering the central portion of the semiconductor element connection pad 2. In addition, after removing the thin film 5b, it is preferable to clean the exposed surface of the external connection pad 3 by thin etching with an etching solution containing hydrogen peroxide and sulfuric acid.

次に、図1(f)に示すように、露出した外部接続パッド3の表面に無電解めっき法によりめっき金属層6を形成する。めっき金属層6としてはニッケルめっき層と、パラジウムめっき層と、金めっき層とを順次被着させたニッケル−パラジウム−金めっき層が好ましい。ニッケルめっき層は、例えば硫酸ニッケルとクエン酸ナトリウム、酢酸ナトリウム、次亜リン酸ナトリウム、塩化アンモニウム等を含有する無電解ニッケル−リンめっき液を用いて外部接続パッド3の露出面上にリンを3〜10質量%程度含有する無電解ニッケルめっき層を析出させることにより被着される。無電解ニッケルめっき層の厚みは0.5〜10μmの範囲が好ましい。パラジウムめっき層は、例えば塩化テトラアンミンパラジウムとエチレンジアミン、次亜燐酸ナトリウム等を含有する還元型無電解パラジウム−リンめっき液を用いてニッケルめっき層上にリンを2〜5質量%含有する還元型無電解パラジウムめっき層を析出させることにより被着される。パラジウムめっき層の厚みは0.01〜0.2μm範囲が好ましく、0.03〜0.1μmの範囲が特に好ましい。金めっき層は、例えばシアン化金カリウムと水酸化カリウム、スルホン酸塩、シアン化カリウム、アミノアルコール等を含有する置換還元型無電解金めっき液を用いてパラジウムめっき層上に置換還元型無電解金めっき層を析出させることにより被着される。金めっき層の厚みは0.01〜0.5μm範囲が好ましい。なお、めっき金属層6としては、ニッケルめっき層と金めっき層とを順次被着させたニッケル−金めっき層を用いても良い。   Next, as shown in FIG. 1F, a plated metal layer 6 is formed on the exposed surface of the external connection pad 3 by an electroless plating method. The plating metal layer 6 is preferably a nickel-palladium-gold plating layer in which a nickel plating layer, a palladium plating layer, and a gold plating layer are sequentially deposited. The nickel plating layer is formed by using an electroless nickel-phosphorous plating solution containing, for example, nickel sulfate and sodium citrate, sodium acetate, sodium hypophosphite, ammonium chloride, and the like to form phosphorus 3 on the exposed surface of the external connection pad 3. It deposits by depositing the electroless nickel plating layer which contains about 10 mass%. The thickness of the electroless nickel plating layer is preferably in the range of 0.5 to 10 μm. The palladium plating layer is, for example, a reduced electroless material containing 2 to 5% by mass of phosphorus on the nickel plated layer using a reduced electroless palladium-phosphorous plating solution containing tetraamminepalladium chloride, ethylenediamine, sodium hypophosphite and the like. Deposited by depositing a palladium plating layer. The thickness of the palladium plating layer is preferably in the range of 0.01 to 0.2 μm, particularly preferably in the range of 0.03 to 0.1 μm. The gold plating layer is, for example, a substitution reduction type electroless gold plating on a palladium plating layer using a substitution reduction type electroless gold plating solution containing potassium gold cyanide and potassium hydroxide, sulfonate, potassium cyanide, amino alcohol, etc. Deposited by depositing a layer. The thickness of the gold plating layer is preferably in the range of 0.01 to 0.5 μm. The plated metal layer 6 may be a nickel-gold plated layer in which a nickel plated layer and a gold plated layer are sequentially deposited.

このとき、上面側の半導体素子接続パッド2は、ソルダーレジスト用樹脂層4の硬化した薄膜4bで覆われているので、めっき金属層が半導体素子接続パッドに被着されることはない。また、めっき金属層6を被着するためのめっき液は、強いアルカリ性を示すものの、半導体素子接続パッド2の中央部を被覆する薄膜4bは硬化して樹脂成分の架橋が進んでいるので、めっき液中に溶出することはなく、したがって、外部接続パッドにめっき金属層6を良好に被着させることができる。   At this time, since the semiconductor element connection pad 2 on the upper surface side is covered with the hardened thin film 4b of the solder resist resin layer 4, the plated metal layer is not attached to the semiconductor element connection pad. In addition, although the plating solution for depositing the plating metal layer 6 exhibits strong alkalinity, the thin film 4b covering the central portion of the semiconductor element connection pad 2 is cured and the crosslinking of the resin component is proceeding. Therefore, the plating metal layer 6 can be satisfactorily adhered to the external connection pad.

次に、図1(g)に示すように、硬化した上面側のソルダーレジスト用樹脂層4における薄膜4bを除去して半導体素子接続パッド2の中央部を露出させる。薄膜4bの除去には、薄膜5bの場合と同様に例えばウェットブラスト法が用いられる。具体的には、半導体素子接続パッド2の中央部を覆う薄膜4bが消失するまで上面側のソルダーレジスト用樹脂層4の全面にアルミナ等から成る砥粒を水とともに高圧で吹き付ける方法が採用される。この吹き付けにより、上面側のソルダーレジスト用樹脂層4の表面が薄く削り取られて薄膜4bが除去される。なお、薄膜4bの除去後には、露出した半導体素子接続パッド2の表面を過酸化水素および硫酸を含有するエッチング液で薄くエッチングして清浄化することが好ましい。   Next, as shown in FIG. 1G, the thin film 4b in the cured solder resist resin layer 4 on the upper surface side is removed to expose the central portion of the semiconductor element connection pad 2. For the removal of the thin film 4b, for example, a wet blast method is used as in the case of the thin film 5b. Specifically, a method is adopted in which abrasive grains made of alumina or the like are sprayed together with water at high pressure on the entire surface of the solder resist resin layer 4 on the upper surface side until the thin film 4b covering the central portion of the semiconductor element connection pad 2 disappears. . By this spraying, the surface of the solder resist resin layer 4 on the upper surface side is thinly scraped off and the thin film 4b is removed. In addition, after the removal of the thin film 4b, it is preferable to clean the exposed surface of the semiconductor element connection pad 2 by thin etching with an etching solution containing hydrogen peroxide and sulfuric acid.

最後に、図1(h)に示すように、露出した半導体素子接続パッド2の上に鉛フリー半田から成る半田バンプ7を直接溶着することによって本発明による配線基板が完成する。なお、半導体素子接続パッド2に半田バンプ7を溶着するには、半導体素子接続パッド2上に半田ペーストをスクリーン印刷法により印刷した後、リフローする方法や、半導体素子接続パッド上に半田ボールを搭載した後、リフローする方法が採用される。   Finally, as shown in FIG. 1H, the wiring board according to the present invention is completed by directly welding solder bumps 7 made of lead-free solder on the exposed semiconductor element connection pads 2. In order to weld the solder bumps 7 to the semiconductor element connection pads 2, a solder paste is printed on the semiconductor element connection pads 2 by a screen printing method and then reflowed, or solder balls are mounted on the semiconductor element connection pads. Then, a reflow method is adopted.

かくして、本発明の配線基板の製造方法によれば、絶縁基板の下面に設けた銅から成る外部接続パッドに無電解めっき法によるめっき金属層が良好に被着されているとともに、絶縁基板の上面に設けた銅から成る半導体素子接続パッドに半田が直接溶着された配線基板を提供することができる。   Thus, according to the method for manufacturing a wiring board of the present invention, the plated metal layer by the electroless plating method is satisfactorily applied to the external connection pad made of copper provided on the lower surface of the insulating substrate, and the upper surface of the insulating substrate. It is possible to provide a wiring substrate in which solder is directly welded to a semiconductor element connection pad made of copper.

1 絶縁基板
2 半導体素子接続パッド
3 外部接続パッド
4,5 ソルダーレジスト用樹脂層
4a,5a 未露光部
4b,5b 薄膜
6 めっき金属層
7 半田
DESCRIPTION OF SYMBOLS 1 Insulation board | substrate 2 Semiconductor element connection pad 3 External connection pad 4,5 Solder resist resin layer 4a, 5a Unexposed part 4b, 5b Thin film 6 Plating metal layer 7 Solder

Claims (1)

絶縁基板の上面に半導体素子の電極が接続される半導体素子接続パッドを形成するとともに該絶縁基板の下面に外部電気回路基板に接続される外部接続パッドを形成する工程と、
感光性を有するソルダーレジスト用樹脂層を、前記絶縁基板の上面および下面に前記半導体素子接続パッドおよび前記外部接続パッドを覆うように被着させる工程と、
感光性を有する前記ソルダーレジスト用樹脂層を、該ソルダーレジスト用樹脂層における前記半導体素子接続パッドの中央部に対応する部位と前記外部接続パッドの中央部に対応する部位とが選択的に未露光部として残り、該未露光部以外の部位が感光されるように露光する工程と、
露光された前記ソルダーレジスト用樹脂層を、前記感光された部位がそのままで残るとともに前記未露光部の一部が前記感光された部位よりも薄い薄膜となって前記半導体素子接続パッドの中央部および前記外部接続パッドの中央部を覆って残るように現像した後、現像されたソルダーレジスト用樹脂層を硬化させる工程と、
硬化した前記ソルダーレジスト用樹脂層における前記薄膜を絶縁基板の下面側のみ除去して前記外部接続パッドの中央部を露出させる工程と、
前記半導体素子接続パッドの中央部を前記薄膜で覆ったままの状態で、前記外部接続パッドの露出した中央部に無電解めっき法によりめっき金属層を被着させる工程と、
絶縁基板の上面側の前記ソルダーレジスト用樹脂層における前記薄膜を除去して前記半導体素子接続パッドの中央部を露出させる工程と、
露出した前記半導体素子接続パッドの中央部に半田を溶着させる工程と、
を行なうことを特徴とする配線基板の製造方法。
Forming a semiconductor element connection pad connected to the electrode of the semiconductor element on the upper surface of the insulating substrate and forming an external connection pad connected to the external electric circuit substrate on the lower surface of the insulating substrate;
Applying a photosensitive solder resist resin layer to the upper and lower surfaces of the insulating substrate so as to cover the semiconductor element connection pads and the external connection pads;
The solder resist resin layer having photosensitivity is selectively unexposed to a portion corresponding to the center portion of the semiconductor element connection pad and a portion corresponding to the center portion of the external connection pad in the solder resist resin layer. A step of exposing so that a portion other than the unexposed portion is exposed;
In the exposed solder resist resin layer, the exposed part remains as it is, and a part of the unexposed part becomes a thin film thinner than the exposed part, and the central part of the semiconductor element connection pad and Step of curing the developed solder resist resin layer after developing so as to cover the central portion of the external connection pad, and
Removing the thin film of the cured resin layer for solder resist only on the lower surface side of the insulating substrate to expose the central portion of the external connection pad; and
A step of depositing a plating metal layer by an electroless plating method on the exposed central portion of the external connection pad while the central portion of the semiconductor element connection pad is covered with the thin film;
Removing the thin film in the solder resist resin layer on the upper surface side of the insulating substrate to expose a central portion of the semiconductor element connection pad;
A step of welding solder to the exposed central portion of the semiconductor element connection pad;
A method for manufacturing a wiring board, comprising:
JP2011041048A 2011-02-28 2011-02-28 Manufacturing method of wiring board Withdrawn JP2012178482A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104378933A (en) * 2013-08-12 2015-02-25 株式会社东芝 Method for manufacturing wiring substrate and semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104378933A (en) * 2013-08-12 2015-02-25 株式会社东芝 Method for manufacturing wiring substrate and semiconductor device
TWI607546B (en) * 2013-08-12 2017-12-01 Toshiba Memory Corp Wiring substrate manufacturing method and semiconductor device manufacturing method

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