JP5959255B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP5959255B2
JP5959255B2 JP2012065989A JP2012065989A JP5959255B2 JP 5959255 B2 JP5959255 B2 JP 5959255B2 JP 2012065989 A JP2012065989 A JP 2012065989A JP 2012065989 A JP2012065989 A JP 2012065989A JP 5959255 B2 JP5959255 B2 JP 5959255B2
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lead
die pad
lower electrode
semiconductor element
power supply
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JP2013197517A (en
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康次 野口
康次 野口
聖明 門井
聖明 門井
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Ablic Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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Description

本発明は、容量素子を内蔵した半導体装置に関する。   The present invention relates to a semiconductor device incorporating a capacitor element.

通常、フィードバック回路などを搭載する半導体装置においては、電源用リードと接地用リードとの間に外付けの容量素子を設け、発振などの誤動作を防いでいる。チップコンデンサなどが同時に実装されることもある。電子機器の小型化・軽量化・高機能化に伴い、電子機器に搭載する部品を高密度に実装することが要求されている。   Normally, in a semiconductor device equipped with a feedback circuit or the like, an external capacitor element is provided between a power supply lead and a ground lead to prevent malfunction such as oscillation. A chip capacitor or the like may be mounted at the same time. As electronic devices become smaller, lighter, and more functional, it is required to mount components to be mounted on the electronic device with high density.

近年、容量素子をパッケージ内部に搭載した半導体装置が求められている。特許文献１においては、図１９に示すように、半導体素子と、半導体素子に電気的に接続される電源用リード５と、半導体素子に電気的に接続される接地用リード６と、半導体素子に電気的に接続される信号用リード７と、半導体素子を囲むように配置され、電源用リード５と接地用リード６とを容量結合する容量素子４と、それらを被覆するモールド樹脂ケースとを備えた半導体装置が示されている。   In recent years, there has been a demand for a semiconductor device in which a capacitive element is mounted inside a package. In Patent Document 1, as shown in FIG. 19, a semiconductor element, a power supply lead 5 electrically connected to the semiconductor element, a ground lead 6 electrically connected to the semiconductor element, and a semiconductor element A signal lead 7 that is electrically connected, a capacitive element 4 that is disposed so as to surround the semiconductor element and capacitively couples the power supply lead 5 and the grounding lead 6, and a molded resin case that covers them. A semiconductor device is shown.

特開平０６−１９６６２３号公報Japanese Patent Laid-Open No. 06-196623

しかし、特許文献１に開示された技術では、容量素子は半導体装置内部で半導体素子を囲むように配置されるので、容量素子のためのスペースが狭い。よって、容量素子の静電容量が十分ではなく、発振などの誤動作が完全に防止されないことがある。
本発明は、上記課題に鑑みてなされ、十分な静電容量を有する容量素子を有する半導体装置を提供することを課題とする。 However, in the technique disclosed in Patent Document 1, since the capacitive element is arranged so as to surround the semiconductor element inside the semiconductor device, the space for the capacitive element is narrow. Therefore, the capacitance of the capacitive element is not sufficient, and malfunctions such as oscillation may not be completely prevented.
The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device having a capacitor having a sufficient capacitance.

本発明は、上記課題を解決するため、半導体素子と、電源用リードと、信号用リードと、接地用リードと、ダイパッドと、前記ダイパッド上に前記半導体素子を接着する接着剤と、前記半導体素子と外部との電気的接続のためのボンディングワイヤと、前記電源用リードと前記接地用リードに接続される前記ダイパッドとの間に、および／または、前記信号用リードと前記接地用リードに接続される前記ダイパッドとの間に、挟まれた誘電体と、前記半導体素子と前記接着剤と前記電源用リードと前記信号用リードと前記接地用リードと前記ダイパッドと前記ボンディングワイヤと前記誘電体とを、封止する封止樹脂と、を備えることを特徴とする半導体装置を提供する。   In order to solve the above-described problems, the present invention provides a semiconductor element, a power supply lead, a signal lead, a ground lead, a die pad, an adhesive that bonds the semiconductor element on the die pad, and the semiconductor element. And a bonding wire for electrical connection with the outside and between the power supply lead and the die pad connected to the ground lead and / or connected to the signal lead and the ground lead A dielectric sandwiched between the die pad, the semiconductor element, the adhesive, the power supply lead, the signal lead, the ground lead, the die pad, the bonding wire, and the dielectric. A semiconductor device comprising: a sealing resin for sealing.

本発明では、接地用リードに接続される半導体装置のダイパッド全体が、半導体装置内部における容量素子の接地電圧の電極として機能する。よって、その容量素子の各電極の対向面積が広くなり、その静電容量が大きくなる。   In the present invention, the entire die pad of the semiconductor device connected to the ground lead functions as an electrode for the ground voltage of the capacitive element inside the semiconductor device. Therefore, the opposing area of each electrode of the capacitive element is increased, and the capacitance is increased.

半導体装置の第一の実施形態を示す斜視図である。1 is a perspective view showing a first embodiment of a semiconductor device. 図１の上面図である。FIG. 2 is a top view of FIG. 1. 図１の側面図である。It is a side view of FIG. 半導体装置の第二の実施形態を示す斜視図である。It is a perspective view which shows 2nd embodiment of a semiconductor device. 図４の上面図である。FIG. 5 is a top view of FIG. 4. 図４の側面図である。FIG. 5 is a side view of FIG. 4. 半導体装置の第三の実施形態を示す斜視図である。It is a perspective view which shows 3rd embodiment of a semiconductor device. 図７の上面図である。FIG. 8 is a top view of FIG. 7. 図７の側面図である。FIG. 8 is a side view of FIG. 7. 半導体装置の第四の実施形態を示す斜視図である。It is a perspective view which shows 4th embodiment of a semiconductor device. 図１０の上面図である。It is a top view of FIG. 図１０の側面図である。It is a side view of FIG. 半導体装置の第五の実施形態を示す斜視図である。It is a perspective view which shows 5th embodiment of a semiconductor device. 図１３の上面図である。FIG. 14 is a top view of FIG. 13. 図１３の側面図である。FIG. 14 is a side view of FIG. 13. 半導体装置の第六の実施形態を示す斜視図である。It is a perspective view which shows 6th embodiment of a semiconductor device. 図１６の上面図である。FIG. 17 is a top view of FIG. 16. 図１６の側面図である。FIG. 17 is a side view of FIG. 16. 従来の半導体装置を示す図である。It is a figure which shows the conventional semiconductor device.

以下、本発明の実施形態を、図面を参照して説明する。
＜第一実施形態＞
図１は、半導体装置を示す斜視図である。図２は、図１の上面図である。図３は、図１の側面図である。 Embodiments of the present invention will be described below with reference to the drawings.
<First embodiment>
FIG. 1 is a perspective view showing a semiconductor device. FIG. 2 is a top view of FIG. FIG. 3 is a side view of FIG.

半導体装置は、半導体素子１と、ダイパッド５と、ダイパッド５上に半導体素子１を接着する接着剤１０（図３に表示）と、電源用リード２と、信号用リード３と、接地用リード４と、半導体素子１と各リードあるいはダイパッドとの間の電気的接続のためのボンディングワイヤ６を有しており、各ボンディングワイヤ６は、半導体素子１の電源用パッドと電源用リード２、半導体素子１の信号用パッドと信号用リード３、半導体素子１の接地用パッドとダイパッド５、ダイパッド５と接地用リード４を、それぞれ電気的に接続している。電源用リード２と信号用リード３とはダイパッド５の下にもぐりこむような形で大きく広がっており、それぞれ容量素子の下側電極（１２Ａ、１２Ｂ）となっている。さらに、電源用リード２とダイパッド５との間及び信号用リード３とダイパッド５との間に挟まれた誘電体７と、半導体素子１とダイパッド５と接着剤１０と電源用リード２と信号用リード３と接地用リード４とボンディングワイヤ６と誘電体７とを封止する封止樹脂８を備えている。各リードの外側の先端部は封止樹脂８から突出しておりそれぞれ外部端子になっている。   The semiconductor device includes a semiconductor element 1, a die pad 5, an adhesive 10 (shown in FIG. 3) for bonding the semiconductor element 1 on the die pad 5, a power lead 2, a signal lead 3, and a ground lead 4. And a bonding wire 6 for electrical connection between the semiconductor element 1 and each lead or die pad. Each bonding wire 6 includes a power supply pad and a power supply lead 2 of the semiconductor element 1, and a semiconductor element. 1 signal pad and signal lead 3, the ground pad of semiconductor element 1 and die pad 5, and the die pad 5 and ground lead 4 are electrically connected. The power supply lead 2 and the signal lead 3 are greatly expanded so as to be recessed under the die pad 5, and serve as lower electrodes (12A, 12B) of the capacitive elements, respectively. Furthermore, the dielectric 7 sandwiched between the power lead 2 and the die pad 5 and between the signal lead 3 and the die pad 5, the semiconductor element 1, the die pad 5, the adhesive 10, the power lead 2, and the signal. A sealing resin 8 for sealing the lead 3, the grounding lead 4, the bonding wire 6, and the dielectric 7 is provided. The outer tip of each lead protrudes from the sealing resin 8 and serves as an external terminal.

こうした構造をとることで、半導体装置においては、電源用リード２の下側電極と接地用リード４との間、及び、信号用リード３の下側電極と接地用リード４との間に、十分な静電容量を有する容量素子を配置することが可能となる。ダイパッド５全体が容量素子の接地電圧の電極として機能するので、電源用リード２と信号用リード３を誘電体７の下で大きく広げることで容量素子の対向電極の面積が広くなり、静電容量を大きくすることが可能となる。外付け容量を不要とすることも可能となり、実装工程の生産性の向上、部品コストの低減が図れる。   By adopting such a structure, in the semiconductor device, it is sufficient between the lower electrode of the power supply lead 2 and the grounding lead 4 and between the lower electrode of the signal lead 3 and the grounding lead 4. It is possible to arrange a capacitive element having a sufficient capacitance. Since the entire die pad 5 functions as an electrode for the ground voltage of the capacitive element, the area of the counter electrode of the capacitive element is increased by widening the power supply lead 2 and the signal lead 3 under the dielectric 7, thereby increasing the capacitance. Can be increased. It is also possible to eliminate the need for an external capacitor, which can improve the productivity of the mounting process and reduce the component cost.

電源用リード２に電源電圧が印加されると、ボンディングワイヤ６を介して半導体素子１に電力が供給され、半導体素子１は動作し、信号用リード３から信号を入力あるいは出力する。このとき、電源用リード２の電源電圧に含まれるノイズ成分は、電源用リード２と接地用リード４との間の静電容量を通過し、接地用リード４に逃げる。また、信号用リード３の信号に含まれるノイズ成分は、信号用リード３と接地用リード４との間の静電容量を通過し、接地用リード４に逃げる。よって、信号用リード３が入力であれば半導体素子１への入力信号のノイズ成分が少なくなるので、半導体素子１のノイズ成分による誤動作が少なくなる。   When a power supply voltage is applied to the power supply lead 2, power is supplied to the semiconductor element 1 through the bonding wire 6, and the semiconductor element 1 operates to input or output a signal from the signal lead 3. At this time, the noise component included in the power supply voltage of the power supply lead 2 passes through the capacitance between the power supply lead 2 and the grounding lead 4 and escapes to the grounding lead 4. The noise component included in the signal of the signal lead 3 passes through the electrostatic capacitance between the signal lead 3 and the ground lead 4 and escapes to the ground lead 4. Therefore, if the signal lead 3 is input, the noise component of the input signal to the semiconductor element 1 is reduced, so that malfunction due to the noise component of the semiconductor element 1 is reduced.

次にダイパッドおよび誘電体の厚みについて説明する。
ダイパッド５は、例えば、銅等の金属である。ダイパッド５の厚みは、およそ０．０２５〜０．０７ｍｍに設定される。厚みが０．０１ｍｍよりも薄いと、ダイパッド５の機械的強度が小さくなるので、ボンディングワイヤ６の接続時にダイパッド５が破壊され易くなり、反対に、厚みが０．１ｍｍよりも厚いと、半導体装置全体の厚みが必要以上に厚くなるからである。 Next, the thickness of the die pad and the dielectric will be described.
The die pad 5 is, for example, a metal such as copper. The thickness of the die pad 5 is set to approximately 0.025 to 0.07 mm. If the thickness is less than 0.01 mm, the mechanical strength of the die pad 5 is reduced. Therefore, the die pad 5 is easily broken when the bonding wire 6 is connected. Conversely, if the thickness is greater than 0.1 mm, the semiconductor device This is because the overall thickness becomes thicker than necessary.

電源用リード２と接地用リード４に接続されるダイパッド５との間、及び、信号用リード３と接地用リード４に接続されるダイパッド５との間に配置される誘電体７には誘電率の大きな誘電体粉末を含む樹脂を用いることが好ましく、誘電率が６０以上である誘電体粉末（チタン酸バリウムやチタン酸ストロンチウム等の粉末）が５０〜９０重量％含有されることにより、誘電体７による静電容量が高くなる。誘電体７の厚みは、およそ０．０１〜０．０７ｍｍに設定される。厚みが０．０１ｍｍよりも薄いと、誘電体７による電気的絶縁性が不完全になり易くなり、反対に厚みが０．０７ｍｍよりも厚いと、誘電体７による静電容量の容量値が小さくなるからである。   The dielectric 7 disposed between the power supply lead 2 and the die pad 5 connected to the ground lead 4 and between the signal lead 3 and the die pad 5 connected to the ground lead 4 has a dielectric constant. It is preferable to use a resin containing a large dielectric powder, and 50 to 90% by weight of a dielectric powder (powder such as barium titanate or strontium titanate) having a dielectric constant of 60 or more is contained. The capacitance due to 7 increases. The thickness of the dielectric 7 is set to approximately 0.01 to 0.07 mm. If the thickness is less than 0.01 mm, the electrical insulation by the dielectric 7 tends to be incomplete, whereas if the thickness is thicker than 0.07 mm, the capacitance value of the capacitance by the dielectric 7 is small. Because it becomes.

ロウ材やガラスや樹脂等の接着剤１０は、半導体素子１をダイパッド５の上に固定するために用いられる。半導体素子１などを包む封止樹脂８は、エポキシ樹脂等の耐熱性樹脂から構成され、各リードの外側の先端部を除いて半導体装置全体を気密に被覆する。   An adhesive 10 such as a brazing material, glass or resin is used to fix the semiconductor element 1 on the die pad 5. The sealing resin 8 that encloses the semiconductor element 1 and the like is made of a heat-resistant resin such as an epoxy resin, and covers the entire semiconductor device in an airtight manner except for the outer end portion of each lead.

＜第二実施形態＞
図４は、半導体装置を示す斜視図である。図５は、図４の上面図である。図６は、図４の側面図である。 <Second embodiment>
FIG. 4 is a perspective view showing the semiconductor device. FIG. 5 is a top view of FIG. FIG. 6 is a side view of FIG.

第一実施形態では、電源用リード２及び信号用リード３と接地用リードの間の両方にそれぞれ容量素子が設けられたが、第二実施形態では、電源用リード２と接地用リード４の間にのみ容量素子が設けられている。この場合、電源用リードは誘電体７の下で大きく広がった下側電極１２を有しており、所望の静電容量が得られる電極面積を有している。ダイパッド５とほぼ同じ大きさまで面積を大きくすることが可能である。
なお、図示しないが、信号用リード３にのみ容量素子を設けても良い。 In the first embodiment, the capacitive elements are provided between the power supply lead 2 and the signal lead 3 and the ground lead, respectively, but in the second embodiment, between the power supply lead 2 and the ground lead 4. Only the capacitor element is provided. In this case, the power supply lead has a lower electrode 12 that spreads greatly under the dielectric 7, and has an electrode area that provides a desired capacitance. The area can be increased to almost the same size as the die pad 5.
Although not shown, a capacitive element may be provided only on the signal lead 3.

＜第三実施形態＞
図７は、半導体装置を示す斜視図である。図８は、図７の上面図である。図９は、図７の側面図である。 <Third embodiment>
FIG. 7 is a perspective view showing a semiconductor device. FIG. 8 is a top view of FIG. FIG. 9 is a side view of FIG.

第一実施形態と比較すると、図９に示すように、本実施形態においては、各リードが誘電体７の下側の電極となり広がる部分の手前において、各リードにつぶし９が設けられている。このようにすることで各リードの外部端子となる部分の厚さを変えずに、容量素子の下側の電極となる金属の厚さのみを薄くすることができ、半導体装置の厚みを薄くすることができる。   Compared with the first embodiment, as shown in FIG. 9, in this embodiment, each lead is provided with a crush 9 in front of a portion where each lead becomes an electrode on the lower side of the dielectric 7. By doing so, it is possible to reduce only the thickness of the metal serving as the lower electrode of the capacitor element without changing the thickness of the portion serving as the external terminal of each lead, thereby reducing the thickness of the semiconductor device. be able to.

＜第四実施形態＞
図１０は、半導体装置を示す斜視図である。図１１は、図１０の上面図である。図１２は、図１０の側面図である。 <Fourth embodiment>
FIG. 10 is a perspective view showing a semiconductor device. FIG. 11 is a top view of FIG. FIG. 12 is a side view of FIG.

第三実施形態では、電源用リード２及び信号用リード３の両方に容量素子を設けたが、第四実施形態では、電源用リード２のみに容量素子を設けている。電源用リード２が誘電体７の下側の電極となり広がる部分の手前において、電源リードにつぶし９が設けられている。
なお、図示しないが、信号用リード３のみに静電容量を設けても良い。 In the third embodiment, the capacitive element is provided in both the power supply lead 2 and the signal lead 3, but in the fourth embodiment, the capacitive element is provided only in the power supply lead 2. A crush 9 is provided in the power supply lead before the portion where the power supply lead 2 becomes the lower electrode of the dielectric 7 and spreads.
Although not shown, a capacitance may be provided only for the signal lead 3.

＜第五実施形態＞
図１３は、半導体装置を示す斜視図である。図１４は、図１３の上面図である。図１５は、図１３の側面図である。 <Fifth embodiment>
FIG. 13 is a perspective view showing a semiconductor device. FIG. 14 is a top view of FIG. FIG. 15 is a side view of FIG.

第一実施形態では、樹脂により封止されるダイパッド５が使用されたが、第五実施形態では、一部が封止樹脂８から露出し、ダイパッド及び接地用リードの両方として機能するダイパッド兼接地用リード１１を使用している。ダイパッド兼接地用リード１１はダイパッドなる部分とダイパッドから延伸され屈曲された基板に届く形状の接地用リードの部分とを備えている。ダイパッド兼接地用リード１１は一部がダイパッドの幅を有したまま封止樹脂８から露出しており、屈曲されて直接実装基板に接続されるので、半導体素子１は、誘電体７を介さないで実装基板に金属を介して熱的に接続されることになり、高い放熱性を得ることが可能である。
なお、リードには第三実施形態で示したつぶしを設けても良い。 In the first embodiment, the die pad 5 sealed with resin is used. However, in the fifth embodiment, a part of the die pad that is exposed from the sealing resin 8 and functions as both a die pad and a ground lead is used. The lead 11 is used. The die pad / ground lead 11 includes a die pad portion and a ground lead portion shaped so as to reach the substrate extended from the die pad and bent. A part of the die pad / ground lead 11 is exposed from the sealing resin 8 while having the width of the die pad, and is bent and directly connected to the mounting substrate. Therefore, the semiconductor element 1 does not have the dielectric 7 interposed therebetween. Thus, it is thermally connected to the mounting substrate through a metal, and high heat dissipation can be obtained.
The lead may be provided with the squash shown in the third embodiment.

＜第六実施形態＞
図１６は、半導体装置を示す斜視図である。図１７は、図１６の上面図である。図１８は、図１６の側面図である。 <Sixth embodiment>
FIG. 16 is a perspective view showing a semiconductor device. FIG. 17 is a top view of FIG. 18 is a side view of FIG.

第五実施形態では、電源用リード２及び信号用リード３と接地用リードの間の両方にそれぞれ容量素子が設けられたが、第六実施形態では、電源用リード２と接地用リード４の間にのみ容量素子が設けられている。
なお、図示しないが、信号用リード３にのみ容量素子を設けても良い。さらに、第三実施形態で示したつぶしを設けても良い。 In the fifth embodiment, the capacitive element is provided between each of the power supply lead 2 and the signal lead 3 and the ground lead. However, in the sixth embodiment, between the power supply lead 2 and the ground lead 4. Only the capacitor element is provided.
Although not shown, a capacitive element may be provided only on the signal lead 3. Further, the squashing shown in the third embodiment may be provided.

１ 半導体素子
２ 電源用リード
３ 信号用リード
４ 接地用リード
５ ダイパッド
６ ボンディングワイヤ
７ 誘電体
８ 封止樹脂
９ つぶし
１０ 接着剤
１１ ダイパッド兼接地用リード
１２、１２Ａ、１２Ｂ 下側電極 DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Power supply lead 3 Signal lead 4 Grounding lead 5 Die pad 6 Bonding wire 7 Dielectric 8 Sealing resin 9 Squash 10 Adhesive 11 Die pad and grounding leads 12, 12A, 12B Lower electrode

Claims (2)

半導体素子と、
前記半導体素子を搭載したダイパッドと、
前記ダイパッド上に前記半導体素子を接着している接着剤と、
前記ダイパッドの下に広がって配置された第１の下側電極を有する電源用リードおよび第２の下側電極を有する信号用リードと、
接地用リードと、
前記半導体素子と前記電源用リード、前記半導体素子と前記信号用リード、および前記ダイパッドと前記接地用リードをそれぞれ電気的に接続しているボンディングワイヤと、
前記第１の下側電極および前記第２の下側電極と前記ダイパッドとの間に、挟まれて配置された誘電体と、
前記半導体素子と前記接着剤と前記電源用リードと前記信号用リードと前記接地用リードと前記ダイパッドと前記ボンディングワイヤと前記誘電体とを、封止する封止樹脂と、を備え、
前記ダイパッドと前記誘電体と前記第１の下側電極とが第１の容量素子、前記ダイパッドと前記誘電体と前記第２の下側電極とが第２の容量素子を形成し、
前記電源用リードは前記第１の下側電極となり広がる部分の手前につぶしが設けられており、前記第１の下側電極は前記電源用リードの外部端子となる部分よりも厚さが薄く、前記信号用リードは前記第２の下側電極となり広がる部分の手前につぶしが設けられており、前記第２の下側電極は前記信号用リードの外部端子となる部分よりも厚さが薄くなっている半導体装置。 A semiconductor element;
A die pad on which the semiconductor element is mounted;
An adhesive bonding the semiconductor element on the die pad;
A power lead having a first lower electrode and a signal lead having a second lower electrode disposed under the die pad;
A grounding lead;
Bonding wires electrically connecting the semiconductor element and the power supply lead, the semiconductor element and the signal lead, and the die pad and the grounding lead, respectively;
A dielectric disposed sandwiched between the first lower electrode, the second lower electrode, and the die pad;
A sealing resin that seals the semiconductor element, the adhesive, the power lead, the signal lead, the ground lead, the die pad, the bonding wire, and the dielectric;
The die pad, the dielectric, and the first lower electrode form a first capacitive element; the die pad, the dielectric, and the second lower electrode form a second capacitive element ;
The power supply lead is provided with a crush in front of a portion that becomes the first lower electrode and expands, and the first lower electrode is thinner than a portion that becomes an external terminal of the power supply lead, The signal lead is crushed in front of a portion that becomes the second lower electrode and spreads, and the second lower electrode is thinner than a portion that becomes an external terminal of the signal lead. Semiconductor device. 前記ダイパッドと前記接地用リードとは一体の金属から構成されており、その一部が前記ダイパッドの幅を有したまま前記封止樹脂より露出している請求項１記載の半導体装置。
The semiconductor device according to claim 1, wherein the die pad and the ground lead are made of an integral metal, and a part of the die pad is exposed from the sealing resin while having a width of the die pad.
JP2012065989A 2012-03-22 2012-03-22 Semiconductor device Expired - Fee Related JP5959255B2 (en)

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