JP3233196B2 - Semiconductor device packaging system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor (LSI)
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device packaging system, and more particularly to a semiconductor device packaging system having a structure that is hardly affected by external noise.

[0002]

2. Description of the Related Art In general, in a semiconductor device packaging system, noise generated at the time of signal transfer is a problem, and it is necessary to adopt a structure which is hardly affected by external noise at all. Conventionally, when connecting between devices or circuits, if the area of the loop formed by the ground line and the signal line is large, (1) noise is induced in the circuit by external induction, and (2) it acts as inductance. That is known. Therefore, as a method of reducing the influence of this external noise, when connecting between devices and between circuits,
A method is adopted in which a loop formed by the ground line and the signal line is reduced to reduce the influence of parallel noise (normal mode noise).

In the case of a logic circuit, as shown in FIG. 13, a semiconductor package (hereinafter, referred to as “L LSI chip”) incorporating a semiconductor chip (hereinafter, referred to as “LSI chip”) 101 is used.
A method of providing a coupling capacitor 105 on the signal input line 103 of the LSI chip 101 outside of the “SI package” 102 to reduce noise components is also known. In FIG. 13, reference numeral 104 denotes a ground wire leading to the LSI chip 101.

Further, as another structure, there is a technique disclosed in, for example, JP-A-1-300546. In the semiconductor device packaging system disclosed in Japanese Patent Application Laid-Open No. 1-300546, a dielectric plate is formed between a grounding conductor and a bias supply terminal of the semiconductor device packaging system, and a capacitor is provided outside a region of an LSI chip. The noise component is reduced.

[0005]

However, FIG.
In the conventional structure shown in (1), since the coupling capacitor 105 is provided outside the LSI package 102, there is a problem that an occupied area at the time of mounting is increased and mounting cost is easily increased. On the other hand, in the conventional structure disclosed in Japanese Patent Application Laid-Open No. 1-300546, since a capacitor is formed outside the area of the LSI chip, the only way to increase the capacitance is to increase the size of the package. This is not preferable because it increases the cost of mounting.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a semiconductor device packaging system capable of increasing the packaging density and reducing the packaging cost. It is in.

[0007]

Means for Solving the Problems The present invention is characterized by taking the following technical means in order to achieve the above object.
That is, in a semiconductor device packaging system in which a bonding table for bonding a semiconductor chip is formed as a coupling capacitor, a plurality of coupling capacitors are formed on the bonding table, and between the adjacent coupling capacitors. A conductor for preventing interference between the coupling capacitors is provided.

According to this, the coupling capacitor capable of removing noise can be compactly provided inside the package. Thus, the mounting density can be increased and the mounting cost can be reduced. Further, since the dielectric A is formed of a low dielectric material and the dielectric B is formed of a high dielectric material, a parasitic capacitance generated between the metal plates A and B is reduced.

[0009]

Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In addition, although the form described below is a preferable specific example of the present invention, various technically preferable limitations are added thereto. However, the scope of the present invention is not limited to the following description, which particularly limits the present invention. It is not limited to these forms unless otherwise stated.

FIGS. 1 to 3 show a semiconductor package (hereinafter referred to as "LSI") as a first preferred embodiment of the present invention.
FIG. 2 is an overall view of the package, FIG. 3 is a perspective view taken along a line AA of FIG. 2, and FIG. 1 schematically shows the internal structure of the package. FIG. 1 to 3, this LSI package 10 has ten lead pins 1 on each side in series.
This is a DIP in which a total of 20 are arranged in parallel on both sides
A semiconductor chip (hereinafter, referred to as an “LSI chip”) 3 is mounted on a bonding table 2 and is made of a resin material (package).
4 is a structure sealed.

More specifically, the bonding table 2 is used as a coupling capacitor. As shown in a perspective view in FIG. 4 and a vertical sectional side view in FIG. Plate B5, metal plate C5,
Dielectric A interposed between metal plate A5 and metal plate B5
6, and a dielectric B6 interposed between the metal plate B5 and the metal plate C5. Here, as the metal plate A5, the metal plate B5, and the metal plate C5, for example, aluminum (Al), copper (Cu), gold (Au), tungsten (W), tantalum (Ta), titanium (Ti), molybdenum (Mo) or the like having a low resistivity is used. Further, the dielectric A6 is made of, for example, SiOF (relative permittivity ε) in addition to SiO _2.
= 3 to 3.5) or a low dielectric material such as an organic low dielectric material (ε = 2 to 3) reduces the parasitic capacitance C2 (see FIG. 6). In addition, as the organic low dielectric material, Teflon (ε = 1.9), fluorinated polyimide (ε =
2.5-3.0), Parylene-N (ε = 2.7), Paryle
ne-F (ε = 2.3), BCB (ε = 2.7), Cytop
(Ε = 2.1) and the like are used. On the other hand, for example, SiO ₂ may also be used for the dielectric B6, but Ta ₂ O ₅ (ε = 2
By using a high dielectric material such as 7 to 30), a small-sized and large-capacity coupling capacitor can be realized.
The capacitance is controlled by (1) changing the material of the dielectric B6, (2) changing the thick film of the dielectric B6, and (3) processing the metal plate B5 or the metal plate C5 to change the electrode area. Do.

When attaching the LSI chip 3 to the bonding table 2 configured as described above, as shown in FIG. 1, the LSI chip 3 is bonded to a metal plate A5 and wiring is performed. The wiring here will be described with reference to FIG. 1. First, the metal plate A5 is grounded (), one end of the metal plate B5 is connected to the signal input pad of the LSI chip 3 (), and one end of the metal plate C5 is packaged. Connected to the signal input terminal (not shown) of
Achieved by: When this connection is expressed by a circuit, it becomes an equivalent circuit shown in FIG. 6, and the bonding table 2 functions as a coupling capacitor C1. further,
The metal plate A5 functions to supply the ground potential and conduct heat of the LSI chip 3 to cool the LSI chip 3.

Therefore, according to the structure of the first embodiment, as shown in FIG. 7, the LSI package 10 in which the coupling capacitor C1 is disposed inside the package 4 can be formed, so that the mounting density can be increased. And at the same time reduce the cost of mounting. In this embodiment, the coupling capacitor for an input signal is shown, but it is needless to say that the coupling capacitor can be used as a coupling capacitor for an output signal.

FIG. 8 is a diagram schematically showing the internal configuration of a semiconductor device as a second preferred embodiment of the present invention. In FIG. 8, components denoted by the same reference numerals as those in FIGS. 1 to 7 indicate the same components as those in FIGS. 1 to 7. The major difference between the second embodiment and the first embodiment shown in FIGS. 1 to 7 is that the metal of the bonding table 2 shown in the structure of the first embodiment is different in the structure of the second embodiment. As shown in FIG. 9, the plate B5 is a metal plate B51, a metal plate B52, and a metal plate B53.
The metal plate B51 is an electrode of an input coupling capacitor, the metal plate B52 is a ground electrode, and the metal plate B5
3 is used as an electrode of an output signal coupling capacitor, and the metal plate C5 of the bonding table 2 shown in the first embodiment is replaced with a metal plate C51 and a metal plate C5 as shown in FIG.
2. The metal plate C53 is separated into three, the metal plate C51 is used as an electrode of an input coupling capacitor, the metal plate C52 is used as a ground electrode, and the metal plate C53 is used as an electrode of an output signal coupling capacitor. Then, the metal plate B51 and the metal plate C
51 constitutes an input coupling capacitor C11;
The metal plate B53 and the metal plate C53 constitute an output coupling capacitor C12.
And the metal plate C52 are connected to a fixed potential such as a ground potential or a power supply potential. The capacitance of each of the capacitors C11 and C12 is controlled by the area of the metal plate B5, the dielectric constant ε of the dielectric B6, and the thickness of the dielectric B6. Also, in the second embodiment, similarly to the first embodiment, when a low dielectric material is used for the dielectric A6, the parasitic capacitance on the input side and the parasitic capacitance on the output side can be reduced. When a high dielectric material is used for B6, the capacitance can be increased.

In this semiconductor device, when the LSI chip 3 is attached to the bonding table 2, as shown in FIG.
And the metal plates C51, C52, and C53 are bonded to the package 4, and then wiring is performed.

The wiring here will be described with reference to FIG. 8. First, the metal plate A5 is grounded (), and the metal plate B5 is grounded.
1 is connected to the input signal pad of the LSI chip 3 (), and one end of the metal plate C51 is connected to the input signal terminal of the package (). One end of the metal plate B53 is connected to the output signal pad of the LSI chip 3 (), and the metal plate C5 is connected.
3 is connected to the output signal terminal of the package (). One end of the metal plate B52 and one end of the metal plate C52 are grounded (,). In the present embodiment, the metal plate B52 and the metal plate C52 are grounded, but may be a power supply potential or the like.

When this connection is represented by a circuit, FIG.
And functions as an input signal coupling capacitor C11 and an output signal coupling capacitor C12. Then, the grounded metal plate B5
2 and a metal plate C52 are respectively a metal plate B51 and a metal plate B5.
3. Since there is between the metal plate C51 and the metal plate C53, mutual leakage of the output signal and the input signal is eliminated. That is, when the metal plate B52 and the metal plate C52 do not exist, the metal plate B52
51 and the metal plate B53, and between the metal plate C51 and the metal plate C
Capacitors 53 are capacitively coupled, and an output signal may leak to an input line. However, as in this embodiment,
When the metal plate B52 and the metal plate C52 exist, the metal plate B5
1 and the metal plate B52 and between the metal plate B53 and the metal plate B52
Between the metal plate C51 and the metal plate C52 and between the metal plate C5
3 and the metal plate C52, the parasitic capacitances C21 and C22 (FIG. 1)
1), but since the metal plate B52 and the metal plate C52 are grounded, no signal leaks between the input and the output. Further, also in the structure of the present embodiment, the metal plate A5 supplies the ground potential and conducts the heat of the LSI chip 3,
It functions to cool the LSI chip 3. As in the case of the first embodiment, the control of the capacitance is as follows: (1) changing the material of the dielectric B6, (2) changing the thick film of the dielectric B6, (3) changing the metal plate B51, B52, B53 or metal plates C51, C52, C53 are machined to change the electrode area.

Therefore, even in the case of the structure of the second embodiment, as shown in FIG. 12, the LSI package 10 in which the input coupling capacitor C11 and the output coupling capacitor C12 are arranged inside the package 4 can be formed. Therefore, the mounting density can be increased and the mounting cost can be reduced.

[0019]

As described above, according to the present invention, the mounting density can be increased and, at the same time, the mounting can be performed at low cost.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing an internal configuration of a semiconductor package according to a first embodiment of the present invention.

FIG. 2 is an overall view of a semiconductor package according to a first embodiment of the present invention.

FIG. 3 is a perspective view of a section taken along line AA of FIG. 2;

FIG. 4 is an external perspective view of a single bonding table in the first embodiment.

FIG. 5 is a vertical sectional side view of a bonding stand alone in the first embodiment.

FIG. 6 is an equivalent circuit diagram of the first embodiment.

FIG. 7 is a connection diagram of the first embodiment.

FIG. 8 is a schematic diagram showing an internal configuration of a semiconductor package according to a second embodiment of the present invention.

FIG. 9 is a structural diagram of a metal plate B in a second embodiment.

FIG. 10 is a structural diagram of a metal plate C in a second embodiment.

FIG. 11 is an equivalent circuit diagram of the second embodiment.

FIG. 12 is a circuit connection diagram of the second embodiment.

FIG. 13 is a connection diagram of a conventional semiconductor device package.

[Explanation of symbols]

2 Bonding stand 3 Semiconductor chip (LSI chip) 4 Resin material (package) 10 Semiconductor package (LSI package) A5, B5, B51, B52, B53, C5, C51,
C52, C53 Metal plate A6, B6 Dielectric C1, C11, C12 Coupling capacitor C2, C21, C22 Parasitic capacitance

Claims (4)

(57) [Claims] 1. A semiconductor device packaging system in which a bonding table for bonding a semiconductor chip is formed as a coupling capacitor, wherein a plurality of coupling capacitors are formed on the bonding table and adjacent ones for different signals. A semiconductor device packaging system comprising a conductor provided between coupling capacitors to prevent interference between the coupling capacitors. 2. The semiconductor device packaging system according to claim 1, wherein an input signal coupling capacitor and an output signal coupling capacitor are provided as said coupling capacitors. 3. The bonding table includes a metal plate C, a dielectric B made of a high dielectric material, a metal plate B, a dielectric A made of a low dielectric material, and a metal plate A to which the semiconductor chip is bonded. The semiconductor device packaging system according to claim 1, wherein the semiconductor device packaging system is formed as a stacked body. 4. The dielectric A has a relative dielectric constant ε of 2 to 4.
4. The semiconductor device packaging system according to claim 3, wherein a low dielectric material of about 3.5 is used, and a high dielectric material having a relative dielectric constant [epsilon] of about 27 to 30 is used as the dielectric B.