JP5943868B2 - Semiconductor switching element gate drive circuit - Google Patents

Description

  The present invention relates to a gate drive circuit for a semiconductor switching element.

  As a gate drive circuit of a conventional semiconductor switching element, between a second terminal and a gate terminal of a voltage-driven element including first and second terminals related to input / output of a main current and a gate terminal having an insulated gate structure, A voltage having a circuit for removing the gate voltage via the first switch means and the first resistance means, and a circuit for applying the gate voltage from the external control power source via the second switch means and the second resistance means In the drive circuit of the drive element, at least one of the voltage detection means for detecting the voltage between the first and second terminals and the first or second resistance means is a resistor based on the voltage detection signal from the voltage detection means. There is a variable resistance means for changing the value, and the surge voltage and noise generated at turn-off are suppressed by slowing down the speed at which the gate voltage at turn-off is reduced ( In example, see Patent Document 1).

Japanese Unexamined Patent Publication No. Hei 6-291163

  The conventional gate driving circuit of the semiconductor switching element is configured as described above, and when the speed of decreasing the gate voltage of the voltage driving type element as the semiconductor switching element is decreased, the first switching circuit is connected between the second terminal and the gate terminal. The circuit must be provided with a circuit for removing the gate voltage via the switch means and the first resistance means, and a resistance variable means for changing the resistance value based on the voltage detection signal from the voltage detection means. There was a problem of becoming.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a gate driving circuit for a semiconductor switching element that can suppress the occurrence of abnormal voltage between main terminals with a simple configuration.

In the gate driving circuit of the semiconductor switching element according to the present invention,
A gate driving circuit of a semiconductor switching element comprising a voltage detection circuit, a gate-on circuit, a gate- off circuit, and a control circuit,
The voltage detection circuit detects a voltage between main terminals of the semiconductor switching element,
The gate-on circuit is to turn on the semiconductor switching element by supplying current to the gate of the semiconductor switching element,
The gate-off circuit is for turning off between the main terminals by discharging the semiconductor connected to said gate charge stored in the capacitor of the gate of the switching element,
The control circuit suppresses a voltage generated between the main terminals by slowing a rate at which the charge is discharged by supplying a current from the gate-on circuit to the gate- off circuit when the semiconductor switching element is turned off. is there.

  Since the gate drive circuit for a semiconductor switching element according to the present invention is configured as described above, a gate drive circuit for a semiconductor switching element capable of suppressing the occurrence of abnormal voltage between main terminals at the time of turn-off with a simple configuration is obtained. be able to.

It is a circuit diagram which shows the structure of the gate drive circuit of the semiconductor switching element which is Embodiment 1 of this invention. It is a wave form diagram for demonstrating operation | movement. It is a circuit diagram which shows the structure of the gate drive circuit of the semiconductor switching element which is Embodiment 2 of this invention. It is a circuit diagram which shows the structure of the gate drive circuit of the semiconductor switching element which is Embodiment 3 of this invention. FIG. 5 is a circuit diagram illustrating a configuration of a memory circuit in FIG. 4. FIG. 5 is a waveform diagram for explaining the operation of the memory circuit of FIG. 4. It is a circuit diagram which shows the structure of the gate drive circuit of the semiconductor switching element which is Embodiment 4 of this invention.

Embodiment 1 FIG.
1 and 2 show a first embodiment for carrying out the present invention. FIG. 1 is a circuit diagram showing a configuration of a gate driving circuit of a semiconductor switching element, and FIG. 2 is a diagram for explaining an operation. It is a waveform diagram. In the present embodiment, the case where the semiconductor switching element 1 is an insulated gate bipolar transistor (IGBT) formed of silicon will be described as an example. A semiconductor switching element may be used. In FIG. 1, a voltage Vcc is applied between terminals 6 and 8 from a control power supply (not shown) as a drive power supply for the semiconductor switching element 1 with reference to the terminal 8 on the emitter side. The semiconductor switching element 1 has an emitter and a collector (hereinafter also referred to as a main terminal) which are a pair of main terminals through which a main current flows, and the main terminals are opened and closed. The emitter and collector of the semiconductor switching element 1 are connected to terminals 8 and 9, respectively.

  Resistors 31 and 32 connected in series as voltage detection circuits are connected to the terminals 8 and 9, and the voltage Vce between the collector and the emitter of the semiconductor switching element 1 is divided and detected. The current supply circuit 19 that also serves as a gate-on circuit is composed of a resistor 37, a resistor 38, an operational amplifier 4, and a MOSFET 2. The source of the MOSFET 2 is connected to the terminal 6 through the resistor 37, and the drain is connected to the gate of the semiconductor switching element 1 through the connection point 11. The connection point between the resistor 37 and the source of the MOSFET 2 is connected to one input terminal of the operational amplifier 4. The resistor 38 has one end connected to the terminal 6 and the other end connected to the other input terminal of the operational amplifier 4 via the connection point 10. The output terminal of the operational amplifier 4 is connected to the gate of the MOSFET 2. The gate of the semiconductor switching element 1 is connected to the terminal 8 through a resistor 40 and a MOSFET 3 as a gate-off circuit. The gate-off circuit is connected to the gate of the semiconductor switching element 1 and turns off the main terminals by discharging the charge accumulated in the capacitance of the gate of the semiconductor switching element 1. Note that the on-resistance of the MOSFET 3 can be substituted without providing the resistor 40 in the gate-off circuit. In order to set a reference value to the terminal 17, a constant voltage of a predetermined magnitude is applied to the terminal 6 from a power source (not shown).

  A series circuit of a voltage dividing resistor 33 and a resistor 34 is connected between the terminal 17 and the terminal 8, and gives a reference value to the operational amplifier 5. The voltage between the main terminals of the semiconductor switching element 1 detected by the resistors 31 and 32 is input to the operational amplifier 5 as a control circuit via the resistor 36. A resistor 35 is connected between the input terminal and the output terminal of the operational amplifier 5. The output terminal of the operational amplifier 5 is connected to the connection point 10 via the diode 13. The diode 13 is connected such that the cathode side is on the output terminal side of the operational amplifier 5 and the anode side is on the connection point 10 side. The signal input terminal 7 is connected to the connection point 10 of the current supply circuit 19 through a resistor 39 and is connected to the gate of the MOSFET 3 through a resistor 41. The semiconductor switching element driving circuit shown in FIG. 1 turns off the semiconductor switching element 1 when the voltage equal to the voltage Vcc is input as the external signal S1 between the signal input terminal 7 and the terminal 8, and the emitter voltage This circuit turns on the semiconductor switching element 1 when the following voltage is input. In the following description, a voltage based on the terminal 8 is simply referred to as a voltage unless otherwise specified.

  First, when the semiconductor switching element 1 is turned on, the signal input terminal 7 and the terminal 8 are short-circuited, that is, an L (low) signal is input to the signal input terminal 7, and the terminal 6 and the signal input terminal 7 are connected. A voltage Vcc is applied between them, and the voltage Vcc is divided by the resistors 38 and 39. The divided voltage is input to the operational amplifier 4 and the current flowing through the resistor 37 is controlled by the MOSFET 2 so that the voltage across the resistor 37 becomes equal to the voltage across the resistor 38. As a result, the same voltage as the voltage across the resistor 39 is applied to the gate of the semiconductor switching element 1, and the semiconductor switching element 1 is turned on.

  On the other hand, when the semiconductor switching element 1 is turned off and the turn-off speed at the time of interruption is high, the current change di / dt of the current i flowing through the main terminal of the semiconductor switching element 1 and the floating circuit of the circuit to which the semiconductor switching element 1 is connected Due to the inductance and the like, a phenomenon occurs in which the voltage Vce between the main terminals of the semiconductor switching element 1 jumps greatly. In this case, it is effective to reduce the turn-off speed at the time of interruption, that is, to suppress the gate current of the semiconductor switching element 1 and to reduce the jump of the voltage Vce. For this reason, in this embodiment, the gate voltage of the MOSFET 2 on the gate current supply side is controlled in order to reduce the jump of the voltage Vce. That is, the voltage Vce of the semiconductor switching element 1 is detected by the resistance voltage division of the resistors 31 and 32, and the voltage V10 at the connection point 10 of the current supply circuit 19 (see FIG. 2A, details will be described later) is adjusted low.

  Prior to detailed description of the operation, the basic concept will be described. It is assumed that a turn-off signal, that is, a voltage substantially the same as the voltage Vcc of the terminal 6 is input to the signal input terminal 7 as the external signal S1. Then, since the signal input terminal 7 becomes almost the same potential (voltage Vcc) as the terminal 6 and the voltage across the resistor 38 becomes 0, the operational amplifier 4 turns off the MOSFET 2 and the MOSFET 3 corresponds to the voltage Vcc at the gate by the turn-off signal. Since the voltage is applied to turn on, the voltage V11 at the connection point 11 as the gate voltage is maintained at the mirror voltage corresponding to the magnitude of the current flowing through the semiconductor switching element 1. Since the semiconductor switching element 1 is turned off at the end of the mirror period, the voltage Vce of the semiconductor switching element 1 supplies the inductance and power of the wiring to which the semiconductor switching element 1 is connected in addition to the power supply voltage applied from the outside. A voltage corresponding to the energy stored in the inductance such as the load that has been stored is applied.

  The jump of the voltage Vce at the time of turn-off is mainly due to the energy stored in the inductance. Therefore, the magnitude of the current change di / dt of the current i flowing through the main terminal at the time of turn-off and the magnitude of the voltage Vce appearing as an abnormal voltage have a substantially proportional relationship. Therefore, the magnitude of the abnormal voltage can be suppressed by suppressing the current change rate di / dt at the time of turn-off, that is, by lengthening the time until the semiconductor switching element 1 is turned off. The time during which the semiconductor switching element 1 is turned off, that is, the cutoff time is determined by the magnitude of the gate current at the time of turn-off, and the magnitude of the abnormal voltage can be controlled by adjusting the magnitude of the gate current.

  Prior to the description of the detailed operation, the outline of each waveform in FIG. 2 will be described. FIG. 2A shows the voltage V10 at the connection point 10, V10a is a voltage when control is not performed at time T2, and V10b is a voltage when control is performed. FIG. 2B shows the voltage (gate voltage) V11 at the connection point 11, the voltage V11a is a voltage when control is not performed at time T2, and the voltage V11b is a voltage when control is performed. FIG. 2C shows the voltage at the terminal 9, that is, the voltage Vce between the main terminals. The voltage Vcea indicates the voltage when the control is not performed at time T2, and the voltage Vceb indicates the voltage when the control is performed. FIG. 2D shows a current i as a main current flowing through the semiconductor switching element 1, where the current ia indicates a current when control is not performed at time T2, and a current ib indicates a current when control is performed. . FIG. 2E shows an injection current J2 injected from the current supply circuit 19 to the connection point 11 for control. FIG. 2F shows the gate current J1 flowing out from the gate of the semiconductor switching element 1, and the gate current J1a shows the current when the injection current J2 is not injected from the current supply circuit 19 to the connection point 11. The gate current J1b indicates the current when the injection current J2 is injected from the current supply circuit 19 to the connection point 11.

  Next, the detailed operation will be described. A detection voltage Vd obtained by dividing the voltage Vce between the main terminals of the semiconductor switching element 1 by the resistors 31 and 32 is input to the operational amplifier 5 through the resistor 36 and is set by the detection voltage Vd and the resistors 33 and 34. The voltage ΔV with respect to the reference value Vs is amplified to control the voltage at the connection point 10 via the diode 13. That is, when the detection voltage Vd exceeds the reference value Vs at time T2, the voltage at the connection point 10 is lowered by the difference voltage ΔV between the two (V10b in FIG. 2A). Then, the injected current J2 (see FIG. 2 (e)) is supplied from the control power supply to the connection point 11 via the MOSFET 2 so that the voltage across the resistor 37 matches the voltage across the resistor 38 by the operational amplifier 4.

  The injection current J2 becomes larger as the difference voltage ΔV is larger. Then, the gate current J1 is suppressed according to the magnitude of the injection current J2. That is, since the gate voltage is limited by the injection current J2 from the current supply circuit 19, the magnitude of the gate current J1 of the semiconductor switching element 1 is suppressed from J1a to J1b (see FIG. 2 (f)), and the gate By slowing down the rate at which the electric charge accumulated in the current is discharged, the current change of the semiconductor switching element 1 becomes gradual as shown by currents ia to ib in FIG. When the voltage Vce becomes equal to or lower than the reference value Vs at time T3, the differential voltage ΔV is also zero, the MOSFET 2 is turned off, and the injection current J2 is zero. The current J3 flowing from the connection point 11 to the terminal 8 via the resistor 40 is the sum of the gate current J1 and the injection current J2, and is the same current as the gate current J1 between the time T1 and the time T2. As described above, by controlling the magnitude of the injection current J2 supplied from the current supply circuit 19 according to the magnitude of the voltage Vce, the jump of the voltage Vce between the main terminals can be suppressed with a simple configuration and the generation of an abnormal voltage can be prevented. Can be prevented. The current supply circuit 19 also serves as a gate-on circuit for turning on the semiconductor switching element 1 as described above.

Embodiment 2. FIG.
FIG. 3 is a circuit diagram showing a gate drive circuit of the semiconductor switching element according to the second embodiment. In the second embodiment, the gate voltage of the semiconductor switching element 1 at the turn-off time is directly controlled in order to reduce the jump of the voltage Vce. In FIG. 2, an output terminal of an operational amplifier 15 serving as a control circuit and a current supply circuit is connected to a connection point 11 between the gate of the semiconductor switching element 1 and a resistor 40 via a diode 23. The diode 23 has an anode side connected to the resistor 48 and a cathode side connected to the connection point 11. The current supply circuit 19 in FIG. 1 is not shown in the present embodiment because it is not used (also used) when the semiconductor switching element 1 is turned off. Since other configurations are the same as those of the first embodiment shown in FIG. 1, the same reference numerals are given to the corresponding components and the description thereof is omitted.

  When a voltage almost the same as the voltage Vcc is input to the signal input terminal 7 as a turn-off signal, the gate voltage of the MOSFET 3 is increased, the MOSFET 3 is turned on, the gate current J1 flows out from the gate of the semiconductor switching element 1, and the semiconductor switching element 1 Opens. At this time, the detection voltage Vd obtained by dividing the voltage Vce between the main terminals of the semiconductor switching element 1 by the resistors 31 and 32 is input to the operational amplifier 15 via the resistor 36. Then, the difference voltage ΔV between the detection voltage Vd and the reference value Vs set by the resistors 33 and 34 is amplified and supplied directly to the connection point 11 via the diode 23. That is, the injection current J2 corresponding to the differential voltage ΔV is supplied from the operational amplifier 15 to the connection point 11.

  Therefore, the voltage at the connection point 11 (gate voltage) is determined by the current J3 (= J1 + J2) obtained by adding the injection current J2 flowing through the resistor 40 and the gate current J1 flowing out from the gate of the semiconductor switching element 1. The gate voltage of the semiconductor switching element 1 is increased. Thereby, the decreasing rate of the gate current J1 is suppressed, and the turn-off speed of the semiconductor switching element 1 is decreased. That is, by reducing the current change di / dt of the current i at the time of turn-off, the jump of the voltage Vce can be suppressed and the occurrence of an abnormal voltage can be prevented. In this way, by directly controlling the voltage applied to the connection point 11, that is, the gate of the semiconductor switching element 1 according to the magnitude of the voltage Vce, it is possible to prevent the occurrence of an abnormal voltage with a simple configuration.

Embodiment 3 FIG.
4 to 6 show the third embodiment. FIG. 4 is a circuit diagram showing a configuration of a gate driving circuit of a semiconductor switching element, FIG. 5 is a circuit diagram showing a configuration of a memory circuit, and FIG. 6 is a memory circuit. It is a wave form diagram for demonstrating operation | movement. The current change di / dt at turn-off that causes an abnormal voltage of the voltage Vce varies depending not only on the magnitude of the current i but also on the temperature of the semiconductor switching element 1. The allowable voltage Vce varies depending on the type of the semiconductor switching element 1 and the like. In addition, the time from when the current interruption starts until the voltage Vce jumps is very short, and the protection operation after detecting an abnormal voltage due to the delay time of the voltage detection circuit or the drive circuit may be difficult.

  Therefore, in this embodiment, a storage circuit for storing the voltage Vce is provided, and the magnitude of the injection current J2 is controlled to limit the jump of the voltage Vce based on the stored voltage. Further, a reference value adjustment circuit 26 is provided to adjust the level of the voltage Vce to be limited according to the type of the semiconductor switching element 1 or the like. In FIG. 4, the voltage Vce between the main terminals of the semiconductor switching element 1 is divided by the resistors 31 and 32 and input to the memory circuit 100, and the output of the memory circuit 100 is output to the operational amplifier 25 as a control circuit. . The reference value Vs set by the resistors 33 and 34 is input to the reference value adjustment circuit 26, changed to the reference value Vsb corresponding to the characteristics of the semiconductor switching element 1, and input to the operational amplifier 25. Since other configurations are the same as those of the first embodiment shown in FIG. 1, the same reference numerals are given to the corresponding components and the description thereof is omitted.

  In the memory circuit 100, for example, as shown in FIG. 5, a capacitor 101 and a resistor 102 are connected in parallel, and one side of the parallel circuit is connected to an output terminal 107 and also connected to an input terminal 106 via a diode 103. The other side is connected to the terminal 8 (see FIG. 4). When the voltage Vce is divided and input by the resistors 31 and 32 to the input terminal 106 of the memory circuit 100, the peak value of the voltage is stored in the capacitor 101 as the peak voltage Vh as shown in FIG. The The stored peak voltage Vh is discharged by the resistor 102 with a predetermined time constant. The operational amplifier 25 receives the peak voltage Vh stored in the capacitor 101.

  The reference value Vs set by the resistors 33 and 34 is input to the reference value adjustment circuit 26, changed to the reference value Vsb corresponding to the characteristics of the semiconductor switching element 1, and input to the operational amplifier 25. Specifically, when the rated voltage V1 of the semiconductor switching element 1 is large, a large jump of the voltage Vce can be allowed. Therefore, the turn-off speed of the semiconductor switching element 1 may be increased. Therefore, the reference value Vsb is set high. The level of the injection current J2 is lowered. On the other hand, when the rated voltage V1 is small, the jump of the voltage Vce at turn-off cannot be allowed to be so large, so the reference value Vsb is set low and the level of the injection current J2 is increased. In the operational amplifier 25, the output voltage of the operational amplifier 25 is determined based on the peak voltage Vh and the reference value Vsb set by the reference value adjustment circuit 26.

  Here, when a voltage of the same level as the voltage Vcc is input as a turn-off signal to the signal input terminal 7, the MOSFET 3 becomes conductive, the gate current J 1 flows out from the semiconductor switching element 1, and the voltage at the connection point 10 from the current supply circuit 19. The injection current J2 corresponding to the above is injected into the connection point 11. The subsequent operation is the same as that of the first embodiment shown in FIG. 1, but the output terminal of the operational amplifier 25 is connected to the connection point 10 via the reversely connected diode 13. The voltage at the connection point 10 is controlled, and the injection current J2 is controlled according to this voltage.

  Therefore, the speed at the time of turn-off of the semiconductor switching element 1 becomes slow, the jump of the voltage Vce can be suppressed, and the occurrence of abnormal voltage can be prevented. Note that when the rated voltage V1 of the semiconductor switching element 1 is large, the voltage at the connection point 10 is set high, so the magnitude of the injected current J2 is small and the degree to which the gate current J1 is suppressed is small. On the other hand, when the rated voltage V1 is small, the voltage at the connection point 10 is set low, the injection current J2 is increased, and the degree to which the gate current J1 is suppressed is increased.

  As a result, the delay time of the voltage detection and the drive circuit is eliminated, and the peak value of the voltage Vce at turn-off can be suppressed by controlling the current change di / dt at turn-off with high accuracy. In addition, an appropriate turn-off speed can be selected by setting the reference value Vsb in accordance with the type of the semiconductor switching element 1, and the turn-off speed is unnecessarily slowed to increase the loss of the semiconductor switching element 1. Can be prevented.

  It should be noted that the average pattern is held by averaging a plurality of patterns of the change in the voltage Vce between the main terminals when the semiconductor switching element 1 is turned off, and the output voltage of the operational amplifier 25 is controlled based on the average pattern. Good. The functions of the memory circuit 100 and the operational amplifier 25 can also be realized by a microcomputer (DSP), a DSP (Digital Signal Processor), or the like. Furthermore, the reference value may be adjusted by adjusting the resistance values of the resistors 33 and 34 instead of providing the reference value adjusting circuit 26.

Embodiment 4 FIG.
FIG. 7 is a circuit diagram showing the configuration of the gate drive circuit of the semiconductor switching element according to the fourth embodiment. In FIG. 7, the voltage Vce between the main terminals of the semiconductor switching element 1 is divided by a resistor 31 and a resistor 32 and input to the memory circuit 100. Then, the output of the memory circuit 100 is output to the input terminal of the operational amplifier 45 as a control circuit and a current supply circuit. The reference value Vs set by the resistors 33 and 34 is input to the reference value adjusting circuit 26, changed to the reference value Vsb corresponding to the characteristics of the semiconductor switching element 1, and input to the operational amplifier 45. Since other configurations are the same as those of the second embodiment shown in FIG. 3, the corresponding components are denoted by the same reference numerals and description thereof is omitted.

  As with the operation shown in FIG. 4, in the operational amplifier 45, the operation is based on the peak voltage Vh of the voltage Vce stored in the storage circuit 100 and the reference value Vsb input from the reference value adjustment circuit 26. The output voltage of the operational amplifier 45 is determined, and the voltage at the connection point 11 is controlled via the diode 23. When the rated voltage V1 of the semiconductor switching element 1 is large, a large jump of the voltage Vce can be allowed. Therefore, the turn-off speed of the semiconductor switching element 1 may be increased. Therefore, the reference value Vsb of the reference value adjusting circuit 26 is decreased. The voltage at the connection point 11 is lowered and set to lower the level of the injection current J2. On the other hand, when the rated voltage V1 is small, the jump of the voltage Vce at the time of turn-off cannot be allowed to be so large. Therefore, the reference value Vsb of the reference value adjustment circuit 26 is increased to set the voltage at the connection point 11 high. Increase the level of

  In the above embodiment, the semiconductor switching element 1 is formed of silicon. However, the semiconductor switching element 1 may be formed of a wide band gap semiconductor having a larger band gap than silicon. Examples of the wide band gap semiconductor include silicon carbide, a gallium nitride-based material, and diamond.

  Since the semiconductor switching element 1 formed of such a wide band gap semiconductor has high withstand voltage and high allowable current density, the semiconductor switching element 1 can be miniaturized, and these miniaturized semiconductor switching elements By using 1, it is possible to reduce the size of a semiconductor module incorporating this. At this time, since the current change di / dt at turn-off is larger than that in the case of the conventional Si semiconductor, the voltage Vce generated at turn-off, that is, the voltage jump between the main terminals becomes large. Therefore, the present invention suppresses the voltage at turn-off. It is effective to do. In addition, the response can be improved by using a wide band gap semiconductor for the semiconductor components constituting the operational amplifier.

  Further, since the heat resistance is high, the heat radiation fins of the heat sink can be downsized and the water cooling part can be air cooled, so that the semiconductor module can be further downsized.

  Furthermore, since the power loss is low, it is possible to increase the efficiency of the semiconductor switching element 1, and as a result, the efficiency of the semiconductor module can be increased when modularized.

  In the present invention, the above-described embodiments can be freely combined within the scope of the invention, or each embodiment can be appropriately changed or omitted.

1 Semiconductor switching element, 4, 5 operational amplifier, 10 connection point, 11 connection point,
15 operational amplifier, 19 current supply circuit, 25 operational amplifier, 26 reference value adjustment circuit,
31, 32 resistors, 45 operational amplifiers, 100 memory circuits.

Claims (5)

A gate driving circuit of a semiconductor switching element comprising a voltage detection circuit, a gate-on circuit, a gate- off circuit, and a control circuit,
The voltage detection circuit detects a voltage between main terminals of the semiconductor switching element,
The gate-on circuit is to turn on the semiconductor switching element by supplying current to the gate of the semiconductor switching element,
The gate-off circuit is for turning off between the main terminals by discharging the semiconductor connected to said gate charge stored in the capacitor of the gate of the switching element,
The control circuit suppresses a voltage generated between the main terminals by slowing a rate at which the charge is discharged by supplying a current from the gate-on circuit to the gate- off circuit when the semiconductor switching element is turned off. A gate drive circuit of a semiconductor switching element. A storage circuit for storing a voltage between the main terminals when the semiconductor switching element is turned off;
The current supplied from the gate-on circuit to the gate- off circuit is controlled based on the stored voltage between the main terminals.
The gate drive circuit of the semiconductor switching element according to claim 1 . The memory circuit stores a peak value of a voltage between the main terminals when the semiconductor switching element is turned off.
The gate drive circuit of the semiconductor switching element according to claim 2 . 4. The gate drive circuit for a semiconductor switching element according to claim 1 , wherein the semiconductor switching element is formed of a wide band gap semiconductor having a larger band gap than silicon. 5. The wide band gap semiconductor is silicon carbide, gallium nitride-based material, or diamond.
The gate drive circuit of the semiconductor switching element according to claim 4 .

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