JP5940211B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP5940211B2
JP5940211B2 JP2015504080A JP2015504080A JP5940211B2 JP 5940211 B2 JP5940211 B2 JP 5940211B2 JP 2015504080 A JP2015504080 A JP 2015504080A JP 2015504080 A JP2015504080 A JP 2015504080A JP 5940211 B2 JP5940211 B2 JP 5940211B2
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power semiconductor
gate
circuit
overcurrent
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JPWO2014136252A1 (en
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中武　浩
浩 中武
加藤　昌則
昌則 加藤
静里 田村
静里 田村
裕二 宮崎
裕二 宮崎
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
    • H03K17/0822—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
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    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
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    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
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    • H01L2224/4903—Connectors having different sizes, e.g. different diameters
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    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0009—Devices or circuits for detecting current in a converter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0027—Measuring means of, e.g. currents through or voltages across the switch

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electronic Switches (AREA)
  • Power Conversion In General (AREA)

Description

この発明は、パワー半導体素子に流れる電流を分流させて、電流検出用の電流を得る電流センスセルを備えたパワー半導体素子を用いた半導体装置に関するものである。   The present invention relates to a semiconductor device using a power semiconductor element including a current sense cell that diverts a current flowing through the power semiconductor element and obtains a current for current detection.

パワー半導体素子を用いた半導体装置において、過電流が流れた場合にパワー半導体素子を保護する目的などで電流を検出するために、パワー半導体素子に流れる電流を分流させて検出用の電流を得る電流センスセルを備えたものがある(例えば特許文献１)。   In a semiconductor device using a power semiconductor element, in order to detect a current for the purpose of protecting the power semiconductor element when an overcurrent flows, a current for dividing the current flowing through the power semiconductor element to obtain a detection current Some have a sense cell (for example, Patent Document 1).

特許文献１に記載されている半導体装置では、パワー半導体素子と、電流センスセルの出力電流を検出する電流検出部と、過電流制限回路と、過電流保護回路と、駆動回路とを備えている。過電流制限回路は、電流検出部の出力電圧が所定の動作電圧を超えると、ゲート電圧を所定電圧に低下させ、パワー半導体素子に流れる電流を制限する。過電流保護回路は、電流検出部の出力電圧が所定の動作電圧を超えると、所定時間経過後にパワー半導体素子をオフする。つまり、パワー半導体素子に流れる電流を制限した上で、その後パワー半導体素子をオフする。速やかにパワー半導体素子に流れる過電流を低減することで、パワー半導体素子の短絡耐量内で保護することが可能である。   The semiconductor device described in Patent Document 1 includes a power semiconductor element, a current detection unit that detects an output current of a current sense cell, an overcurrent limiting circuit, an overcurrent protection circuit, and a drive circuit. When the output voltage of the current detection unit exceeds a predetermined operating voltage, the overcurrent limiting circuit reduces the gate voltage to a predetermined voltage and limits the current flowing through the power semiconductor element. When the output voltage of the current detection unit exceeds a predetermined operating voltage, the overcurrent protection circuit turns off the power semiconductor element after a lapse of a predetermined time. That is, the current flowing through the power semiconductor element is limited, and then the power semiconductor element is turned off. By quickly reducing the overcurrent flowing through the power semiconductor element, it is possible to protect within the short-circuit tolerance of the power semiconductor element.

特開平０８−３１６８０８号公報Japanese Patent Laid-Open No. 08-316808

特許文献１に記載された半導体装置において、低いゲート電圧から電流が流れ始める、いわゆるスレッシホールド電圧Ｖｔｈが低いパワー半導体素子を用いる場合、過電流制限回路のトランジスタのコレクタ電圧を下げる必要がある。過電流制限回路のトランジスタのコレクタ電圧を下げるためには、主セルに対する電流センスセルの比率を上昇させ、電流センスセルから流れる電流を増やせば良い。しかし、電流センスセルの比率を上げるほど主セルの割合が低下する、すなわち効率が悪化するため望ましくない。電流容量を増やすため複数のＭＯＳＦＥＴチップを並列接続しているパワー半導体モジュールにおいて、複数のＭＯＳＦＥＴチップに電流センスセルを設けると、効率が悪化することに加え、各チップの電流センスセルから電流を取り出すための配線をする必要があり、パワー半導体モジュール内の配線が増えるため小型化や設計の自由度の面から望ましくない。   In the semiconductor device described in Patent Document 1, when using a power semiconductor element in which a current starts to flow from a low gate voltage, that is, a so-called threshold voltage Vth is low, it is necessary to lower the collector voltage of the transistor of the overcurrent limiting circuit. In order to reduce the collector voltage of the transistor of the overcurrent limiting circuit, the ratio of the current sense cell to the main cell may be increased to increase the current flowing from the current sense cell. However, the ratio of the main cells decreases as the ratio of the current sense cells is increased, that is, the efficiency deteriorates, which is not desirable. In a power semiconductor module in which a plurality of MOSFET chips are connected in parallel in order to increase the current capacity, if a current sense cell is provided in a plurality of MOSFET chips, in addition to deteriorating efficiency, a current is extracted from the current sense cell of each chip. Wiring needs to be performed, and wiring in the power semiconductor module increases, which is undesirable from the viewpoint of miniaturization and design freedom.

他にも駆動回路内のゲート抵抗を大きくすれば、過電流制限回路のコレクタ電圧を下げることが可能だが、ゲート抵抗の増加は半導体装置の損失の増加につながるため望ましくない。他にも、センス電流を増幅し、トランジスタのベース電流を増やして動作させる手法もあるが、増幅するには時間遅れが生じるため望ましくない。   In addition, if the gate resistance in the drive circuit is increased, the collector voltage of the overcurrent limiting circuit can be lowered. However, an increase in the gate resistance leads to an increase in the loss of the semiconductor device, which is not desirable. In addition, there is a method of amplifying the sense current and increasing the base current of the transistor to operate, but this is not desirable because a time delay occurs.

この発明は、上記のような問題点を解決するためになされたものであり、Ｖｔｈが低いパワー半導体素子を用いた半導体装置においても、損失を増加させずに過電流保護できる半導体装置を得ることを目的とする。   The present invention has been made to solve the above-described problems, and provides a semiconductor device capable of overcurrent protection without increasing loss even in a semiconductor device using a power semiconductor element having a low Vth. With the goal.

この発明は、第一電極と第二電極の間に流れる主電流をゲートに印加される電圧により制御するパワー半導体素子が複数並列接続され、この並列接続された複数のパワー半導体素子のうち一個のパワー半導体素子が主セルと電流センスセルを備え、主セルの電流を電流センスセルの出力電流により検出して、一個のパワー半導体素子の電流が過電流となった場合に複数のパワー半導体素子を保護するように制御するための過電流保護回路を備えた半導体装置において、過電流保護回路は、電流センスセルの出力電流を検出する電流検出部と、この電流検出部の出力信号に応じて複数のパワー半導体素子のゲートに印加される電圧を低下させる過電流制限回路と、複数のパワー半導体素子のゲートに印加される電圧を制御して複数のパワー半導体素子のオンオフを制御するための駆動回路と、複数のパワー半導体素子のゲートと駆動回路との間に接続され、出力電流が所定の一定値となるよう制御するゲート電流制御回路とを備え、複数のパワー半導体素子を、銅パターンが形成された１枚の基板上に、複数のパワー半導体素子のそれぞれの第一電極が前記銅パターンに接続されるように配置し、複数のパワー半導体素子の、電流センスセルの第二電極以外のそれぞれの第二電極同士を複数のパワー半導体素子以外の部材を介さずに直接接続するワイヤ配線により電気接続した構成とした。 In the present invention, a plurality of power semiconductor elements for controlling a main current flowing between the first electrode and the second electrode by a voltage applied to the gate are connected in parallel, and one of the plurality of power semiconductor elements connected in parallel is connected. The power semiconductor element includes a main cell and a current sense cell, and detects the current of the main cell from the output current of the current sense cell, and protects a plurality of power semiconductor elements when the current of one power semiconductor element becomes an overcurrent. The overcurrent protection circuit includes a current detection unit that detects an output current of the current sense cell, and a plurality of power semiconductors according to the output signal of the current detection unit. an overcurrent limiting circuit to reduce the voltage applied to the gate of the device, a plurality of power semiconductors to control the voltage applied to the gate of the plurality of power semiconductor devices Comprising a drive circuit for controlling the on-off device, it is connected between the gate and the drive circuit of the plurality of power semiconductor devices, the output current and a gate current control circuit for controlling such that a predetermined constant value, more The power semiconductor element is disposed on a single substrate on which a copper pattern is formed so that the first electrodes of the plurality of power semiconductor elements are connected to the copper pattern. Each of the second electrodes other than the second electrode of the current sense cell was electrically connected to each other by wire wiring that was directly connected without a member other than a plurality of power semiconductor elements .

本発明によれば、パワー半導体素子のＶｔｈが低い場合においても、損失が増加せずに過電流を保護できる半導体装置を得ることができる。   According to the present invention, it is possible to obtain a semiconductor device capable of protecting an overcurrent without increasing loss even when the power semiconductor element has a low Vth.

この発明の実施の形態１による半導体装置の概略構成を示すブロック図である。1 is a block diagram showing a schematic configuration of a semiconductor device according to a first embodiment of the present invention. この発明の実施の形態１による半導体装置の別の概略構成を示すブロック図である。It is a block diagram which shows another schematic structure of the semiconductor device by Embodiment 1 of this invention. この発明の実施の形態１による半導体装置のさらに別の概略構成を示すブロック図である。It is a block diagram which shows another schematic structure of the semiconductor device by Embodiment 1 of this invention. パワー半導体素子の一例としてのＭＯＳＦＥＴのゲート電圧とドレイン電流の関係を示す図である。It is a figure which shows the relationship between the gate voltage and drain current of MOSFET as an example of a power semiconductor element. この発明の実施の形態１による半導体装置のゲート電流制御回路の一例を示す回路図である。1 is a circuit diagram showing an example of a gate current control circuit of a semiconductor device according to a first embodiment of the present invention. この発明の実施の形態１による半導体装置のゲート電流制御回路のＶ−Ｉ特性の一例を示す図である。It is a figure which shows an example of the VI characteristic of the gate current control circuit of the semiconductor device by Embodiment 1 of this invention. この発明の実施の形態１による半導体装置の出力が短絡状態となった場合の保護動作のシーケンス図である。It is a sequence diagram of a protection operation when the output of the semiconductor device according to the first embodiment of the present invention is in a short circuit state. この発明の効果を説明するための比較例の半導体装置の概略構成を示すブロック図である。It is a block diagram which shows schematic structure of the semiconductor device of the comparative example for demonstrating the effect of this invention. 比較例の半導体装置の正常動作のシーケンス図である。It is a sequence diagram of normal operation of a semiconductor device of a comparative example. 比較例の半導体装置の出力が短絡状態となった場合の保護動作のシーケンス図である。It is a sequence diagram of protection operation when the output of the semiconductor device of a comparative example is in a short circuit state. 過電流制限回路のトランジスタの動作を説明するためのコレクタ電流−コレクタ電圧の特性図である。It is a characteristic diagram of collector current-collector voltage for demonstrating operation | movement of the transistor of an overcurrent limiting circuit. この発明の実施の形態２による半導体装置の概略構成を示すブロック図である。It is a block diagram which shows schematic structure of the semiconductor device by Embodiment 2 of this invention. この発明の半導体装置を適用する電力変換器の一例としての３相インバータを示す概略回路図である。It is a schematic circuit diagram which shows the three-phase inverter as an example of the power converter to which the semiconductor device of this invention is applied. この発明の実施の形態３による半導体装置の要部を示す回路図である。It is a circuit diagram which shows the principal part of the semiconductor device by Embodiment 3 of this invention. この発明の実施の形態３による半導体装置の要部の実装状態を示す平面図である。It is a top view which shows the mounting state of the principal part of the semiconductor device by Embodiment 3 of this invention.

実施の形態１．
図１は本発明の実施の形態１による半導体装置を示す回路図である。ここでは、パワー半導体素子１として、ＭＯＳＦＥＴ１（Ｍｅｔａｌ Ｏｘｉｄｅ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｆｉｅｌｄ Ｅｆｆｅｃｔ Ｔｒａｎｓｉｓｔｏｒ）を用いているが、ＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ Ｇａｔｅ Ｂｉｐｏｌａｒ Ｔｒａｎｓｉｓｔｏｒ）などゲート電極で制御する他のパワー半導体を用いても良い。図１では、パワー半導体素子１に対向して配置される還流ダイオードは省略して図示している。ここで述べる半導体装置は、例えば図１３に示す３相インバータ回路など、各種電力変換器に用いることが可能である。Embodiment 1 FIG.
FIG. 1 is a circuit diagram showing a semiconductor device according to Embodiment 1 of the present invention. Although the MOSFET 1 (Metal Oxide Field Effect Transistor) is used as the power semiconductor element 1 here, another power semiconductor controlled by a gate electrode such as an IGBT (Insulated Gate Bipolar Transistor) may be used. In FIG. 1, the free-wheeling diode disposed to face the power semiconductor element 1 is omitted. The semiconductor device described here can be used for various power converters such as a three-phase inverter circuit shown in FIG.

パワー半導体素子１は、主に電流を通電する主セル２、および電流を分流させる電流センスセル３を持ち、ドレイン端子とゲート端子はお互いに接続されている。電流センスセル３のソースと主セル２のソースとの間には、電流センスセル３の電流を検出する電流検出部４が接続される。図１では、電流検出部の例として、抵抗を用いて電流を電圧に変換する電流検出部４を示した。   The power semiconductor element 1 has a main cell 2 that mainly conducts current and a current sense cell 3 that shunts current, and a drain terminal and a gate terminal are connected to each other. Between the source of the current sense cell 3 and the source of the main cell 2, a current detection unit 4 that detects the current of the current sense cell 3 is connected. In FIG. 1, as an example of the current detection unit, the current detection unit 4 that converts a current into a voltage using a resistor is illustrated.

上記のように、パワー半導体素子にはＭＯＳＦＥＴやＩＧＢＴなど種々あるが、本発明を適用するパワー半導体素子は、２電極間に流れる主電流をゲート電極の電圧により制御する構造のパワー半導体素子である。主電流が流れる２電極をそれぞれ第一電極、第二電極と呼ぶことにする。図１に示すＭＯＳＦＥＴでは、ドレインが第一電極であり、ソースが第二電極である。パワー半導体素子がＩＧＢＴの場合、コレクタが第一電極であり、エミッタが第二電極である。主セルの第一電極と電流センスセルの第一電極とは接続されている。一方、電流センスセルの第二電極と主セルの第二電極とは、別々に外部に電気接続できる構造となっている。図１では、電流センスセルの第二電極と主セルの第二電極と間に電流検出部４が接続されている。   As described above, there are various power semiconductor elements such as MOSFET and IGBT, but the power semiconductor element to which the present invention is applied is a power semiconductor element having a structure in which the main current flowing between the two electrodes is controlled by the voltage of the gate electrode. . The two electrodes through which the main current flows are called the first electrode and the second electrode, respectively. In the MOSFET shown in FIG. 1, the drain is the first electrode and the source is the second electrode. When the power semiconductor element is an IGBT, the collector is the first electrode and the emitter is the second electrode. The first electrode of the main cell and the first electrode of the current sense cell are connected. On the other hand, the second electrode of the current sense cell and the second electrode of the main cell have a structure that can be electrically connected to the outside separately. In FIG. 1, a current detection unit 4 is connected between the second electrode of the current sense cell and the second electrode of the main cell.

図２に電流検出部４の、図１とは別の例を示す。電流検出抵抗４１両端の電圧と基準電圧源４２の電圧を比較器４０で比較し、電流検出抵抗４１の両端電圧のほうが大きければ比較器４０の出力がハイインピーダンスとなり、電流検出部４は高出力信号を出力する。比較器４０と基準電圧源４２で短絡電流検出レベルを設定するので、図１に示す、抵抗のみで構成する電流検出部４よりも精度が高いことが利点である。   FIG. 2 shows an example of the current detection unit 4 different from FIG. The voltage across the current detection resistor 41 and the voltage of the reference voltage source 42 are compared by the comparator 40. If the voltage across the current detection resistor 41 is larger, the output of the comparator 40 becomes high impedance, and the current detection unit 4 has a high output. Output a signal. Since the short circuit current detection level is set by the comparator 40 and the reference voltage source 42, it is an advantage that the accuracy is higher than that of the current detection unit 4 including only the resistance shown in FIG.

電流検出部４のさらに別の例を図３に示す。演算増幅器４３の反転入力端子を電流センスセル３のソースに接続し、非反転入力端子を主セル２のソースに接続する。反転入力端子と出力端子の間に抵抗４４を接続する。演算増幅器４３の出力電圧は、電流センスセル３の出力電流に比例した電圧となるため、比較器４０において基準電圧源４２と比較し、基準電圧源４２のほうが大きければ比較器４０の出力がハイインピーダンスとなり、電流検出部４は高出力信号を出力する。この方式の利点は次のとおりである。演算増幅器４３の反転入力端子と非反転入力端子間の電圧がゼロとなるため、主セル２と電流センスセル３のゲート‐ソース間電圧およびドレイン‐ソース間電圧が等しくなる。そのため、電流センスセル３と主セル２の電流の比は各セル数の比と等しくなり、高い精度での電流検出が可能となる。   Another example of the current detection unit 4 is shown in FIG. The inverting input terminal of the operational amplifier 43 is connected to the source of the current sense cell 3, and the non-inverting input terminal is connected to the source of the main cell 2. A resistor 44 is connected between the inverting input terminal and the output terminal. Since the output voltage of the operational amplifier 43 is proportional to the output current of the current sense cell 3, the comparator 40 compares the output voltage of the operational amplifier 43 with the reference voltage source 42. If the reference voltage source 42 is larger, the output of the comparator 40 has a high impedance. Thus, the current detection unit 4 outputs a high output signal. The advantages of this method are as follows. Since the voltage between the inverting input terminal and the non-inverting input terminal of the operational amplifier 43 becomes zero, the gate-source voltage and the drain-source voltage of the main cell 2 and the current sense cell 3 become equal. Therefore, the current ratio between the current sense cell 3 and the main cell 2 is equal to the ratio of the number of cells, and current detection with high accuracy is possible.

電流検出部４の出力信号は、過電流制限回路５へ入力される。過電流制限回路５はこの信号を受けて、ＭＯＳＦＥＴ１のゲート電圧を低減させる。ゲート電圧が低下すれば、ＭＯＳＦＥＴ１に流れるドレイン電流も低下し、ＭＯＳＦＥＴ１は過電流から保護される。この状態ではまだ駆動回路６からの出力が出ており、ゲート電流制御回路１４で制御された電流が、過電流制限回路５のトランジスタ１３に流れる。図１〜図３では、過電流制限回路５として一つのトランジスタを用いたが、この構成に限るわけではなく、例えば、複数のトランジスタを用いて電流検出部４の出力信号を増幅させてからパワー半導体素子１のゲート電圧を低減させても良い。   The output signal of the current detector 4 is input to the overcurrent limiting circuit 5. The overcurrent limiting circuit 5 receives this signal and reduces the gate voltage of the MOSFET 1. If the gate voltage decreases, the drain current flowing through the MOSFET 1 also decreases, and the MOSFET 1 is protected from overcurrent. In this state, the output from the drive circuit 6 is still output, and the current controlled by the gate current control circuit 14 flows to the transistor 13 of the overcurrent limiting circuit 5. In FIG. 1 to FIG. 3, one transistor is used as the overcurrent limiting circuit 5. However, the present invention is not limited to this configuration. For example, a plurality of transistors are used to amplify the output signal of the current detection unit 4 before power supply. The gate voltage of the semiconductor element 1 may be reduced.

図１〜図３に示す本発明の実施の形態１による半導体装置では、電流検出部４と過電流検出回路９との間に、フィルタ回路１０を入れている。大容量の半導体装置では、装置が大型になるため、電流検出部４、過電流制限回路５、ＭＯＳＦＥＴ１からなるパワー半導体モジュール１１と駆動回路６、過電流検出回路９などからなる制御回路１２との距離が離れていることが多い。大容量の半導体装置では装置が発生するノイズが大きいため、パワー半導体モジュール１１と制御回路１２の間にノイズ除去用のフィルタ回路１０を挿入する必要がある。フィルタ回路１０によって、過電流検出信号が遅れるため、過電流制限回路５にはＭＯＳＦＥＴ１が破壊しないようにドレイン電流がほぼゼロとなる程度までドレイン電流を制限する機能が求められる。   In the semiconductor device according to the first embodiment of the present invention shown in FIGS. 1 to 3, a filter circuit 10 is inserted between the current detection unit 4 and the overcurrent detection circuit 9. In a large-capacity semiconductor device, the size of the device becomes large. Therefore, a power semiconductor module 11 composed of a current detection unit 4, an overcurrent limiting circuit 5, a MOSFET 1 and a control circuit 12 composed of a drive circuit 6, an overcurrent detection circuit 9, and the like. Often far away. Since a large-capacity semiconductor device generates a large amount of noise, it is necessary to insert a noise removal filter circuit 10 between the power semiconductor module 11 and the control circuit 12. Since the overcurrent detection signal is delayed by the filter circuit 10, the overcurrent limiting circuit 5 is required to have a function of limiting the drain current to the extent that the drain current becomes substantially zero so that the MOSFET 1 is not destroyed.

図１〜図３に示す本発明の実施の形態１による半導体装置では、ＭＯＳＦＥＴのゲートと過電流制限回路５のトランジスタ１３のコレクタとの間に通常接続されるツェナーダイオードを省略している。これは次の理由による。図４にパワー半導体素子の一例であるＭＯＳＦＥＴのゲート電圧とドレイン電流の関係を示す。従来の過電流保護回路では、スレッシホールド電圧Ｖｔｈが高く、ドレイン電流の変化が大きいパワー半導体素子を対象にしていた。そのため、必要以上にゲート電圧を下げないようにするため、ＭＯＳＦＥＴのゲートと過電流制限回路５のトランジスタ１３のコレクタとの間にツェナーダイオードを接続して保護時のゲート電圧を調整していた。本発明では、図４中に示すＶｔｈが低いＭＯＳＦＥＴをも対象にする。そのため、保護時のゲート電圧は、低減目標ゲート電圧で示す電圧まで下げる必要があり、ツェナーダイオードを省いた。ＭＯＳＦＥＴのゲートと過電流制限回路５のトランジスタ１３のコレクタとの間には、保護用としてダイオードや抵抗などの素子が挿入される場合もあるが、この保護用の素子による電圧降下が２Ｖ以下となるようにすれば良い。   In the semiconductor device according to the first embodiment of the present invention shown in FIGS. 1 to 3, the Zener diode normally connected between the gate of the MOSFET and the collector of the transistor 13 of the overcurrent limiting circuit 5 is omitted. This is due to the following reason. FIG. 4 shows the relationship between the gate voltage and drain current of a MOSFET which is an example of a power semiconductor element. In the conventional overcurrent protection circuit, a power semiconductor element having a high threshold voltage Vth and a large change in drain current is targeted. Therefore, in order not to lower the gate voltage more than necessary, the gate voltage at the time of protection is adjusted by connecting a Zener diode between the gate of the MOSFET and the collector of the transistor 13 of the overcurrent limiting circuit 5. In the present invention, a MOSFET having a low Vth shown in FIG. 4 is also targeted. Therefore, the gate voltage at the time of protection needs to be lowered to the voltage indicated by the reduced target gate voltage, and the Zener diode is omitted. An element such as a diode or a resistor may be inserted for protection between the gate of the MOSFET and the collector of the transistor 13 of the overcurrent limiting circuit 5, but the voltage drop due to this protection element is 2 V or less. What should I do?

電流検出部４からの信号はフィルタ回路１０に入力され、一定の遅れ時間を経たのち、過電流検出回路９へ入力される。過電流検出回路９は電流検出部４の出力信号と過電流設定値を比較し、過電流と判定すればエラー信号出力回路１５とオフ指令出力回路１６に信号を出力する。オフ指令出力回路１６は駆動回路６にオフ指令を出力し、駆動回路６からの出力がオフになる。それに伴い、過電流制限回路５のトランジスタ１３に流れる電流も低下する。   A signal from the current detection unit 4 is input to the filter circuit 10 and is input to the overcurrent detection circuit 9 after a certain delay time. The overcurrent detection circuit 9 compares the output signal of the current detection unit 4 with the overcurrent set value, and outputs a signal to the error signal output circuit 15 and the off command output circuit 16 if it is determined as an overcurrent. The off command output circuit 16 outputs an off command to the drive circuit 6, and the output from the drive circuit 6 is turned off. Along with this, the current flowing through the transistor 13 of the overcurrent limiting circuit 5 also decreases.

ゲート電流制御回路１４の制御電流値は、正常動作時のミラー期間のゲート電流値に設定する。正常動作のスイッチング時だけでなく、アーム短絡、もしくは負荷短絡時に過電流制限回路５が動作した時にも、駆動回路から流れ出る電流値は、ゲート電流制御回路１４の制御電流値に制御される。スイッチング時間はミラー期間のゲート電流値によって定まるため、ゲート電流制御回路１４によってゲート電流値を所定の一定値、すなわちパワー半導体素子１の正常動作時のミラー期間のゲート電流値となるように制御しても、スイッチング損失が増加することはない。   The control current value of the gate current control circuit 14 is set to the gate current value in the mirror period during normal operation. The current value flowing out of the drive circuit is controlled by the control current value of the gate current control circuit 14 not only when switching in normal operation but also when the overcurrent limiting circuit 5 operates when the arm is short-circuited or the load is short-circuited. Since the switching time is determined by the gate current value in the mirror period, the gate current control circuit 14 controls the gate current value to be a predetermined constant value, that is, the gate current value in the mirror period during normal operation of the power semiconductor element 1. However, the switching loss does not increase.

ゲート電流制御回路１４の構成例を図５に示す。ゲート電流制御回路１４に電流が流れ始めたときは、抵抗１９に流れる電流が小さく、トランジスタ１８はオフしたままであるので、トランジスタ１７がオンし、ゲート電流は制御されない。抵抗１９に流れる電流が大きくなるとトランジスタ１８がオンし、トランジスタ１７のエミッタ‐ベース間電圧が低下し、ゲート電流が所定の一定値に制御される。すなわち、抵抗１９による電圧降下がトランジスタ１８をオンさせるエミッタ‐ベース間電圧に等しくなるように、抵抗１９に流れる電流が制御される。駆動回路６とパワー半導体素子１のゲートの間に、ゲート電流制御回路１４以外にゲート電流を制御する回路がないため、ゲート電流は所定の一定値に制御される。図６にゲート電流制御回路１４のＶ−Ｉ特性を示す。パワー半導体素子１のゲート電圧値によって、ゲート電流制御回路１４の電圧値は変化するが、ゲート電流制御回路１４の出力電流は所定の一定値、すなわちパワー半導体素子１の正常動作時のミラー期間のゲート電流値となるように制御される。また、駆動回路６とパワー半導体素子１のゲートの間に、ミラー期間のゲート電流値に大きな影響を与えない程度（例えば、ゲート電流を１０％変更させない程度）の低抵抗を接続しても良い。   A configuration example of the gate current control circuit 14 is shown in FIG. When the current starts to flow through the gate current control circuit 14, the current flowing through the resistor 19 is small and the transistor 18 remains off, so that the transistor 17 is turned on and the gate current is not controlled. When the current flowing through the resistor 19 increases, the transistor 18 is turned on, the emitter-base voltage of the transistor 17 decreases, and the gate current is controlled to a predetermined constant value. That is, the current flowing through the resistor 19 is controlled so that the voltage drop due to the resistor 19 becomes equal to the emitter-base voltage that turns on the transistor 18. Since there is no circuit for controlling the gate current other than the gate current control circuit 14 between the drive circuit 6 and the gate of the power semiconductor element 1, the gate current is controlled to a predetermined constant value. FIG. 6 shows the VI characteristics of the gate current control circuit 14. Although the voltage value of the gate current control circuit 14 varies depending on the gate voltage value of the power semiconductor element 1, the output current of the gate current control circuit 14 is a predetermined constant value, that is, the mirror period during normal operation of the power semiconductor element 1. The gate current value is controlled. Further, a low resistance that does not significantly affect the gate current value in the mirror period (for example, does not change the gate current by 10%) may be connected between the drive circuit 6 and the gate of the power semiconductor element 1. .

図７に、図１の回路の出力が短絡状態となった場合の保護動作のシーケンスを示す。ｔ０のタイミングでスイッチングオン指令が入ると、ゲート電流は所定の一定値の電流となる。ゲート電流が一定であるため、ゲート電圧は一定の傾きで上昇する。ゲート電圧がしきい値を超えると（ｔ１のタイミング）ドレイン電流は通電を始める。ゲート電圧の値が駆動回路６の電源電圧に達すると（ｔ４のタイミング）、ゲート電圧とドレイン電流は一定となり、ゲート電流はゼロとなる。回路が短絡状態となっているため過電流が流れ、ｔ５のタイミングから過電流制限動作を始める。駆動回路６から過電流制限回路５のトランジスタ１３に流れ込む電流は、ゲート電流制御回路１４で所定の一定値に制御される。過電流制限回路５のトランジスタ１３には、ＭＯＳＦＥＴ１のゲートからの放電電流も重畳されるが、駆動回路６から流れる電流がゲート電流制御回路１４で所定の一定値に制御されているので、トランジスタ１３のコレクタ電圧は低い値に保たれ、ＭＯＳＦＥＴ１のゲート電圧もｔ６のタイミングでほぼゼロに低減させることができる。図７に示すように、駆動回路６から過電流制限回路５のトランジスタ１３に流れ込む電流を制限すると、過電流制限時のゲート電圧を大幅に低下できることがわかる。   FIG. 7 shows a protective operation sequence when the output of the circuit of FIG. When a switching-on command is input at the timing t0, the gate current becomes a predetermined constant current. Since the gate current is constant, the gate voltage rises with a constant slope. When the gate voltage exceeds the threshold (timing of t1), the drain current starts to be energized. When the value of the gate voltage reaches the power supply voltage of the drive circuit 6 (timing at t4), the gate voltage and the drain current become constant and the gate current becomes zero. Since the circuit is in a short circuit state, an overcurrent flows, and the overcurrent limiting operation starts from the timing t5. The current flowing from the drive circuit 6 into the transistor 13 of the overcurrent limiting circuit 5 is controlled by the gate current control circuit 14 to a predetermined constant value. A discharge current from the gate of the MOSFET 1 is also superimposed on the transistor 13 of the overcurrent limiting circuit 5, but the current flowing from the drive circuit 6 is controlled to a predetermined constant value by the gate current control circuit 14, so that the transistor 13 Is kept at a low value, and the gate voltage of MOSFET 1 can be reduced to almost zero at the timing of t6. As shown in FIG. 7, it can be seen that if the current flowing from the drive circuit 6 to the transistor 13 of the overcurrent limiting circuit 5 is limited, the gate voltage when the overcurrent is limited can be significantly reduced.

ここで、図８に示す、ゲート電流制御回路１４の代わりに駆動回路６内部に備えられたゲート抵抗７を用いて、パワー半導体素子１のスイッチング時間を制御する従来の回路方式による動作を比較例として説明する。図８に示す回路は、比較のため、ゲート電流制御回路１４を備えず、ゲート抵抗７を備えている以外は、図１の回路と同じ構成としている。ゲート抵抗７はゲート電流を制限する効果はあるものの、その電流値は、ゲート抵抗７の両端に印加される電圧値に依存する。すなわち、ゲート抵抗７の駆動回路側の電位は変化せず、ＭＯＳＦＥＴ１のゲート電圧が変化するので、ゲート抵抗７の両端に印加される電圧値が変化し、ゲート電流も変化する。   Here, the operation of the conventional circuit system for controlling the switching time of the power semiconductor element 1 using the gate resistor 7 provided in the drive circuit 6 instead of the gate current control circuit 14 shown in FIG. Will be described. For comparison, the circuit shown in FIG. 8 has the same configuration as the circuit of FIG. 1 except that it does not include the gate current control circuit 14 but includes the gate resistor 7. Although the gate resistor 7 has an effect of limiting the gate current, the current value depends on the voltage value applied to both ends of the gate resistor 7. That is, the potential on the drive circuit side of the gate resistor 7 does not change, and the gate voltage of the MOSFET 1 changes, so that the voltage value applied across the gate resistor 7 changes and the gate current also changes.

図８の比較例の回路の通常スイッチング時のスイッチング波形を図９に示す。ｔ０のタイミングでオンのスイッチング指令が入り、ゲート電圧がｔ１のタイミングでしきい値を超えると、ドレイン電流が流れ始める。このときの図９に示すゲート電流の最大値は、
（ゲート電流の最大値）＝（駆動回路の電源電圧）÷（ゲート抵抗） （１）
となる。ゲート電圧が上昇するとともにゲート電流は低下し、ｔ２からｔ３の期間に一定の電流値になる。ゲート電流が一定となるｔ２からｔ３の期間をミラー期間と呼び、スイッチング速度はミラー期間のゲート電流によって定まる。一般にパワー半導体素子１の定格電流におけるミラー電圧は１１Ｖ程度になる。駆動回路６の電源電圧を１５Ｖとすれば、ミラー期間のゲート電流は、
（ミラー期間のゲート電流）＝（４Ｖ）÷（ゲート抵抗） （２）
となる。ｔ３のタイミングでドレイン電圧の変化が終わるとミラー期間も終了し、再びゲート電圧は上昇し、ｔ４のタイミングで駆動回路６の電源電圧まで上昇する。FIG. 9 shows switching waveforms during normal switching of the circuit of the comparative example of FIG. When an ON switching command is input at the timing t0 and the gate voltage exceeds the threshold value at the timing t1, the drain current starts to flow. The maximum value of the gate current shown in FIG.
(Maximum value of gate current) = (Power supply voltage of drive circuit) / (Gate resistance) (1)
It becomes. As the gate voltage increases, the gate current decreases, and becomes a constant current value during the period from t2 to t3. The period from t2 to t3 in which the gate current is constant is called a mirror period, and the switching speed is determined by the gate current in the mirror period. In general, the mirror voltage at the rated current of the power semiconductor element 1 is about 11V. If the power supply voltage of the drive circuit 6 is 15V, the gate current during the mirror period is
(Gate current during mirror period) = (4V) ÷ (gate resistance) (2)
It becomes. When the change of the drain voltage ends at the timing of t3, the mirror period also ends, the gate voltage rises again, and rises to the power supply voltage of the drive circuit 6 at the timing of t4.

次に過電流が流れたときの、図８に示す比較例における過電流保護回路の動作を図１０の動作シーケンス図に従って説明する。負荷短絡もしくはアーム短絡の状態でオン指令が入ると、ゲート電圧の上昇にしたがってドレイン電流も上昇する。電流センスセル３にはドレイン電流に比例した電流が流れるため、電流検出部４からはドレイン電流に比例した信号が出力される。電流検出部４からの信号にしたがって過電流制限回路５のトランジスタ１３のベース電流が上昇すると、ｔ５のタイミングでトランジスタ１３のコレクタ電圧が低下し始め、ＭＯＳＦＥＴ１のゲート電圧が低下するので、ＭＯＳＦＥＴ１のドレイン電流もｔ６のタイミングでＩｄ１まで低下する。トランジスタ１３のコレクタ電圧Ｖｃｅは図１０に示すように、トランジスタ１３の静特性と次式に示す回路特性からＶｇｓ１に定まる。
Ｉｃ＝（Ｖｃｃ−Ｖｃｅ）／Ｒｇ （３）
ただし、Ｉｃはトランジスタ１３のコレクタ電流、Ｖｃｅはトランジスタ１３のコレクタ電圧、Ｖｃｃは駆動回路６の電源電圧、Ｒｇは駆動回路６内部のゲート抵抗７である。Next, the operation of the overcurrent protection circuit in the comparative example shown in FIG. 8 when overcurrent flows will be described with reference to the operation sequence diagram of FIG. When an ON command is input in the state of a load short circuit or an arm short circuit, the drain current increases as the gate voltage increases. Since a current proportional to the drain current flows through the current sense cell 3, a signal proportional to the drain current is output from the current detection unit 4. When the base current of the transistor 13 of the overcurrent limiting circuit 5 increases according to the signal from the current detection unit 4, the collector voltage of the transistor 13 begins to decrease at the timing t5, and the gate voltage of the MOSFET 1 decreases. The current also decreases to Id1 at the timing of t6. As shown in FIG. 10, the collector voltage Vce of the transistor 13 is determined to be Vgs1 from the static characteristics of the transistor 13 and the circuit characteristics shown in the following equation.
Ic = (Vcc−Vce) / Rg (3)
Here, Ic is the collector current of the transistor 13, Vce is the collector voltage of the transistor 13, Vcc is the power supply voltage of the drive circuit 6, and Rg is the gate resistor 7 in the drive circuit 6.

図４に示すＶｔｈが低いＭＯＳＦＥＴを保護するためには、保護時にゲート電圧をゼロ付近まで下げる必要があるが、そのためには、過電流制限回路５のトランジスタ１３に式（１）で示すゲート電流の最大値に近い電流まで流さなければならない。式（１）と式（２）の比較から、トランジスタ１３は、ミラー期間のゲート電流の４倍近い電流を流さなければならないことがわかる。   In order to protect the MOSFET having a low Vth shown in FIG. 4, it is necessary to lower the gate voltage to near zero at the time of protection. For this purpose, the gate current represented by the equation (1) is applied to the transistor 13 of the overcurrent limiting circuit 5. The current must be close to the maximum value. From the comparison between Expression (1) and Expression (2), it can be seen that the transistor 13 must pass a current that is nearly four times the gate current in the mirror period.

過電流制限動作時のトランジスタ１３のコレクタ電圧を下げるためには、主セル２に対する電流センスセル３の比率を上昇させ、電流センスセル３から流れる電流を増やせば良い。しかし、電流センスセル３の比率を上げるほど主セル２の割合が低下する、すなわち効率が悪化するため望ましくない。電流容量を増やすため複数のＭＯＳＦＥＴチップを並列接続しているパワー半導体モジュールにおいて、複数のＭＯＳＦＥＴチップに電流センスセルを設けると、効率が悪化することに加え、各チップの電流センスセルから電流を取り出すための配線をする必要があり、パワー半導体モジュール内の配線が増えるため小型化や設計の自由度の面から望ましくない。   In order to reduce the collector voltage of the transistor 13 during the overcurrent limiting operation, the ratio of the current sense cell 3 to the main cell 2 may be increased to increase the current flowing from the current sense cell 3. However, as the ratio of the current sense cell 3 is increased, the ratio of the main cell 2 is decreased, that is, the efficiency is deteriorated, which is not desirable. In a power semiconductor module in which a plurality of MOSFET chips are connected in parallel in order to increase the current capacity, if a current sense cell is provided in a plurality of MOSFET chips, in addition to deteriorating efficiency, a current is extracted from the current sense cell of each chip. Wiring needs to be performed, and wiring in the power semiconductor module increases, which is undesirable from the viewpoint of miniaturization and design freedom.

図１１に、過電流制限回路５のトランジスタ１３の静特性と、動作状態を示す。図１１の横軸はトランジスタ１３のコレクタ電圧Ｖｃｅ、縦軸はコレクタ電流Ｉｃである。トランジスタ１３のベース電流をパラメータとして、Ｉｃ−Ｖｃｅの特性を示している。斜めの直線は、図８に示した比較例の回路における回路特性、すなわち式（３）を示している。比較例の回路では、ベース電流で決まる静特性とこの斜めの直線の交点がトランジスタ１３の動作点となる。例えば、過電流保護時のベース電流がＩｂ０であれば、トランジスタ１３のコレクタ電圧はＶｃｅ２となる。比較例の回路においては、駆動回路内のゲート抵抗Ｒｇを大きくすれば、図１１における、回路定数から定まる直線の縦軸の切片が下がり、過電流制限回路のコレクタ電圧を下げることが可能だが、ゲート抵抗の増加は半導体装置の損失の増加につながるため望ましくない。他にも、センス電流を増幅し、トランジスタのベース電流を増やして動作させる手法もあるが、増幅するには時間遅れが生じるため望ましくない。   FIG. 11 shows the static characteristics and operation state of the transistor 13 of the overcurrent limiting circuit 5. In FIG. 11, the horizontal axis represents the collector voltage Vce of the transistor 13, and the vertical axis represents the collector current Ic. The characteristics of Ic-Vce are shown using the base current of the transistor 13 as a parameter. The diagonal straight line indicates the circuit characteristic in the circuit of the comparative example shown in FIG. 8, that is, the equation (3). In the circuit of the comparative example, the intersection of the static characteristic determined by the base current and this oblique straight line is the operating point of the transistor 13. For example, if the base current during overcurrent protection is Ib0, the collector voltage of the transistor 13 is Vce2. In the circuit of the comparative example, if the gate resistance Rg in the drive circuit is increased, the intercept of the vertical axis of the straight line determined from the circuit constant in FIG. 11 can be lowered, and the collector voltage of the overcurrent limiting circuit can be lowered. An increase in gate resistance is undesirable because it leads to an increase in the loss of the semiconductor device. In addition, there is a method of amplifying the sense current and increasing the base current of the transistor to operate, but this is not desirable because a time delay occurs.

そこで、本発明では、図１〜図３に示すように、ゲート電流制御回路１４を設けた。ゲート電流制御回路１４は、その出力電流を所定の一定値、すなわちパワー半導体素子１の正常動作時のミラー期間のゲート電流値となるように制御する。なお、所定の一定値はパワー半導体素子１の正常動作時のゲート電流値に正確に同じではなくても良く、正常動作時のゲート電流値の９０％〜１１０％の範囲の値であれば良い。この構成により、式（１）と式（２）の比較でわかるように、過電流制限回路５のトランジスタ１３のコレクタ電流が、比較例の過電流制限時のコレクタ電流の４分の１に近い低い電流値に制御されるため、同じベース電流が流れた場合でもトランジスタ１３のコレクタ電圧を、例えばＶｃｅ１で示す値まで低く抑えることができる。電流センスセル３から流れ出る電流は小さく、トランジスタ１３のベースに流れ込む電流も小さいが、本発明を適用することで、過電流保護動作時のＭＳＦＥＴ１のゲート電圧を、図１１に示すＶｃｅ１のように低く抑えることができるため、過電流から確実に保護することができる。   Therefore, in the present invention, a gate current control circuit 14 is provided as shown in FIGS. The gate current control circuit 14 controls the output current so as to be a predetermined constant value, that is, the gate current value in the mirror period during normal operation of the power semiconductor element 1. The predetermined constant value may not be exactly the same as the gate current value during normal operation of the power semiconductor element 1, and may be a value in the range of 90% to 110% of the gate current value during normal operation. . With this configuration, as can be seen from the comparison between Expression (1) and Expression (2), the collector current of the transistor 13 of the overcurrent limiting circuit 5 is close to one-fourth of the collector current at the time of overcurrent limitation in the comparative example. Since the current value is controlled to be low, the collector voltage of the transistor 13 can be suppressed to a value indicated by Vce1, for example, even when the same base current flows. Although the current flowing out from the current sense cell 3 is small and the current flowing into the base of the transistor 13 is also small, by applying the present invention, the gate voltage of the MSFET 1 during the overcurrent protection operation is kept low as Vce1 shown in FIG. Therefore, it is possible to reliably protect against overcurrent.

本発明におけるパワー半導体素子は、珪素によって形成されてもよい。また、珪素に比べてバンドギャップが大きいワイドバンドギャップ半導体によって形成してもよい。ワイドバンドギャップ半導体としては、例えば、炭化珪素、窒化ガリウム系材料又はダイヤモンドがある。   The power semiconductor element in the present invention may be formed of silicon. Alternatively, a wide band gap semiconductor having a larger band gap than silicon may be used. Examples of the wide band gap semiconductor include silicon carbide, a gallium nitride-based material, and diamond.

このようなワイドバンドギャップ半導体は、Ｖｔｈが低い特性を持つ傾向が強いため、本発明によって得られる効果は大きくなる。また、ワイドバンドギャップ半導体によって形成されたパワー半導体素子は、耐電圧が高く、許容電流密度も高いため、パワー半導体素子の小型化が可能である。これら小型化されたパワー半導体素子を用いることにより、これらの素子を組み込んだ半導体装置の小型化が可能となる。   Since such a wide band gap semiconductor has a strong tendency to have a low Vth characteristic, the effect obtained by the present invention is increased. In addition, since the power semiconductor element formed of a wide band gap semiconductor has a high withstand voltage and a high allowable current density, the power semiconductor element can be downsized. By using these miniaturized power semiconductor elements, a semiconductor device incorporating these elements can be miniaturized.

またワイドバンドギャップ半導体は、耐熱性も高いため、ヒートシンクの放熱フィンの小型化や、水冷部の空冷化が可能であるので、半導体装置の一層の小型化が可能になる。更に電力損失が低いため、パワー半導体素子の高効率化が可能であり、延いては半導体装置の高効率化が可能になる。   In addition, since the wide band gap semiconductor has high heat resistance, it is possible to reduce the size of the heat dissipating fins of the heat sink and the air cooling of the water cooling portion, thereby further reducing the size of the semiconductor device. Furthermore, since the power loss is low, it is possible to increase the efficiency of the power semiconductor element, and further increase the efficiency of the semiconductor device.

実施の形態２．
図１２は、本発明の実施の形態２による半導体装置を示す回路図である。図１２において、図１と同一符号は、同一または相当する部分を示す。図１２に示す回路は、図１の回路にラッチ回路２０が付加されている。電流検出部４において、過電流と判断される所定の閾値を超えた電流が検出されると、過電流保護回路８が動作して、パワー半導体素子１の電流が小さくなる。パワー半導体素子１の電流が小さくなると、電流検出部４における電流検出値も小さくなるため、過電流制限回路５への入力も小さくなり、過電流制限回路５のトランジスタ１３のコレクタ電圧が上昇する。トランジスタ１３のコレクタ電圧が上昇すると、パワー半導体素子１のゲート電圧も上昇し、パワー半導体素子１の電流が大きくなってしまう。再び過電流と判断される所定の閾値まで電流が達すると、過電流保護回路８が動作するというように、パワー半導体素子１の電流の上昇と下降が繰り返される。ラッチ回路２０は、一旦電流検出部４において、過電流と判断される所定の閾値を超えた電流が検出されると、電流検出値が下がっても、所定時間、トランジスタ１３への出力を下げない、すなわちラッチ動作を行う回路である。Embodiment 2. FIG.
FIG. 12 is a circuit diagram showing a semiconductor device according to the second embodiment of the present invention. 12, the same reference numerals as those in FIG. 1 denote the same or corresponding parts. In the circuit shown in FIG. 12, a latch circuit 20 is added to the circuit shown in FIG. When the current detection unit 4 detects a current exceeding a predetermined threshold value that is determined to be an overcurrent, the overcurrent protection circuit 8 operates to reduce the current of the power semiconductor element 1. When the current of the power semiconductor element 1 decreases, the current detection value in the current detection unit 4 also decreases, so the input to the overcurrent limit circuit 5 also decreases, and the collector voltage of the transistor 13 of the overcurrent limit circuit 5 increases. When the collector voltage of the transistor 13 increases, the gate voltage of the power semiconductor element 1 also increases, and the current of the power semiconductor element 1 increases. When the current reaches a predetermined threshold value that is again determined to be an overcurrent, the current of the power semiconductor element 1 is repeatedly increased and decreased so that the overcurrent protection circuit 8 operates. The latch circuit 20 does not decrease the output to the transistor 13 for a predetermined time even if the current detection value decreases once the current detection unit 4 detects a current exceeding a predetermined threshold value determined to be an overcurrent. That is, it is a circuit that performs a latch operation.

ラッチ回路２０を設けることにより、特にスレッシホールド電圧の低いパワー半導体素子に対しゲート電流制御回路を設けた場合に、パワー半導体素子１の電流の上昇と下降を防ぐことができるので、確実に過電流保護動作を行うことができる半導体装置を提供できる。   By providing the latch circuit 20, particularly when a gate current control circuit is provided for a power semiconductor element having a low threshold voltage, an increase and a decrease in the current of the power semiconductor element 1 can be prevented. A semiconductor device capable of performing a current protection operation can be provided.

実施の形態３．
図１３は、本発明の半導体装置を適用する電力変換器の一例としての３相インバータ回路を示す回路図である。図１３の回路は、交流を直流に変換し、変換された直流をスイッチングして３相の交流に変換してモータＭを駆動する電力変換器である。図１３の回路では、上側のアーム１００ａ、１００ｂ、１００ｃ、下側のアーム２００ａ、２００ｂ、２００ｃそれぞれに、複数のパワー半導体素子が並列に接続された構成となっている。上側のアーム１００ａと下側のアーム２００ａの詳細を図１４に示す。下側のアーム２００ａを例にとって詳細を説明すると、それぞれパワー半導体素子としてのＩＧＢＴ２１ａ〜２８ａと、それぞれのＩＧＢＴにそれぞれ並列接続されたダイオード３１ａ〜３８ａのセットが並列接続された構成となっている。さらに、ＩＧＢＴと並列に接続されたダイオードのセット８個は、ＩＧＢＴと並列に接続されたダイオードのセット４個ずつを基板２０１ａおよび基板２０２ａに配置した２個のモジュールを並列に接続して実装されている。Embodiment 3 FIG.
FIG. 13 is a circuit diagram showing a three-phase inverter circuit as an example of a power converter to which the semiconductor device of the present invention is applied. The circuit in FIG. 13 is a power converter that converts alternating current into direct current, switches the converted direct current to convert it into three-phase alternating current, and drives the motor M. In the circuit of FIG. 13, a plurality of power semiconductor elements are connected in parallel to the upper arms 100a, 100b, and 100c and the lower arms 200a, 200b, and 200c, respectively. Details of the upper arm 100a and the lower arm 200a are shown in FIG. The details will be described taking the lower arm 200a as an example. The IGBTs 21a to 28a as power semiconductor elements and the sets of diodes 31a to 38a connected in parallel to the respective IGBTs are connected in parallel. Furthermore, eight sets of diodes connected in parallel with the IGBT are mounted by connecting two modules each having four sets of diodes connected in parallel with the IGBT on the substrate 201a and the substrate 202a in parallel. ing.

図１５に、下側のアーム２００ａの実装の概略構成の平面図を示す。ＩＧＢＴ２１ａ〜２４ａの第一電極であるコレクタを銅パターンが形成された基板２０１ａ上に、それぞれの第一電極が銅パターンに接続されるように配置している。ＩＧＢＴ２１ａ〜２４ａの第二電極であるエミッタは、それぞれの第二電極同士をアルミワイヤ配線２０３により銅パターンやダイオードなど、パワー半導体素子以外の部材を介さずに直接接続している。同様に基板２０２ａ上に配置されたＩＧＢＴ２５ａ〜２８ａの第二電極であるエミッタもアルミワイヤ配線２０４によりそれぞれ銅パターンやダイオードなど、パワー半導体素子以外の部材を介さずに接続している。ただし、ＩＧＢＴ２１ａ〜２８ａのうち１個のＩＧＢＴだけに電流センスセルが設けられており、この電流センスセルの第二電極であるエミッタは、別途電流検出部４に接続される。   FIG. 15 is a plan view of a schematic configuration for mounting the lower arm 200a. The collectors which are the first electrodes of the IGBTs 21a to 24a are arranged on the substrate 201a on which the copper pattern is formed so that each first electrode is connected to the copper pattern. The emitters that are the second electrodes of the IGBTs 21 a to 24 a are directly connected to each other by the aluminum wire wiring 203 without using a member other than the power semiconductor element such as a copper pattern or a diode. Similarly, the emitters that are the second electrodes of the IGBTs 25a to 28a arranged on the substrate 202a are also connected by the aluminum wire wiring 204 without any member other than the power semiconductor element such as a copper pattern or a diode. However, the current sense cell is provided in only one IGBT among the IGBTs 21a to 28a, and the emitter which is the second electrode of the current sense cell is connected to the current detection unit 4 separately.

アルミワイヤ配線２０３、２０４が無い場合、エミッタ間のインピーダンスは、端子台Ｎ１や端子台Ｎ２を介する、破線で示す経路のインピーダンスとなる。これに対し、エミッタ間を直接アルミワイヤ配線で接続することにより、エミッタ間のインピーダンスは、アルミワイヤ配線２０３や２０４による短い経路のインピーダンスとなり、インピーダンスが小さくなる。これにより、複数接続されているＩＧＢＴのエミッタ電位が全て等しくなるため、それぞれのＩＧＢＴのゲート電圧も等しく低減することができる。例えば、ワイドバンドギャップ半導体のようにスレッシホールド電圧の低いパワー半導体素子に対し、エミッタ間をアルミワイヤ配線で接続しなければそれぞれのエミッタ電位に差が生じるため、一部のパワー半導体素子のゲート電圧がスレッシホールド電圧以上、一部のパワー半導体素子のゲート電圧がスレッシホールド電圧以下という状態が生じ、ゲート電圧の高いパワー半導体素子に過電流が流れ続けてしまう。また、左右の端子台Ｎ１と端子台Ｎ２を短いアルミワイヤ配線２０５で接続することにより、左右の基板２０１ａおよび２０２ａのＩＧＢＴのエミッタ間のインピーダンスが小さくなり、同様の効果が得られる。   When there is no aluminum wire wiring 203, 204, the impedance between the emitters is the impedance of the path indicated by the broken line through the terminal block N1 and the terminal block N2. On the other hand, by connecting the emitters directly with the aluminum wire wiring, the impedance between the emitters becomes an impedance of a short path by the aluminum wire wirings 203 and 204, and the impedance is reduced. Thereby, since the emitter potentials of the plurality of connected IGBTs are all equal, the gate voltage of each IGBT can be reduced equally. For example, a power semiconductor element with a low threshold voltage, such as a wide band gap semiconductor, has a difference in emitter potential unless the emitters are connected by an aluminum wire wiring. A state occurs in which the voltage is equal to or higher than the threshold voltage and the gate voltage of some power semiconductor elements is equal to or lower than the threshold voltage, and an overcurrent continues to flow through the power semiconductor element having a high gate voltage. Further, by connecting the left and right terminal blocks N1 and N2 with the short aluminum wire wiring 205, the impedance between the IGBT emitters of the left and right substrates 201a and 202a is reduced, and the same effect is obtained.

特に、本発明のゲート電流制御回路５を、ワイドバンドギャップ半導体のようにスレッシホールド電圧の低いパワー半導体素子に対し設けた場合、以上のような実装構造によれば、確実に並列に接続したすべてのパワー半導体素子に過電流保護動作を行うことができるという効果を奏する。また、以上では、パワー半導体素子としてＩＧＢＴを例にとって説明したが、パワー半導体素子がＭＯＳＦＥＴでも同様である。   In particular, when the gate current control circuit 5 of the present invention is provided for a power semiconductor element having a low threshold voltage such as a wide band gap semiconductor, the mounting structure as described above ensures reliable connection in parallel. There is an effect that an overcurrent protection operation can be performed on all power semiconductor elements. In the above description, the IGBT is described as an example of the power semiconductor element, but the same applies to the case where the power semiconductor element is a MOSFET.

なお、本発明は、その発明の範囲内において、各実施の形態を組み合わせたり、各実施の形態を適宜、変形、省略したりすることが可能である。   It should be noted that the present invention can be combined with each other within the scope of the invention, or can be appropriately modified or omitted from each embodiment.

１：パワー半導体素子、２：主セル、３：電流センスセル、
４：電流検出部、５：過電流制限回路、６：駆動回路、
８：過電流保護回路、９：過電流検出回路、１０：フィルタ回路、
１３：トランジスタ、１４：ゲート電流制御回路、２０１ａ、
２０２ａ：基板1: power semiconductor element, 2: main cell, 3: current sense cell,
4: current detection unit, 5: overcurrent limiting circuit, 6: drive circuit,
8: Overcurrent protection circuit, 9: Overcurrent detection circuit, 10: Filter circuit,
13: transistor, 14: gate current control circuit, 201a,
202a: substrate

Claims (7)

第一電極と第二電極の間に流れる主電流をゲートに印加される電圧により制御するパワー半導体素子が複数並列接続され、この並列接続された複数のパワー半導体素子のうち一個のパワー半導体素子が主セルと電流センスセルを備え、前記主セルの電流を前記電流センスセルの出力電流により検出して、前記一個のパワー半導体素子の電流が過電流となった場合に前記複数のパワー半導体素子を保護するための過電流保護回路を備えた半導体装置において、
前記過電流保護回路は、前記電流センスセルの出力電流を検出する電流検出部と、この電流検出部の出力信号に応じて前記複数のパワー半導体素子のゲートに印加される電圧を低下させる過電流制限回路と、前記複数のパワー半導体素子のゲートに印加される電圧を制御して前記複数のパワー半導体素子のオンオフを制御するための駆動回路と、前記複数のパワー半導体素子のゲートと前記駆動回路との間に接続され、出力電流が所定の一定値となるように制御するゲート電流制御回路とを備え、
前記複数のパワー半導体素子を、銅パターンが形成された１枚の基板上に、前記複数のパワー半導体素子のそれぞれの第一電極が前記銅パターンに接続されるように配置し、前記複数のパワー半導体素子の、前記電流センスセルの第二電極以外のそれぞれの第二電極同士を前記複数のパワー半導体素子以外の部材を介さずに直接接続するワイヤ配線により電気接続したことを特徴とする半導体装置。 A plurality of power semiconductor elements that control the main current flowing between the first electrode and the second electrode by a voltage applied to the gate are connected in parallel, and one power semiconductor element of the plurality of power semiconductor elements connected in parallel is A main cell and a current sense cell, wherein the current of the main cell is detected by an output current of the current sense cell, and the plurality of power semiconductor elements are protected when the current of the one power semiconductor element becomes an overcurrent In a semiconductor device provided with an overcurrent protection circuit for
The overcurrent protection circuit includes a current detector that detects an output current of the current sense cell, and an overcurrent limit that reduces a voltage applied to the gates of the plurality of power semiconductor elements in accordance with an output signal of the current detector. A drive circuit for controlling on / off of the plurality of power semiconductor elements by controlling a voltage applied to the gates of the plurality of power semiconductor elements; a gate of the plurality of power semiconductor elements; and the drive circuit; And a gate current control circuit that controls the output current to be a predetermined constant value .
The plurality of power semiconductor elements are disposed on a single substrate on which a copper pattern is formed so that the first electrodes of the plurality of power semiconductor elements are connected to the copper pattern, and the plurality of power semiconductor elements are arranged. A semiconductor device characterized in that each second electrode of the semiconductor element other than the second electrode of the current sense cell is electrically connected by a wire wiring that directly connects the second electrodes other than the plurality of power semiconductor elements . 前記所定の一定値は、前記複数のパワー半導体素子の正常動作時のゲート電流の値の９０％から１１０％の範囲の値であることを特徴とする請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the predetermined constant value is a value in a range of 90% to 110% of a gate current value during normal operation of the plurality of power semiconductor elements. 前記過電流制限回路は、前記複数のパワー半導体素子のゲートと前記ゲート電流制御回路の出力との接続点にコレクタが接続され、前記主セルの前記第二電極にエミッタが接続され、前記電流検出部の出力がベースに接続されたトランジスタにより構成されたことを特徴とする請求項１に記載の半導体装置。 The overcurrent limiting circuit has a collector connected to a connection point between a gate of the plurality of power semiconductor elements and an output of the gate current control circuit, an emitter connected to the second electrode of the main cell, and the current detection 2. The semiconductor device according to claim 1, wherein the output of the part is constituted by a transistor connected to a base. 前記過電流制限回路の前記トランジスタのコレクタと前記複数のパワー半導体素子のゲートとの間には、保護用の素子が挿入され、この保護用の素子による電圧降下が２Ｖ以下
であることを特徴とする請求項３に記載の半導体装置。 A protective element is inserted between the collector of the transistor of the overcurrent limiting circuit and the gates of the plurality of power semiconductor elements, and a voltage drop due to the protective element is 2 V or less. The semiconductor device according to claim 3. 前記電流検出部と前記過電流制限回路との間に、前記電流検出部が前記一個のパワー半導体素子の過電流を検出した場合、その検出状態を所定時間保持するラッチ回路を備えたことを特徴とする請求項１から４のいずれか１項に記載の半導体装置。 A latch circuit is provided between the current detection unit and the overcurrent limiting circuit to hold the detection state for a predetermined time when the current detection unit detects an overcurrent of the one power semiconductor element. The semiconductor device according to any one of claims 1 to 4. 前記複数のパワー半導体素子がワイドバンドギャップ半導体により形成されていることを特徴とする請求項１から５のいずれか１項に記載の半導体装置。 The semiconductor device according to any one of claims 1-5, wherein the plurality of power semiconductor elements are formed by a wide band gap semiconductor. 前記ワイドバンドギャップ半導体は、炭化珪素、窒化ガリウム系材料、ダイヤモンドのいずれかの半導体であることを特徴とする請求項６に記載の半導体装置。 The semiconductor device according to claim 6 , wherein the wide band gap semiconductor is one of silicon carbide, a gallium nitride-based material, and diamond.
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