JP2009060358A - Overcurrent protection circuit and power conversion system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the following problem: fail processing is performed erroneously due to the influence of noise in an overcurrent protection circuit which, when current flowing in a switching element SW is determined to be a threshold or more based on detection of an electrical state amount (sense voltage) correlated with the above current, generates a fail signal indicating that the overcurrent flows in the switching element SW. <P>SOLUTION: When a sense voltage keeps a first threshold voltage vref1 or higher for a specified time Delay1 or longer, an output signal of an OR circuit 47 is becomes logic "H", thereby the fail signal FL is output from a fail signal generating circuit 53. When a driving signal of the switching element SW is OFF, however, since an output signal of an AND circuit 52 becomes logic "L", even when the sense voltage keeps the first threshold voltage vref1 or higher for the specific time Delay1 or longer, the fail signal FL is prohibited from being generated. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  In the present invention, when it is determined that the current flowing between the input / output terminals is greater than or equal to a threshold based on the detected value of the electrical state quantity correlated with the current flowing between the input / output terminals of the power switching element, the power The present invention relates to an overcurrent protection circuit that generates a fail signal indicating that an excessive current flows in a switching element, and a power conversion system including the same.

  An example of this type of protection circuit is found in Patent Document 1 below. Here, as shown in FIG. 5, when a drive signal for driving the switching element SW is output from the microcomputer (microcomputer 100), the drive signal is sent via the latch circuit 102 to the drive circuit 104 and the turn-off circuit 106. Is taken in. In the drive circuit 104, a predetermined voltage is applied to the gate to turn on the switching element SW. On the other hand, in the turn-off circuit 106, the charge charged in the gate is discharged in order to turn off the switching element SW.

  The switching element SW is provided with a sense terminal ST. The sense terminal ST correlates with the current flowing between the input / output terminals of the switching element SW and outputs a current that is slightly smaller than the current flowing between the input / output terminals. The sense terminal ST is grounded via the resistor 108, and the amount of voltage drop (sense voltage) of the resistor 108 due to the current output from the sense terminal ST has a correlation with the current flowing between the input and output terminals. Are taken into the non-inverting input terminals of the comparators 110 and 112. A first threshold voltage vref1 for determining whether or not an excessive current flows between the input and output terminals of the switching element SW is applied to the inverting input terminal of the comparator 110. Further, the output of the comparator 110 is taken into the delay circuit 114. When the period during which the sense voltage taken into the comparator 110 is equal to or higher than the first threshold voltage vref1 is equal to or longer than the delay time Delay by the delay circuit 114, the fail signal FL is output from the delay circuit 114 to the latch circuit 102 and the microcomputer 100. Is done. Thereby, the switching element SW is turned off.

  On the other hand, a second threshold voltage vref2 for determining whether or not a short-circuit current flows is applied to the inverting input terminal of the comparator 112. Then, the output of the comparator 112 is taken into the latch circuit 116. Accordingly, when the sense voltage taken into the comparator 112 is equal to or higher than the second threshold voltage vref2, the voltage applied to the gate of the switching element SW is reduced by the latch circuit 116.

  FIG. 6 shows the operation of the protection circuit. Specifically, FIG. 6A shows the transition of the sense voltage, FIG. 6B shows the transition of the voltage applied to the gate of the switching element SW, and FIG. 6C shows the failure signal FL. FIG. 6 (d) shows the transition of the drive signal.

As shown in the figure, when the switching element SW is in the ON state, the fail signal FL is output when the period in which the sense voltage is equal to or higher than the first threshold voltage vref1 is equal to or longer than the delay time Delay, and the switching element SW is Forced off. On the other hand, if the sense voltage becomes equal to or higher than the second threshold voltage vref2 when the switching element SW is in the on state, the voltage applied to the gate of the switching element SW is reduced, so that the sense voltage is lowered. However, since the sense voltage does not decrease below the first threshold voltage vref1 depending on this, the fail signal FL is output when the period during which the sense threshold voltage is higher than the first threshold voltage vref1 is longer than the delay time Delay. The element SW is forcibly turned off.
Japanese Patent Laid-Open No. 3-40517

  By the way, as shown in FIG. 6, when the sense voltage rises due to the influence of noise when the switching element SW is off, the fail signal FL is output. For this reason, even when the switching element SW is in an OFF state and no excessive current actually flows, there is a possibility that an abnormal current is processed by the microcomputer or the like if an excessive current flows.

  The present invention has been made in order to solve the above-described problems, and the object of the present invention is to establish a connection between input and output terminals based on detection of an electrical state quantity having a correlation with a current flowing between input and output terminals of a power switching element. When it is determined that the flowing current is equal to or greater than the threshold value, it is preferable to generate a fail signal indicating that an excessive current flows in the power switching element, and to appropriately perform a fail process due to the influence of noise. It is an object of the present invention to provide an overcurrent protection circuit that can be avoided and a power conversion system including the circuit.

  Hereinafter, means for solving the above-described problems and the operation and effects thereof will be described.

  According to the first aspect of the present invention, it is determined that the current flowing between the input / output terminals is equal to or greater than a threshold based on the detected value of the electrical state quantity correlated with the current flowing between the input / output terminals of the power switching element. In the case of an overcurrent protection circuit that generates a fail signal indicating that an excessive current flows in the power switching element, the overcurrent protection circuit includes invalidating means for invalidating the fail signal when the power switching element is in an off state. Features.

  When the switching element is in an OFF state, no excessive current flows between the input / output terminals of the switching element. For this reason, if it is determined that the current flowing between the input and output terminals is greater than or equal to the threshold value based on the detection value even though the switching element is in the OFF state, it is considered to be an erroneous determination due to the influence of noise. . In the above invention, in view of this point, it is possible to suitably avoid the failure process due to the influence of noise by invalidating the fail signal when the switching element is in the OFF state.

  The invention according to claim 2 is the invention according to claim 1, wherein the invalidating means is a prohibiting means for prohibiting the generation of the fail signal itself when the power switching element is in an OFF state. To do.

  In the above-described invention, when the switching element is in the OFF state, it is possible to suitably avoid the failure process due to the influence of noise by prohibiting the generation of the fail signal itself.

  The invention according to claim 3 is the invention according to claim 1 or 2, wherein the power switching element is one of a plurality of switching elements connected in series with each other, and the threshold value is the power connected in series with each other. Including a value for determining that a through-current flows through a plurality of adjacent switching elements among the switching elements and a value smaller than the value, and the switching element is in an on state or an off state Regardless of this, when the detected value is equal to or greater than a value for determining that the through current is flowing, the conduction control terminal of the switching element reduces the current flowing through the input / output terminal of the switching element. Further, it is characterized by further comprising operating means for operating to the side.

  When a through current flows through a plurality of adjacent switching elements, the current value increases rapidly and the maximum value tends to be much larger than when excessive current flows through a single switching element. It is in. For this reason, if the current is limited only when the power switching element is in the ON state, it may be difficult to sufficiently suppress the through current from becoming large enough to reduce the reliability of the switching element. . In the above invention, in view of this point, by providing the operation means, it is possible to suitably avoid a situation in which the reliability of the switching element is lowered due to the through current.

  In the invention according to claim 3, the invalidation means validates the fail signal when the detected value is equal to or larger than a value for determining that the through current is flowing. This may be a feature.

  According to a fourth aspect of the present invention, in the invention according to any one of the first to third aspects, whether or not the power switching element is in an off state is determined based on a drive signal of the power switching element. It is characterized by.

  In the said invention, it can be judged suitably that a power switching element is an OFF state by using a drive signal.

  A fifth aspect of the present invention is the power conversion circuit according to any one of the first to fourth aspects, wherein the power switching element is one of a plurality of switching elements constituting a power conversion circuit. Is shut down based on the fail signal.

  In the above invention, since the power conversion circuit is shut down based on the fail signal, the power conversion circuit is erroneously shut down when the fail signal is generated due to the influence of noise even though the switching element is in the OFF state. It will be. For this reason, inconvenience due to the generation of the fail signal despite the switching element being in the OFF state is great. For this reason, the utility value of the invention according to any one of claims 1 to 4 is particularly high.

  A sixth aspect of the present invention is a power conversion system comprising the overcurrent protection circuit according to the fifth aspect and the power conversion circuit.

  Since the power conversion system includes the overcurrent protection circuit, the power conversion system is a system with high operation reliability.

  Hereinafter, an embodiment in which an overcurrent protection circuit and a power conversion system according to the present invention are applied to a high-voltage system of a hybrid vehicle will be described with reference to the drawings.

  FIG. 1 shows the overall configuration of a motor generator control system according to this embodiment.

  As shown in the figure, an inverter 12 is connected to three phases (U phase, V phase, and W phase) of the motor generator 10. The inverter 12 is a three-phase inverter, and appropriately applies the voltage of the high voltage battery 14 to the three phases of the motor generator 10. Specifically, the inverter 12 is a parallel connection body of the switching elements SW1, SW2, the switching elements SW3, SW4, and the switching elements SW5, SW6 so that each of the three phases and the positive electrode side or the negative electrode side of the high voltage battery 14 are electrically connected. It is configured with. A connection point for connecting switching element SW <b> 1 and switching element SW <b> 2 in series is connected to the U phase of motor generator 10. Further, a connection point for connecting switching element SW3 and switching element SW4 in series is connected to the V phase of motor generator 10. Furthermore, a connection point for connecting switching element SW5 and switching element SW6 in series is connected to the W phase of motor generator 10. Incidentally, these switching elements SW1 to SW6 are constituted by insulated gate bipolar transistors (IGBT) in this embodiment. The inverter 12 includes flywheel diodes D1 to D6 connected in antiparallel to the switching elements SW1 to SW6.

  The switching elements SW <b> 1 to SW <b> 6 are operated by a microcomputer (microcomputer 20) using the low voltage battery 18 as a power source via the driver unit 16. FIG. 2 shows a component related to driving of one of the switching elements SW1 to SW6 (hereinafter referred to as switching element SW) in the driver unit 16.

  As illustrated, the driver unit 16 includes a drive circuit 30 and a protection circuit 40 for driving the switching element SW.

  The drive circuit 30 includes a driver 31 that applies a voltage to the conduction control terminal (gate) of the switching element SW. The driver 31 is a serial connection body of a P-channel transistor 31p and an N-channel transistor 31n. Capacitors 32 are connected to both ends of the driver 31. A drive voltage generation circuit 33 is connected between both electrodes of the capacitor 32. The drive voltage generation circuit 33 generates a voltage to be applied to the driver 31.

  In the drive voltage generation circuit 33, a power source 33b and a capacitor 33c are connected in parallel to the primary side of the transformer 33a, and a switching element 33d that connects and disconnects the transformer 33a, the power source 33b, and the capacitor 33c is provided. ing. The output voltage on the secondary side of the transformer 33a is applied to the capacitor 32 via the diode 33e. According to such a configuration, the output voltage of the drive voltage generation circuit 33 can be variably set by performing ON / OFF operation of the switching element 33d by duty ratio control (duty control), and the voltage applied to the capacitor 32 Can be variably set. Thereby, the voltage applied to the driver 31 can be variably set, and as a result, the voltage applied to the gate of the switching element SW can be variably set.

  The driver 31 is driven in accordance with a drive signal from the microcomputer 20. Specifically, it is driven by a drive signal subjected to power conversion by the photocoupler 60 and the drive IC 35. In the drive IC 35, when the drive signal is an on command, the P-channel transistor 31p is turned on and the N-channel transistor 31n is turned off. On the other hand, when the drive signal is an off command, the P-channel transistor 31p is turned off and the N-channel transistor 31n is turned on. Thus, when the switching element SW is commanded to be turned on, the voltage of the capacitor 32 is applied to the gate G of the switching element SW, and when the switching element SW is commanded to be off, the gate G of the switching element SW is set to the same potential as the emitter E.

  The switching element SW includes a sense terminal ST that outputs a minute current (sense current) having a correlation with a current (collector current) flowing between the collector C and the emitter E. The sense terminal ST is connected to the protection circuit 40.

  The protection circuit 40 includes a resistor (sense resistor 41), and connects the sense terminal ST to the emitter E through the sense resistor 41. The amount of voltage drop (sense voltage) due to the sense resistor 41 is determined according to the sense current. For this reason, the sense voltage is determined by the current (collector current Ic) flowing through the switching element SW.

  An RC filter circuit 42 including a resistor 42a and a capacitor 42b is connected to the sense resistor 41 in parallel. The RC filter circuit 42 is means for removing noise superimposed on the sense voltage immediately after the switching element SW is turned on. The voltage across the sense resistor 41, that is, the sense voltage is applied to the non-inverting input terminals of the overcurrent comparator 43 and the through current comparator 44 via the RC filter circuit 42. Two different threshold voltages vref1 and vref2 are applied to the inverting input terminals of the overcurrent comparator 43 and the through current comparator 44, respectively. Thus, the output signal of the overcurrent comparator 43 becomes logic “H” when the sense voltage becomes equal to or higher than the threshold voltage vref1, and the output signal of the through current comparator 44 indicates that the sense voltage becomes equal to or higher than the threshold voltage vref2. As a result, the logic becomes “H”.

  The output signal of the overcurrent comparator 43 is taken into the timer latch 45. The timer latch 45 outputs a signal of logic “H” when the duration time during which the output signal of the overcurrent comparator 43 becomes logic “H” reaches a specified time Delay 1 (for example, “4 to 5 μs”). On the other hand, the output signal of the through current comparator 44 is taken into the timer latch 46. The timer latch 46 outputs a signal of logic “H” when the duration of the output signal of the through current comparator 44 being logic “H” reaches a specified time Delay2 (<Delay1, eg, “0 to 4 μs”). .

  The OR circuit 47 outputs a logical sum signal based on the output signal of the timer latch 45 and the output signal of the timer latch 46 via the AND circuit 52 described later to the cutoff command circuit 48. The shutoff command circuit 48 operates the drive IC 35 and the soft shutoff circuit 49 when the output signal of the OR circuit 47 is logic “H”. The soft cutoff circuit 49 includes an N-channel transistor that conducts and cuts off between the gate G and the emitter E of the switching element SW via the resistor 50. In the shutoff command circuit 48, when the output signal of the OR circuit 47 is logic “H”, both the P channel transistor 31p and the N channel transistor 31n of the driver 31 are forcibly turned off by operating the drive circuit IC. At the same time, the N-channel transistor of the soft cutoff circuit 49 is turned on. As a result, the switching element SW is switched more slowly than the switching from the on state to the off state by the drive signal. This can be achieved by adjusting the resistance value of the resistor 50 in advance. This setting is made in view of the possibility that the surge voltage may become excessively large if the switching element is switched to the off state at the same speed as that in the normal state when a larger current flows than in the normal state.

  According to such a configuration, when the duration when the sense voltage becomes the threshold voltage vref1 is equal to or longer than the specified time Delay1, or when the duration when the sense voltage becomes the threshold voltage vref2 is equal to or longer than the specified time Delay2, the switching element SW is turned on. It can be forcibly set to an off state (blocking state).

  The through current comparator 44 detects and copes with a through current flowing through the pair of switching elements connected in series when both the switching elements SW of the upper and lower arms of the inverter 12 are turned on. Is for. On the other hand, the overcurrent comparator 43 detects when an excessive current flows through the switching element SW when one switching element SW of the arm of the inverter 12 is on. It is for coping. Here, when the through current flows through the switching element SW, the rate of increase in current is greater than when the through current does not flow. For this reason, when a through current flows, it is desired to detect this quickly and shut off the switching element SW.

  For this reason, the specified time Delay2 for through current is set shorter than the specified time Delay1 for overcurrent. In addition, when a through current flows, the current flowing through the switching element SW is particularly larger than normal. Therefore, the current threshold value Ith2 (corresponding to the threshold voltage vref2) for determining the through current is a pair of switching elements. It is set larger than the current threshold value Ith1 (corresponding to the threshold voltage vref1) when one of the elements SW is in the ON state.

  The output signal of the OR circuit 47 is further taken into the fail signal generation circuit 53. The fail signal generation circuit 53 outputs a fail signal FL when the output signal of the OR circuit 47 becomes logic “H”. Thereby, all the switching elements SW1 to SW6 in the inverter 12 are forcibly turned off, and the inverter 12 is shut down. This is performed by forcibly turning off the photocoupler 60 that captures the drive signals of the switching elements SW1 to SW6. That is, as shown in the drawing, the cathode side of the photodiode of the photocoupler 60 is grounded, and the anode side is connected to the low voltage side power source 62 via the resistor 64 and the switching element 63. Then, a shutdown signal SD is applied to the conduction control terminal (gate) of the switching element 63 by using the fail signal FL as a trigger, whereby the switching element 63 is turned off.

  FIG. 3 shows a circuit configuration for shutting down the inverter 12 using the fail signal FL as a trigger. As shown in the figure, the fail signal FL corresponding to each of the switching elements SW1 to SW6 switches the on state and the off state of the photocoupler 70 corresponding to each of the switching elements SW1 to SW6. Specifically, when the fail signal FL is not output normally, the photocoupler 70 is turned on, and when the fail signal FL is output, the corresponding photocoupler 70 is turned off. The secondary sides of these six photocouplers 70 are connected in series, one end of the series connection body is grounded, and the other end is connected to the inverting input terminal of the comparator 76. A voltage obtained by dividing the voltage of the low-voltage power source 72 by the resistors 74 and 78 is applied to the non-inverting input terminal of the comparator 76. The low voltage power source 72 is further connected to the inverting input terminal via a resistor 80.

  In such a configuration, at the normal time when the fail signal FL is not output, the inverting input terminal of the comparator 76 is grounded, so that the output of the comparator 76 becomes logic “H”. On the other hand, when the fail signal FL is output from at least one of the protection circuits 40 corresponding to each of the switching elements SW1 to SW6, at least one photocoupler 70 is turned off, so that the inversion of the comparator 76 is performed. The voltage applied to the input terminal becomes higher than the voltage applied to the non-inverting input terminal, and the output signal of the comparator 76 is inverted to logic “L”. The output signal of the comparator 76 is output to the microcomputer 20 and to the NAND circuit 82.

  The NAND circuit 82 generates a shutdown signal SD that is a logical product inversion signal of the output signal of the comparator 76 and the shutdown command signal from the microcomputer 20. The shutdown signal SD is applied to the gate of the switching element 63 that shuts off the photocoupler 60 and the low-voltage power source 62. Here, a logic “H” signal is output from the microcomputer 20 in a normal state. Therefore, when the fail signal FL is not output normally, the shutdown signal SD becomes logic “L”, and the switching element 63 is turned on. On the other hand, when the fail signal FL is output, the output signal of the comparator 76 becomes logic “L”, so that the shutdown signal SD becomes logic “H”, and the switching element 63 is turned off. As a result, all of the photocouplers 60 to which the drive signals of the switching elements SW1 to SW6 are input are turned off, and the inverter 12 is shut down.

  The output signal of the comparator 76 is taken into the microcomputer 20 as a fail signal. The microcomputer 20 outputs a shutdown command signal (logic “L” signal) to the NAND circuit 82 and outputs the photocoupler 60 when the output signal of the comparator 76 becomes logic “L” for a predetermined time or more. All drive signals to be output to are turned off.

  According to the above configuration, when it is determined that an overcurrent or a through current flows through at least one of the switching elements SW1 to SW6, the inverter 12 is shut down. For this reason, for example, even if one of the switching elements SW is in an OFF state, the inverter 12 may be shut down even when the sense voltage exceeds the first threshold voltage vref1 due to the influence of noise. .

  Therefore, in the present embodiment, when the switching element SW is in the off state, the generation of the fail signal FL based on the sense voltage being equal to or higher than the threshold voltage vref1 is prohibited. Specifically, when the output signal of the timer latch 45 shown in FIG. 2 is logic “H”, this is output to the OR circuit 47 only when the switching element SW is in the ON state. Specifically, as shown in the figure, the AND circuit 52 outputs a logical product signal of the output signal of the timer latch 45 and the signal obtained by logically inverting the output signal of the photocoupler 60 from the AND circuit 52 to the OR circuit 47. And Here, the inverter 51 is provided in view of the fact that the logical value of the output signal of the photocoupler 60 is obtained by inverting the logical value of the drive signal corresponding to the logical “H” of the ON command of the switching element SW. .

  According to such a configuration, when the switching element SW is in the OFF state, the output of the AND circuit 52 becomes the logic “L”. Therefore, even if the sense voltage becomes equal to or higher than the first threshold voltage vref1, The output of the OR circuit 47 does not become logic “H” unless the threshold voltage vref2 is exceeded.

  FIG. 4 shows the operation of the protection circuit according to the present embodiment. Specifically, FIG. 4A shows the transition of the sense voltage, FIG. 4B shows the transition of the voltage applied to the gate of the switching element SW, and FIG. 4C shows the failure signal FL. FIG. 4D shows the transition of the drive signal.

  As shown in the figure, when the switching element SW is in the ON state, the fail signal FL is output when the period during which the sense voltage is equal to or higher than the first threshold voltage vref1 is equal to or longer than the specified time Delay1, and the switching element SW is Forced off. In addition, when the switching element SW is in the ON state, the fail signal FL is also output when the period during which the sense voltage is equal to or higher than the second threshold voltage vref2 is equal to or longer than the specified time Delay2, and the switching element SW is forcibly set. It is turned off. However, when the switching element SW is in the off state, even if the sense voltage becomes equal to or higher than the first threshold voltage vref1 due to the influence of noise, the fail signal FL is not generated unless it becomes equal to or higher than the second threshold voltage vref2. The inverter 12 is not shut down.

  According to the embodiment described in detail above, the following effects can be obtained.

  (1) When the switching element SW is in the OFF state, the generation of the fail signal FL itself is prohibited. As a result, it is possible to preferably avoid erroneously performing the fail process (shut down of the inverter 12) due to the influence of noise.

  (2) Regardless of whether the switching element SW is in the on state or the off state, when the sense voltage is equal to or higher than the second threshold voltage vref2, the gate charge of the switching element SW is discharged. As described above, when a through current flows, compared to a case where an excessive current flows through a single switching element, the current value increases rapidly and the maximum value tends to be much larger. . For this reason, if the current is limited only when the switching element is in the ON state, it may be difficult to sufficiently suppress the through current from becoming large enough to reduce the reliability of the switching element. In this respect, the setting described above can preferably avoid the through current from lowering the reliability of the switching element.

  (3) Whether the switching element SW is in the OFF state is determined based on the drive signal of the switching element SW. Thereby, it can be suitably determined that the switching element SW is in the OFF state.

  (4) The inverter 12 is shut down based on the fail signal FL. For this reason, inconvenience due to the generation of a fail signal despite the fact that the switching element SW is in the OFF state is great. For this reason, the utility value of the present invention is particularly high.

(Other embodiments)
The above embodiment may be modified as follows.

  In the above embodiment, the logical product signal of the output signal of the timer latch 45 and the drive signal is output to the OR circuit 47 in order to invalidate the fail signal FL when the switching element SW is in the OFF state. For example, a logical product signal of the output signal of the overcurrent comparator 43 and the drive signal may be output to the timer latch 45. The logical product signal of the output signal of the fail signal generation circuit 53 and the drive signal may be used as the fail signal FL.

  The signal for determining that the switching element SW is in the OFF state is not limited to the output signal of the photocoupler 60. For example, the output signal of the driver 31 may be used.

  In the above embodiment, when it is determined that a through current flows (when the sense voltage is determined to be equal to or higher than the second threshold voltage vref2), the fail signal is validated, but the present invention is not limited to this. If a protection function is provided to turn off a switching element in which it is determined that a through current flows when it is determined that a through current flows, the reliability of the switching element SW may be reduced even if the fail signal is disabled. It can be suitably avoided that a current flows.

  -The protection function of the switching element SW is not limited to the function of turning off the switching element SW. For example, the signal output to the conduction control terminal of the switching element SW may be a value that reduces (limits) the current flowing between the input and output terminals of the switching element SW.

  The protection circuit 40 may not include the through current comparator 44 and the timer latch 46. If the dedicated circuit shown in FIG. 3 for turning off all the switching elements SW1 to SW6 of the inverter 12 using the fail signal FL as a trigger is provided, the microcomputer 20 instructs the NAND circuit 86 to shut down based on the fail signal. A function for outputting a signal may not be provided. Alternatively, when an overcurrent flows in any one of the switching elements SW1 to SW6, a circuit for turning off only the switching element in which the overcurrent flows is provided and a fail signal is output to the microcomputer 20. You may do it. Even in these cases, by applying the present invention, it is possible to prevent the inverter 12 from being shut down due to the influence of noise. Furthermore, the inverter 12 is not limited to being shut down based on the fail signal. For example, it may be notified to the outside (user) that an abnormality has occurred based on a fail signal. In the case of a configuration that does not include a dedicated circuit for shutdown shown in FIG. 3 and outputs a fail signal to the microcomputer 20, instead of prohibiting the generation of the fail signal when the switching element SW is in an off state, The fail signal taken into the microcomputer 20 may be invalidated.

  The electrical state quantity having a correlation with the current flowing between the input / output terminals of the switching element SW is not limited to that exemplified in the above embodiment. For example, as seen in Japanese Patent No. 3367699, the voltage between the collector and the emitter may be used.

  The in-vehicle power conversion circuit is not limited to the inverter 12, and may be a DCDC converter that steps down the voltage of the high voltage battery 14 and outputs it to the low voltage battery 18. Furthermore, it is not limited to a protection circuit for an in-vehicle power conversion circuit. In short, in the case of generating a fail signal when an excessive current flows in the power switching element, the present invention is applied to avoid erroneous fail processing due to the influence of noise. It is effective to do.

1 is a system diagram according to one embodiment. The circuit diagram which shows the circuit structure of the overcurrent protection circuit concerning the embodiment. The circuit diagram which shows the circuit structure which shuts down the inverter concerning the embodiment. The time chart which shows the overcurrent protection aspect concerning the embodiment. The circuit diagram which shows the circuit structure of the conventional overcurrent protection circuit. The time chart which shows the said conventional overcurrent protection aspect.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 41 ... Sense resistor, 43 ... Overcurrent comparator, 44 ... Through current comparator, 45, 46 ... Timer latch, 52 ... AND circuit (one embodiment of prohibition means), SW ... Switching element.

Claims (6)

When it is determined that the current flowing between the input / output terminals is greater than or equal to a threshold based on the detected value of the electrical state quantity correlated with the current flowing between the input / output terminals of the power switching element, In the overcurrent protection circuit that generates a fail signal indicating that the current of
An overcurrent protection circuit comprising invalidating means for invalidating the fail signal when the power switching element is in an off state.   2. The overcurrent protection circuit according to claim 1, wherein the invalidating unit is a prohibiting unit that prohibits generation of the fail signal itself when the power switching element is in an OFF state. The power switching element is one of a plurality of switching elements connected in series to each other,
The threshold includes a value for determining that a through current flows through a plurality of adjacent switching elements among the power switching elements connected in series to each other, and a value smaller than the value.
Regardless of whether the switching element is in an on state or an off state, if the detected value is equal to or greater than a value for determining that the through current is flowing, the conduction control terminal of the switching element is 3. The overcurrent protection circuit according to claim 1, further comprising operation means for operating the current flowing through the input / output terminal of the switching element to a side that reduces the current.   4. The overcurrent protection circuit according to claim 1, wherein whether or not the power switching element is in an off state is determined based on a drive signal of the power switching element. The power switching element is one of a plurality of switching elements constituting a power conversion circuit,
The overcurrent protection circuit according to claim 1, wherein the power conversion circuit is shut down based on the fail signal. An overcurrent protection circuit according to claim 5;
A power conversion system comprising the power conversion circuit.

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