JP5940752B1 - Semiconductor memory device - Google Patents

Abstract

To provide a semiconductor memory device in which a nonvolatile semiconductor element or the like is arranged in accordance with restrictions on the shape and size of a substrate and deterioration of performance characteristics thereof can be suppressed. A first main surface of a multilayer wiring board includes a first non-volatile semiconductor element, a second non-volatile semiconductor element, and a controller, and the second main surface includes a first non-volatile semiconductor element. 3 non-volatile semiconductor element 10, fourth non-volatile semiconductor element 10, and connector, and includes a first signal line, a second signal line, a third signal line, and a fourth signal line. A semiconductor memory device is provided. The multilayer wiring board 8 is configured so that the first region provided with the first signal line and the region provided with the third or fourth signal line do not overlap in plan view. [Selection] Figure 9

Description

  Embodiments described herein relate generally to a semiconductor memory device.

  Conventionally, a semiconductor device is used in which a nonvolatile semiconductor memory element such as a NAND flash memory is mounted on a substrate on which a connector is formed. In addition to the nonvolatile semiconductor memory element, the semiconductor device includes a volatile semiconductor memory element, and a controller that controls the nonvolatile semiconductor element and the volatile semiconductor element.

  In such a semiconductor device, the shape and size of the substrate may be restricted in accordance with the usage environment, standards, and the like. In addition, it is required to suppress deterioration of performance characteristics while arranging a nonvolatile semiconductor memory element or the like in accordance with the shape and size of the substrate.

JP 2010-79445 A

  An object of one embodiment of the present invention is to provide a semiconductor memory device in which a nonvolatile semiconductor element or the like is arranged in accordance with restrictions on the shape and size of a substrate, and deterioration of performance characteristics can be suppressed. To do.

  According to one embodiment of the present invention, a multilayer wiring board, a volatile semiconductor element, a first nonvolatile semiconductor element, a second nonvolatile semiconductor element, a third nonvolatile semiconductor element, There is provided a semiconductor memory device including four nonvolatile semiconductor elements, a controller, a connector, a first signal line, a second signal line, a third signal line, and a fourth signal line. The The volatile semiconductor element, the first nonvolatile semiconductor element, and the second nonvolatile semiconductor element are provided on the first main surface of the multilayer wiring board. The third non-volatile semiconductor element and the fourth non-volatile semiconductor element are provided on the second main surface facing in the direction opposite to the first main surface of the multilayer wiring board. The controller is provided on the first main surface of the multilayer wiring board and controls the first to fourth nonvolatile semiconductor elements and volatile semiconductor elements. The connector is provided on the multilayer wiring board. The first signal line connects the connector and the controller. The second signal line connects the controller and the volatile semiconductor element. The third signal line connects the controller and the first and third nonvolatile semiconductor elements. The fourth signal line connects the controller and the second and fourth nonvolatile semiconductor elements. The first nonvolatile semiconductor element and the third nonvolatile semiconductor element are provided at symmetrical positions with respect to the multilayer wiring board. The second nonvolatile semiconductor element and the fourth nonvolatile semiconductor element are provided at symmetrical positions with respect to the multilayer wiring board. The third signal line is connected to the first common signal line, the signal line branched from the first common signal line and connected to the first nonvolatile semiconductor element, and the third nonvolatile semiconductor element. A signal line. The fourth signal line includes a second common signal line, a signal line branched from the second common signal line and connected to the second nonvolatile semiconductor element, and connected to the fourth nonvolatile semiconductor element. A signal line. The multi-layer wiring board is configured such that the first region provided with the first signal line and the region provided with the third or fourth signal line do not overlap in plan view.

FIG. 1 is a block diagram illustrating a configuration example of the semiconductor device according to the first embodiment. FIG. 2 is a plan view showing a schematic configuration of the semiconductor device. FIG. 3 is a plan view showing a detailed configuration of the semiconductor device. FIG. 4 is a perspective view showing a schematic configuration of the resistance element. FIG. 5 is a diagram showing a circuit configuration in the surface layer (first layer) of the substrate. FIG. 6 is a diagram showing a circuit configuration of the back layer (eighth layer) of the substrate. FIG. 7 is a diagram showing the configuration of the wiring that connects the drive control circuit and the NAND memory, and is a conceptual diagram of the layer configuration of the substrate. FIG. 8 is a bottom view illustrating a schematic configuration of the semiconductor device according to the first modification of the first embodiment. FIG. 9 is a diagram showing the configuration of the wiring that connects the drive control circuit and the NAND memory, and is a conceptual diagram of the layer configuration of the substrate. FIG. 10 is a plan view showing a detailed configuration of the semiconductor device according to the second embodiment. FIG. 11 is a cross-sectional view taken along line AA shown in FIG. FIG. 12 is a bottom view illustrating a schematic configuration of the semiconductor device according to the first modification of the second embodiment. 13 is a cross-sectional view taken along line BB shown in FIG. FIG. 14 is a plan view showing a schematic configuration of the semiconductor device according to the third embodiment. FIG. 15 is a diagram illustrating the bottom surface of the NAND memory. FIG. 16 is a bottom view illustrating a schematic configuration of the semiconductor device according to the first modification of the third embodiment. FIG. 17 is a plan view showing a schematic configuration of the semiconductor device according to the fourth embodiment. FIG. 18 is a bottom view illustrating a schematic configuration of the semiconductor device according to the first modification of the fourth embodiment.

  Exemplary embodiments of a semiconductor memory device will be explained below in detail with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments.

(First embodiment)
FIG. 1 is a block diagram illustrating a configuration example of the semiconductor device according to the first embodiment. The semiconductor device 100 is connected to a host device (hereinafter abbreviated as a host) 1 such as a personal computer or a CPU core via a memory connection interface such as a SATA interface (ATA I / F) 2 and functions as an external memory of the host 1. To do. Examples of the host 1 include a CPU of a personal computer, a CPU of an imaging apparatus such as a still camera and a video camera. Further, the semiconductor device 100 can transmit and receive data to and from the debugging device 200 via the communication interface 3 such as an RS232C interface (RS232C I / F).

  A semiconductor device 100 includes a NAND flash memory (hereinafter abbreviated as “NAND memory”) 10 as a nonvolatile semiconductor memory element, a drive control circuit 4 as a controller, and a volatile semiconductor capable of a higher-speed storage operation than the NAND memory 10. It includes a DRAM 20, which is a storage element, a power supply circuit 5, a status display LED 6, and a temperature sensor 7 for detecting the temperature inside the drive. The temperature sensor 7 measures the temperature of the NAND memory 10 directly or indirectly, for example. The drive control circuit 4 limits the writing of information to the NAND memory 10 when the measurement result by the temperature sensor 7 is equal to or higher than a certain temperature, and suppresses further temperature rise.

  The power supply circuit 5 generates a plurality of different internal DC power supply voltages from an external DC power supply supplied from a power supply circuit on the host 1 side, and supplies these internal DC power supply voltages to each circuit in the semiconductor device 100. Further, the power supply circuit 5 detects the rise of the external power supply, generates a power-on reset signal, and supplies it to the drive control circuit 4.

  FIG. 2 is a plan view showing a schematic configuration of the semiconductor device 100. FIG. 3 is a plan view showing a detailed configuration of the semiconductor device 100. The power supply circuit 5, DRAM 20, drive control circuit 4, and NAND memory 10 are mounted on a substrate 8 on which a wiring pattern is formed. The substrate 8 has a substantially rectangular shape in plan view. A connector 9 that is connected to the host 1 and functions as the above-described SATA interface 2 and communication interface 3 is provided on one short side of the substrate 8 having a substantially rectangular shape. The connector 9 functions as a power input unit that supplies power supplied from the host 1 to the power circuit 5. The connector 9 is, for example, an LIF connector. The connector 9 is formed with a slit 9a at a position shifted from the center position along the short direction of the substrate 8 so as to be fitted with a protrusion (not shown) provided on the host 1 side. It has become. This can prevent the semiconductor device 100 from being attached upside down.

  The substrate 8 has a multilayer structure formed by overlapping synthetic resins, and has, for example, an eight-layer structure. Note that the number of layers of the substrate 8 is not limited to eight. On the substrate 8, wiring patterns are formed in various shapes on the surface or inner layer of each layer made of synthetic resin. The power supply circuit 5, DRAM 20, drive control circuit 4, and NAND memory 10 mounted on the substrate 8 are electrically connected to each other through a wiring pattern formed on the substrate 8.

  Next, the arrangement of the power supply circuit 5, DRAM 20, drive control circuit 4, and NAND memory 10 with respect to the substrate 8 will be described. As shown in FIGS. 2 and 3, the power supply circuit 5 and the DRAM 20 are arranged in the vicinity of the connector 9. A drive control circuit 4 is arranged next to the power supply circuit 5 and the DRAM 20. A NAND memory 10 is arranged next to the drive control circuit 4. That is, the DRAM 20, the drive control circuit 4, and the NAND memory 10 are arranged in this order from the connector 9 side along the longitudinal direction of the substrate 8.

  A plurality of NAND memories 10 are mounted on the substrate 8, and the plurality of NAND memories 10 are arranged side by side along the longitudinal direction of the substrate 8. In the first embodiment, four NAND memories 10 are arranged. However, if a plurality of NAND memories 10 are arranged, the number of mounted NAND memories 10 is not limited to this.

  Of the four NAND memories 10, two NAND memories 10 are arranged close to one long side of the substrate 8, and the remaining two NAND memories 10 are arranged close to the other long side of the substrate 8. Is done.

  A resistance element 12 is mounted on the substrate 8. The resistance element 12 is provided in the middle of a wiring pattern (wiring) connecting the drive control circuit 4 and the NAND memory 10, and functions as a resistance to a signal input / output to / from the NAND memory 10. FIG. 4 is a perspective view showing a schematic configuration of the resistance element 12. As shown in FIG. 4, the resistance element 12 is configured by covering a plurality of resistance films 12a provided between the electrodes 12c together with a protective film 12b. One resistance element 12 is provided for one NAND memory 10. Each resistive element 12 is arranged in the vicinity of the NAND memory 10 connected to the resistive element 12.

  Next, the wiring pattern formed on the substrate 8 will be described. As shown in FIG. 3, there is a region S between the power supply circuit 5 and the drive control circuit 4 where almost no electronic components are mounted. A signal line (SATA signal line) for connecting the connector 9 and the drive control circuit 4 is formed in a region S of the substrate 8 as a part of the wiring pattern. In this way, the SATA signal line 14 is formed on the connector 8 side across the drive control circuit 4 on the substrate 8, and the NAND memories 10 are arranged in a row along the longitudinal direction of the substrate 8 on the opposite side. Arranged side by side.

  FIG. 5 is a diagram showing a circuit configuration in the surface layer (first layer) L1 of the substrate 8. As shown in FIG. FIG. 6 is a diagram showing a circuit configuration in the back surface layer (eighth layer) L8 of the substrate 8. As shown in FIG. In the region S of the surface layer L 1 of the substrate 8, the SATA signal line 14 is formed from the position where the drive control circuit 4 is disposed to the vicinity of the connector 9. The SATA signal line 14 penetrates to the back surface layer L8 of the substrate 8 near the connector 9 and reaches the connector 9 by the SATA signal line 14 formed on the back surface layer L8. When it is necessary to form an electrode on the back surface layer L8 side of the substrate 8 at the connector 9 portion, it is necessary to penetrate the SATA signal line 14 to the back surface layer L8 of the substrate 8 in this way.

  In the back surface layer L8 of the substrate 8, most of the region except the SATA signal line 14 is a ground 18. Although illustration is omitted, in the inner layer between the front surface layer L1 and the back surface layer L8 of the substrate 8, almost no wiring pattern other than the SATA signal line 14 is formed in a portion overlapping the SATA signal line 14. That is, almost no wiring pattern other than the SATA signal line 14 is formed in the portion of the substrate 8 that overlaps the region S.

  Further, in the surface layer L1, a part of the SATA signal line 14 is interrupted, but the signal passing through the SATA signal line 14 is relayed by the relay element 16 (see also FIG. 3) mounted on the corresponding part on the substrate 8. Is not a problem. The surface of the substrate 8 is covered with an insulating protective film (not shown), and the insulation of the wiring pattern formed on the surface layer L1 is ensured.

  FIG. 7 is a diagram showing the configuration of the wiring that connects the drive control circuit 4 and the NAND memory 10, and is a conceptual diagram of the layer configuration of the substrate 8. In FIG. 7, a part of the layer structure of the substrate 8 is omitted for simplification of the drawing.

  As shown in FIG. 7, the wiring that connects the drive control circuit 4 and the resistance element 12 is connected to the drive control circuit 4 by the surface layer L <b> 1 of the substrate 8, and is drawn into the inner layer of the substrate 8 by the via hole 21. Then, the wiring is routed through the inner layer of the substrate 8, is again drawn out to the surface layer L 1 of the substrate 8 by the via hole 22, and is connected to the resistance element 12.

  Further, the wiring connecting the resistance element 12 and the NAND memory 10 is connected to the resistance element 12 by the surface layer L 1 of the substrate 8 and is drawn into the inner layer of the substrate 8 by the via hole 23. Then, the wiring is routed through the inner layer of the substrate 8 and is again drawn out to the surface layer L 1 of the substrate 8 by the via hole 24 and connected to the NAND memory 10.

  As described above, since the resistance element 12 is disposed in the vicinity of the NAND memory 10, the wiring that connects the resistance element 12 and the NAND memory 10 is more than the wiring that connects the drive control circuit 4 and the resistance element 12. Shorter.

  Here, since a plurality of NAND memories 10 are provided in the semiconductor device 100, a plurality of wirings for connecting the resistance element 12 and the NAND memory 10 are also formed on the substrate 8. Since the resistance element 12 is disposed in the vicinity of the NAND memory 10, variations in length among a plurality of wirings connecting the resistance element 12 and the NAND memory 10 can be suppressed.

  As described above, by disposing the power supply circuit 5, the drive control circuit 4, the DRAM 20, the NAND memory 10, and the SATA signal line 14, each of these elements is appropriately arranged on the substrate 8 that has a substantially rectangular shape in plan view. Can be arranged.

  Further, since the power supply circuit 5 is disposed in the vicinity of the connector 9 and away from the SATA signal line 14, it becomes difficult for other elements and the SATA signal line 14 to pick up noise generated from the power supply circuit 5, and the semiconductor device The stability of the operation of 100 can be improved.

  Further, since the DRAM 20 is arranged at a position avoiding the SATA signal line 14, it becomes difficult for the SATA signal line 14 to pick up noise generated from the DRAM 20, and the operation stability of the semiconductor device 100 can be improved.

  In general, the DRAM 20 is preferably arranged in the vicinity of the drive control circuit 4. In the first embodiment, since the DRAM 20 is arranged in the vicinity of the drive control circuit 4, it is possible to suppress deterioration in performance characteristics of the semiconductor device 100.

  Of the four NAND memories 10, two NAND memories 10 are arranged close to one long side of the substrate 8, and the remaining two NAND memories 10 are arranged close to the other long side of the substrate 8. Is done. With this configuration, the wiring pattern can be prevented from being biased to one side of the substrate 8, and the wiring pattern can be formed in a well-balanced manner.

  In addition, since the resistive element 12 is disposed in the vicinity of the NAND memory 10, variations in the lengths of the wirings connecting the resistive element 12 and the NAND memory 10 can be suppressed, so that deterioration in performance characteristics of the semiconductor device 100 can be suppressed. be able to.

  In addition, in the back surface layer L8 of the substrate 8, most of the region except the SATA signal line 14 is the ground 18. Therefore, for example, when the semiconductor device 100 is attached to the host 1, the device on the host 1 side is the semiconductor device 100. In this case, it is possible to suppress the influence of noise from the device from affecting the wiring pattern of the semiconductor device 100 and each element such as the NAND memory 10. Similarly, it becomes difficult for the device on the host 1 side to pick up the influence of noise from the wiring pattern and each element of the semiconductor device 100.

  Further, when it is necessary to form an electrode on the back layer side of the substrate 8 at the connector 9 portion as in the present embodiment, the SATA signal line 14 is penetrated to the back layer L8 of the substrate 8 in the vicinity of the connector 9. Thus, the SATA signal line 14 formed on the back surface layer L8 can be made shorter. Thereby, when the device on the host 1 side exists on the back layer side of the semiconductor device 100, it becomes difficult for the SATA signal line 14 to pick up noise from the device.

  Further, since almost no wiring pattern other than the SATA signal line 14 is formed in the portion of the substrate 8 that overlaps the region S, the impedance management for the SATA signal line 14 can be facilitated.

  In the present embodiment, the substrate 8 having the eight-layer structure is illustrated, but the present invention is not limited to this, and the substrate 8 having a different number of layers may be used.

  FIG. 8 is a bottom view showing a schematic configuration of the semiconductor device 100 according to Modification 1 of the first embodiment. FIG. 9 is a diagram showing the configuration of the wiring that connects the drive control circuit 4 and the NAND memory 10, and is a conceptual diagram of the layer configuration of the substrate 8. In FIG. 9, a part of the layer structure of the substrate 8 is omitted to simplify the drawing.

  In the first modification, the NAND memory 10 is also mounted on the back layer side of the substrate 8, and the semiconductor device 100 includes eight NAND memories 10. The NAND memory 10 mounted on the back layer side of the substrate 8 is disposed at a position symmetrical to the NAND memory 10 mounted on the surface layer side of the substrate 8.

  The resistance element 12 is not mounted on the back surface layer side of the substrate 8 but only on the front surface layer side. Therefore, the wiring connecting the resistance element 12 and the NAND memory 10 is routed through the inner layer of the substrate 8 and branched by the via hole 24, and is drawn out not only to the surface layer L 1 of the substrate 8 but also to the back surface layer L 8. Then, the NAND memory 10 provided on the surface layer side is connected to the wiring drawn out to the surface layer L1, and the NAND memory 10 provided on the back surface layer side is connected to the wiring drawn out to the back surface layer L8. . That is, two NAND memories 10 are connected to one resistance element 12.

  As described above, by mounting the NAND memory 10 on both surfaces of the substrate 8, the storage capacity of the semiconductor device 100 can be further increased. Further, a plurality of (in this modification, two) NAND memories 10 can be connected to the resistance element 12 by branching the wiring on the way, and the NAND memories 10 having more channels than the drive control circuit 4 have. Can be provided in the semiconductor device 100. In this modification, the drive control circuit 4 has four channels, but eight NAND memories 10 can be provided for the four channels. Of the two NAND memories 10 connected to one wiring, which NAND memory 10 operates depends on whether CE (chip enable) of the NAND memory 10 is active or not. 10 Judgment itself.

(Second Embodiment)
FIG. 10 is a plan view showing a detailed configuration of the semiconductor device according to the second embodiment. FIG. 11 is a cross-sectional view taken along line AA shown in FIG. In addition, about the structure similar to the said embodiment, the same code | symbol is attached | subjected and detailed description is abbreviate | omitted.

  In the second embodiment, all of the four NAND memories 10 included in the semiconductor device 102 are brought closer to one long side of the substrate 8, more specifically, to the long side on the side where the power supply circuit 5 is provided. Are arranged in parallel. Then, by bringing all the NAND memories 10 toward one long side, the resistance elements 12 are collectively arranged in a space vacated on the other long side.

  In general, the NAND memory 10 is often configured higher than other elements mounted on the substrate 8. Therefore, in the region T where the resistive elements 12 are collectively arranged in the region T along the other long side of the substrate 8, as shown in FIG. 11, the semiconductor device 102 is located more than the region U where the NAND memory 10 is arranged. The height can be kept low.

  Therefore, when a part of the region of the semiconductor device 102 must be made lower than the other region due to a requirement such as a standard, the NAND memory 10 is disposed so as to avoid the region, thereby satisfying the requirement. In some cases, the semiconductor device 102 can be obtained. In the present embodiment, the case where the region along the other long side of the substrate 8 must be lower than the other regions is taken as an example. The DRAM 20 and the temperature sensor 7 are also provided in the region T. However, since the DRAM 20 and the temperature sensor 7 are often configured lower than the NAND memory 10, the height of the semiconductor device 102 can be suppressed lower than the region U in the entire region T.

  FIG. 12 is a bottom view illustrating a schematic configuration of the semiconductor device 102 according to the first modification of the second embodiment. 13 is a cross-sectional view taken along line BB shown in FIG. In the first modification, as in the first modification of the first embodiment, the NAND memory 10 is disposed on the back layer side of the substrate 8 and at a position symmetrical to the NAND memory 10 disposed on the front surface layer side. Provided. As a result, the storage capacity of the semiconductor device 102 can be further increased.

  Further, by providing the NAND memory 10 at a position symmetrical to the NAND memory 10 arranged on the surface layer side of the substrate 8, the NAND memory 10 is arranged close to one long side also on the back surface layer side of the substrate 8. Therefore, the height of the semiconductor device 102 in the region T can be suppressed low.

  Further, the configuration and effect of providing the resistance element 12 only on the surface layer side of the substrate 8 and connecting the two NAND memories 10 to one resistance element 12 have been described in the first modification of the first embodiment. It is the same as that.

(Third embodiment)
FIG. 14 is a plan view showing a schematic configuration of the semiconductor device according to the third embodiment. In addition, about the structure similar to the said embodiment, the same code | symbol is attached | subjected and detailed description is abbreviate | omitted. In the present embodiment, two NAND memories 10 are arranged on the connector 9 side with respect to the drive control circuit 4, and two more NAND memories 10 are arranged on the opposite side. That is, a plurality of NAND memories 10 are arranged along the longitudinal direction of the substrate 8 so as to sandwich the drive control circuit 4.

  By arranging the NAND memories 10 in this way, the wiring length of the wiring connecting the NAND memory 10 and the drive control circuit 4 is larger than arranging the four NAND memories 10 on one side of the drive control circuit 4 in parallel. The variation of can be suppressed. For example, in the present embodiment, the ratio of the shortest wiring to the longest wiring among the wirings connecting the NAND memory 10 and the drive control circuit 4 can be suppressed to about twice. On the other hand, when four NAND memories 10 are arranged in parallel on one side of the drive control circuit 4, the ratio of the shortest wiring to the longest wiring is about four times.

  As described above, in the present embodiment, the difference in the optimal driver setting for the NAND memory 10 can be reduced by suppressing the variation in the wiring length. Therefore, the occurrence of data errors can be suppressed and the operation of the semiconductor device 103 can be stabilized.

  The NAND memory 10 provided on the connector 9 side with respect to the drive control circuit 4 is provided above the SATA signal line 14. In this embodiment, since the NAND memory 10 is of the BGA (Ball Grid Array) type, when the SATA signal line 14 is formed in the surface layer L1, the ball formed in the NAND memory 10 is used. It is necessary to avoid the electrode (bump).

  However, as shown in FIG. 15, since many ball-shaped electrodes 25 are provided on the bottom surface of the NAND memory 10, it is difficult to avoid the ball-shaped electrodes 25 and form the SATA signal line 14. Therefore, in the present embodiment, the SATA signal line 14 that connects the connector 9 and the drive control circuit 4 is formed in the inner layer of the substrate 8.

  Further, since the NAND memory 10 is arranged close to one long side of the substrate 8, the height of the semiconductor device 103 can be kept low in a region along the other long side. Further, by disposing the resistance element 12 in the vicinity of the NAND memory 10, it is possible to suppress the deterioration of the performance characteristics of the semiconductor device 103. Note that the number of NAND memories 10 included in the semiconductor device 103 is not limited to four, and may be more than that as long as it is plural.

  FIG. 16 is a bottom view illustrating a schematic configuration of the semiconductor device according to the first modification of the third embodiment. In the first modification, as in the first modification of the first embodiment, the NAND memory 10 is disposed on the back layer side of the substrate 8 and at a position symmetrical to the NAND memory 10 disposed on the front surface layer side. Provided. Thereby, the storage capacity of the semiconductor device 103 can be further increased.

  Further, by providing the NAND memory 10 at a position symmetrical to the NAND memory 10 arranged on the surface layer side of the substrate 8, the NAND memory 10 is arranged close to one long side also on the back surface layer side of the substrate 8. Therefore, the height of the semiconductor device 103 can be kept low in the region along the other long side.

  Further, the configuration and effect of providing the resistance element 12 only on the surface layer side of the substrate 8 and connecting the two NAND memories 10 to one resistance element 12 have been described in the first modification of the first embodiment. It is the same as that.

(Fourth embodiment)
FIG. 17 is a plan view showing a schematic configuration of the semiconductor device according to the fourth embodiment. In addition, about the structure similar to the said embodiment, the same code | symbol is attached | subjected and detailed description is abbreviate | omitted. In the present embodiment, one NAND memory 10 is arranged on the connector 9 side with respect to the drive control circuit 4, and one NAND memory 10 is further arranged on the opposite side. That is, the semiconductor device 104 includes two NAND memories 10.

  When the two NAND memories 10 are arranged so as to sandwich the drive control circuit 4 as in the present embodiment, the lengths of a plurality of wirings connecting the drive control circuit 4 and the NAND memory 10 are made substantially equal. be able to. On the other hand, when two NAND memories 10 are arranged in parallel on one side of the drive control circuit 4, the ratio between the shortest wiring and the longest wiring is about twice.

  Thus, in this embodiment, the optimal driver setting for the NAND memory 10 can be made substantially equal by making the wiring lengths of the plurality of wirings substantially equal. Therefore, the occurrence of data errors can be suppressed and the operation of the semiconductor device 104 can be stabilized.

  The SATA signal line 14 is formed in the inner layer of the substrate 8 as in the third embodiment. Further, since the NAND memory 10 is arranged close to one long side of the substrate 8, the height of the semiconductor device 104 can be kept low in a region along the other long side. Further, by disposing the resistance element 12 in the vicinity of the NAND memory 10, it is possible to suppress the deterioration of the performance characteristics of the semiconductor device 104.

  FIG. 18 is a bottom view illustrating a schematic configuration of the semiconductor device according to the first modification of the fourth embodiment. In the first modification, as in the first modification of the first embodiment, the NAND memory 10 is disposed on the back layer side of the substrate 8 and at a position symmetrical to the NAND memory 10 disposed on the front surface layer side. Provided. Thereby, the storage capacity of the semiconductor device 104 can be further increased.

  Further, by providing the NAND memory 10 at a position symmetrical to the NAND memory 10 arranged on the surface layer side of the substrate 8, the NAND memory 10 is arranged close to one long side also on the back surface layer side of the substrate 8. Therefore, the height of the semiconductor device 104 can be kept low in the region along the other long side.

  Further, the configuration and effect of providing the resistance element 12 only on the surface layer side of the substrate 8 and connecting the two NAND memories 10 to one resistance element 12 have been described in the first modification of the first embodiment. It is the same as that.

  1 host, 2 SATA interface (ATA / IF), 3 communication interface, 4 drive control circuit (controller), 5 power supply circuit, 7 temperature sensor, 8 substrate, 9 connector, 9a slit, 10 NAND memory (NAND flash memory, Nonvolatile semiconductor memory element), 12 resistance element, 12a resistance film, 12b protective film, 12c electrode, 14 SATA signal line (signal line), 15 via hole, 18 ground, 20 DRAM (volatile semiconductor memory element), 21, 22 , 23, 24 Via hole, 25 Ball electrode, 100, 102, 103, 104 Semiconductor device, 200 Debugging equipment, S, T, U region.

Claims (24)

A multilayer wiring board;
A volatile semiconductor element provided on the first main surface of the multilayer wiring board;
A first nonvolatile semiconductor element provided on the first main surface of the multilayer wiring board;
A second nonvolatile semiconductor element provided on the first main surface of the multilayer wiring board;
A third non-volatile semiconductor element provided on a second main surface of the multilayer wiring board facing away from the first main surface;
A fourth nonvolatile semiconductor element provided on the second main surface of the multilayer wiring board;
A controller for controlling the four nonvolatile semiconductor elements and the volatile semiconductor elements provided on the first main surface of the multilayer wiring board;
A connector provided on the multilayer wiring board;
A first signal line connecting the connector and the controller;
A second signal line connecting the controller and the volatile semiconductor element;
A third signal line connecting the controller and the first and third nonvolatile semiconductor elements;
A fourth signal line connecting the controller and the second and fourth nonvolatile semiconductor elements;
A semiconductor memory device comprising:
The first nonvolatile semiconductor element and the third nonvolatile semiconductor element are provided at symmetrical positions with respect to the multilayer wiring board,
The second nonvolatile semiconductor element and the fourth nonvolatile semiconductor element are provided at symmetrical positions with respect to the multilayer wiring board,
The third signal line includes a first common signal line, a signal line branched from the first common signal line and connected to the first nonvolatile semiconductor element, and the third nonvolatile line. A signal line connected to the semiconductor element,
The fourth signal line includes a second common signal line, a signal line branched from the second common signal line and connected to the second nonvolatile semiconductor element, and the fourth nonvolatile line. A signal line connected to the semiconductor element,
The multilayer wiring board is a semiconductor configured such that the first region provided with the first signal line and the region provided with the third or fourth signal line do not overlap in a plan view. Memory device.   2. The semiconductor memory device according to claim 1, wherein the multilayer wiring board is configured such that the first region and the region provided with the second signal line do not overlap in a plan view.   The first and third nonvolatile semiconductor elements connected to the third signal line are configured to select which nonvolatile semiconductor element operates based on whether or not chip enable is active. 3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is provided.   A first resistor provided in the middle of the first common signal line and functioning as a resistance to a signal between the controller and the first or third nonvolatile semiconductor element; and the second common signal line. And a second resistor that functions as a resistor for a signal between the controller and the second or fourth nonvolatile semiconductor element. 5. The semiconductor memory device described in 1.   The first common signal line and the first resistor are connected by a layer formed on the first main surface of the multilayer wiring board, and the second common signal line and the second resistor are connected to the multilayer wiring board. The semiconductor memory device according to claim 4, wherein the semiconductor memory devices are connected by a layer formed on the first main surface. A power circuit provided on the first main surface;
The power supply circuit is configured to generate an internal voltage based on power supplied from the outside via the connector and supply the generated internal voltage to the first to fourth nonvolatile semiconductor elements. The semiconductor memory device according to claim 1.   The semiconductor memory device according to claim 6, wherein the connector is connectable to a host, and supplies power supplied from the host to the power supply circuit. The connector is provided at one end of the multilayer wiring board,
8. The semiconductor memory according to claim 1, wherein the first to second nonvolatile semiconductor elements are provided on a side opposite to the connector when viewed from the position of the controller in a plan view. apparatus.   The semiconductor memory device according to claim 8, wherein the volatile semiconductor element is provided on the same side as the connector when viewed from a position of the controller in a plan view. A fifth nonvolatile semiconductor element and a sixth nonvolatile semiconductor element provided on the first main surface;
Along the first long side of the multilayer wiring board, the controller, the first nonvolatile semiconductor element, the second nonvolatile semiconductor element, the fifth nonvolatile semiconductor element, and the sixth nonvolatile semiconductor element The semiconductor memory device according to claim 1, which is arranged in the order of semiconductor elements.   The semiconductor memory device according to claim 1, wherein the connector further includes an electrode provided on the second main surface side. The multilayer wiring board is provided between a first layer formed on the first main surface, a second layer formed on the second main surface, and the first layer and the second layer. A plurality of third layers formed, and
The first signal line is connected to the controller and passes through the first layer, the signal line that passes through the plurality of third layers and reaches the second layer, and the second layer. The semiconductor memory device according to claim 11, further comprising: a signal line connected to the electrode.   Each of the first to second nonvolatile semiconductor elements has a first surface facing the first main surface, and each of the first to second nonvolatile semiconductor elements is formed on the first surface. The semiconductor memory device according to claim 1, further comprising a ball-shaped electrode.   The semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor element is a NAND flash memory. A first signal layer having a first side and a second side perpendicular to the first side and having a wiring pattern formed on the first main surface, and a second wiring pattern formed on the second main surface A multilayer wiring board further comprising a second signal layer formed and an internal signal layer on which a wiring pattern is formed, and a connector for connecting to an external device on the first side;
A first nonvolatile semiconductor memory mounted on the first signal layer;
A second non-volatile semiconductor memory mounted on the second signal layer;
A first resistance element mounted on the first signal layer;
A volatile memory mounted on the multilayer wiring board;
A controller mounted on the multilayer wiring board for controlling the volatile memory and the first and second nonvolatile semiconductor memories;
A first signal line connecting the controller and the first resistance element;
A second signal line connecting the first resistance element and the first nonvolatile semiconductor memory;
A semiconductor memory device comprising a third signal line branched from the second signal line and connected to the second nonvolatile semiconductor memory,
The first nonvolatile semiconductor memory and the second nonvolatile semiconductor memory are arranged symmetrically with respect to the multilayer wiring board,
The second signal line connects the first part formed in the first signal layer, the second part formed in the internal signal layer, and the first part and the second part. A third portion extending in a direction substantially perpendicular to the first main surface, and a second portion substantially perpendicular to the first main surface for connecting the second portion and the first nonvolatile semiconductor memory. A fourth portion extending in the direction,
The third signal line includes a fifth portion branched from the second portion and extending in a direction substantially perpendicular to the first main surface to connect to the second nonvolatile semiconductor memory. A semiconductor memory device.   The semiconductor memory device according to claim 15, wherein the connector is provided on a first short side of the multilayer wiring board.   17. The semiconductor memory device according to claim 15, wherein the first and second nonvolatile semiconductor memories are provided on a side opposite to the connector as viewed from a position of an area where the controller is provided in a plan view. .   The controller can communicate with a first external device according to a first interface standard via the connector and can communicate with a second external device according to a second interface standard via the connector. The semiconductor memory device according to claim 15.   The semiconductor memory device according to claim 18, wherein the first interface standard is a SATA interface standard.   The semiconductor memory device according to claim 15, wherein the first resistance element is mounted in the vicinity of the first nonvolatile semiconductor memory. A third nonvolatile semiconductor memory mounted on the first signal layer;
A fourth nonvolatile semiconductor memory mounted on the second signal layer;
A second resistance element mounted on the first signal layer;
A fourth signal line connecting the controller and the second resistance element;
A fifth signal line connecting the second resistance element and the third nonvolatile semiconductor memory;
A sixth signal line branched from the fifth signal line and connected to the fourth nonvolatile semiconductor memory,
The third nonvolatile semiconductor memory and the fourth nonvolatile semiconductor memory are arranged symmetrically with respect to the multilayer wiring board,
The fifth signal line includes a sixth portion formed in the first signal layer, a seventh portion formed in the internal signal layer, the sixth portion, and the seventh portion. An eighth portion extending in a direction substantially perpendicular to the first main surface to connect the first main surface, and the first main surface to connect the seventh portion and the first nonvolatile semiconductor memory. A ninth portion extending in a substantially vertical direction,
The sixth signal line includes a tenth portion branched from the seventh portion and extending in a direction substantially perpendicular to the first main surface to connect to the fourth nonvolatile semiconductor memory. The semiconductor memory device according to claim 15. Further comprising a power circuit mounted on the multilayer wiring board,
The power supply circuit is configured to generate an internal voltage based on power supplied from the outside via the connector and supply the generated internal voltage to the first and second nonvolatile semiconductor memories. The semiconductor memory device according to any one of claims 15 to 21.   The semiconductor memory device according to any one of claims 15 to 22, wherein the controller and the volatile semiconductor memory are provided in the first signal layer.   The first signal line is formed in a signal layer different from an eleventh portion formed in the first signal layer and a signal layer in which the second portion of the internal signal layers is formed. 16. A twelfth portion, a thirteenth portion connecting the eleventh portion and the twelfth portion, and a fourteenth portion connecting the twelfth portion and the controller. 24. The semiconductor memory device according to claim 23.

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