JP6672522B2 - Semiconductor storage device - Google Patents

Description

  Embodiments of the present invention relate to a semiconductor memory device.

  Conventionally, a semiconductor device in which a nonvolatile semiconductor storage element such as a NAND flash memory is mounted on a substrate on which a connector is formed has been used. Further, in addition to the nonvolatile semiconductor memory element, a volatile semiconductor memory element and a controller for controlling the nonvolatile semiconductor element and the volatile semiconductor element are mounted on the semiconductor device.

  In such a semiconductor device, the shape and size of the substrate may be restricted in accordance with the usage environment and the standard. In addition, it is required to suppress deterioration of performance characteristics while arranging a nonvolatile semiconductor memory element or the like according to the shape and size of the substrate.

JP 2010-79445 A

  An object of one embodiment of the present invention is to provide a semiconductor memory device in which a non-volatile semiconductor element or the like can be arranged in accordance with restrictions on the shape and size of a substrate, and deterioration in performance characteristics thereof can be suppressed. I do.

  According to one embodiment of the present invention, a first nonvolatile semiconductor memory, a second nonvolatile semiconductor memory, a volatile semiconductor memory, a circuit element, a controller, a first signal line, A semiconductor memory device including two signal lines, a via hole, a third signal line, a connector, and a substrate is provided. The circuit element includes a first electrode, a second electrode, a film provided between the first electrode and the second electrode, and a film covering the film. The controller controls the first and second nonvolatile semiconductor memories and the volatile semiconductor memory. The first signal line connects the controller and the circuit element. The second signal line connects the circuit element and the first nonvolatile semiconductor memory. The third signal line is branched from the second signal line by a via hole, and is connected to the second nonvolatile semiconductor memory. The connector is provided for connecting to an external device. The substrate has the first and second nonvolatile semiconductor memories, circuit elements, controller, and connector mounted thereon. The substrate also includes a wiring pattern formed on the surface of the substrate, a surface layer on which the first nonvolatile semiconductor memory and the circuit element are mounted, and a wiring pattern formed on the back surface of the substrate. And a plurality of internal wiring layers provided between the surface layer and the back layer and having a wiring pattern. The second signal line is a signal line formed on a first wiring layer which is any one of the plurality of internal wiring layers, and a first signal line formed on any one of the plurality of internal wiring layers. And a signal line formed in a second wiring layer different from the wiring layer. In a plan view, the volatile semiconductor memory is configured to be provided on the same side as the connector when viewed from the first nonvolatile semiconductor memory or the second nonvolatile semiconductor memory.

FIG. 1 is a block diagram illustrating a configuration example of the semiconductor device according to the first embodiment. FIG. 2 is a plan view showing a schematic configuration of the semiconductor device. FIG. 3 is a plan view showing a detailed configuration of the semiconductor device. FIG. 4 is a perspective view showing a schematic configuration of the resistance element. FIG. 5 is a diagram showing a circuit configuration on a surface layer (first layer) of the substrate. FIG. 6 is a diagram showing a circuit configuration on the back surface layer (eighth layer) of the substrate. FIG. 7 is a diagram showing a configuration of a wiring connecting the drive control circuit and the NAND memory, and is a conceptual diagram of a layer configuration of a substrate. FIG. 8 is a bottom view illustrating a schematic configuration of the semiconductor device according to the first modification of the first embodiment. FIG. 9 is a diagram showing a configuration of a wiring connecting the drive control circuit and the NAND memory, and is a conceptual diagram of a layer configuration of a substrate. FIG. 10 is a plan view showing a detailed configuration of the semiconductor device according to the second embodiment. FIG. 11 is a cross-sectional view taken along the line AA shown in FIG. FIG. 12 is a bottom view illustrating a schematic configuration of a semiconductor device according to a first modification of the second embodiment. FIG. 13 is a sectional view taken along the line BB shown in FIG. FIG. 14 is a plan view illustrating a schematic configuration of the semiconductor device according to the third embodiment. FIG. 15 is a diagram showing the bottom surface of the NAND memory. FIG. 16 is a bottom view illustrating a schematic configuration of a semiconductor device according to a first modification of the third embodiment. FIG. 17 is a plan view illustrating a schematic configuration of the semiconductor device according to the fourth embodiment. FIG. 18 is a bottom view illustrating a schematic configuration of a semiconductor device according to a first modification of the fourth embodiment.

  Hereinafter, a semiconductor memory device according to an embodiment will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited by these embodiments.

(First Embodiment)
FIG. 1 is a block diagram illustrating a configuration example of the semiconductor device according to the first embodiment. The semiconductor device 100 is connected to a host device (hereinafter abbreviated as a host) 1 such as a personal computer or a CPU core via a memory connection interface such as a SATA interface (ATA I / F) 2 and functions as an external memory of the host 1. I do. Examples of the host 1 include a CPU of a personal computer and a CPU of an imaging device such as a still camera and a video camera. In addition, the semiconductor device 100 can transmit and receive data to and from the debugging device 200 via the communication interface 3 such as an RS232C interface (RS232C I / F).

  The semiconductor device 100 includes a NAND flash memory (hereinafter, abbreviated as NAND memory) 10 as a nonvolatile semiconductor memory element, a drive control circuit 4 as a controller, and a volatile semiconductor capable of performing a higher-speed storage operation than the NAND memory 10. It includes a DRAM 20, which is a storage element, a power supply circuit 5, an LED 6 for status display, and a temperature sensor 7 for detecting the temperature inside the drive. The temperature sensor 7 measures, for example, the temperature of the NAND memory 10 directly or indirectly. The drive control circuit 4 restricts the writing of information to the NAND memory 10 when the measurement result of the temperature sensor 7 becomes equal to or higher than a certain temperature, and suppresses a further rise in temperature.

  The power supply circuit 5 generates a plurality of different internal DC power supply voltages from an external DC power supply supplied from a power supply circuit on the host 1 side, and supplies these internal DC power supply voltages to each circuit in the semiconductor device 100. The power supply circuit 5 detects the rise of the external power supply, generates a power-on reset signal, and supplies the power-on reset signal to the drive control circuit 4.

  FIG. 2 is a plan view showing a schematic configuration of the semiconductor device 100. FIG. 3 is a plan view showing a detailed configuration of the semiconductor device 100. The power supply circuit 5, the DRAM 20, the drive control circuit 4, and the NAND memory 10 are mounted on a substrate 8 on which a wiring pattern is formed. The substrate 8 has a substantially rectangular shape in plan view. A connector 9 connected to the host 1 and functioning as the above-described SATA interface 2 and communication interface 3 is provided on one short side of the substrate 8 having a substantially rectangular shape. The connector 9 functions as a power input unit that supplies power input from the host 1 to the power circuit 5. The connector 9 is, for example, a LIF connector. The connector 9 has a slit 9a formed at a position deviated from a center position along the lateral direction of the board 8 so that the connector 9 fits with a projection (not shown) provided on the host 1 side. It has become. This can prevent the semiconductor device 100 from being mounted upside down.

  The substrate 8 has a multilayer structure formed by laminating synthetic resins, for example, has an eight-layer structure. The number of layers of the substrate 8 is not limited to eight. On the substrate 8, wiring patterns are formed in various shapes on the surface or the inner layer of each layer made of a synthetic resin. The power supply circuit 5, the DRAM 20, the drive control circuit 4, and the NAND memory 10 mounted on the substrate 8 are electrically connected to each other via a wiring pattern formed on the substrate 8.

  Next, the arrangement of the power supply circuit 5, the DRAM 20, the drive control circuit 4, and the NAND memory 10 with respect to the substrate 8 will be described. As shown in FIGS. 2 and 3, power supply circuit 5 and DRAM 20 are arranged near connector 9. Then, the drive control circuit 4 is arranged next to the power supply circuit 5 and the DRAM 20. Then, the NAND memory 10 is arranged next to the drive control circuit 4. That is, the DRAM 20, the drive control circuit 4, and the NAND memory 10 are arranged in this order from the connector 9 side along the longitudinal direction of the substrate 8.

  Note that a plurality of NAND memories 10 are mounted on the substrate 8, and the plurality of NAND memories 10 are arranged side by side along the longitudinal direction of the substrate 8. In the first embodiment, four NAND memories 10 are arranged. However, if a plurality of NAND memories 10 are arranged, the number of mounted NAND memories 10 is not limited to this.

  Further, of the four NAND memories 10, two NAND memories 10 are arranged close to one long side of the substrate 8, and the remaining two NAND memories 10 are arranged close to the other long side of the substrate 8. Is done.

  In addition, a resistance element 12 is mounted on the substrate 8. The resistance element 12 is provided in the middle of a wiring pattern (wiring) connecting the drive control circuit 4 and the NAND memory 10, and functions as a resistance to signals input to and output from the NAND memory 10. FIG. 4 is a perspective view showing a schematic configuration of the resistance element 12. As shown in FIG. 4, the resistance element 12 is configured such that a plurality of resistance films 12a provided between the electrodes 12c are collectively covered with a protective film 12b. One resistance element 12 is provided for one NAND memory 10. Each resistance element 12 is arranged near the NAND memory 10 connected to the resistance element 12.

  Next, a wiring pattern formed on the substrate 8 will be described. As shown in FIG. 3, there is an area S between the power supply circuit 5 and the drive control circuit 4 where electronic components and the like are hardly mounted. In a region S of the substrate 8, a signal line (SATA signal line) for connecting the connector 9 and the drive control circuit 4 is formed as a part of a wiring pattern. As described above, the SATA signal line 14 is formed on the board 9 on the connector 9 side with the drive control circuit 4 interposed therebetween, and on the opposite side, the NAND memories 10 are arranged in a line along the longitudinal direction of the board 8. They are arranged side by side.

  FIG. 5 is a diagram showing a circuit configuration in a surface layer (first layer) L1 of the substrate 8. FIG. 6 is a diagram showing a circuit configuration in the back surface layer (eighth layer) L8 of the substrate 8. In the region S of the surface layer L1 of the substrate 8, the SATA signal line 14 is formed from the position where the drive control circuit 4 is arranged to the vicinity of the connector 9. Then, the SATA signal line 14 penetrates to the back surface layer L8 of the substrate 8 by the via hole 15 near the connector 9 and reaches the connector 9 by the SATA signal line 14 formed on the back surface layer L8. When it is necessary to form an electrode on the back surface layer L8 side of the substrate 8 in the connector 9 part, it is necessary to penetrate the SATA signal line 14 to the back surface layer L8 of the substrate 8 as described above.

  In the rear surface layer L <b> 8 of the substrate 8, most of the region except the SATA signal line 14 is the ground 18. Although not shown, in the inner layer between the front surface layer L1 and the back surface layer L8 of the substrate 8, a wiring pattern other than the SATA signal lines 14 is hardly formed in a portion overlapping with the SATA signal lines 14. That is, a wiring pattern other than the SATA signal line 14 is hardly formed in a portion overlapping the region S on the substrate 8.

  In the surface layer L1, a part of the SATA signal line 14 is interrupted. However, a signal passing through the SATA signal line 14 is relayed by a relay element 16 (see also FIG. 3) mounted on a corresponding portion on the substrate 8. Is not a problem. Further, the surface of the substrate 8 is covered with an insulating protective film (not shown), and the insulation of the wiring pattern formed on the surface layer L1 is ensured.

  FIG. 7 is a diagram showing a configuration of a wiring connecting the drive control circuit 4 and the NAND memory 10, and is a conceptual diagram of a layer configuration of the substrate 8. In FIG. 7, a part of the layer structure of the substrate 8 is omitted for simplification of the drawing.

  As shown in FIG. 7, the wiring connecting the drive control circuit 4 and the resistance element 12 is connected to the drive control circuit 4 at the surface layer L1 of the substrate 8 and drawn into the inner layer of the substrate 8 through the via hole 21. Then, the wiring is drawn around the inner layer of the substrate 8, drawn out again to the surface layer L 1 of the substrate 8 through the via hole 22, and connected to the resistance element 12.

  The wiring connecting the resistance element 12 and the NAND memory 10 is connected to the resistance element 12 at the surface layer L1 of the substrate 8 and drawn into the inner layer of the substrate 8 through the via hole 23. Then, the wiring is drawn around the inner layer of the substrate 8, drawn out again to the surface layer L 1 of the substrate 8 through the via hole 24, and connected to the NAND memory 10.

  As described above, since the resistance element 12 is arranged near the NAND memory 10, the wiring connecting the resistance element 12 and the NAND memory 10 is better than the wiring connecting the drive control circuit 4 and the resistance element 12. Be shorter.

  Here, since a plurality of NAND memories 10 are provided in the semiconductor device 100, a plurality of wirings for connecting the resistance elements 12 and the NAND memories 10 are also formed on the substrate 8. Since the resistive element 12 is arranged near the NAND memory 10, variation in length between a plurality of wirings connecting the resistive element 12 and the NAND memory 10 can be suppressed.

  As described above, by arranging the power supply circuit 5, the drive control circuit 4, the DRAM 20, the NAND memory 10, and the SATA signal line 14, these elements can be appropriately placed on the substrate 8 having a substantially rectangular shape in plan view. Can be arranged.

  In addition, since the power supply circuit 5 is arranged near the connector 9 and at a position avoiding the SATA signal line 14, noise generated from the power supply circuit 5 is hardly picked up by other elements or the SATA signal line 14, and the semiconductor device 100 can improve the stability of operation.

  Further, by arranging the DRAM 20 at a position avoiding the SATA signal line 14, it becomes difficult for the SATA signal line 14 to pick up noise generated from the DRAM 20, and the operation stability of the semiconductor device 100 can be improved.

  Generally, it is preferable that the DRAM 20 is arranged near the drive control circuit 4. In the first embodiment, since the DRAM 20 is disposed near the drive control circuit 4, the performance characteristics of the semiconductor device 100 can be prevented from deteriorating.

  Further, of the four NAND memories 10, two NAND memories 10 are arranged close to one long side of the substrate 8, and the remaining two NAND memories 10 are arranged close to the other long side of the substrate 8. Is done. With such a configuration, it is possible to suppress the wiring pattern from being biased toward one side of the substrate 8 and to form the wiring pattern in a well-balanced manner.

  In addition, since the resistance element 12 is arranged near the NAND memory 10, variation in the length of the wiring connecting the resistance element 12 and the NAND memory 10 can be suppressed, so that deterioration of the performance characteristics of the semiconductor device 100 can be suppressed. be able to.

  In addition, since most of the area other than the SATA signal line 14 is the ground 18 on the back surface layer L8 of the substrate 8, for example, when the semiconductor device 100 is mounted on the host 1, In this case, the influence of noise from the device can be suppressed from affecting the wiring pattern of the semiconductor device 100 and each element such as the NAND memory 10. Similarly, it becomes difficult for the device on the host 1 side to pick up the influence of noise from the wiring pattern of the semiconductor device 100 and each element.

  Further, when it is necessary to form an electrode on the back surface layer side of the substrate 8 at the connector 9 portion as in the present embodiment, the SATA signal line 14 is made to penetrate to the back surface layer L8 of the substrate 8 near the connector 9. Thus, the SATA signal line 14 formed on the back surface layer L8 can be made shorter. This makes it difficult for the SATA signal line 14 to pick up noise from the device when the host-side device exists on the back layer side of the semiconductor device 100.

  Further, since almost no wiring pattern other than the SATA signal line 14 is formed in a portion overlapping the region S on the substrate 8, it is possible to easily manage the impedance of the SATA signal line 14.

  In the present embodiment, the substrate 8 having an eight-layer structure is described as an example. However, the present invention is not limited to this, and the substrate 8 may have a different number of layers.

  FIG. 8 is a bottom view illustrating a schematic configuration of the semiconductor device 100 according to the first modification of the first embodiment. FIG. 9 is a diagram showing a configuration of a wiring connecting the drive control circuit 4 and the NAND memory 10, and is a conceptual diagram of a layer configuration of the substrate 8. In FIG. 9, a part of the layer structure of the substrate 8 is omitted for simplification of the drawing.

  In the first modification, the NAND memory 10 is also mounted on the back layer side of the substrate 8, and the semiconductor device 100 includes eight NAND memories 10. The NAND memory 10 mounted on the back layer of the substrate 8 is arranged at a position symmetrical to the NAND memory 10 mounted on the front layer of the substrate 8.

  Note that the resistance element 12 is not mounted on the back surface layer side of the substrate 8, but is mounted only on the front surface layer side. Therefore, the wiring connecting the resistance element 12 and the NAND memory 10 is routed through the inner layer of the substrate 8, branched by the via hole 24, and led out to not only the surface layer L 1 of the substrate 8 but also the back layer L 8. The wiring drawn to the surface layer L1 is connected to the NAND memory 10 provided on the front layer, and the wiring drawn to the back layer L8 is connected to the NAND memory 10 provided on the back layer. . That is, two NAND memories 10 are connected to one resistance element 12.

  By mounting the NAND memories 10 on both sides of the substrate 8 in this manner, the storage capacity of the semiconductor device 100 can be further increased. In addition, a plurality of (two in this modification) NAND memories 10 can be connected to the resistance element 12 by branching the wiring in the middle, and the number of the NAND memories 10 equal to or greater than the number of channels of the drive control circuit 4 is increased. Can be provided in the semiconductor device 100. In this modification, the drive control circuit 4 has four channels, but eight NAND memories 10 can be provided for the four channels. It should be noted that which of the two NAND memories 10 connected to one wiring operates depends on whether or not CE (chip enable) of the NAND memory 10 is active. 10 itself decides.

(Second embodiment)
FIG. 10 is a plan view showing a detailed configuration of the semiconductor device according to the second embodiment. FIG. 11 is a cross-sectional view taken along the line AA shown in FIG. In addition, about the structure similar to the said embodiment, the same code | symbol is attached | subjected and detailed description is omitted.

  In the second embodiment, all of the four NAND memories 10 included in the semiconductor device 102 are shifted to one long side of the substrate 8, more specifically, to the long side on which the power supply circuit 5 is provided. Are arranged in parallel. Then, the resistance elements 12 are collectively arranged in a space vacated on the other long side by bringing all the NAND memories 10 toward one long side.

  Generally, the NAND memory 10 is often configured higher than other elements mounted on the substrate 8. Therefore, in the region T along the other long side of the substrate 8 where the resistive elements 12 are collectively arranged, as shown in FIG. 11, the semiconductor device 102 is smaller than the region U where the NAND memory 10 is arranged. The height can be kept low.

  Therefore, when a part of the region of the semiconductor device 102 needs to be lower than the other region due to a requirement such as a standard, the requirement is satisfied by arranging the NAND memory 10 so as to avoid the region. May be obtained in some cases. In the present embodiment, an example is described in which the region along the other long side of substrate 8 must be lower than the other region. Note that the DRAM 20 and the temperature sensor 7 are also provided in the region T. However, since the DRAM 20 and the temperature sensor 7 are also often configured lower than the NAND memory 10, the height of the semiconductor device 102 can be suppressed lower than the region U in the entire region T.

  FIG. 12 is a bottom view illustrating a schematic configuration of the semiconductor device 102 according to the first modification of the second embodiment. FIG. 13 is a sectional view taken along the line BB shown in FIG. In the first modification, similarly to the first modification of the first embodiment, the NAND memory 10 is also placed at a position symmetrical to the NAND memory 10 disposed on the back layer of the substrate 8 and on the front layer. Provided. Thus, the storage capacity of the semiconductor device 102 can be further increased.

  Further, by providing the NAND memory 10 at a position symmetrical to the NAND memory 10 arranged on the surface layer side of the substrate 8, the NAND memory 10 is arranged close to one long side even on the back layer side of the substrate 8. Therefore, the height of the semiconductor device 102 in the region T can be kept low.

  The provision of the resistance element 12 only on the surface layer side of the substrate 8 and the configuration and effect of connecting the two NAND memories 10 to one resistance element 12 have been described in the first modification of the first embodiment. Same as the one.

(Third embodiment)
FIG. 14 is a plan view illustrating a schematic configuration of the semiconductor device according to the third embodiment. In addition, about the structure similar to the said embodiment, the same code | symbol is attached | subjected and detailed description is omitted. In the present embodiment, two NAND memories 10 are arranged on the connector 9 side with respect to the drive control circuit 4, and two more NAND memories 10 are arranged on the opposite side. That is, a plurality of NAND memories 10 are arranged along the longitudinal direction of the substrate 8 so as to sandwich the drive control circuit 4.

  By arranging the NAND memories 10 in this manner, the wiring length of the wiring connecting the NAND memories 10 and the drive control circuit 4 is longer than that of arranging the NAND memories 10 in parallel on one side of the drive control circuit 4. Can be suppressed. For example, in the present embodiment, the ratio of the shortest wire to the longest wire among the wires connecting the NAND memory 10 and the drive control circuit 4 can be suppressed to about twice. On the other hand, if four NAND memories 10 are arranged in parallel on one side of the drive control circuit 4, the ratio of the shortest wiring to the longest wiring is about four times.

  As described above, in the present embodiment, by suppressing the variation in the wiring length, the difference between the optimal driver settings for the NAND memory 10 can be reduced. Therefore, the occurrence of data errors can be suppressed, and the operation of the semiconductor device 103 can be stabilized.

  The NAND memory 10 provided on the connector 9 side with respect to the drive control circuit 4 is provided above the SATA signal line 14. In the present embodiment, since a BGA (Ball Grid Array) type is used for the NAND memory 10, when the SATA signal line 14 is formed on the surface layer L1, the ball formed on the NAND memory 10 is used. It is necessary to avoid the shape electrode (bump).

  However, as shown in FIG. 15, since many ball-shaped electrodes 25 are provided on the bottom surface of the NAND memory 10, it is difficult to form the SATA signal line 14 avoiding the ball-shaped electrodes 25. Therefore, in the present embodiment, the SATA signal line 14 that connects the connector 9 and the drive control circuit 4 is formed on an inner layer of the substrate 8.

  Further, since the NAND memory 10 is arranged close to one long side of the substrate 8, the height of the semiconductor device 103 can be suppressed low in a region along the other long side. Further, by arranging the resistance element 12 near the NAND memory 10, deterioration of the performance characteristics of the semiconductor device 103 can be suppressed. The number of the NAND memories 10 included in the semiconductor device 103 is not limited to four, and may be more than two as long as the number is plural.

  FIG. 16 is a bottom view illustrating a schematic configuration of a semiconductor device according to a first modification of the third embodiment. In the first modification, similarly to the first modification of the first embodiment, the NAND memory 10 is also placed at a position symmetrical to the NAND memory 10 disposed on the back layer of the substrate 8 and on the front layer. Provided. Thus, the storage capacity of the semiconductor device 103 can be further increased.

  Further, by providing the NAND memory 10 at a position symmetrical to the NAND memory 10 arranged on the surface layer side of the substrate 8, the NAND memory 10 is arranged close to one long side even on the back layer side of the substrate 8. Therefore, the height of the semiconductor device 103 can be reduced in a region along the other long side.

  The provision of the resistance element 12 only on the surface layer side of the substrate 8 and the configuration and effect of connecting the two NAND memories 10 to one resistance element 12 have been described in the first modification of the first embodiment. Same as the one.

(Fourth embodiment)
FIG. 17 is a plan view illustrating a schematic configuration of the semiconductor device according to the fourth embodiment. In addition, about the structure similar to the said embodiment, the same code | symbol is attached | subjected and detailed description is omitted. In the present embodiment, one NAND memory 10 is arranged on the connector 9 side with respect to the drive control circuit 4, and another NAND memory 10 is arranged on the opposite side. That is, the semiconductor device 104 includes two NAND memories 10.

  When two NAND memories 10 are arranged so as to sandwich the drive control circuit 4 as in the present embodiment, the lengths of a plurality of wirings connecting the drive control circuit 4 and the NAND memory 10 are made substantially equal. be able to. On the other hand, when two NAND memories 10 are arranged in parallel on one side of the drive control circuit 4, the ratio of the shortest wiring to the longest wiring is about twice.

  As described above, in the present embodiment, by making the wiring lengths of the plurality of wirings substantially equal, the optimum driver setting for the NAND memory 10 can be made substantially equal. Therefore, the occurrence of data errors can be suppressed, and the operation of the semiconductor device 104 can be stabilized.

  Note that the SATA signal line 14 is formed in an inner layer of the substrate 8 as in the third embodiment. Further, since the NAND memory 10 is arranged close to one long side of the substrate 8, the height of the semiconductor device 104 can be suppressed low in a region along the other long side. Further, by arranging the resistance element 12 near the NAND memory 10, deterioration of the performance characteristics of the semiconductor device 104 can be suppressed.

  FIG. 18 is a bottom view illustrating a schematic configuration of a semiconductor device according to a first modification of the fourth embodiment. In the first modification, similarly to the first modification of the first embodiment, the NAND memory 10 is also placed at a position symmetrical to the NAND memory 10 disposed on the back layer of the substrate 8 and on the front layer. Provided. Thus, the storage capacity of the semiconductor device 104 can be further increased.

  Further, by providing the NAND memory 10 at a position symmetrical to the NAND memory 10 arranged on the surface layer side of the substrate 8, the NAND memory 10 is arranged close to one long side even on the back layer side of the substrate 8. Therefore, the height of the semiconductor device 104 can be reduced in a region along the other long side.

  The provision of the resistance element 12 only on the surface layer side of the substrate 8 and the configuration and effect of connecting the two NAND memories 10 to one resistance element 12 have been described in the first modification of the first embodiment. Same as the one.

  1 host, 2 SATA interface (ATA / IF), 3 communication interface, 4 drive control circuit (controller), 5 power supply circuit, 7 temperature sensor, 8 board, 9 connector, 9a slit, 10 NAND memory (NAND flash memory, Nonvolatile semiconductor memory element, 12 resistive element, 12a resistive film, 12b protective film, 12c electrode, 14 SATA signal line (signal line), 15 via hole, 18 ground, 20 DRAM (volatile semiconductor memory element), 21, 22 , 23, 24 via holes, 25 ball electrodes, 100, 102, 103, 104 semiconductor devices, 200 debugging equipment, S, T, U regions.

Claims (15)

A first nonvolatile semiconductor memory;
A second nonvolatile semiconductor memory;
A volatile semiconductor memory;
A circuit element on which a first electrode, a second electrode, a film provided between the first electrode and the second electrode, and a film covering the film are formed;
A controller for controlling the first and second nonvolatile semiconductor memories and the volatile semiconductor memory;
A first signal line connecting the controller and the circuit element;
A second signal line connecting the circuit element and the first nonvolatile semiconductor memory;
Via holes,
A third signal line branched from the second signal line by the via hole and connected to the second nonvolatile semiconductor memory;
A connector for connecting to an external device,
A board on which the first and second nonvolatile semiconductor memories, the circuit element, the controller, and the connector are mounted;
The substrate is
A surface layer including a wiring pattern formed on a surface of the substrate, on which the first nonvolatile semiconductor memory and the circuit element are mounted;
A backside layer including a wiring pattern formed on a backside of the substrate, on which the second nonvolatile semiconductor memory is mounted;
A plurality of internal wiring layers provided between the front surface layer and the back surface layer and having a wiring pattern,
The second signal line is a signal line formed on a first wiring layer that is any one of the plurality of internal wiring layers, and any one of the plurality of internal wiring layers. A signal line formed on a second wiring layer different from the first wiring layer;
In a plan view, a semiconductor memory device configured such that the volatile semiconductor memory is provided on the same side as the connector when viewed from the first nonvolatile semiconductor memory or the second nonvolatile semiconductor memory.   The second signal line extends in a direction substantially perpendicular to the surface of the substrate for connecting the signal line formed on the first wiring layer and the signal line formed on the second wiring layer. 2. The semiconductor memory device according to claim 1, comprising:   The substrate is configured such that a region where a fourth signal line connecting the controller and the connector is provided and a region where the volatile semiconductor memory is provided do not overlap in a plan view. 3. The semiconductor memory device according to claim 1 or 2.   4. The semiconductor memory device according to claim 3, wherein said fourth signal line is a SATA signal line. The connector includes an electrode for connecting to the external device on the back surface of the substrate,
The said 4th signal line is provided with the part connected to the electrode of the said connector through the back surface layer of the said board | substrate, and the part formed in any wiring layer of these internal wiring layers. 5. The semiconductor memory device according to claim 3 or claim 4. The first nonvolatile semiconductor memory includes a plurality of ball-shaped electrodes on a bottom surface,
The first nonvolatile semiconductor memory is connected to the substrate via a plurality of ball-shaped electrodes of the first nonvolatile semiconductor memory;
The second nonvolatile semiconductor memory includes a plurality of ball-shaped electrodes on a bottom surface,
6. The semiconductor according to claim 1, wherein the second nonvolatile semiconductor memory is connected to the substrate via the plurality of ball electrodes of the second nonvolatile semiconductor memory. 7. Storage device. The substrate includes a first side and a second side perpendicular to the first side in a plan view,
The connector is provided on the first side of the board,
7. The semiconductor memory device according to claim 1, wherein the first and second nonvolatile semiconductor memories are provided on a side opposite to the connector when viewed from a position of the controller in a plan view. 8. .   The semiconductor memory device according to claim 1, further comprising a temperature sensor.   The first signal line is for connecting a first portion formed on the front surface layer, a second portion formed on the back surface layer, and the first portion and the second portion. 9. The semiconductor memory device according to claim 1, further comprising: a third portion extending in a direction substantially perpendicular to a surface of said substrate. 10.   The semiconductor memory device according to claim 1, wherein the first nonvolatile semiconductor memory and the second nonvolatile semiconductor memory are arranged symmetrically with respect to the substrate.   11. The semiconductor memory device according to claim 1, wherein the number of layers of the substrate is eight.   2. The method according to claim 1, wherein the first nonvolatile semiconductor memory determines whether to operate on a signal from the second signal line based on a chip enable of the first nonvolatile semiconductor memory. 3. Item 12. The semiconductor memory device according to any one of items 11.   The first and second nonvolatile semiconductor memories are configured to be individually operable depending on whether a chip enable of each of the first and second nonvolatile semiconductor memories is active. The semiconductor memory device according to claim 1.   The power supply circuit further includes a power supply circuit mounted on the substrate, wherein the power supply circuit generates an internal voltage based on a power supply externally supplied through the connector, and generates the internal voltage based on the first and second power supply voltages. 14. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is configured to supply the data to a nonvolatile semiconductor memory.   15. The semiconductor memory device according to claim 14, wherein said connector is connectable to a host, and supplies power supplied from said host to said power supply circuit.