JP7464769B2 - Semiconductor memory device - Google Patents

Description

An embodiment of the present invention relates to a semiconductor memory device.

Conventionally, semiconductor devices have been used in which nonvolatile semiconductor memory elements such as NAND flash memory are mounted on a substrate on which a connector is formed. In addition to the nonvolatile semiconductor memory elements, the semiconductor device also has volatile semiconductor memory elements and a controller that controls the nonvolatile semiconductor elements and the volatile semiconductor elements.

The shape and size of the substrate for such semiconductor devices may be restricted according to the environment in which they are used and the standards they meet. There is a need to arrange non-volatile semiconductor memory elements and other components in accordance with the shape and size of the substrate while suppressing degradation of their performance characteristics.

JP 2010-79445 A

One embodiment of the present invention aims to provide a semiconductor memory device that can arrange non-volatile semiconductor elements and other components in accordance with the limitations of the substrate shape and size while suppressing degradation of their performance characteristics.

According to one embodiment of the present invention, a semiconductor storage device is provided that includes a first nonvolatile semiconductor memory, a second nonvolatile semiconductor memory, a volatile semiconductor memory, a circuit element, a controller, a first signal line, a second signal line, a third signal line, a connector, and a substrate. The circuit element is formed with a first electrode, a second electrode, a film provided between the first electrode and the second electrode, and a film covering the film. The controller controls the first and second nonvolatile semiconductor memories and the volatile semiconductor memory. The first signal line connects the controller and the circuit element. The second signal line connects the circuit element and the first nonvolatile semiconductor memory and includes a first via hole. The third signal line is branched from the second signal line by the first via hole and connected to the second nonvolatile semiconductor memory. The connector is provided for connecting to an external device. The first and second nonvolatile semiconductor memories, the circuit element, the controller, and the connector are mounted on the substrate. The substrate has a surface layer, a back layer, and multiple internal wiring layers. The surface layer has a wiring pattern formed on the surface of the substrate, and the first nonvolatile semiconductor memory and the circuit element are mounted on it. The back layer has a wiring pattern formed on the back surface of the substrate, and the second nonvolatile semiconductor memory is mounted on it. The multiple internal wiring layers are provided between the surface layer and the back layer, and have wiring patterns. The third signal line includes a second via hole. In a plan view, the first region in which the first via hole is provided and the second region in which the second via hole is provided are configured not to overlap.

FIG. 1 is a block diagram illustrating a configuration example of a semiconductor device according to a first embodiment. FIG. 2 is a plan view showing a schematic configuration of the semiconductor device. FIG. 3 is a plan view showing a detailed configuration of the semiconductor device. FIG. 4 is a perspective view showing a schematic configuration of a resistance element. FIG. 5 is a diagram showing a circuit configuration on the surface layer (first layer) of the substrate. FIG. 6 is a diagram showing the circuit configuration on the back surface layer (eighth layer) of the substrate. FIG. 7 is a diagram showing the configuration of wiring connecting the drive control circuit and the NAND memory, and is a conceptual diagram of the layer configuration of the substrate. FIG. 8 is a bottom view showing a schematic configuration of a semiconductor device according to a first modification of the first embodiment. FIG. 9 is a diagram showing the configuration of wiring connecting the drive control circuit and the NAND memory, and is a conceptual diagram of the layer configuration of the substrate. FIG. 10 is a plan view showing a detailed configuration of the semiconductor device according to the second embodiment. FIG. 11 is a cross-sectional view taken along line AA shown in FIG. FIG. 12 is a bottom view showing a schematic configuration of a semiconductor device according to a first modification of the second embodiment. FIG. 13 is a cross-sectional view taken along line BB shown in FIG. FIG. 14 is a plan view showing a schematic configuration of a semiconductor device according to the third embodiment. FIG. 15 is a diagram showing the bottom surface of the NAND memory. FIG. 16 is a bottom view showing a schematic configuration of a semiconductor device according to a first modification of the third embodiment. FIG. 17 is a plan view showing a schematic configuration of a semiconductor device according to the fourth embodiment. FIG. 18 is a bottom view showing a schematic configuration of a semiconductor device according to a first modification of the fourth embodiment.

The semiconductor memory device according to the embodiment will be described in detail below with reference to the attached drawings. Note that the present invention is not limited to these embodiments.

(First embodiment)
1 is a block diagram showing a configuration example of a semiconductor device according to a first embodiment. The semiconductor device 100 is connected to a host device (hereinafter, abbreviated as host) 1 such as a personal computer or a CPU core via a memory connection interface such as a SATA interface (ATA I/F) 2, and functions as an external memory of the host 1. Examples of the host 1 include the CPU of a personal computer, and the CPU of an imaging device such as a still camera or a video camera. The semiconductor device 100 can also transmit and receive data to and from a debugging device 200 via a communication interface 3 such as an RS232C interface (RS232C I/F).

The semiconductor device 100 includes a NAND flash memory (hereafter abbreviated as NAND memory) 10 as a non-volatile semiconductor memory element, a drive control circuit 4 as a controller, a DRAM 20 as a volatile semiconductor memory element capable of faster storage operation than the NAND memory 10, a power supply circuit 5, an LED 6 for displaying a status, and a temperature sensor 7 for detecting the temperature inside the drive. The temperature sensor 7 measures the temperature of the NAND memory 10 directly or indirectly, for example. When the measurement result by the temperature sensor 7 reaches or exceeds a certain temperature, the drive control circuit 4 restricts writing of information to the NAND memory 10, thereby suppressing any further temperature rise.

The power supply circuit 5 generates multiple different internal DC power supply voltages from an external DC power supply supplied from the power supply circuit on the host 1 side, and supplies these internal DC power supply voltages to each circuit in the semiconductor device 100. The power supply circuit 5 also detects the rise of the external power supply, generates a power-on reset signal, and supplies it to the drive control circuit 4.

2 is a plan view showing a schematic configuration of the semiconductor device 100. FIG. 3 is a plan view showing a detailed configuration of the semiconductor device 100. The power supply circuit 5, the DRAM 20, the drive control circuit 4, and the NAND memory 10 are mounted on a substrate 8 on which a wiring pattern is formed. The substrate 8 has a substantially rectangular shape in a plan view. On one short side of the substantially rectangular substrate 8, a connector 9 is provided which is connected to the host 1 and functions as the SATA interface 2 and the communication interface 3 described above. The connector 9 functions as a power input section which supplies the power input from the host 1 to the power supply circuit 5. The connector 9 is, for example, an LIF connector. In addition, a slit 9a is formed in the connector 9 at a position offset from the center position along the short side direction of the substrate 8, and is adapted to fit into a protrusion (not shown) or the like provided on the host 1 side. This makes it possible to prevent the semiconductor device 100 from being attached upside down.

The substrate 8 has a multi-layer structure formed by stacking layers of synthetic resin, for example an eight-layer structure. The number of layers of the substrate 8 is not limited to eight. On the substrate 8, wiring patterns of various shapes are formed on the surface or inner layer of each layer made of synthetic resin. The power supply circuit 5, DRAM 20, drive control circuit 4, and NAND memory 10 mounted on the substrate 8 are electrically connected to each other via the wiring patterns formed on the substrate 8.

Next, the arrangement of the power supply circuit 5, DRAM 20, drive control circuit 4, and NAND memory 10 on the board 8 will be described. As shown in Figures 2 and 3, the power supply circuit 5 and DRAM 20 are arranged near the connector 9. The drive control circuit 4 is then arranged next to the power supply circuit 5 and DRAM 20. The NAND memory 10 is then arranged next to the drive control circuit 4. That is, the DRAM 20, drive control circuit 4, and NAND memory 10 are arranged in this order from the connector 9 side along the longitudinal direction of the board 8.

Note that multiple NAND memories 10 are mounted on the substrate 8, and these multiple NAND memories 10 are arranged side by side along the longitudinal direction of the substrate 8. Note that, in the first embodiment, four NAND memories 10 are arranged, but the number of NAND memories 10 mounted is not limited to this, as long as multiple NAND memories 10 are arranged.

In addition, of the four NAND memories 10, two NAND memories 10 are arranged close to one long side of the substrate 8, and the remaining two NAND memories 10 are arranged close to the other long side of the substrate 8.

Also, a resistive element 12 is mounted on the substrate 8. The resistive element 12 is provided in the middle of the wiring pattern (wiring) that connects the drive control circuit 4 and the NAND memory 10, and functions as a resistor for signals input and output to the NAND memory 10. FIG. 4 is a perspective view showing a schematic configuration of the resistive element 12. As shown in FIG. 4, the resistive element 12 is configured by covering a plurality of resistive films 12a provided between electrodes 12c together with a protective film 12b. One resistive element 12 is provided for one NAND memory 10. Each resistive element 12 is then disposed in the vicinity of the NAND memory 10 to which it is connected.

Next, the wiring pattern formed on the substrate 8 will be described. As shown in FIG. 3, between the power supply circuit 5 and the drive control circuit 4 there is an area S where almost no electronic components are mounted. In the area S of the substrate 8, a signal line (SATA signal line) that connects the connector 9 and the drive control circuit 4 is formed as part of the wiring pattern. In this way, on the substrate 8, the SATA signal line 14 is formed on the connector 9 side across the drive control circuit 4, and on the opposite side, the NAND memories 10 are arranged in a row along the longitudinal direction of the substrate 8.

Figure 5 is a diagram showing the circuit configuration in the surface layer (first layer) L1 of the substrate 8. Figure 6 is a diagram showing the circuit configuration in the back layer (eighth layer) L8 of the substrate 8. In the area S of the surface layer L1 of the substrate 8, the SATA signal line 14 is formed from the position where the drive control circuit 4 is arranged to the vicinity of the connector 9. The SATA signal line 14 penetrates to the back layer L8 of the substrate 8 by a via hole 15 near the connector 9, and reaches the connector 9 through the SATA signal line 14 formed on the back layer L8. If it is necessary to form an electrode on the back layer L8 side of the substrate 8 in the connector 9 area, it is necessary to penetrate the SATA signal line 14 to the back layer L8 of the substrate 8 in this way.

Most of the back surface layer L8 of the substrate 8 is ground 18, except for the SATA signal line 14. Although not shown, in the inner layer between the front surface layer L1 and the back surface layer L8 of the substrate 8, wiring patterns other than the SATA signal line 14 are hardly formed in the portion that overlaps with the SATA signal line 14. In other words, in the portion of the substrate 8 that overlaps with the region S, wiring patterns other than the SATA signal line 14 are hardly formed.

Although a portion of the SATA signal line 14 is disconnected in the surface layer L1, this does not pose a problem because the signal passing through the SATA signal line 14 is relayed by the relay element 16 (see also FIG. 3) mounted in the corresponding portion on the substrate 8. In addition, the surface of the substrate 8 is covered with an insulating protective film (not shown), ensuring the insulation of the wiring pattern formed on the surface layer L1.

Figure 7 shows the wiring configuration connecting the drive control circuit 4 and the NAND memory 10, and is a conceptual diagram of the layer structure of the substrate 8. Note that in Figure 7, some of the layer structure of the substrate 8 is omitted to simplify the drawing.

As shown in FIG. 7, the wiring connecting the drive control circuit 4 and the resistive element 12 is connected to the drive control circuit 4 on the surface layer L1 of the substrate 8, and is drawn into the inner layer of the substrate 8 by a via hole 21. The wiring is then routed through the inner layer of the substrate 8, and is again drawn out to the surface layer L1 of the substrate 8 by a via hole 22, where it is connected to the resistive element 12.

The wiring connecting the resistive element 12 and the NAND memory 10 is connected to the resistive element 12 on the surface layer L1 of the substrate 8 and is drawn into the inner layer of the substrate 8 by a via hole 23. The wiring is then routed through the inner layer of the substrate 8 and again drawn out to the surface layer L1 of the substrate 8 by a via hole 24, and connected to the NAND memory 10.

As described above, since the resistive element 12 is placed near the NAND memory 10, the wiring connecting the resistive element 12 to the NAND memory 10 is shorter than the wiring connecting the drive control circuit 4 to the resistive element 12.

Here, since the semiconductor device 100 is provided with multiple NAND memories 10, multiple wirings connecting the resistive elements 12 and the NAND memories 10 are also formed on the substrate 8. Since the resistive elements 12 are disposed in the vicinity of the NAND memories 10, the variation in length between the multiple wirings connecting the resistive elements 12 and the NAND memories 10 is suppressed.

As described above, by arranging the power supply circuit 5, drive control circuit 4, DRAM 20, NAND memory 10, and SATA signal line 14, each of these elements can be appropriately arranged on the substrate 8, which has a roughly rectangular shape in a plan view.

In addition, by locating the power supply circuit 5 near the connector 9 and away from the SATA signal line 14, noise generated by the power supply circuit 5 is less likely to be picked up by other elements or the SATA signal line 14, which improves the stability of the operation of the semiconductor device 100.

In addition, by placing the DRAM 20 in a position that avoids the SATA signal line 14, the SATA signal line 14 is less likely to pick up noise generated by the DRAM 20, which improves the operational stability of the semiconductor device 100.

In addition, it is generally preferable to place the DRAM 20 near the drive control circuit 4. In the first embodiment, the DRAM 20 is placed near the drive control circuit 4, which can suppress deterioration of the performance characteristics of the semiconductor device 100.

In addition, of the four NAND memories 10, two NAND memories 10 are arranged close to one long side of the substrate 8, and the remaining two NAND memories 10 are arranged close to the other long side of the substrate 8. By configuring in this way, it is possible to prevent the wiring pattern from being biased to one side of the substrate 8, and a wiring pattern can be formed in a balanced manner.

In addition, since the resistive element 12 is placed near the NAND memory 10, the variation in the length of the wiring connecting the resistive element 12 and the NAND memory 10 is suppressed, thereby suppressing deterioration of the performance characteristics of the semiconductor device 100.

In addition, most of the area of the back surface layer L8 of the substrate 8, except for the SATA signal line 14, is ground 18. Therefore, for example, when the semiconductor device 100 is attached to the host 1 and a device on the host 1 side is present on the back surface layer side of the semiconductor device 100, the influence of noise from that device can be prevented from reaching the wiring pattern of the semiconductor device 100 and each element such as the NAND memory 10. Similarly, the device on the host 1 side is less likely to pick up the influence of noise from the wiring pattern and each element of the semiconductor device 100.

In addition, as in this embodiment, when it is necessary to form an electrode on the back layer side of the substrate 8 at the connector 9 portion, the SATA signal line 14 can be made shorter by penetrating the SATA signal line 14 to the back layer L8 of the substrate 8 near the connector 9. As a result, if a device on the host 1 side is present on the back layer side of the semiconductor device 100, the SATA signal line 14 is less likely to pick up noise from that device.

In addition, since almost no wiring patterns other than the SATA signal line 14 are formed in the portion of the substrate 8 that overlaps with the area S, it is easy to manage the impedance for the SATA signal line 14.

In this embodiment, a substrate 8 having an eight-layer structure is illustrated, but the present invention is not limited to this and the substrate 8 may have a different number of layers.

Figure 8 is a bottom view showing a schematic configuration of a semiconductor device 100 according to a first modified example of the first embodiment. Figure 9 shows the configuration of wiring connecting the drive control circuit 4 and the NAND memory 10, and is a conceptual diagram of the layer structure of the substrate 8. Note that in Figure 9, a portion of the layer structure of the substrate 8 is omitted to simplify the drawing.

In this first modified example, a NAND memory 10 is also mounted on the back layer side of the substrate 8, and the semiconductor device 100 has eight NAND memories 10. The NAND memory 10 mounted on the back layer side of the substrate 8 is disposed in a position symmetrical to the NAND memory 10 mounted on the front layer side of the substrate 8.

The resistive element 12 is not mounted on the back layer side of the substrate 8, but only on the front layer side. Therefore, the wiring connecting the resistive element 12 and the NAND memory 10 is routed through the inner layer of the substrate 8, branched by via holes 24, and drawn out to the back layer L8 as well as the front layer L1 of the substrate 8. The NAND memory 10 provided on the front layer side is connected to the wiring drawn out to the back layer L8, and the NAND memory 10 provided on the back layer side is connected to the wiring drawn out to the back layer L8. In other words, two NAND memories 10 are connected to one resistive element 12.

In this way, by mounting the NAND memories 10 on both sides of the substrate 8, it is possible to increase the storage capacity of the semiconductor device 100. In addition, by branching the wiring midway, multiple (two in this modification) NAND memories 10 can be connected to the resistance element 12, and the semiconductor device 100 can be equipped with NAND memories 10 greater than the number of channels that the drive control circuit 4 has. In this modification, the drive control circuit 4 has four channels, but it is possible to provide eight NAND memories 10 for it. Note that the NAND memory 10 itself determines which of the two NAND memories 10 connected to one wiring is operating, depending on whether the CE (chip enable) of the NAND memory 10 is active or not.

Second Embodiment
Fig. 10 is a plan view showing a detailed configuration of a semiconductor device according to a second embodiment. Fig. 11 is a cross-sectional view taken along line A-A shown in Fig. 10. Note that the same components as those in the above-mentioned embodiments are denoted by the same reference numerals and detailed description thereof will be omitted.

In the second embodiment, all of the four NAND memories 10 included in the semiconductor device 102 are arranged in parallel along one long side of the substrate 8, more specifically, along the long side on which the power supply circuit 5 is provided. By moving all of the NAND memories 10 toward one long side, the resistive elements 12 are arranged together in the space that is freed up on the other long side.

In general, the NAND memory 10 is often configured to be taller than other elements mounted on the substrate 8. Therefore, in the portion of the region T along the other long side of the substrate 8 where the resistive elements 12 are arranged together, the height of the semiconductor device 102 can be kept lower than the region U where the NAND memory 10 is arranged, as shown in FIG. 11.

Therefore, if some areas of the semiconductor device 102 must be lower than other areas due to requirements such as standards, it may be possible to obtain a semiconductor device 102 that satisfies the requirement by arranging the NAND memory 10 to avoid that area. In this embodiment, an example is given of a case where the area along the other long side of the substrate 8 must be lower than other areas. The DRAM 20 and temperature sensor 7 are also provided in area T. However, since the DRAM 20 and temperature sensor 7 are often configured lower than the NAND memory 10, the height of the semiconductor device 102 can be kept lower in the entire area T than in area U.

Figure 12 is a bottom view showing a schematic configuration of a semiconductor device 102 according to a first modification of the second embodiment. Figure 13 is a cross-sectional view taken along line B-B in Figure 12. In this first modification, similar to the first modification of the first embodiment, a NAND memory 10 is also provided on the back layer side of the substrate 8 in a position symmetrical to the NAND memory 10 arranged on the front layer side. This makes it possible to increase the memory capacity of the semiconductor device 102.

In addition, by providing the NAND memory 10 at a position symmetrical to the NAND memory 10 arranged on the front layer side of the substrate 8, the NAND memory 10 is also arranged close to one of the long sides on the back layer side of the substrate 8, so that the height of the semiconductor device 102 in the region T can be kept low.

In addition, the configuration and effects of providing the resistive element 12 only on the surface layer side of the substrate 8 and connecting two NAND memories 10 to one resistive element 12 are the same as those described in Variation 1 of the first embodiment.

Third Embodiment
14 is a plan view showing a schematic configuration of a semiconductor device according to a third embodiment. The same components as those in the above-mentioned embodiments are given the same reference numerals and detailed description is omitted. In this embodiment, two NAND memories 10 are arranged on the connector 9 side with respect to the drive control circuit 4, and two more NAND memories 10 are arranged on the opposite side. That is, a plurality of NAND memories 10 are arranged along the longitudinal direction of the substrate 8 so as to sandwich the drive control circuit 4 therebetween.

By arranging the NAND memories 10 separately in this manner, it is possible to suppress variation in the wiring length of the wiring connecting the NAND memories 10 and the drive control circuit 4, compared to arranging four NAND memories 10 in parallel on one side of the drive control circuit 4. For example, in this embodiment, the ratio of the shortest wiring to the longest wiring among the wiring connecting the NAND memories 10 and the drive control circuit 4 can be suppressed to about two times. On the other hand, if the same four NAND memories 10 are arranged in parallel on one side of the drive control circuit 4, the ratio of the shortest wiring to the longest wiring will be about four times.

In this way, in this embodiment, by suppressing the variation in wiring length, it is possible to reduce the difference in the optimal driver settings for the NAND memory 10. As a result, it is possible to suppress the occurrence of data errors and stabilize the operation of the semiconductor device 103.

The NAND memory 10 provided on the connector 9 side of the drive control circuit 4 is provided above the SATA signal line 14. In this embodiment, a BGA (Ball Grid Array) type NAND memory 10 is used, so when forming the SATA signal line 14 on the surface layer L1, it is necessary to avoid the ball-shaped electrodes (bumps) formed on the NAND memory 10.

However, as shown in FIG. 15, many ball-shaped electrodes 25 are provided on the bottom surface of the NAND memory 10, so it is difficult to form the SATA signal line 14 while avoiding the ball-shaped electrodes 25. Therefore, in this embodiment, the SATA signal line 14 that connects the connector 9 and the drive control circuit 4 is formed on the inner layer of the substrate 8.

In addition, since the NAND memory 10 is arranged close to one long side of the substrate 8, the height of the semiconductor device 103 can be kept low in the area along the other long side. In addition, by arranging the resistive element 12 near the NAND memory 10, deterioration of the performance characteristics of the semiconductor device 103 can be suppressed. Note that the number of NAND memories 10 included in the semiconductor device 103 is not limited to four, and may be more than one.

Figure 16 is a bottom view showing a schematic configuration of a semiconductor device according to a first modification of the third embodiment. In this first modification, similar to the first modification of the first embodiment, a NAND memory 10 is also provided on the back layer side of the substrate 8 at a position symmetrical to the NAND memory 10 arranged on the front layer side. This makes it possible to further increase the memory capacity of the semiconductor device 103.

In addition, by providing the NAND memory 10 at a position symmetrical to the NAND memory 10 arranged on the front layer side of the substrate 8, the NAND memory 10 is also arranged close to one of the long sides on the back layer side of the substrate 8, so that the height of the semiconductor device 103 can be kept low in the area along the other long side.

In addition, the configuration and effects of providing the resistive element 12 only on the surface layer side of the substrate 8 and connecting two NAND memories 10 to one resistive element 12 are the same as those described in Variation 1 of the first embodiment.

(Fourth embodiment)
17 is a plan view showing a schematic configuration of a semiconductor device according to a fourth embodiment. Note that the same components as those in the above-mentioned embodiments are given the same reference numerals and detailed description is omitted. In this embodiment, one NAND memory 10 is arranged on the connector 9 side with respect to the drive control circuit 4, and another NAND memory 10 is arranged on the opposite side. That is, the semiconductor device 104 includes two NAND memories 10.

When two NAND memories 10 are arranged on either side of the drive control circuit 4 as in this embodiment, the lengths of the multiple wirings connecting the drive control circuit 4 and the NAND memory 10 can be made approximately equal. On the other hand, when two NAND memories 10 are arranged in parallel on one side of the drive control circuit 4, the ratio of the shortest wiring to the longest wiring is approximately twice as long.

In this manner, in this embodiment, by making the wiring lengths of the multiple wirings approximately equal, the optimal driver settings for the NAND memory 10 can also be made approximately equal. This makes it possible to suppress the occurrence of data errors and stabilize the operation of the semiconductor device 104.

The SATA signal line 14 is formed in the inner layer of the substrate 8, as in the third embodiment. In addition, since the NAND memory 10 is arranged close to one long side of the substrate 8, the height of the semiconductor device 104 can be kept low in the area along the other long side. In addition, by arranging the resistive element 12 near the NAND memory 10, deterioration of the performance characteristics of the semiconductor device 104 can be suppressed.

Figure 18 is a bottom view showing a schematic configuration of a semiconductor device according to a first modification of the fourth embodiment. In this first modification, similar to the first modification of the first embodiment, a NAND memory 10 is also provided on the back layer side of the substrate 8 at a position symmetrical to the NAND memory 10 arranged on the front layer side. This makes it possible to increase the memory capacity of the semiconductor device 104.

In addition, by providing the NAND memory 10 at a position symmetrical to the NAND memory 10 arranged on the front layer side of the substrate 8, the NAND memory 10 is also arranged close to one of the long sides on the back layer side of the substrate 8, so that the height of the semiconductor device 104 can be kept low in the area along the other long side.

In addition, the configuration and effects of providing the resistive element 12 only on the surface layer side of the substrate 8 and connecting two NAND memories 10 to one resistive element 12 are the same as those described in Variation 1 of the first embodiment.

1 host, 2 SATA interface (ATA/IF), 3 communication interface, 4 drive control circuit (controller), 5 power supply circuit, 7 temperature sensor, 8 substrate, 9 connector, 9a slit, 10 NAND memory (NAND type flash memory, non-volatile semiconductor memory element), 12 resistance element, 12a resistance film, 12b protective film, 12c electrode, 14 SATA signal line (signal line), 15 via hole, 18 ground, 20 DRAM (volatile semiconductor memory element), 21, 22, 23, 24 via hole, 25 ball-shaped electrode, 100, 102, 103, 104 semiconductor device, 200 debugging equipment, S, T, U area.

Claims (18)

A first non-volatile semiconductor memory;
A second non-volatile semiconductor memory;
A volatile semiconductor memory;
a circuit element including a first electrode, a second electrode, a coating provided between the first electrode and the second electrode, and a film covering the coating;
a controller that controls the first and second nonvolatile semiconductor memories and the volatile semiconductor memory;
a first signal line connecting the controller and the circuit element;
a second signal line connecting the circuit element and the first nonvolatile semiconductor memory and including a first via hole;
a third signal line branched from the second signal line by the first via hole and connected to the second nonvolatile semiconductor memory;
A connector for connecting to an external device;
a substrate on which the first and second nonvolatile semiconductor memories, the circuit element, the controller, and the connector are mounted,
The substrate is
a surface layer including a wiring pattern formed on a surface of the substrate, the surface layer having the first nonvolatile semiconductor memory and the circuit element mounted thereon;
a back surface layer having a wiring pattern formed on a back surface of the substrate and on which the second nonvolatile semiconductor memory is mounted;
a plurality of internal wiring layers provided between the front surface layer and the back surface layer and having wiring patterns;
the third signal line includes a second via hole;
A semiconductor memory device configured such that a first region in which the first via hole is provided and a second region in which the second via hole is provided do not overlap each other in a plan view. The semiconductor memory device according to claim 1, wherein the second signal line includes a signal line formed in a first wiring layer that is one of the plurality of internal wiring layers, and a signal line formed in a second wiring layer that is one of the plurality of internal wiring layers and different from the first wiring layer. The semiconductor memory device according to claim 2, wherein the third signal line includes a signal line formed in a third wiring layer that is one of the plurality of internal wiring layers and is different from the first wiring layer and the second wiring layer. The semiconductor storage device according to claim 1 or 2, wherein the volatile semiconductor memory is configured to be provided on the same side as the connector when viewed from the first nonvolatile semiconductor memory or the second nonvolatile semiconductor memory in a plan view. The semiconductor memory device according to claim 2, wherein the second signal line includes a portion that extends in a direction substantially perpendicular to the surface of the substrate to connect a signal line formed in the first wiring layer and a signal line formed in the second wiring layer. The semiconductor memory device according to claim 4, wherein the substrate is configured such that an area in which a fourth signal line connecting the controller and the connector is provided and an area in which the volatile semiconductor memory is provided do not overlap in a plan view. The semiconductor memory device according to claim 6, wherein the fourth signal line is a SATA signal line. the connector includes electrodes on the rear surface of the substrate for connection to the external device;
8. The semiconductor memory device according to claim 6, wherein the fourth signal line has a portion that passes through a back surface layer of the substrate and is connected to an electrode of the connector, and a portion that is formed in any one of the plurality of internal wiring layers. the first nonvolatile semiconductor memory has a plurality of ball-shaped electrodes on a bottom surface;
the first nonvolatile semiconductor memory is connected to the substrate via a plurality of ball-shaped electrodes of the first nonvolatile semiconductor memory;
the second nonvolatile semiconductor memory has a plurality of ball-shaped electrodes on a bottom surface;
2. The semiconductor memory device according to claim 1, wherein said second nonvolatile semiconductor memory is connected to said substrate via said plurality of ball-shaped electrodes of said second nonvolatile semiconductor memory. The substrate has a first side and a second side perpendicular to the first side in a plan view,
the connector is provided on the first side of the substrate,
2. The semiconductor storage device according to claim 1, wherein the first and second nonvolatile semiconductor memories are provided on an opposite side of the connector from the position of the controller in a plan view. The semiconductor memory device according to claim 1, further comprising a temperature sensor. The semiconductor memory device according to claim 1, wherein the first signal line includes a first portion formed on the surface layer, a second portion formed on the back layer, and a third portion extending in a direction substantially perpendicular to the surface of the substrate to connect the first portion and the second portion. The semiconductor memory device according to claim 1, wherein the first non-volatile semiconductor memory and the second non-volatile semiconductor memory are arranged symmetrically with respect to the substrate. The semiconductor memory device according to claim 1, wherein the number of layers of the substrate is eight. The semiconductor storage device according to claim 1, wherein the first non-volatile semiconductor memory determines whether or not to operate in response to a signal from the second signal line based on a chip enable of the first non-volatile semiconductor memory. The semiconductor storage device according to claim 1, wherein the first and second non-volatile semiconductor memories are configured to be able to operate individually depending on whether the chip enable of each of the first and second non-volatile semiconductor memories is active or not. The semiconductor memory device according to claim 1, further comprising a power supply circuit mounted on the substrate, the power supply circuit configured to generate an internal voltage based on a power source supplied from the outside via the connector, and to supply the generated internal voltage to the first and second non-volatile semiconductor memories. The semiconductor memory device according to claim 17, wherein the connector is connectable to a host and supplies power input from the host to the power supply circuit.

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