JP7238177B2 - system - Google Patents

Description

Embodiments of the present invention relate to systems.

2. Description of the Related Art Conventionally, a semiconductor device has been used in which a nonvolatile semiconductor memory element such as a NAND flash memory is mounted on a substrate on which a connector is formed. In addition to the nonvolatile semiconductor memory elements, the semiconductor device also includes a volatile semiconductor memory element and a controller that controls the nonvolatile semiconductor element and the volatile semiconductor element.

The shape and size of the substrate of such a semiconductor device may be restricted in accordance with the usage environment, standards, and the like. In addition, it is required to arrange nonvolatile semiconductor memory elements and the like according to the shape and size of the substrate while suppressing deterioration of their performance characteristics.

JP 2010-79445 A

An object of one embodiment of the present invention is to provide a system capable of suppressing deterioration of performance characteristics while arranging non-volatile semiconductor elements and the like according to restrictions on the shape and size of a substrate.

According to one embodiment of the present invention, a connector, a volatile semiconductor memory, first to n-th (n is an integer equal to or greater than 2) non-volatile semiconductor memories, a controller, and first to n-th circuits A system is provided that includes an element, a multilayer wiring board, and a computer. Each of the nonvolatile semiconductor memories has a plurality of ball-shaped electrodes on its bottom surface. The controller controls the volatile semiconductor memory and the first to n-th nonvolatile semiconductor memories. A first electrode, a second electrode, a film provided between the first electrode and the second electrode, and a film covering the film are formed on the first to n-th circuit elements, respectively. be done. The volatile semiconductor memory, the first to n-th nonvolatile semiconductor memories, the first to n-th circuit elements, the controller, and the connector are mounted on the multilayer wiring board. The multilayer wiring board is formed in a rectangular shape in plan view, and the connectors are provided on short sides thereof. The computer is connected with the connector. The first to n-th nonvolatile semiconductor memories are arranged in a line along the longitudinal direction of the multilayer wiring board. In plan view, the controller is arranged between the connector and the first to n-th nonvolatile semiconductor memories. The multilayer wiring board includes a surface layer, a back layer, a plurality of internal wiring layers, first to nth signal lines, (n+1)th to 2nth signal lines, and (2n+1)th to 3nth signal lines. and a signal line. A wiring pattern for mounting the volatile semiconductor memory, the first to n-th nonvolatile semiconductor memories, and the controller is formed on the surface layer. (n+1)-th to 2n-th nonvolatile semiconductor memories having a plurality of ball-shaped electrodes provided on the bottom surface of the back surface layer, respectively, are provided with respect to the first to n-th nonvolatile semiconductor memories and the multilayer wiring board; Wiring patterns are formed for mounting at symmetrical positions. The plurality of internal wiring layers are provided between the surface layer and the back layer. Wiring patterns are formed in the plurality of internal wiring layers. The first to n-th signal lines connect the controller and the first to n-th circuit elements, respectively. The (n+1)th to 2nth signal lines connect the first to nth circuit elements and the first to nth nonvolatile semiconductor memories, respectively. The (n+1)th to 2nth signal lines have portions passing through the internal wiring layer. The (2n+1)th to 3nth signal lines branch from the (n+1)th to 2nth signal lines and connect the (n+1)th to 2nth nonvolatile semiconductor memories, respectively.

FIG. 1 is a block diagram of a configuration example of a semiconductor device according to a first embodiment. FIG. 2 is a plan view showing a schematic configuration of the semiconductor device. FIG. 3 is a plan view showing the detailed configuration of the semiconductor device. FIG. 4 is a perspective view showing a schematic configuration of a resistive element. FIG. 5 is a diagram showing the circuit configuration in the surface layer (first layer) of the substrate. FIG. 6 is a diagram showing the circuit configuration in the back layer (eighth layer) of the substrate. FIG. 7 is a diagram showing the configuration of wiring that connects the drive control circuit and the NAND memory, and is a conceptual diagram of the layer configuration of the substrate. FIG. 8 is a bottom view showing a schematic configuration of a semiconductor device according to Modification 1 of the first embodiment. FIG. 9 is a diagram showing the configuration of wiring that connects the drive control circuit and the NAND memory, and is a conceptual diagram of the layer configuration of the substrate. FIG. 10 is a plan view showing the detailed configuration of the semiconductor device according to the second embodiment. 11 is a cross-sectional view taken along the line AA shown in FIG. 10. FIG. FIG. 12 is a bottom view of a schematic configuration of a semiconductor device according to Modification 1 of the second embodiment. 13 is a cross-sectional view taken along line BB shown in FIG. 12. FIG. FIG. 14 is a plan view showing a schematic configuration of a semiconductor device according to a third embodiment; FIG. 15 is a diagram showing the bottom surface of the NAND memory. FIG. 16 is a bottom view showing a schematic configuration of a semiconductor device according to Modification 1 of the third embodiment. FIG. 17 is a plan view showing a schematic configuration of a semiconductor device according to a fourth embodiment; FIG. FIG. 18 is a bottom view showing a schematic configuration of a semiconductor device according to Modification 1 of the fourth embodiment.

Semiconductor memory devices according to embodiments will be described in detail below with reference to the accompanying drawings. In addition, the present invention is not limited by these embodiments.

(First embodiment)
FIG. 1 is a block diagram of a configuration example of a semiconductor device according to a first embodiment. A semiconductor device 100 is connected to a host device (hereinafter abbreviated as host) 1 such as a personal computer or a CPU core via a memory connection interface such as a SATA interface (ATA I/F) 2, and functions as an external memory of the host 1. do. Examples of the host 1 include the CPU of a personal computer, the CPU of an imaging device such as a still camera and a video camera, and the like. Also, the semiconductor device 100 can transmit and receive data to and from the debugging device 200 via the communication interface 3 such as an RS232C interface (RS232C I/F).

The semiconductor device 100 includes a NAND flash memory (hereinafter abbreviated as NAND memory) 10 as a nonvolatile semiconductor memory element, a drive control circuit 4 as a controller, and a volatile semiconductor capable of faster memory operation than the NAND memory 10. It has a DRAM 20 as a storage element, a power supply circuit 5, a status display LED 6, and a temperature sensor 7 for detecting the temperature inside the drive. The temperature sensor 7 directly or indirectly measures the temperature of the NAND memory 10, for example. The drive control circuit 4 restricts writing of information to the NAND memory 10 when the temperature measured by the temperature sensor 7 exceeds a certain temperature, thereby suppressing a further temperature rise.

The power supply circuit 5 generates a plurality of different internal DC power supply voltages from an external DC power supply supplied from the power supply circuit on the host 1 side, and supplies these internal DC power supply voltages to each circuit in the semiconductor device 100 . Also, the power supply circuit 5 detects the rise of the external power supply, generates a power-on reset signal, and supplies it to the drive control circuit 4 .

FIG. 2 is a plan view showing a schematic configuration of the semiconductor device 100. FIG. FIG. 3 is a plan view showing the detailed configuration of the semiconductor device 100. FIG. The power supply circuit 5, DRAM 20, drive control circuit 4, and NAND memory 10 are mounted on a substrate 8 on which wiring patterns are formed. The substrate 8 has a substantially rectangular shape in plan view. A connector 9 that is connected to the host 1 and functions as the above-described SATA interface 2 and communication interface 3 is provided on one short side of the board 8 having a substantially rectangular shape. The connector 9 functions as a power input section that supplies power input from the host 1 to the power supply circuit 5 . Connector 9 is, for example, a LIF connector. A slit 9a is formed in the connector 9 at a position deviated from the central position along the width direction of the substrate 8 so as to fit with a projection (not shown) provided on the host 1 side. It has become. This can prevent the semiconductor device 100 from being mounted upside down.

The substrate 8 has a multi-layer structure formed by stacking synthetic resins, and has an eight-layer structure, for example. Note that the number of layers of the substrate 8 is not limited to eight. On the substrate 8, wiring patterns of various shapes are formed on the surface of each layer made of synthetic resin or on the inner layer. The power supply circuit 5, the DRAM 20, the drive control circuit 4, and the NAND memory 10 mounted on the substrate 8 are electrically connected to each other through wiring patterns formed on the substrate 8. FIG.

Next, the arrangement of the power supply circuit 5, the DRAM 20, the drive control circuit 4, and the NAND memory 10 with respect to the substrate 8 will be described. As shown in FIGS. 2 and 3, power supply circuit 5 and DRAM 20 are arranged near connector 9 . Drive control circuit 4 is arranged next to power supply circuit 5 and DRAM 20 . A NAND memory 10 is arranged next to the drive control circuit 4 . That is, along the longitudinal direction of the substrate 8, the DRAM 20, the drive control circuit 4, and the NAND memory 10 are arranged in this order from the connector 9 side.

A plurality of NAND memories 10 are mounted on the substrate 8 and arranged side by side along the longitudinal direction of the substrate 8 . Although four NAND memories 10 are arranged in the first embodiment, the number of mounted NAND memories 10 is not limited to this as long as a plurality of NAND memories 10 are arranged.

Two NAND memories 10 out of the four NAND memories 10 are arranged close to one long side of the substrate 8, and the remaining two NAND memories 10 are arranged close to the other long side of the substrate 8. be done.

A resistance element 12 is mounted on the substrate 8 . The resistance element 12 is provided in the middle of the wiring pattern (wiring) connecting the drive control circuit 4 and the NAND memory 10 and functions as a resistance for signals input/output to/from the NAND memory 10 . FIG. 4 is a perspective view showing a schematic configuration of the resistance element 12. As shown in FIG. As shown in FIG. 4, the resistive element 12 is constructed by collectively covering a plurality of resistive films 12a provided between electrodes 12c with a protective film 12b. One resistance element 12 is provided for one NAND memory 10 . Each resistive element 12 is arranged near the NAND memory 10 connected to the resistive element 12 .

Next, wiring patterns formed on the substrate 8 will be described. As shown in FIG. 3, between the power supply circuit 5 and the drive control circuit 4, there is an area S in which almost no electronic components are mounted. A signal line (SATA signal line) connecting the connector 9 and the drive control circuit 4 is formed in the area S of the substrate 8 as part of the wiring pattern. Thus, on the substrate 8, the SATA signal line 14 is formed on the connector 9 side with the drive control circuit 4 interposed therebetween, and the NAND memories 10 are arranged in a row along the longitudinal direction of the substrate 8 on the opposite side. placed side by side.

FIG. 5 is a diagram showing the circuit configuration in the surface layer (first layer) L1 of the substrate 8. As shown in FIG. FIG. 6 is a diagram showing the circuit configuration in the back layer (eighth layer) L8 of the substrate 8. As shown in FIG. A SATA signal line 14 is formed from the position where the drive control circuit 4 is arranged to the vicinity of the connector 9 in the region S of the surface layer L1 of the substrate 8 . In the vicinity of the connector 9, the SATA signal line 14 penetrates to the back layer L8 of the substrate 8 through the via hole 15, and reaches the connector 9 by the SATA signal line 14 formed in the back layer L8. If it is necessary to form an electrode on the back layer L8 side of the substrate 8 at the connector 9 portion, the SATA signal line 14 must be passed through to the back layer L8 of the substrate 8 in this manner.

Most of the area of the rear surface layer L8 of the substrate 8 except for the SATA signal line 14 serves as a ground 18. As shown in FIG. Although not shown, in the inner layer between the surface layer L1 and the back layer L8 of the substrate 8, almost no wiring pattern other than the SATA signal line 14 is formed in the portion overlapping the SATA signal line 14. That is, almost no wiring pattern other than the SATA signal lines 14 is formed in the portion of the substrate 8 that overlaps with the region S. FIG.

In addition, although part of the SATA signal line 14 is interrupted in the surface layer L1, the signal passing through the SATA signal line 14 is relayed by the relay element 16 (see also FIG. 3) mounted on the relevant portion on the substrate 8. It is not a problem because it is Further, the surface of the substrate 8 is covered with an insulating protective film (not shown) to ensure the insulating properties of the wiring pattern formed on the surface layer L1.

FIG. 7 is a diagram showing the configuration of wiring connecting the drive control circuit 4 and the NAND memory 10, and is a conceptual diagram of the layer configuration of the substrate 8. As shown in FIG. In FIG. 7, part of the layer structure of the substrate 8 is omitted for simplification of the drawing.

As shown in FIG. 7, the wiring that connects the drive control circuit 4 and the resistance element 12 is connected to the drive control circuit 4 on the surface layer L1 of the substrate 8 and drawn into the inner layer of the substrate 8 through the via hole 21 . Then, the wiring is routed through the inner layer of the substrate 8 and pulled out to the surface layer L1 of the substrate 8 again through the via hole 22 and connected to the resistance element 12 .

Also, the wiring that connects the resistance element 12 and the NAND memory 10 is connected to the resistance element 12 on the surface layer L1 of the substrate 8 and drawn into the inner layer of the substrate 8 through the via hole 23 . Then, the wiring is routed through the inner layer of the substrate 8 and pulled out again to the surface layer L1 of the substrate 8 through the via hole 24 to be connected to the NAND memory 10 .

As described above, since the resistance element 12 is arranged near the NAND memory 10, the wiring connecting the resistance element 12 and the NAND memory 10 is more convenient than the wiring connecting the drive control circuit 4 and the resistance element 12. Shorten.

Here, since a plurality of NAND memories 10 are provided in the semiconductor device 100 , a plurality of wirings connecting the resistive elements 12 and the NAND memories 10 are also formed on the substrate 8 . Since the resistance element 12 is arranged in the vicinity of the NAND memory 10, variations in the lengths of the wirings connecting the resistance element 12 and the NAND memory 10 can be suppressed.

As described above, by arranging the power supply circuit 5, the drive control circuit 4, the DRAM 20, the NAND memory 10, and the SATA signal lines 14, these elements can be appropriately arranged on the substrate 8, which has a substantially rectangular shape in plan view. can be placed in

Further, by arranging the power supply circuit 5 in the vicinity of the connector 9 and away from the SATA signal line 14, noise generated from the power supply circuit 5 is less likely to be picked up by other elements and the SATA signal line 14. The stability of the operation of 100 can be improved.

Further, by arranging the DRAM 20 at a position avoiding the SATA signal line 14, noise generated from the DRAM 20 is less likely to be picked up by the SATA signal line 14, and the stability of the operation of the semiconductor device 100 can be improved.

Also, it is generally preferable to arrange the DRAM 20 near the drive control circuit 4 . In the first embodiment, since the DRAM 20 is arranged in the vicinity of the drive control circuit 4, deterioration of performance characteristics of the semiconductor device 100 can be suppressed.

Two NAND memories 10 out of the four NAND memories 10 are arranged close to one long side of the substrate 8, and the remaining two NAND memories 10 are arranged close to the other long side of the substrate 8. be done. By configuring in this way, it is possible to prevent the wiring pattern from biasing toward one side of the substrate 8, and the wiring pattern can be formed in a well-balanced manner.

In addition, since the resistance element 12 is arranged near the NAND memory 10, variations in the lengths of the wirings connecting the resistance element 12 and the NAND memory 10 are suppressed, so deterioration of the performance characteristics of the semiconductor device 100 is suppressed. be able to.

In addition, most of the area on the back surface layer L8 of the substrate 8 except for the SATA signal line 14 is the ground 18. Therefore, for example, when the semiconductor device 100 is attached to the host 1, the equipment on the host 1 side is the semiconductor device 100. , the influence of noise from the device can be suppressed from reaching the wiring pattern of the semiconductor device 100 and each element such as the NAND memory 10 . Similarly, it becomes difficult for the device on the host 1 side to pick up the influence of noise from the wiring pattern and each element of the semiconductor device 100 .

Further, when it is necessary to form electrodes on the back surface layer side of the substrate 8 at the connector 9 portion as in this embodiment, the SATA signal line 14 is passed through to the back surface layer L8 of the substrate 8 in the vicinity of the connector 9. Thus, the SATA signal line 14 formed on the back surface layer L8 can be made shorter. As a result, when the device on the host 1 side exists on the back layer side of the semiconductor device 100, the SATA signal line 14 is less likely to pick up noise from that device.

In addition, almost no wiring pattern other than the SATA signal line 14 is formed in the portion of the substrate 8 that overlaps the area S, so that the impedance to the SATA signal line 14 can be easily managed.

Although the substrate 8 having an eight-layer structure is exemplified in the present embodiment, the present invention is not limited to this, and the substrate 8 may have a different number of layers.

FIG. 8 is a bottom view showing a schematic configuration of a semiconductor device 100 according to Modification 1 of the first embodiment. FIG. 9 is a diagram showing the configuration of wiring that connects the drive control circuit 4 and the NAND memory 10, and is a conceptual diagram of the layer configuration of the substrate 8. As shown in FIG. In FIG. 9, part of the layer structure of the substrate 8 is omitted for simplification of the drawing.

In Modification 1, the NAND memory 10 is also mounted on the back surface layer side of the substrate 8 , and the semiconductor device 100 includes eight NAND memories 10 . The NAND memory 10 mounted on the back surface layer side of the substrate 8 is arranged at a position symmetrical to the NAND memory 10 mounted on the surface layer side of the substrate 8 .

Note that the resistance element 12 is not mounted on the back surface layer side of the substrate 8, but is mounted only on the surface layer side. Therefore, the wiring that connects the resistance element 12 and the NAND memory 10 is routed through the inner layer of the substrate 8 and branched by the via hole 24, and is drawn out not only to the surface layer L1 of the substrate 8 but also to the back surface layer L8. The NAND memory 10 provided on the surface layer side is connected to the wiring drawn out to the surface layer L1, and the NAND memory 10 provided on the back layer side is connected to the wiring drawn out to the back layer L8. . That is, two NAND memories 10 are connected to one resistance element 12 .

By mounting the NAND memories 10 on both sides of the substrate 8 in this manner, the storage capacity of the semiconductor device 100 can be increased. In addition, by branching the wiring on the way to the resistance element 12, a plurality of (two in this modification) NAND memories 10 can be connected, and the number of NAND memories 10 equal to or larger than the number of channels of the drive control circuit 4 can be connected. can be provided in the semiconductor device 100 . In this modification, the drive control circuit 4 has four channels, but eight NAND memories 10 can be provided for them. Note that which of the two NAND memories 10 connected to one wiring operates depends on whether CE (chip enable) of the NAND memory 10 is active or not. 10 decide for himself.

(Second embodiment)
FIG. 10 is a plan view showing the detailed configuration of the semiconductor device according to the second embodiment. 11 is a cross-sectional view taken along the line AA shown in FIG. 10. FIG. It should be noted that the same reference numerals are given to the same configurations as in the above-described embodiment, and detailed description thereof will be omitted.

In the second embodiment, all the four NAND memories 10 provided in the semiconductor device 102 are moved to one long side of the substrate 8, more specifically, to the long side on which the power supply circuit 5 is provided. are arranged in parallel. By moving all the NAND memories 10 to one long side, the resistance elements 12 are collectively arranged in the space left on the other long side.

In general, NAND memory 10 is often constructed higher than other elements mounted on substrate 8 . Therefore, as shown in FIG. 11, in a region T along the other long side of the substrate 8, the portion where the resistor elements 12 are collectively arranged has a higher density of the semiconductor device 102 than the region U where the NAND memory 10 is arranged. Height can be kept low.

Therefore, if a part of the area of the semiconductor device 102 must be made lower than other areas due to requirements such as standards, the requirement can be satisfied by arranging the NAND memory 10 so as to avoid that area. In some cases, the semiconductor device 102 can be obtained. In this embodiment, the case where the area along the other long side of the substrate 8 must be made lower than the other areas is taken as an example. Note that the DRAM 20 and the temperature sensor 7 are also provided in the area T. FIG. However, since the DRAM 20 and the temperature sensor 7 are often configured lower than the NAND memory 10, the height of the semiconductor device 102 in the entire region T can be kept lower than in the region U.

FIG. 12 is a bottom view showing a schematic configuration of a semiconductor device 102 according to Modification 1 of the second embodiment. 13 is a cross-sectional view taken along line BB shown in FIG. 12. FIG. In Modification 1, as in Modification 1 of the first embodiment, the NAND memory 10 is also provided on the rear surface layer side of the substrate 8 and at a position symmetrical to the NAND memory 10 arranged on the surface layer side. are provided. This makes it possible to further increase the storage capacity of the semiconductor device 102 .

In addition, by providing the NAND memory 10 at a position symmetrical to the NAND memory 10 arranged on the surface layer side of the substrate 8, the NAND memory 10 is also arranged closer to one long side on the back surface layer side of the substrate 8. Therefore, the height of the semiconductor device 102 in the region T can be kept low.

Also, the configuration and effects of providing the resistance element 12 only on the surface layer side of the substrate 8 and connecting two NAND memories 10 to one resistance element 12 have been described in the first modification of the first embodiment. It is the same as a thing.

(Third Embodiment)
FIG. 14 is a plan view showing a schematic configuration of a semiconductor device according to a third embodiment; It should be noted that the same reference numerals are given to the same configurations as in the above-described embodiment, and detailed description thereof will be omitted. In this embodiment, two NAND memories 10 are arranged on the connector 9 side with respect to the drive control circuit 4, and two more NAND memories 10 are arranged on the opposite side. That is, a plurality of NAND memories 10 are arranged along the longitudinal direction of the substrate 8 so as to sandwich the drive control circuit 4 .

By arranging the NAND memories 10 separately in this way, the wiring length of the wiring connecting the NAND memories 10 and the drive control circuit 4 can be reduced compared to arranging the four NAND memories 10 in parallel on one side of the drive control circuit 4 . variation can be suppressed. For example, in the present embodiment, the ratio of the shortest wiring to the longest wiring among the wirings connecting the NAND memory 10 and the drive control circuit 4 can be suppressed to approximately double. On the other hand, similarly, when four NAND memories 10 are arranged in parallel on one side of the drive control circuit 4, the ratio between the shortest wiring and the longest wiring becomes about four times.

As described above, in the present embodiment, by suppressing the variation in wiring length, the difference in optimal driver settings for the NAND memory 10 can be reduced. Therefore, the occurrence of data errors can be suppressed, and the operation of the semiconductor device 103 can be stabilized.

The NAND memory 10 provided on the connector 9 side with respect to the drive control circuit 4 is provided above the SATA signal line 14 . In the present embodiment, since a BGA (Ball Grid Array) type is used for the NAND memory 10, when forming the SATA signal line 14 on the surface layer L1, the ball It is necessary to avoid shaped electrodes (bumps).

However, since many ball-shaped electrodes 25 are provided on the bottom surface of the NAND memory 10 as shown in FIG. 15, it is difficult to form the SATA signal lines 14 while avoiding the ball-shaped electrodes 25 . Therefore, in this embodiment, the SATA signal line 14 connecting the connector 9 and the drive control circuit 4 is formed in the inner layer of the substrate 8 .

In addition, since the NAND memory 10 is arranged close to one long side of the substrate 8, the height of the semiconductor device 103 can be kept low in the region along the other long side. Further, by arranging the resistance element 12 in the vicinity of the NAND memory 10, deterioration of performance characteristics of the semiconductor device 103 can be suppressed. The number of NAND memories 10 included in the semiconductor device 103 is not limited to four, and may be more than four.

FIG. 16 is a bottom view showing a schematic configuration of a semiconductor device according to Modification 1 of the third embodiment. In Modification 1, as in Modification 1 of the first embodiment, the NAND memory 10 is also provided on the rear surface layer side of the substrate 8 and at a position symmetrical to the NAND memory 10 arranged on the surface layer side. are provided. This makes it possible to further increase the storage capacity of the semiconductor device 103 .

In addition, by providing the NAND memory 10 at a position symmetrical to the NAND memory 10 arranged on the surface layer side of the substrate 8, the NAND memory 10 is also arranged closer to one long side on the back surface layer side of the substrate 8. Therefore, the height of the semiconductor device 103 can be kept low in the region along the other long side.

Also, the configuration and effects of providing the resistance element 12 only on the surface layer side of the substrate 8 and connecting two NAND memories 10 to one resistance element 12 have been described in the first modification of the first embodiment. It is the same as a thing.

(Fourth embodiment)
FIG. 17 is a plan view showing a schematic configuration of a semiconductor device according to a fourth embodiment; FIG. It should be noted that the same reference numerals are given to the same configurations as in the above-described embodiment, and detailed description thereof will be omitted. In this embodiment, one NAND memory 10 is arranged on the connector 9 side with respect to the drive control circuit 4, and another NAND memory 10 is arranged on the opposite side. That is, the semiconductor device 104 has two NAND memories 10 .

When two NAND memories 10 are arranged so as to sandwich the drive control circuit 4 as in the present embodiment, the lengths of the plurality of wires connecting the drive control circuit 4 and the NAND memories 10 are made substantially equal. be able to. On the other hand, similarly, when two NAND memories 10 are arranged in parallel on one side of the drive control circuit 4, the ratio between the shortest wiring and the longest wiring is approximately doubled.

In this way, in the present embodiment, by making the wiring lengths of a plurality of wires substantially equal, the optimal driver settings for the NAND memory 10 can also be made substantially equal. Therefore, the occurrence of data errors can be suppressed, and the operation of the semiconductor device 104 can be stabilized.

The SATA signal line 14 is formed in the inner layer of the substrate 8 as in the third embodiment. Moreover, since the NAND memory 10 is arranged close to one long side of the substrate 8, the height of the semiconductor device 104 can be kept low in the region along the other long side. Further, by arranging the resistance element 12 in the vicinity of the NAND memory 10, the deterioration of the performance characteristics of the semiconductor device 104 can be suppressed.

FIG. 18 is a bottom view showing a schematic configuration of a semiconductor device according to Modification 1 of the fourth embodiment. In Modification 1, as in Modification 1 of the first embodiment, the NAND memory 10 is also provided on the rear surface layer side of the substrate 8 and at a position symmetrical to the NAND memory 10 arranged on the surface layer side. are provided. This makes it possible to further increase the storage capacity of the semiconductor device 104 .

In addition, by providing the NAND memory 10 at a position symmetrical to the NAND memory 10 arranged on the surface layer side of the substrate 8, the NAND memory 10 is also arranged closer to one long side on the back surface layer side of the substrate 8. Therefore, the height of the semiconductor device 104 can be kept low in the region along the other long side.

Also, the configuration and effects of providing the resistance element 12 only on the surface layer side of the substrate 8 and connecting two NAND memories 10 to one resistance element 12 have been described in the first modification of the first embodiment. It is the same as a thing.

1 host, 2 SATA interface (ATA/IF), 3 communication interface, 4 drive control circuit (controller), 5 power supply circuit, 7 temperature sensor, 8 substrate, 9 connector, 9a slit, 10 NAND memory (NAND flash memory, nonvolatile semiconductor memory element), 12 resistance element, 12a resistive film, 12b protective film, 12c electrode, 14 SATA signal line (signal line), 15 via hole, 18 ground, 20 DRAM (volatile semiconductor memory element), 21, 22 , 23, 24 via hole, 25 ball-shaped electrode, 100, 102, 103, 104 semiconductor device, 200 debugging device, S, T, U region.

Claims (13)

a connector;
a volatile semiconductor memory;
first to n-th (n is an integer equal to or greater than 2) nonvolatile semiconductor memories each having a plurality of ball-shaped electrodes on the bottom;
a controller that controls the volatile semiconductor memory and the first to n-th nonvolatile semiconductor memories;
first to n-th circuit elements each having a first electrode, a second electrode, a film provided between the first electrode and the second electrode, and a film covering the film;
The volatile semiconductor memory, the first to n-th nonvolatile semiconductor memories, the first to n-th circuit elements, the controller, and the connector are mounted, and are formed in a rectangular shape in a plan view with short sides a multilayer wiring board provided with the connector;
a computer connected to the connector,
the first to n-th nonvolatile semiconductor memories are arranged in a line along the longitudinal direction of the multilayer wiring board;
In plan view, the controller is arranged between the connector and the first to n-th nonvolatile semiconductor memories,
The multilayer wiring board is
a surface layer formed with wiring patterns for mounting the volatile semiconductor memory, the first to n-th nonvolatile semiconductor memories, and the controller;
(n+1)th to 2nth nonvolatile semiconductor memories each having a plurality of ball-shaped electrodes provided on the bottom surface thereof are mounted at symmetrical positions with respect to the first to nth nonvolatile semiconductor memories and the multilayer wiring board. a back layer on which a wiring pattern for
a plurality of internal wiring layers provided between the surface layer and the back layer and having wiring patterns formed thereon;
first to n-th signal lines connecting the controller and the first to n-th circuit elements, respectively;
(n+1)-th to 2n-th signal lines for connecting the first to n-th circuit elements and the first to n-th nonvolatile semiconductor memories, respectively, and passing through the internal wiring layer; (n+1)th to 2nth signal lines provided;
(2n+1)th to 3nth signal lines branched from the (n+1)th to 2nth signal lines for connecting the (n+1)th to 2nth nonvolatile semiconductor memories, respectively;
A system with Each of the (n+1)-th to 2n-th signal lines is a signal line formed in a first wiring layer which is one wiring layer of the plurality of internal wiring layers and a signal line formed in one of the plurality of internal wiring layers. 2. The system of claim 1, including one wiring layer and a signal line formed in a second wiring layer different from said first wiring layer. Each of the (n+1)th to 2nth signal lines is for connecting the signal line formed in the first wiring layer and the signal line formed in the second wiring layer to the multilayer wiring board. 3. The system of claim 2, including a portion extending substantially perpendicular to the surface of the. In the multilayer wiring board, a region provided with a (3n+1)th signal line connecting the controller and the connector and a region provided with the volatile semiconductor memory do not overlap in plan view. 4. A system as claimed in any one of claims 1 to 3, configured. 5. The system of claim 4, wherein the (3n+1)th signal line is a SATA signal line. the connector includes an electrode for connection with the computer on the back layer of the multilayer wiring board;
The (3n+1)-th signal line has a portion connected to the electrode of the connector through the back surface layer of the multilayer wiring board, a portion formed in any wiring layer of the plurality of internal wiring layers, 6. A system according to claim 4 or claim 5, comprising: 7. In plan view, the volatile semiconductor memory is arranged on the same side as the connector when viewed from the first to n-th nonvolatile semiconductor memories. The system described in . 8. The system of any one of claims 1-7, further comprising a temperature sensor. Each of the first to n-th signal lines includes a first portion formed on the surface layer, a second portion formed on the back surface layer, the first portion and the second portion. 9. A system according to any one of claims 1 to 8, comprising a third portion extending substantially perpendicularly to the surface of the multilayer wiring board for connecting to. 10. The system according to any one of claims 1 to 9, wherein the multilayer wiring board has eight layers. The k-th (k is an integer that satisfies 1≤k≤n) non-volatile semiconductor memory responds to the signal from the (n+k)-th signal line based on the chip enable of the k-th non-volatile semiconductor memory. 11. A system according to any one of claims 1 to 10, wherein the system determines whether to operate with the Further comprising a power supply circuit mounted on the multilayer wiring board,
The computer inputs power to the connector,
the connector supplies the input power to the power supply circuit;
1. The power supply circuit is configured to generate an internal voltage based on the supplied power and to supply the generated internal voltage to the first to n-th nonvolatile semiconductor memories. Item 12. The system according to any one of Item 11. 13. A system according to any preceding claim, wherein n is four.

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