JP5917990B2 - Nitride semiconductor device - Google Patents

Description

  The present invention relates to a nitride semiconductor device.

  Conventionally, as a nitride semiconductor device, an oxygen plasma treatment is performed on the surface of an n-type GaN contact layer to form an oxygen-doped layer, and then an ohmic electrode is formed on the n-type GaN contact layer, whereby an n-type GaN Some reduce the contact resistance between the contact layer and the ohmic electrode (see Japanese Patent No. 2967743 (Patent Document 1)).

  However, for the nitride semiconductor device, when the inventor actually conducted an experiment and formed an ohmic electrode after performing oxygen plasma treatment on the GaN layer, the ohmic electrode has a high contact resistance and a sufficiently low contact resistance. I just couldn't get it.

Japanese Patent No. 2967743

  Accordingly, an object of the present invention is to provide a nitride semiconductor device capable of reducing the contact resistance between the nitride semiconductor layer and the ohmic electrode.

  As a result of intensive studies on the contact resistance of the ohmic electrode formed on the nitride semiconductor layer, the inventor has found that the substrate side region near the interface between the ohmic electrode made of TiAl-based material and the nitride semiconductor layer is in the vicinity of the interface. When the first chlorine concentration peak and the second chlorine concentration peak at a position deeper than the first chlorine concentration peak are generated, the nitride semiconductor layer and the ohmic contact are generated according to the chlorine concentration of the second chlorine concentration peak. It was discovered that the characteristics of contact resistance with the electrode change.

  Furthermore, the present inventor has found for the first time that the contact resistance is greatly reduced when the chlorine concentration at the second chlorine concentration peak on the substrate side from the interface is within a specific range.

Based on the above discovery, the nitride semiconductor device of the present invention is
A substrate,
A nitride semiconductor multilayer body formed on the substrate and having a heterointerface;
An ohmic electrode made of a TiAl-based material formed at least partially on the nitride semiconductor multilayer body or in the nitride semiconductor multilayer body,
The nitride semiconductor laminate is
A first nitride semiconductor layer formed on the substrate;
A second nitride semiconductor layer formed on the first nitride semiconductor layer and forming a heterointerface with the first nitride semiconductor layer;
In the chlorine concentration distribution in the depth direction from the ohmic electrode made of the TiAl-based material to the nitride semiconductor laminate,
A first chlorine concentration peak at a position near the interface in a region closer to the substrate than the interface between the ohmic electrode and the nitride semiconductor multilayer body;
A second chlorine concentration peak at a position deeper than the first chlorine concentration peak;
The chlorine concentration of the second chlorine concentration peak is 3 × 10 ¹⁶ cm ⁻³ or more and 1.3 × 10 ¹⁷ cm ⁻³ or less.

According to the nitride semiconductor device of the present invention, in the region on the substrate side of the interface between the ohmic electrode made of the TiAl-based material and the nitride semiconductor multilayer body, the position of the first chlorine concentration peak in the vicinity of the interface By having a second chlorine concentration peak of 3 × 10 ¹⁶ cm ⁻³ or more and 1.3 × 10 ¹⁷ cm ⁻³ or less at a deeper position, contact between the nitride semiconductor laminate and the ohmic electrode Resistance can be reduced.

  In the nitride semiconductor device of one embodiment, the position of the second oxygen concentration peak is a depth of 60 nm or more and 100 nm or less from the interface.

  According to this embodiment, since the second oxygen concentration peak is located at a depth of 60 nm or more and 100 nm or less from the interface, the contact resistance between the nitride semiconductor multilayer body and the ohmic electrode can be reduced.

In one embodiment of the nitride semiconductor device, the nitride semiconductor stack is
Having a recess that penetrates the second nitride semiconductor layer and reaches the two-dimensional electron gas layer near the heterointerface;
At least a part of the ohmic electrode is embedded in the recess.

  According to this embodiment, in the nitride semiconductor device having a recess structure, the contact resistance between the two-dimensional electron gas layer near the heterointerface and the ohmic electrode can be reduced.

According to the nitride semiconductor device of the present invention, a position deeper than the position of the first chlorine concentration peak in the vicinity of the interface in the region on the substrate side of the interface between the ohmic electrode made of a TiAl-based material and the nitride semiconductor multilayer body. Further, the second chlorine concentration peak having a chlorine concentration of 1.3 × 10 ¹⁷ cm ⁻³ or less can reduce the contact resistance between the nitride semiconductor multilayer body and the ohmic electrode.

It is sectional drawing of the nitride semiconductor device of embodiment of this invention. It is process sectional drawing for demonstrating the manufacturing method of the said nitride semiconductor device. FIG. 3 is a process cross-sectional view subsequent to FIG. 2. FIG. 4 is a process cross-sectional view subsequent to FIG. 3. FIG. 5 is a process cross-sectional view subsequent to FIG. 4. It is a graph which shows the density | concentration distribution of the chlorine in the depth direction from the ohmic electrode side to the GaN layer side of the interface of the ohmic electrode of the said embodiment, and a GaN layer. It is a graph which shows the relationship between the chlorine concentration (cm ^<-3 >) of the 2nd chlorine concentration peak P2 of the said embodiment, and the contact resistance of an ohmic electrode. It is a graph which shows the relationship between the depth of the 2nd chlorine concentration peak P2 of the said embodiment, and the contact resistance of an ohmic electrode. It is a graph which shows the relationship between the self-bias potential Vdc and the contact resistance of an ohmic electrode in the dry etching of the manufacturing process of the said embodiment. It is a graph which shows the density | concentration distribution of the chlorine in the depth direction from the ohmic electrode side to the GaN layer side of the interface of the ohmic electrode and GaN layer in a comparative example.

  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

  FIG. 1 shows a cross-sectional view of a nitride semiconductor device according to an embodiment of the present invention, and this nitride semiconductor device is a GaN-based HFET (Hetero-junction Field Effect Transistor).

  As shown in FIG. 1, the semiconductor device includes an undoped AlGaN buffer layer 15, an undoped GaN layer 1 as an example of a first nitride semiconductor layer, and an example of a second nitride semiconductor layer on a Si substrate 10. As a result, a nitride semiconductor stacked body 20 composed of the undoped AlGaN layer 2 is formed. A 2DEG layer (two-dimensional electron gas layer) 3 is generated in the vicinity of the interface between the undoped GaN layer 1 and the undoped AlGaN layer 2.

  In place of the GaN layer 1, an AlGaN layer having a smaller band gap than the AlGaN layer 2 may be used. Further, a layer having a thickness of about 1 nm made of GaN, for example, may be provided on the AlGaN layer 2 as a cap layer.

  Further, the source electrode 11 and the drain electrode 12 are formed in the recess 106 and the recess 109 that pass through the AlGaN layer 2 and the 2DEG layer 3 and reach the GaN layer 1 with a space therebetween. Further, a gate electrode 13 is formed on the AlGaN layer 2 between the source electrode 11 and the drain electrode 12 and on the source electrode 11 side. The source electrode 11 and the drain electrode 12 are ohmic electrodes, and the gate electrode 13 is a Schottky electrode. The source electrode 11, the drain electrode 12, the gate electrode 13, and the active regions of the GaN layer 1 and the AlGaN layer 2 on which the source electrode 11, the drain electrode 12, and the gate electrode 13 are formed constitute an HFET.

  Here, the active region means that carriers are generated between the source electrode 11 and the drain electrode 12 by the voltage applied to the gate electrode 13 disposed between the source electrode 11 and the drain electrode 12 on the AlGaN layer 2. This is a region of the flowing nitride semiconductor stacked body 20 (GaN layer 1, AlGaN layer 2).

Then, an insulating film 30 made of SiO ₂ is formed on the AlGaN layer 2 excluding the region where the source electrode 11, the drain electrode 12, and the gate electrode 13 are formed in order to protect the AlGaN layer 2. An interlayer insulating film 40 made of polyimide is formed on the Si substrate 10 on which the source electrode 11, the drain electrode 12, and the gate electrode 13 are formed. In FIG. 1, reference numeral 41 denotes a via as a contact portion, and 42 denotes a drain electrode pad. Note that the insulating film is not limited to SiO ₂ , and SiN, Al ₂ O _3, or the like may be used. In particular, the insulating film preferably has a multilayer structure of a SiN film having a stoichiometric collapse on the surface of the semiconductor layer to suppress collapse and a SiO ₂ or SiN film structure for surface protection. In addition, the interlayer insulating film is not limited to polyimide, but an insulating material such as SiO ₂ film manufactured by p-CVD (plasma CVD), SOG (Spin On Glass), or BPSG (boron, phosphorus, silicate, glass) is used. Also good.

  In the nitride semiconductor device configured as described above, a channel is formed by the two-dimensional electron gas layer (2DEG layer) 3 generated at the interface between the GaN layer 1 and the AlGaN layer 2, and a voltage is applied to the gate electrode 13 through this channel. The HFET having the source electrode 11, the drain electrode 12, and the gate electrode 13 is turned on / off. In the HFET, when a negative voltage is applied to the gate electrode 13, a depletion layer is formed in the GaN layer 1 below the gate electrode 13, and the HFET is turned off. On the other hand, when the voltage of the gate electrode 13 is zero, 13 is a normally-on type transistor in which the depletion layer disappears in the lower GaN layer 1 and is turned on.

  Next, a method for manufacturing the nitride semiconductor device will be described with reference to FIGS. 2 to 5, the Si substrate and the undoped AlGaN buffer layer are not shown in order to make the drawings easy to see, and the sizes and intervals of the source electrode and the drain electrode are changed.

  First, as shown in FIG. 2, an undoped AlGaN buffer layer (not shown), undoped GaN are formed on a Si substrate (not shown) using MOCVD (Metal Organic Chemical Vapor Deposition). A layer 101 and an undoped AlGaN layer 102 are formed in this order. The thickness of the undoped GaN layer 101 is 1 μm, for example, and the thickness of the undoped AlGaN layer 102 is 30 nm, for example. The GaN layer 101 and the AlGaN layer 102 constitute a nitride semiconductor stacked body 120.

Next, an insulating film 130 (for example, SiO ₂ ) is formed on the AlGaN layer 102 to a thickness of 200 nm by, for example, a plasma CVD (Chemical Vapor Deposition) method. In FIG. 2, reference numeral 103 denotes a two-dimensional electron gas layer (2DEG layer) formed in the vicinity of the heterointerface between the GaN layer 101 and the AlGaN layer 102.

  Next, after applying and patterning a photoresist (not shown) on the insulating film 130, a portion where an ohmic electrode is to be formed is removed by dry etching, as shown in FIG. Recesses 106 and 109 deeper than the 2DEG layer 103 are formed in a part of the upper side of the GaN layer 101 so as to penetrate therethrough. In the dry etching, a chlorine-based gas is used. The depths of the recesses 106 and 109 may be equal to or greater than the depth from the surface of the AlGaN layer 102 to the 2DEG layer 103, for example, 50 nm.

  In this embodiment, the voltage Vdc applied between the electrodes in the chamber is set to 180 V or more and 240 V or less in the dry etching.

Next, O ₂ plasma treatment, cleaning with HCl / H ₂ O ₂ , and cleaning with BHF (buffered hydrofluoric acid) or 1% HF (hydrofluoric acid) are sequentially performed. And annealing for reducing the etching damage by the said dry etching is performed at 500-850 degreeC, for example.

  Next, as shown in FIG. 4, Ti, Al, and TiN are sequentially laminated on the insulating film 130 and the concave portions 106 and 109, and Ti / Al / TiN are laminated, thereby forming a laminated metal film that becomes an ohmic electrode. 107 is formed. Here, the TiN layer is a cap layer for protecting the Ti / Al layer from a subsequent process.

  When the laminated metal film 107 is formed by the sputtering, a small amount (for example, 5 sccm) of oxygen is allowed to flow into the chamber during the Ti film formation. Here, the flow rate of the oxygen is set so that Ti oxide is not generated. Instead of flowing a small amount of oxygen into the chamber during the Ti film formation, oxygen may be flowed into the chamber at 50 sccm for 5 minutes before the Ti film formation.

  In the sputtering, both Ti and Al may be sputtered simultaneously. Further, Ti and Al may be deposited instead of sputtering.

  Next, as shown in FIG. 5, patterns of ohmic electrodes 111 and 112 are formed by using normal photolithography and dry etching.

  Then, by annealing the substrate on which the ohmic electrodes 111 and 112 are formed, for example, at 400 ° C. or more and 500 ° C. or less for 10 minutes or more, between the two-dimensional electron gas layer (2DEG layer) 103 and the ohmic electrodes 111 and 112 Ohmic contact is obtained. In this case, the contact resistance can be greatly reduced as compared with the case where annealing is performed at a high temperature exceeding 500 ° C. (for example, 600 ° C. or more). Further, by annealing at a low temperature of 400 ° C. or more and 500 ° C. or less, diffusion of the electrode metal to the insulating film 130 can be suppressed and the characteristics of the insulating film 130 are not adversely affected. In addition, the low temperature annealing can prevent deterioration of current collapse and characteristic fluctuation due to nitrogen desorption from the GaN layer 101. Note that “current collapse” is a phenomenon in which the on-resistance of a transistor in a high-voltage operation becomes higher than the on-resistance of the transistor in a low-voltage operation.

  The ohmic electrodes 111 and 112 become the source electrode 11 and the drain electrode 12, and a gate electrode made of TiN or WN or the like is formed between the ohmic electrodes 111 and 112 in a later step.

According to the method for manufacturing the nitride semiconductor device of the embodiment, in the chlorine concentration distribution in the depth direction from the source electrode 11 and the drain electrode 12 as the ohmic electrodes to the GaN layer 1, the source electrode 11 and the drain electrode In a region on the undoped GaN layer 1 side of the interfaces S1 and S2 between the undoped GaN layer 1 and the first chlorine concentration peak P1, a first chlorine concentration peak P1 is formed at a position near the interfaces S1 and S2. A second chlorine concentration peak P2 is formed at a position deeper than the first chlorine concentration peak P1. Further, the chlorine concentration of the second chlorine concentration peak P2 can be set to 2.0 × 10 ¹⁶ cm ⁻³ or more and 1.3 × 10 ¹⁷ cm ⁻³ or less. The chlorine concentration at the first chlorine concentration peak is higher than the chlorine concentration at the second chlorine concentration peak, for example, 1.0 × 10 ¹⁷ (cm ⁻³ ) or more and 2.2 × 10 ¹⁷ ( cm ⁻³ ) or less.

FIG. 6 is a graph showing an example of a chlorine concentration distribution in the depth direction from the source electrode 11 to the undoped GaN layer 1. 6, the vertical axis scale 1.E + 01,1.E + 02, ..., 1.E + 04 , ^{respectively, 1.0 × 10,1.0 × 10 2,} ..., representative of 1.0 × 10 ^4. This graph shows the results measured by SIMS (secondary ion mass spectrometry) using TEG (test element group), with the horizontal axis representing depth (nm) and the vertical axis representing relative secondary ion intensity. (counts). In FIG. 6, as an example, the first chlorine concentration peak P1 is located at a depth of about 10 nm from the interface S1 to the GaN layer 1 side, and the depth is about 95 nm from the interface S1 to the GaN layer 1 side. In addition, the second chlorine concentration peak P2 is located.

The oxygen concentration distribution in the depth direction from the drain electrode 12 side to the GaN layer 1 side of the interface S2 between the drain electrode 12 and the undoped GaN layer 1 was also the same as the graph of FIG. In the example shown in FIG. 6, the chlorine concentration of the second chlorine concentration peak P2 is 6 × 10 ¹⁶ (cm ⁻³ ), and the contact resistance of 1.1 Ωmm of the ohmic electrodes (source electrode 11 and drain electrode 12) is obtained. It was.

  As shown in FIG. 6, in order to have not only the first chlorine concentration peak P1 but also the second chlorine concentration peak P2, a considerable amount of damage (chlorine penetration, ion However, the present inventors can form a low-resistance ohmic contact by the chlorine concentration distribution in which the second chlorine concentration peak P2 exists. I found.

  That is, according to this embodiment, a recess structure nitride semiconductor device in which the ohmic electrodes 111 and 112 are partially embedded in the recesses 106 and 109 formed so as to penetrate the AlGaN layer 102 and reach the 2DEG layer 3. The contact resistance between the two-dimensional electron gas (2DEG) layer 103 and the ohmic electrodes 111 and 112 in the vicinity of the heterointerface between the GaN layer 101 and the AlGaN layer 102 can be reduced.

Next, in FIG. 7, 2DEG layer 3 and the source electrode 11 of the nitride semiconductor stack 20, the contact resistance between the drain electrode 12 and the (Ωmm), the chlorine concentration of the second chlorine concentration peak P2 (cm ^{- 3} ) shows the relationship. In Figure 7, the horizontal axis scale E + 16, E + 17, E + 18 each represent ^{× 10 16, × 10 17,} × 10 18.

As can be seen from FIG. 7, the chlorine concentration (cm ⁻³ ) of the second chlorine concentration peak P2 is 1.3 × 10 ¹⁷ cm ⁻³ or less and 3 × 10 ¹⁶ cm ⁻³ or more. Contact resistance (Ωmm) can be 3 (Ωmm) or less. For example, as shown in FIG. 7, when the chlorine concentration (cm ⁻³ ) of the second chlorine concentration peak P2 is 6 × 10 ¹⁶ (cm ⁻³ ), the contact resistance is about 1.1 (Ωmm). (Ωmm) was obtained. In addition, when the chlorine concentration (cm ⁻³ ) of the second chlorine concentration peak P2 was 3 × 10 ¹⁶ (cm ⁻³ ), a contact resistance (Ωmm) of about 1.0 (Ωmm) was obtained. .

  On the other hand, when the chlorine concentration of the second chlorine concentration peak P2 is zero as in the case of using a fluorine-based gas instead of the chlorine-based gas during the dry etching, no ohmic contact is formed. This is because when the chlorine concentration of the second chlorine concentration peak P2 is zero, damage (such as chlorine penetration, introduction of defects due to ion bombardment or charge) given to the substrate side during the dry etching is insufficient, This is probably because a low-resistance ohmic contact is not formed.

Further, when the chlorine concentration at the second chlorine concentration peak P2 exceeds 1.3 × 10 ¹⁷ cm ⁻³ , the contact resistance exceeds ³ Ωmm. This is because, if the chlorine concentration of the second chlorine concentration peak P2 is too high, excess chlorine reacts with Ga and Ti, and N from GaN by Ti, which is a reaction on the GaN layer 1 side necessary for ohmic contact formation. This is probably because the drawing reaction of oxygen and the activation of oxygen were inhibited.

That is, according to this embodiment, by setting the chlorine concentration of the second chlorine concentration peak P2 within the range of 3.0 × 10 ¹⁶ cm ^{−3 to} 1.3 × 10 ¹⁷ cm ⁻³ , ohmic Since activation of oxygen on the GaN layer side necessary for contact formation and N extraction reaction from GaN can be promoted, it is considered that an ohmic contact having a low resistance of 3 Ωmm or less could be obtained. Such a nitride semiconductor device having a contact resistance of 3 Ωmm or less has a commercial value in terms of performance and cost as a product that can be driven with a larger current than a silicon element and is suitable for high-temperature operation.

  Further, in the dry etching, when a fluorine-based gas is used instead of the chlorine-based gas, a low-resistance ohmic contact as in the case of using a chlorine-based gas was not formed. Therefore, it is considered that not only physical damage to the GaN layer by dry etching but also the presence of chlorine during dry etching contributes to the formation of a low-resistance ohmic contact.

FIG. 10 is a graph showing the chlorine concentration distribution in the depth direction from the ohmic electrode (source electrode, drain electrode) to the undoped GaN layer in the comparative example of the nitride semiconductor device (GaN-based HFET) of the above embodiment. In FIG. 10, the vertical scales 1.E + 01, 1.E + 02, 1.E + 03, 1.E + 04 are 1.0 × 10, 1.0 × 10 ² , 1.0 × 10 ³ , 1.0, respectively. × 10 ⁴ is represented. The cross-sectional structure of this comparative example is the same as the cross-sectional structure of the above embodiment shown in FIG. 1, but the chlorine concentration distribution shown in the graph is different from that of the above embodiment.

  The graph of FIG. 10 shows the result of measurement by SIMS (secondary ion mass spectrometry) using TEG (test element group), with the horizontal axis representing depth (nm) and the vertical axis representing relative secondary. The ionic strength (counts) is taken. As shown in FIG. 10, in this comparative example, the first chlorine concentration peak P10 in the vicinity of the interface exists, but the second chlorine concentration peak is located deeper on the GaN layer side than the first chlorine concentration peak P10. Does not exist. In the case where the second chlorine concentration peak does not exist as in this comparative example, the contact resistance of the ohmic electrode exceeds 70 Ωmm, which is significantly higher than the contact resistance of 3 Ωmm or less of the ohmic electrode of the above embodiment. Resistive ohmic contact cannot be obtained.

  Next, referring to FIG. 9, in dry etching for forming the recesses 106 and 109, the self-bias potential Vdc of the RIE (reactive ion etching) apparatus, the source electrode 11, and the drain electrode The relationship with the contact resistance (Ωmm) of 12 will be described. As can be seen from FIG. 9, by setting the self-bias potential Vdc at the time of the dry etching to 180 V or more and 240 V or less, the second chlorine concentration peak P2 is formed, and 2DEG of the nitride semiconductor stacked body 20 is formed. The contact resistance (Ωmm) between the layer 3 and the source electrode 11 and the drain electrode 12 can be 2Ωmm or less.

  On the other hand, when the self-bias potential Vdc during the dry etching is less than 180 V, the second chlorine concentration peak is hardly formed, and the contact resistance (Ωmm) is rapidly increased. This is presumably because the GaN layer is less damaged by the dry etching with the self-bias potential Vdc being too small during the dry etching, and the alloy between the electrode and the GaN layer is difficult to proceed during annealing.

  When the self-bias potential Vdc exceeds 240 V, the second chlorine concentration peak is hardly formed, and the contact resistance (Ωmm) is rapidly increased. This is presumably because if the self-bias potential Vdc at the time of the dry etching is too large, the GaN layer 1 side is damaged so much that the alloy between the electrode and the GaN layer hardly progresses during annealing.

  Next, the relationship between the depth (nm) of the second chlorine concentration peak P2 from the interface S1 and the contact resistance (Ωmm) of the source electrode 11 and the drain electrode 12 will be described with reference to FIG. As can be seen from FIG. 8, when the depth (nm) of the second chlorine concentration peak P2 from the interface S1 is 60 nm or more and 100 nm or less, the contact resistance (Ωmm) is set to 2Ωmm or less. it can. When the depth (nm) of the second chlorine concentration peak P2 from the interface S1 is less than 60 nm, the distinction between the first chlorine concentration peak P1 and the second chlorine concentration peak P2 becomes unclear. When the depth (nm) of the second chlorine concentration peak P2 from the interface S1 exceeds 100 nm, the second chlorine concentration peak P2 is hardly formed.

  As shown in FIG. 8, the structure in which the depth from the interface S1 of the second chlorine concentration peak P2 is 60 nm to 100 nm enables ohmic formation on the substrate side in low temperature (400 ° C. to 500 ° C.) ohmic annealing. It is considered that the depth at which necessary reactions (oxygen activation, N extraction by Ti, etc.) occur is optimized, and the ohmic formation reaction is promoted.

According to the manufacturing method of the above-described embodiment, the chlorine concentration of the second chlorine concentration peak P2 is set to a value within the range of 3.0 × 10 ¹⁶ cm ^{−3 to} 1.3 × 10 ¹⁷ cm ^−3. In addition, the depth (nm) of the second chlorine concentration peak P2 from the interface S1 can be 60 nm or more and 100 nm or less (for example, 108 nm), and the contact resistance (Ωmm) can be 2Ωmm or less.

  According to the nitride semiconductor device manufacturing method of the above embodiment, the insulating film 130, the AlGaN layer 102, and the GaN layer 101 are removed by dry etching to form the recesses 106 and 109. However, the insulating film 130 is wet etched. The recesses 106 and 109 may be formed by removing the AlGaN layer 102 and the GaN layer 101 by dry etching.

  Further, according to the nitride semiconductor device manufacturing method of the above embodiment, Ti / Al / TiN is laminated to form an ohmic electrode. However, the present invention is not limited to this, and TiN may be omitted, and Ti / Al is laminated. Then, Au, Ag, Pt or the like may be laminated thereon.

  In the above embodiment, the nitride semiconductor device using the Si substrate has been described. However, the present invention is not limited to the Si substrate, and a sapphire substrate or an SiC substrate may be used, and a nitride semiconductor layer is formed on the sapphire substrate or the SiC substrate. The nitride semiconductor layer may be grown on a substrate made of a nitride semiconductor, such as by growing an AlGaN layer on a GaN substrate. In addition, a buffer layer may be formed between the substrate and the nitride semiconductor layer, or a hetero-improvement layer between the first nitride semiconductor layer and the second nitride semiconductor layer of the nitride semiconductor stacked body. May be formed.

  In the above-described embodiment, the recess structure HFET in which the ohmic electrode reaches the GaN layer has been described. However, the present invention is applied to an HFET in which an ohmic electrode serving as a source electrode and a drain electrode is formed on an undoped AlGaN layer without forming a recess. May be applied. In addition, the nitride semiconductor device of the present invention is not limited to an HFET that uses 2DEG, and the same effect can be obtained even with field effect transistors having other configurations.

  In the above embodiment, a normally-on type HFET has been described. However, the present invention may be applied to a normally-off type nitride semiconductor device. Further, the present invention may be applied not only to a Schottky electrode but also to a field effect transistor having an insulated gate structure. The present invention is not limited to a field effect transistor, and may be applied to an ohmic electrode of a Schottky diode.

The nitride semiconductor of the nitride semiconductor device of the present invention may be any material expressed by Al _x In _y Ga _1-xy N (x ≦ 0, y ≦ 0, 0 ≦ x + y ≦ 1).

  Although specific embodiments of the present invention have been described, the present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the present invention.

DESCRIPTION OF SYMBOLS 1,101 GaN layer 2,102 AlGaN layer 3,103 2DEG layer 10 Si substrate 11 Source electrode 12 Drain electrode 13 Gate electrode 15 AlGaN buffer layer 20,120 Nitride semiconductor laminated body 30,130 Insulating film 40 Interlayer insulating film 41 Via 42 Drain electrode pad 106,109 Recessed portion 111,112 Ohmic electrode P1 First chlorine concentration peak P2 Second chlorine concentration peak S1 interface

Claims (4)

A substrate,
A nitride semiconductor multilayer body formed on the substrate and having a heterointerface;
An ohmic electrode made of a TiAl-based material formed at least partially on the nitride semiconductor multilayer body or in the nitride semiconductor multilayer body,
The nitride semiconductor laminate is
A first nitride semiconductor layer formed on the substrate;
A second nitride semiconductor layer formed on the first nitride semiconductor layer and forming a heterointerface with the first nitride semiconductor layer;
In the chlorine concentration distribution in the depth direction from the ohmic electrode made of the TiAl-based material to the nitride semiconductor laminate,
A first chlorine concentration peak at a position near the interface in a region closer to the substrate than the interface between the ohmic electrode and the nitride semiconductor multilayer body;
A second chlorine concentration peak at a position deeper than the first chlorine concentration peak;
The chlorine concentration of the second chlorine concentration peak is
3 × 10 ¹⁶ cm ⁻³ or more and 1.3 × 10 ¹⁷ cm ⁻³ or less. The nitride semiconductor device according to claim 1,
The nitride semiconductor device, wherein the position of the second chlorine concentration peak is a depth of 60 nm or more and 100 nm or less from the interface. The nitride semiconductor device according to claim 1 or 2,
The nitride semiconductor laminate is
Having a recess that penetrates the second nitride semiconductor layer and reaches the two-dimensional electron gas layer near the heterointerface;
A nitride semiconductor device, wherein at least part of the ohmic electrode is embedded in the recess. Forming a nitride semiconductor multilayer body having a heterointerface on a substrate;
Etching the nitride semiconductor laminate with a chlorine-based gas to form a recess reaching the two-dimensional electron gas layer near the heterointerface,
Forming an ohmic electrode made of a TiAl-based material at least partially embedded in the recess;
By annealing the ohmic electrode at 400 ° C. or more and 500 ° C. or less, a first chlorine concentration peak located near the interface in the region closer to the substrate than the interface between the ohmic electrode and the nitride semiconductor multilayer body And is located deeper than the first chlorine concentration peak, and the chlorine concentration is 3 × 10. ¹⁶ cm ^-3 And 1.3 × 10 ¹⁷ cm ^-3 A method for manufacturing a nitride semiconductor device, comprising: obtaining a second chlorine concentration peak as described below.

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