JP5908165B2 - 半導体メモリ回路用の磁気トンネル接合要素を含む調整可能基準回路 - Google Patents

半導体メモリ回路用の磁気トンネル接合要素を含む調整可能基準回路 Download PDF

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JP5908165B2
JP5908165B2 JP2015510502A JP2015510502A JP5908165B2 JP 5908165 B2 JP5908165 B2 JP 5908165B2 JP 2015510502 A JP2015510502 A JP 2015510502A JP 2015510502 A JP2015510502 A JP 2015510502A JP 5908165 B2 JP5908165 B2 JP 5908165B2
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resistance
path
mtj
pair
circuit
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JP2015520908A (ja
JP2015520908A5 (enExample
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シャ・リ
ジュン・ピル・キム
テヒュン・キム
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クアルコム，インコーポレイテッド
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1673—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Hall/Mr Elements (AREA)
JP2015510502A 2012-05-04 2013-05-06 半導体メモリ回路用の磁気トンネル接合要素を含む調整可能基準回路 Expired - Fee Related JP5908165B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/464,242 US9159381B2 (en) 2012-05-04 2012-05-04 Tunable reference circuit
US13/464,242 2012-05-04
PCT/US2013/039656 WO2013166479A1 (en) 2012-05-04 2013-05-06 A tunable reference circuit comprising magnetic tunnel junction elements for a semiconductor memory circuit

Publications (3)

Publication Number Publication Date
JP2015520908A JP2015520908A (ja) 2015-07-23
JP2015520908A5 JP2015520908A5 (enExample) 2016-01-07
JP5908165B2 true JP5908165B2 (ja) 2016-04-26

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JP2015510502A Expired - Fee Related JP5908165B2 (ja) 2012-05-04 2013-05-06 半導体メモリ回路用の磁気トンネル接合要素を含む調整可能基準回路

Country Status (6)

Country Link
US (1) US9159381B2 (enExample)
EP (1) EP2845197B1 (enExample)
JP (1) JP5908165B2 (enExample)
CN (1) CN104272391B (enExample)
IN (1) IN2014MN01960A (enExample)
WO (1) WO2013166479A1 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6191967B2 (ja) * 2012-06-11 2017-09-06 日本電気株式会社 不揮発性論理ゲート素子
US20140327508A1 (en) * 2013-05-06 2014-11-06 Qualcomm Incorporated Inductor tunable by a variable magnetic flux density component
US9336847B2 (en) 2014-04-21 2016-05-10 Qualcomm Incorporated Method and apparatus for generating a reference for use with a magnetic tunnel junction
US9691462B2 (en) 2014-09-27 2017-06-27 Qualcomm Incorporated Latch offset cancelation for magnetoresistive random access memory
JP2018147532A (ja) * 2017-03-03 2018-09-20 ソニーセミコンダクタソリューションズ株式会社 半導体記憶装置及び情報処理装置
US10431278B2 (en) * 2017-08-14 2019-10-01 Qualcomm Incorporated Dynamically controlling voltage for access operations to magneto-resistive random access memory (MRAM) bit cells to account for ambient temperature
US10790016B2 (en) * 2018-03-02 2020-09-29 Western Digital Technologies, Inc. Probabilistic neuron circuits
KR102097204B1 (ko) * 2018-05-04 2020-04-03 한양대학교 산학협력단 다중 기준 저항 레벨을 적용하는 자기 저항 메모리 소자 및 이에 있어서 최적 기준 저항 레벨을 선택하는 방법
CN110910924B (zh) * 2018-09-18 2021-09-14 联华电子股份有限公司 磁阻式随机存取存储器
US10803913B1 (en) * 2019-06-11 2020-10-13 Applied Materials, Inc. Narrow range sense amplifier with immunity to noise and variation
CN114078507A (zh) 2020-08-12 2022-02-22 三星电子株式会社 根据存储器单元的大小生成改善的写入电压的存储器设备
US11854590B2 (en) 2021-04-23 2023-12-26 Applied Materials, Inc. Reference generation for narrow-range sense amplifiers

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6331943B1 (en) * 2000-08-28 2001-12-18 Motorola, Inc. MTJ MRAM series-parallel architecture
US6721203B1 (en) 2001-02-23 2004-04-13 Western Digital (Fremont), Inc. Designs of reference cells for magnetic tunnel junction (MTJ) MRAM
JP4113423B2 (ja) * 2002-12-04 2008-07-09 シャープ株式会社 半導体記憶装置及びリファレンスセルの補正方法
US6807118B2 (en) 2003-01-23 2004-10-19 Hewlett-Packard Development Company, L.P. Adjustable offset differential amplifier
JP4334284B2 (ja) * 2003-06-26 2009-09-30 株式会社東芝 磁気ランダムアクセスメモリ
US7239537B2 (en) 2005-01-12 2007-07-03 International Business Machines Corporation Method and apparatus for current sense amplifier calibration in MRAM devices
US7321507B2 (en) * 2005-11-21 2008-01-22 Magic Technologies, Inc. Reference cell scheme for MRAM
JP5044432B2 (ja) * 2008-02-07 2012-10-10 株式会社東芝 抵抗変化メモリ
JP5676842B2 (ja) * 2008-05-30 2015-02-25 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置
US7813166B2 (en) 2008-06-30 2010-10-12 Qualcomm Incorporated Controlled value reference signal of resistance based memory circuit
US8203862B2 (en) 2008-10-10 2012-06-19 Seagate Technology Llc Voltage reference generation with selectable dummy regions
US7881094B2 (en) 2008-11-12 2011-02-01 Seagate Technology Llc Voltage reference generation for resistive sense memory cells
KR20100094167A (ko) 2009-02-18 2010-08-26 삼성전자주식회사 메모리 장치 및 이를 포함하는 모바일 장치
US8724414B2 (en) * 2010-02-09 2014-05-13 Qualcomm Incorporated System and method to select a reference cell
JP2012027974A (ja) 2010-07-22 2012-02-09 Panasonic Corp 半導体記憶装置

Also Published As

Publication number Publication date
US9159381B2 (en) 2015-10-13
CN104272391B (zh) 2018-04-27
EP2845197B1 (en) 2018-06-13
EP2845197A1 (en) 2015-03-11
JP2015520908A (ja) 2015-07-23
WO2013166479A1 (en) 2013-11-07
US20130293286A1 (en) 2013-11-07
IN2014MN01960A (enExample) 2015-07-10
CN104272391A (zh) 2015-01-07

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