IN2014MN01960A - - Google Patents
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- Publication number
- IN2014MN01960A IN2014MN01960A IN1960MUN2014A IN2014MN01960A IN 2014MN01960 A IN2014MN01960 A IN 2014MN01960A IN 1960MUN2014 A IN1960MUN2014 A IN 1960MUN2014A IN 2014MN01960 A IN2014MN01960 A IN 2014MN01960A
- Authority
- IN
- India
- Prior art keywords
- path
- mtj
- resistance
- circuit
- reference pair
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1673—Reading or sensing circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5642—Sensing or reading circuits; Data output circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Mram Or Spin Memory Techniques (AREA)
- Hall/Mr Elements (AREA)
Abstract
A circuit includes a first reference pair that includes a first path and a second path. The first path includes a first magnetic tunnel junction (MTJ) element and the second path includes a second MTJ element. The circuit further includes a second reference pair that includes a third path and a fourth path. The third path includes a third MTJ element and the fourth path includes a fourth MTJ element. The first reference pair and the second reference pair are tied together in parallel. A reference resistance of the circuit is based on a resistance of each of the first second third and fourth MTJ elements. The reference resistance of the circuit is adjustable by adjusting a resistance of one of the MTJ elements.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/464,242 US9159381B2 (en) | 2012-05-04 | 2012-05-04 | Tunable reference circuit |
PCT/US2013/039656 WO2013166479A1 (en) | 2012-05-04 | 2013-05-06 | A tunable reference circuit comprising magnetic tunnel junction elements for a semiconductor memory circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
IN2014MN01960A true IN2014MN01960A (en) | 2015-07-10 |
Family
ID=48521406
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IN1960MUN2014 IN2014MN01960A (en) | 2012-05-04 | 2013-05-06 |
Country Status (6)
Country | Link |
---|---|
US (1) | US9159381B2 (en) |
EP (1) | EP2845197B1 (en) |
JP (1) | JP5908165B2 (en) |
CN (1) | CN104272391B (en) |
IN (1) | IN2014MN01960A (en) |
WO (1) | WO2013166479A1 (en) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6191967B2 (en) * | 2012-06-11 | 2017-09-06 | 日本電気株式会社 | Nonvolatile logic gate device |
US20140327508A1 (en) * | 2013-05-06 | 2014-11-06 | Qualcomm Incorporated | Inductor tunable by a variable magnetic flux density component |
US9336847B2 (en) | 2014-04-21 | 2016-05-10 | Qualcomm Incorporated | Method and apparatus for generating a reference for use with a magnetic tunnel junction |
US9691462B2 (en) * | 2014-09-27 | 2017-06-27 | Qualcomm Incorporated | Latch offset cancelation for magnetoresistive random access memory |
JP2018147532A (en) * | 2017-03-03 | 2018-09-20 | ソニーセミコンダクタソリューションズ株式会社 | Semiconductor memory device and information processing device |
US10431278B2 (en) * | 2017-08-14 | 2019-10-01 | Qualcomm Incorporated | Dynamically controlling voltage for access operations to magneto-resistive random access memory (MRAM) bit cells to account for ambient temperature |
US10790016B2 (en) * | 2018-03-02 | 2020-09-29 | Western Digital Technologies, Inc. | Probabilistic neuron circuits |
KR102097204B1 (en) * | 2018-05-04 | 2020-04-03 | 한양대학교 산학협력단 | Magnetoresistive memory device using multiple reference resistance levels and method of selecting optimal reference resistance level in the same |
CN110910924B (en) * | 2018-09-18 | 2021-09-14 | 联华电子股份有限公司 | Magnetoresistive random access memory |
US10803913B1 (en) * | 2019-06-11 | 2020-10-13 | Applied Materials, Inc. | Narrow range sense amplifier with immunity to noise and variation |
KR20220021075A (en) | 2020-08-12 | 2022-02-22 | 삼성전자주식회사 | Memory device which generates optimal program voltage according to size of memory cell |
US11854590B2 (en) | 2021-04-23 | 2023-12-26 | Applied Materials, Inc. | Reference generation for narrow-range sense amplifiers |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6331943B1 (en) * | 2000-08-28 | 2001-12-18 | Motorola, Inc. | MTJ MRAM series-parallel architecture |
US6721203B1 (en) | 2001-02-23 | 2004-04-13 | Western Digital (Fremont), Inc. | Designs of reference cells for magnetic tunnel junction (MTJ) MRAM |
JP4113423B2 (en) * | 2002-12-04 | 2008-07-09 | シャープ株式会社 | Semiconductor memory device and reference cell correction method |
US6807118B2 (en) | 2003-01-23 | 2004-10-19 | Hewlett-Packard Development Company, L.P. | Adjustable offset differential amplifier |
JP4334284B2 (en) * | 2003-06-26 | 2009-09-30 | 株式会社東芝 | Magnetic random access memory |
US7239537B2 (en) | 2005-01-12 | 2007-07-03 | International Business Machines Corporation | Method and apparatus for current sense amplifier calibration in MRAM devices |
US7321507B2 (en) * | 2005-11-21 | 2008-01-22 | Magic Technologies, Inc. | Reference cell scheme for MRAM |
JP5044432B2 (en) * | 2008-02-07 | 2012-10-10 | 株式会社東芝 | Resistance change memory |
JP5676842B2 (en) * | 2008-05-30 | 2015-02-25 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | Semiconductor device |
US7813166B2 (en) | 2008-06-30 | 2010-10-12 | Qualcomm Incorporated | Controlled value reference signal of resistance based memory circuit |
US8203862B2 (en) | 2008-10-10 | 2012-06-19 | Seagate Technology Llc | Voltage reference generation with selectable dummy regions |
US7881094B2 (en) | 2008-11-12 | 2011-02-01 | Seagate Technology Llc | Voltage reference generation for resistive sense memory cells |
KR20100094167A (en) | 2009-02-18 | 2010-08-26 | 삼성전자주식회사 | Memory device and mobile device including the same |
US8724414B2 (en) * | 2010-02-09 | 2014-05-13 | Qualcomm Incorporated | System and method to select a reference cell |
JP2012027974A (en) | 2010-07-22 | 2012-02-09 | Panasonic Corp | Semiconductor memory device |
-
2012
- 2012-05-04 US US13/464,242 patent/US9159381B2/en active Active
-
2013
- 2013-05-06 IN IN1960MUN2014 patent/IN2014MN01960A/en unknown
- 2013-05-06 WO PCT/US2013/039656 patent/WO2013166479A1/en active Application Filing
- 2013-05-06 CN CN201380023029.5A patent/CN104272391B/en not_active Expired - Fee Related
- 2013-05-06 JP JP2015510502A patent/JP5908165B2/en not_active Expired - Fee Related
- 2013-05-06 EP EP13725237.5A patent/EP2845197B1/en not_active Not-in-force
Also Published As
Publication number | Publication date |
---|---|
JP2015520908A (en) | 2015-07-23 |
CN104272391A (en) | 2015-01-07 |
WO2013166479A1 (en) | 2013-11-07 |
EP2845197A1 (en) | 2015-03-11 |
US9159381B2 (en) | 2015-10-13 |
JP5908165B2 (en) | 2016-04-26 |
CN104272391B (en) | 2018-04-27 |
EP2845197B1 (en) | 2018-06-13 |
US20130293286A1 (en) | 2013-11-07 |
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