JP4334284B2 - Magnetic random access memory - Google Patents

Description

【０２７５】
▲８▼ 動作波形例
図２６は、図１８の書き込みワード線ドライバ／シンカーの動作波形例を示している。
【０２７６】
書き込み信号ＷＲＩＴＥが“Ｈ”になると、これを受けて、書き込みワード線ドライブ信号ＷＷＬＤＲＶ及び書き込みワード線シンク信号ＷＷＬＳＮＫが“Ｈ”になる。書き込みワード線ドライブ信号ＷＷＬＤＲＶ及び書き込みワード線シンク信号ＷＷＬＳＮＫを“Ｈ”にするタイミングは、制御信号ＷＳ＜０＞〜ＷＳ＜３＞，／ＷＳ＜０＞〜／ＷＳ＜３＞により制御される。
【０２７７】
書き込み信号ＷＲＩＴＥが“Ｌ”になると、これを受けて、まず、書き込みワード線ドライブ信号ＷＷＬＤＲＶが“Ｌ”になる。そして、それから図２０の遅延回路ＷＤＬ４の遅延時間により決まる一定期間が経過した後、書き込みワード線シンク信号ＷＷＬＳＮＫが“Ｌ”になる。この一定期間は、書き込み動作終了後、書き込みワード線ＷＷＬｉの電位を０Ｖにするための期間である。
【０２７８】
図２７は、図１９の書き込みビット線ドライバ／シンカーの動作波形例を示している。
【０２７９】
書き込み信号ＷＲＩＴＥが“Ｈ”になると、これを受けて、書き込みビット線ドライブ信号ＷＢＬＤＲＶ及び書き込みビット線シンク信号ＷＢＬＳＮＫが“Ｈ”になる。書き込みビット線ドライブ信号ＷＢＬＤＲＶ及び書き込みビット線シンク信号ＷＢＬＳＮＫを“Ｈ”にするタイミングは、制御信号ＢＳ＜０＞〜ＢＳ＜３＞，／ＢＳ＜０＞〜／ＢＳ＜３＞により制御される。
【０２８０】
書き込み信号ＷＲＩＴＥが“Ｌ”になると、これを受けて、まず、書き込みビット線ドライブ信号ＷＢＬＤＲＶが“Ｌ”になる。そして、それから図２１の遅延回路ＢＤＬ４の遅延時間により決まる一定期間が経過した後、書き込みビット線シンク信号ＷＢＬＳＮＫが“Ｌ”になる。この一定期間は、書き込み動作終了後、書き込みビット線ＷＢＬｉの電位を０Ｖにするための期間である。
【０２８１】
▲９▼ まとめ
以上、説明したように、本例の磁気ランダムアクセスメモリによれば、書き込みワード／ビット線に対する書き込み電流の電流波形（大きさ）を、チップごと、又は、メモリセルアレイごとに、プログラミングにより設定できる。また、書き込みワード線電流の電流波形と書き込みビット線電流の電流波形を、互いに独立に、決定できる。さらに、書き込みビット線電流に関しては、書き込みデータの値（書き込み電流の向き）に対しても、個別に、書き込みビット線電流の電流波形を決定できる。
【０２８２】
６． 第６実施の形態
次に、本発明の第６実施の形態に関わるデータ読み出し方法について説明する。
【０２８３】
図２８は、本発明の第１実施の形態に関わる読み出し回路を利用した読み出し方法の例を示している。
【０２８４】
この読み出し方法では、まず、メモリセル及び複数のレファレンスセルを構成する複数のＭＴＪ素子の特性を検査する（ステップＳＴ１）。次に、複数のＭＴＪ素子の特性に基づいて、複数のレファレンスセルの各々に、個別に、“０”データ又は“１”データを書き込む（ステップＳＴ２）。
【０２８５】
ここで、例えば、複数のレファレンスセルのうち、“０”データが書き込まれるセルの数と“１”データが書き込まれるセルの数とは、同数の場合もあるし、異なる場合もある。
【０２８６】
そして、選択されたメモリセルのデータを読み出す際には、これら複数のレファレンスセルを用いてレファレンス電流／電位を生成し、データ値を判定する際の基準とする（ステップＳＴ３）。
【０２８７】
なお、図２９に示すように、メモリセルのデータを読み出す際に、アドレス信号に基づいて、複数のレファレンスセルのうちから少なくとも１つのセル（複数又は全てのセルでもよい）をアクセスし、アクセスされたレファレンスセルに基づいて、レファレンス電流／電位を生成してもよい（ステップＳＴ２’）。
【０２８８】
図３０は、本発明の第２実施の形態に関わる読み出し回路を利用した読み出し方法の例を示している。
【０２８９】
この読み出し方法では、まず、メモリセル、複数のレファレンスセル及び複数のダミーセルを構成する複数のＭＴＪ素子の特性を検査する（ステップＳＴ１）。次に、複数のＭＴＪ素子の特性に基づいて、複数のレファレンスセル及び複数のダミーセルの各々に対して、個別に、“０”データ又は“１”データを書き込む（ステップＳＴ２）。
【０２９０】
この後、アドレス信号に基づいて、複数のレファレンスセルのうちから少なくとも１つのセル（複数又は全てのセルでもよい）をアクセスし、アクセスされたレファレンスセルに基づいて、レファレンス電流／電位を生成する（ステップＳＴ２’）。
【０２９１】
この時、レファレンスセル側の各ＭＴＪ素子に流れる電流とメモリセル側の各ＭＴＪ素子に流れる電流とを合わせるため、ダミーセルに対するアクセス動作を行い、レファレンスセル側の電流駆動力とメモリセル側の電流駆動力との調整を図る（ステップＳＴ２”）。
【０２９２】
そして、このようにして生成されたレファレンス電流／電位を、メモリセルのデータ値を判定する際の基準とする（ステップＳＴ３）。
【０２９３】
なお、本例の読み出し方法の場合、各ＭＴＪ素子に流れる電流値をほぼ等しくするため、メモリセルとそれに並列接続されたダミーセルの合計数が、複数のレファレンスセルのうちアクセスされるセルの数に等しくなるようにする。
【０２９４】
図３１は、本発明の第３実施の形態に関わる読み出し回路を利用した読み出し方法の例を示している。
【０２９５】
この読み出し方法では、まず、メモリセル、複数のレファレンスセル及び複数のダミーセルを構成する複数のＭＴＪ素子の特性を検査する（ステップＳＴ１）。次に、複数のＭＴＪ素子の特性に基づいて、複数のレファレンスセル、複数のダミーセル及び電流源内の複数のＭＴＪ素子の各々に対して、個別に、“０”データ又は“１”データを書き込む（ステップＳＴ２）。
【０２９６】
この後、アドレス信号に基づいて、電流源内の複数のＭＴＪ素子に対するアクセス動作を行う（ステップＳＴ２ａ）。
【０２９７】
また、複数のレファレンスセルのうちから少なくとも１つのセルをアクセスし、アクセスされたレファレンスセルに基づいて、レファレンス電流／電位を生成する（ステップＳＴ２’）。また、ダミーセルに対するアクセス動作を行い、レファレンスセル側の電流駆動力とメモリセル側の電流駆動力との調整を図る（ステップＳＴ２”）。
【０２９８】
そして、このようにして生成されたレファレンス電流／電位を、メモリセルのデータ値を判定する際の基準とする（ステップＳＴ３）。
【０２９９】
７． その他
このように、本発明の例に関わる磁気ランダムアクセスメモリによれば、アクセス時に、選択されたメモリセル（データセル）以外のセル、例えば、レファレンスセルにもアクセスし、書き込み動作、読み出し動作や、モニタ動作などを行うことができる。
【０３００】
また、読み出し動作時に、データ値の判定の基準となるレファレンス電流／電圧を生成する元となる複数のレファレンスセルについては、“１”状態のものと“０”状態のものとが同数である必要がなく、例えば、ＭＴＪ素子の抵抗値のばらつきに応じて、最適なレファレンス電流／電圧を生成できるように、“１”状態のものと“０”状態のものとの割合を任意に決定できる。
【０３０１】
さらに、素子の微細化により、ＭＴＪ素子の抵抗値が上昇しても、メモリセル（ＭＴＪ素子）とは異なるダミーセル（ＭＴＪ素子）を駆動することにより、ビット線やデータ線に対する駆動能力を上げることができる。
【０３０２】
また、セル電流をモニタするためのモニタ回路を読み出し回路内に設けているため、予め、メモリセルのセル電流をモニタしておくことができる。ＭＴＪ素子に与える読み出し電流を生成する電流源についても、ＭＴＪ素子から構成することができる。電流源内のＭＴＪ素子については、各々、独立に、データ書き込みができる。
【０３０３】
なお、この発明は、上記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で、構成要素を変形して具体化できる。また、上記実施の形態に開示されている複数の構成要素の適宜な組み合せにより種々の発明を構成できる。例えば、上記実施の形態に開示される全構成要素から幾つかの構成要素を削除してもよいし、異なる実施の形態の構成要素を適宜組み合わせてもよい。
【０３０４】
【発明の効果】
以上、説明したように、本発明の磁気ランダムアクセスメモリによれば、ＭＴＪ素子のトンネル絶縁膜に厚さのばらつきが生じても、最適なレファレンス電圧を生成でき、また、ＭＴＪ素子の微細化によってその抵抗値が増大しても、読み出し速度の低下がなく、さらに、ＭＴＪ素子に対する最適な書き込み電流の値、供給タイミングを見出すことができる。
【図面の簡単な説明】
【図１】本発明の第１実施の形態に関わる読み出し回路の主要部を示す図。
【図２】図１の読み出し回路の応用例を示す図。
【図３】アドレスコンパレータの例を示す図。
【図４】デコーダ＜ｊ＞の例を示す図。
【図５】デコーダ＜ＢＬｉ＞の例を示す図。
【図６】図３のアドレスコンパレータの回路例を示す図。
【図７】オペアンプの回路例を示す図。
【図８】センスアンプの回路例を示す図。
【図９】本発明の第２実施の形態に関わる読み出し回路の主要部を示す図。
【図１０】図９の読み出し回路の変形例を示す図。
【図１１】本発明の第３実施の形態に関わる電流源を示す図。
【図１２】本発明の第４実施の形態に関わる読み出し回路の主要部を示す図。
【図１３】ＮＡＮＤ型フラッシュメモリの動作例を示す図。
【図１４】ＮＡＮＤ型フラッシュメモリの動作例を示す図。
【図１５】ＲＤＲＡＭの動作例を示す図。
【図１６】本発明の第５実施の形態に関わるＭＲＡＭの概要を示す図。
【図１７】メモリセルアレイの回路例を示す図。
【図１８】書き込みワード線ドライバの回路例を示す図。
【図１９】書き込みビット線ドライバ／シンカーの回路例を示す図。
【図２０】書き込み電流制御回路の回路例その１を示す図。
【図２１】書き込み電流制御回路の回路例その２を示す図。
【図２２】設定回路の回路例を示す図。
【図２３】レジスタ＜ｊ＞の回路例を示す図。
【図２４】Ｖｃｌａｍｐ生成回路の回路例を示す図。
【図２５】デコーダRP＜0＞〜RP＜3＞，CP＜0＞〜CP＜7＞の回路例を示す図。
【図２６】図１６のＭＲＡＭの動作波形の例を示す図。
【図２７】図１６のＭＲＡＭの動作波形の例を示す図。
【図２８】本発明の第６実施の形態に関わる読み出し方法を示す図。
【図２９】本発明の第６実施の形態に関わる読み出し方法を示す図。
【図３０】本発明の第６実施の形態に関わる読み出し方法を示す図。
【図３１】本発明の第６実施の形態に関わる読み出し方法を示す図。
【図３２】センス回路をモデル化した図。
【符号の説明】
１： アドレスコンパレータ、 ２： デコーダ、 １０： レファレンス電位生成回路、 １１： ＭＲＡＭ、 １２： メモリセルアレイ、 １３： レファレンスセルアレイ： １４： ロウデコーダ＆ワード線ドライバ、 １５：ロウデコーダ＆ワード線ドライバ／シンカー、 １６Ａ，１６Ｂ，１７Ａ，１７Ｂ： カラムデコーダ＆ビット線ドライバ／シンカー、 １８： アドレスレシーバ、 １９： データ入力レシーバ、 ２０： センスアンプ、 ２１： データ出力ドライバ、 ２２： 制御回路、 ２３： 設定回路、 ２４： 書き込み電流制御回路、 ＣＳ１： バイアス電流供給回路、 ＯＰ１，ＯＰ２：オペアンプ、 Ｓ／Ａ： センスアンプ、 ＱＰ１，・・・ＱＰ１０： ＰチャネルＭＯＳトランジスタ、 ＱＮ１，・・・ＱＮ１２： ＮチャネルＭＯＳトランジスタ、 ＭＣ： メモリセル、 ＲＣ： レファレンスセル、 Ｉ１： 電流源、 ＡＤ＜ＢＬｉ＞，ＡＤ＜０＞，・・・ＡＤ＜７＞： アンド回路、 ＲＳＴ： 読み出し選択トランジスタ。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a magnetic random access memory (MRAM) that uses a magnetoresistive effect.
[0002]
[Prior art]
Conventionally, a magnetic random access memory using a tunneling magnetoresistive (TMR) has been proposed by, for example, Roy Scheuerlein et.al (see Non-Patent Document 1).
[0003]
An MTJ (Magnetic Tunnel Junction) element exhibiting TMR has a structure in which a thin insulator is disposed between two magnetic bodies. Here, the MTJ element can take two states. One is the case where the magnetizations of the two magnetic bodies are oriented in the same direction, which is defined as a parallel state. The other one is a case where the magnetizations of the two magnetic bodies are opposite to each other, and this is defined as an antiparallel state.
[0004]
When the magnetization direction of the MTJ element is in the parallel state, the resistance value of the insulator when the tunnel current flows through the insulator is the lowest, and this is defined as, for example, the “1” state. When the magnetization direction of the MTJ element is in the antiparallel state, the resistance value of the insulator when the tunnel current flows through the insulator is the highest, and this is defined as, for example, the “0” state.
[0005]
When data is written to the MTJ element arranged at the intersection of the selected word line and the selected data selection line, for example, a write current having a fixed direction is supplied to the selected word line to select the selected data A write current having a direction corresponding to write data is supplied to the selection line.
[0006]
As a result, a magnetic field generated by a write current flowing through these word lines and data selection lines acts on the MTJ element, and the strength of the magnetic field exceeds the magnetization reversal threshold value of the storage layer of the MTJ element, and data is stored in the MTJ element. Written.
[0007]
On the other hand, when reading data stored in the MTJ element, a read current may be passed through the MTJ element to read the resistance value of the MTJ element.
[0008]
(1) Reference current / voltage
In the magnetic random access memory of Non-Patent Document 1, 1-bit data is stored in two cells. On the other hand, in dynamic RAM, flash memory, etc., 1-bit data is stored in one cell. Therefore, if the same CMOS process is used, the latter memory can secure a larger memory capacity than that of the former.
[0009]
For this reason, in the field of magnetic random access memory, a technique for storing 1-bit data in one cell has been proposed by, for example, Peter K. Naji et.al (see Non-Patent Document 2). .
[0010]
According to this technique, when reading cell data, it is necessary to generate a reference current / voltage that serves as a reference for determining a data value.
[0011]
First, a bias voltage Vbiasref is generated based on the original voltage Vbias using a bias voltage generator (Self-Calibrating Reference Bias Voltage Generator). The bias voltage Vbiasref is generated from an MTJ element having a resistance value Rmax (“1” state) and an MTJ element having a resistance value Rmin (“0” state).
[0012]
Vbiasref = (Vbias / 2) × (1 + Rmin / Rmax)
Here, when the reference cell is in the “0” state (resistance value Rmin), the reference current Iref shown below flows through the reference cell.
Iref = Vbiasref / Rmin
= (Vbias / 2) × (1 / Rmin + 1 / Rmax)
= 1/2 x (Vbias / Rmin + Vbias / Rmax)
On the other hand, when the memory cell is in the “1” state (resistance value Rmax), the current Imin shown below flows through the memory cell.
Imin = Vbias / Rmax
When the memory cell is in the “0” state (resistance value Rmin), a current Imax shown below flows through the memory cell.
Imax = Vbias / Rmin
Since the value of the reference current Iref is half of Imax and Imin, it serves as a reference for data determination at the time of reading.
[0013]
There is one problem here. Since the MTJ element has a structure in which a current flows through an insulator as a tunnel insulating film, the resistance value changes exponentially with the change in the thickness of the tunnel insulating film.
[0014]
That is, even if the reference potential is generated based on Non-Patent Document 2, if the read principle based on the differential sense amplifier method using the reference potential used in the NOR type flash memory is employed, the tunnel of the MTJ element is used. Due to the variation in the thickness of the insulating film, the resistance value of the MTJ element may vary, and data may not be read.
[0015]
Therefore, in order to prevent this, for example, a half (margin) of the resistance variation ΔR of the MTJ element determined by the magnetoresistive change rate (MR ratio: Magneto Resistive ratio) due to TMR is used as the resistance of the reference cell and the memory cell in the same state. It must be greater than the value variation.
[0016]
However, generally, since the MR ratio is 20 to 40%, there is a possibility that a sufficient margin cannot be secured in consideration of the manufacturing margin, the yield, etc. in the mass production stage.
[0017]
For example, when the resistance values Rmin and Rmax of the reference cell in the bias voltage generator (Self-Calibrating Reference Bias Voltage Generator) in Non-Patent Document 2 are different from the resistance value R′min of the memory cell in the “0” state. Is assumed.
[0018]
R′min> 10 × Rmax
R′min <10 × Rmin
In general, an MR ratio of about 20 to 40% cannot serve as a reference.
[0019]
As Rmin <R′min <Rmax,
When R′min = Rmin + δRmin,
Iref = Vbiasref / R'min
= Vbias / 2 x (1 / Rmin + 1 / Rmax)
X Rmin / R'min
= 1/2 x (Vbias / Rmin + Vbias / Rmax)
X Rmin / R'min
= 1/2 x (Vbias / Rmin + Vbias / Rmax)
X 1 / (1 + δRmin / Rmin)
[0020]
When MR ratio is expressed as “MR”,
Since Rmax = Rmin × (1 + MR),
Imin = Vbias / Rmax
= Vbias / Rmin x 1 / (1 + MR)
Imax = Vbias / Rmin
Iref
= 1/2 x (Vbias / Rmin + Vbias / Rmax)
× 1 / (1 + δRmin / Rmin)
= 1/2 * Vbias / Rmin * (1 + 1 / (1 + MR))
× 1 / (1 + δRmin / Rmin)
= Vbias / Rmin × 1 / (1 + MR) × (1 + MR / 2)
× 1 / (1 + δRmin / Rmin).
[0021]
Accordingly, when a variation in resistance value occurs between the memory cell and the reference cell by more than half the amount of change in the resistance value of the memory cell (MTJ element) determined by the magnetoresistance change rate (MR ratio) due to TMR (MR / 2 <ΔRmin / Rmin), it becomes impossible to compare the memory cell having the resistance value Rmax and the reference cell. In such a case, the memory cell having the resistance value Rmin cannot be compared with the reference cell.
[0022]
In particular,
1 / (1 + MR) × (1 + MR / 2)
X 1 / (1 + δRmin / Rmin)) <1
That means
MR / 2 × 1 / (1 + MR)> | δRmin / Rmin |
It is necessary to satisfy. If the MR ratio is in the range of 20 to 40%, the variation in the resistance value needs to be less than 8.3 to 14.2% of the variation amount of the resistance value determined by the MR ratio.
[0023]
(2) Bias voltage
The MR ratio has a characteristic of decreasing as the potential difference applied between both terminals of the MTJ element increases. This characteristic has been confirmed, for example, by M. Durlam et.al (see Non-Patent Document 3).
[0024]
Considering this, the optimum value of the bias voltage for the MTJ element is obtained.
[0025]
The bias current for the MTJ element is Ic, the resistance value of the MTJ element in the “0” state is Rc (0), the resistance value of the MTJ element in the “1” state is Rc (1), and the bias current Ic is given. The potential difference generated between both terminals of the MTJ element in the “0” state is sometimes V (0), and the potential difference generated between both terminals of the MTJ element in the “1” state when the bias current Ic is applied is V (1). Then,
V (1) = Ic x Rc (1), V (0) = Ic x Rc (0)
It becomes.
[0026]
Also, the bias voltage dependence of MR ratio is
MR (V) = MR (0) −k × V
(Where V is the bias voltage applied to the MTJ element, MR (V) is the MR ratio when the bias voltage V is applied to the MTJ element, MR (0) is the MR ratio of the MTJ element in the “0” state, MR (1) is the MR ratio of the MTJ element in the “1” state, and k is a constant.)
And
V (1) = Ic x Rc (1) = Ic x Rc (0) x {1 + MR (V)}
= Ic x Rc (0) x {1 + MR (0)-k x V (1)}
It becomes.
[0027]
Therefore,
From V (1) = {1 + MR (0)} ÷ [k + 1 / {Ic × Rc (0)}]
Finding Ic that maximizes V (1)-V (0),
d {V (1) −V (0)} / dIc
= [1 + MR (0) − {Ic × Rc (0) × k + 1} 2] × Rc ÷ {Ic × Rc (0) × k + 1} 2
Than,
Ic = [√ {1 + MR (0)} − 1] / {Rc (0) × k}
It becomes.
[0028]
There is currently no report that MR (0) has exceeded 0.5.
√ {1 + MR (0)} − 1 Approximate to MR (0) / 2. MR is Vh = MR (0) / (2 × k), where Vh is a voltage that is half of MR (0).
[0029]
That means
Ic = [√ {1 + MR (0)} − 1] / {Rc (0) × k} ≒ Vh / Rc (0)
It becomes.
[0030]
Therefore, it is desirable that the bias voltage be near Vh.
[0031]
For example, in the circuit disclosed in Non-Patent Document 4, if the resistance of the MOS transistor is sufficiently smaller than the resistance of the MTJ element, the value of the bias voltage is set to Vh.
[0032]
In this circuit, a bias voltage is generated using a reference cell (MTJ element) and an operational amplifier. However, if the resistance value of the reference cell varies, the bias voltage for the memory cell does not become Vh. If the symbols used in Non-Patent Document 4 are used, the voltage values of SL and bSL will deviate from Vh.
[0033]
For example, as the bias voltage increases, the MR ratio decreases and the signal difference between “1” and “0” also decreases. Further, when the bias voltage is lowered, the difference in bias voltage is reduced, so that the read margin is lowered.
[0034]
(3) Bias current
As for the bias current for the MTJ element, the sense circuit is modeled with a simple configuration as shown in FIG. That is, the difference between the load resistance R1 and the resistance Rc of the memory cell (MTJ element) is read as the output voltage Vo. According to the following consideration, it can be seen that the signal difference between “1” and “0” can be increased by setting the load resistance R1 to the same level as the resistance Rc of the memory cell.
[0035]
In the circuit in Non-Patent Document 4, a constant current source corresponds to this load resistance. Here, when this constant current source is composed of an MTJ element, the area efficiency is improved. For example, this constant current source is composed of one MTJ element and a current mirror circuit.
[0036]
However, as in the above discussion, when the constant current source is composed of one MTJ element, when the resistance value of the one MTJ element is deviated from the resistance value of the memory cell (MTJ element), the signal voltage difference is It becomes smaller than the ideal value. For example, when this constant current source is laid out in a region different from the region where the memory cell array is arranged, there is a possibility that the resistance value of the MTJ element may differ due to processing variations such as lithography.
[0037]
For example, in the circuit shown in FIG. 32, the value of Rl is determined such that the difference between Vo (1) and Vo (0) is large.
[0038]
Here, Vo (1) is the output voltage when the MTJ element is in the “1” state, Vo (0) is the output voltage when the MTJ element is in the “0” state, and Rc (1) is “1”. The resistance value Rc (0) of the MTJ element in the state is the resistance value of the MTJ element in the “0” state.
[0039]
Vo (1) = Vc x Rc (1) / [Rc (1) + Rl]
Vo (0) = Vc x Rc (0) / [Rc (0) + Rl]
Vo (1) −Vo (0) = Vc × {Rc (1) / [Rc (1) + Rl] −Rc (0) / [Rc (0) + Rl]}
Therefore,
d [Vo (1) −Vo (0)] / dRl =
Vc × {Rc (0) / [Rc (0) + Rl] ^ 2−Rc (1) / [Rc (1) + Rl] ^ 2}
= Vc × Rc (0) × Rc (1) × [Rc (1) Rc (0) −Rl ^ 2}
× [Rc (1) −Rc (0)] / [{[Rc (0) + Rl] ^ 2} × {[Rc (1) + Rl] ^ 2}]
From Rc (1)> Rc (0), Vo (1)> Vo (0)> 0. From the condition of Rl> 0, Rl where Vo (1) −Vo (0) is the largest is
Rl = √ (Rc (1) x Rc (0)
It becomes.
[0040]
At this time,
Vo (1) −Vo (0) = Vc × {1 / [1 + Rl / Rc (1)] − 1 / [1 + Rl / Rc (0)]}
= Vc x {1 / [1 + √ {Rc (0) / Rc (1)}]-1 / [1 + √ {Rc (1) / Rc (0)}]}
= Vc x [Rc (1) -Rc (0)] / [√Rc (1) + √Rc (0)] ^ 2
It becomes.
[0041]
Substituting Rc (0) = Rc, Rc (1) = Rc + ΔRc,
Rl = √ [Rc × (Rc + ΔRc)]
From ΔRc <Rc, approximating √
Rl = Rc × √ (1 + ΔRc / Rc)
≒ Rc × (1 + ΔRc / 2 × Rc)
= Rc + ΔRc / 2 ⇒ Intermediate value between Rc (1) and Rc (0)
Vo (1) −Vo (0) = Vc × ΔRc / [2Rc + ΔRc + 2Rc × √ (1 + ΔRc / Rc)]
≒ Vc × ΔRc / [2 × (2 × Rc + ΔRc)]
It becomes.
[0042]
As described above, the reason why the reference cell and the constant current source are used and the MTJ element is used to set the bias voltage value is that the resistance and MR ratio of the MTJ element have temperature dependency and bias dependency. In addition, the MTJ element has a characteristic greatly different from that of the MOS transistor. The temperature dependency of the MR ratio is described in Non-Patent Document 3, for example.
[0043]
(4) Parasitic capacitance
The thickness of the tunnel insulating film of the MTJ element is only about several nm. That is, the thickness of the tunnel insulating film is not 10 times the size of the molecules of the material constituting the tunnel insulating film, but is about several times higher, and it is difficult to further reduce the thickness. Since the size of the MTJ element tends to be reduced by the miniaturization technique, if the thinning of the tunnel insulating film cannot be realized, the resistance of the MTJ element increases due to the miniaturization.
[0044]
By reading, a read potential appears on the bit line. This potential is determined by the value of the read current and the resistance value of the memory cell (MTJ element). The time until the potential is stabilized roughly increases in proportion to the product of the resistance of the MTJ element and the parasitic capacitance of the wiring related to reading such as a bit line.
[0045]
Since the parasitic capacitance has a shorter distance between wirings due to miniaturization, if the wiring width does not change, the capacitance per unit length tends to increase. In addition, although it is conceivable that the width of the bit line becomes narrow due to miniaturization, in the case of a magnetic random access memory, a current of about several mA is passed through the bit line in order to generate a magnetic field for writing. There is a need. That is, in consideration of electromigration, when the line width is reduced, it is necessary to increase the thickness of the line.
[0046]
Therefore, in the magnetic random access memory, the parasitic capacitance per unit length further increases due to miniaturization.
[0047]
[Patent Document 1]
USP6,081,445, "Method to Write / Read MRAM Arrays"
[0048]
[Non-Patent Document 1]
ISSCC2000 Technical Digest p.128, `` A 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell ''
[0049]
[Non-Patent Document 2]
ISSCC2001 Technical Digest p.122, “A 256kb 3.0V 1T1MTJ Nonvolatile Magnetoresistive RAM”
[0050]
[Non-Patent Document 3]
ISSCC2000 Technical Digest p.130 `` Nonvolatile RAM based on Magnetic Tunnel Junction Elements '', Slide Supplement (p.96)
[0051]
[Non-Patent Document 4]
Roy Scheuerlein et.al, `` A 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell '', Figure 7.2.5
[0052]
[Problems to be solved by the invention]
The present invention has been made to solve the above-described problems, and an object of the present invention is to generate an optimum reference voltage even when a thickness variation occurs in the tunnel insulating film of the MTJ element. Even if the resistance value increases due to miniaturization, the read speed is not lowered, and the optimum write current value and supply timing for the MTJ element are found.
[0053]
[Means for Solving the Problems]
  In the example of the present inventionBe involvedMagnetic random access memory is composed of magnetoresistive effect elements.The first and second states can be taken and connected between the first node and the first power supply terminal.A memory cell and a magnetoresistive element,A first state and a second state, wherein the second node and the first power supply terminal are connected in parallel;For making a reference for judging data of the memory celln (n is a plurality)Reference cell andA first clamp circuit for clamping the first node to a predetermined potential; a second clamp circuit for clamping the second node to a predetermined potential; and between the first node and a second power supply terminal. The first MOS transistor to be connected, the second MOS transistor connected between the second node and the second power supply terminal, and the first and second MOS transistors constitute a current mirror circuit, and are generated by a constant current source. A bias current supply circuit for supplying a bias current to the memory cell and the n reference cells based on a constant current, and comparing the potentials of the drain of the first MOS transistor and the drain of the second MOS transistor A sense amplifier that determines the data in the memory cell;Each of the plurality of reference cells can independently write / read data.The ratio between the number of reference cells in the first state and the number of reference cells in the second state can be arbitrarily set, and the current driving capability of the second MOS transistor is the current driving capability of the first MOS transistor. N times.
[0054]
  A magnetic random access memory according to an example of the present invention includes a magnetoresistive effect element, can take a first state and a second state, and is connected to a memory cell connected between a first node and a first power supply terminal. And a magnetoresistive element, which can take the first and second states, and is connected in parallel between the second node and the first power supply terminal, and makes a reference for judging the data of the memory cell. And n (n is a plurality) reference cells and a magnetoresistive effect element, which can take the first and second states, and is parallel between the first node and the first power supply terminal. N-1 dummy cells connected to the first node, a first clamp circuit for clamping the first node to a predetermined potential, a second clamp circuit for clamping the second node to a predetermined potential, and the first 1 node and 2nd power A first MOS transistor connected to the terminal, a second MOS transistor connected between the second node and the second power supply terminal, and the first and second MOS transistors to form a current mirror circuit. A bias current supply circuit for supplying a bias current to the memory cell and the n reference cells based on a constant current generated by a current source; a potential of a drain of the first MOS transistor and a drain of the second MOS transistor; And a sense amplifier that determines the data of the memory cell by comparing the data of the memory cell, and the plurality of reference cells and the n-1 dummy cells can be independently written / read data. , The number of reference cells in the first state and the number of reference cells in the second state Can be arbitrarily set, and the ratio between the number of dummy cells in the first state and the number of dummy cells in the second state can be arbitrarily set, and the current driving capability of the second MOS transistor and the current driving of the first MOS transistor Ability is equal.
[0055]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a magnetic random access memory according to an example of the present invention will be described in detail with reference to the drawings.
[0056]
1. First embodiment
FIG. 1 shows the main part of the read circuit of the magnetic random access memory according to the first embodiment of the present invention.
[0057]
The reference potential generation circuit 10 for generating the reference potential Vref is composed of a plurality of reference cells (MTJ elements) RC having the same structure as the memory cell (MTJ element) MC. A circuit required for writing is arranged in the reference potential generation circuit 10 so that predetermined data can be individually written to each of the plurality of reference cells RC.
[0058]
Generally, the tunnel insulating film used for the MTJ element is Al.₂O₃(Alumina). Here, the tunnel insulating film is usually formed by naturally oxidizing Al (aluminum) in order to suppress variations in thickness. However, it is impossible in reality that the thickness of the tunnel insulating film does not vary due to a manufacturing process.
[0059]
Therefore, in order to generate the reference potential Vref having a value just between the potential generated when data “1” is read and the potential generated when data “0” is read, among the reference cells RC, data It is not sufficient that the number of cells of “1” and the number of cells of data “0” are halved (the same number).
[0060]
That is, it is required that the number of cells of data “1” and the number of cells of data “0” can be freely changed among the plurality of reference cells RC depending on the variation in the thickness of the tunnel insulating film. For example, in order to generate the reference potential Vref having a value intermediate between the potential generated when reading data “1” and the potential generated when reading data “0”, the number of cells of data “1” and the data In some cases, the number of “0” cells must be positively different.
[0061]
That means
Under the condition of Rmax> 1 / n × ΣRref> Rmin,
Rmax -1 / n x ΣRref = 1 / n x ΣRref-Rmin
Is adjusted so that the resistance value Rref of n (n is a plurality) reference cells RC is adjusted.
[0062]
The bias current applied to the reference cell RC is n times the bias current applied to the memory cell MC (n = 8 in this embodiment), and 1 / n is realized. For this purpose, a current mirror circuit is used. Normally, the number of reference cells in the “1” state is equal to the number of reference cells in the “0” state. Here, for example, the number of reference cells in the “1” state depends on variations in the resistance value of the MTJ element. The number of reference cells in the “1” state and the number of reference cells in the “0” state are made different, for example, by increasing the number of reference cells in the “0” state.
[0063]
The reference cell (MTJ element) RC in which the thickness of the tunnel insulating film is extremely deviated from the ideal value is excluded from being used as a reference cell. In this case, the bias current passed through the memory cell MC is increased by an amount corresponding to the number obtained by subtracting the number of reference cells excluded from the total number n of reference cells RC.
[0064]
As a method of eliminating defective reference cells, a redundancy technique that is often used in the field of semiconductor memory is applied. For example, if the address of a defective reference cell is programmed in a storage element (fuse, MTJ element, etc.) by laser cutting, and the programmed address matches the specified address, the column decoder is deselected and the bias current To generate a reference current / potential.
[0065]
A specific configuration of the reading circuit in FIG. 1 will be described.
An MTJ element as a memory cell MC is connected to the bit line BL <i>. One end of the memory cell MC is connected to the ground point via the read selection transistor RST.
[0066]
The gate of the read selection transistor RST is connected to the read word line WLn. The AND circuit AD <WLn> as a decoder controls on / off of the read selection transistor RST based on the row address signal RD <WLn> when the row address enable signal RDenable is “H”. That is, when the row address enable signal RDEnable is “H” and all the bits of the row address signal RD <WLn> are “H”, the read word line WLn is “H” and the read selection transistor RST is turned on. .
[0067]
One end of the bit line BL <i> is connected to the data line DL via the transfer transistor N <BLi>. On / off of the transfer transistor N <BLi> is controlled by an output signal of an AND circuit AD <BLi> as a decoder. For example, when the column address enable signal CDenable is “H” and the all bits of the column address signal CD <BLi> are “H”, the transfer transistor N <BLi> is turned on.
[0068]
A clamp circuit for clamping the node N1 to a predetermined potential is connected to the data line DL. The clamp circuit has an operational amplifier OP1 in which the clamp potential Vclamp is input to the positive input terminal, the potential of the node N1 is input to the negative input terminal, and an output channel OUT that is output from the operational amplifier OP1 is input to the gate. MOS transistor QN1.
[0069]
The sense amplifier S / A compares the reference potential Vref output from the reference potential generation circuit 10 with the potential of the data line DL, and determines the data in the memory cell MC. The sense amplifier S / A outputs the data in the memory cell MC as read data SAOUT.
[0070]
The reference potential generation circuit 10 has n (n is a plurality) reference cells RC composed of the same MTJ elements as the memory cells MC. In each reference cell RC, circuits necessary for writing are arranged in the reference potential generation circuit 10 so that predetermined data can be individually written.
[0071]
One end of the reference cell RC is connected to the ground point via the read selection transistor RST. The gate of the read selection transistor RST is connected to the read word line WLn. The AND circuit AD <WLn> controls on / off of the read selection transistor RST based on the row address signal RD <WLn> when the row address enable signal RDEnable is “H”.
[0072]
For example, when the row address enable signal RDEnable is “H”, when all the bits of the row address signal RD <WLn> are “H”, the read word line WLn is “H” and the read selection transistor RST is turned on.
[0073]
One end of the reference cell bit lines rBL <0>, rBL <1>,... RBL <7> passes through the transfer transistors N <0>, N <1>,. Connected to the cell data line rDL. ON / OFF of the transfer transistors N <0>, N <1>,... N <7> is output signals of AND circuits AD <0>, AD <1>,. Controlled by
[0074]
For example, when the column address enable signal CDenable is “H”, when all the bits of the column address signals CD <0>, CD <1>,... CD <7> are “H”, the transfer transistor N <0>. , N <1>,... N <7> are turned on.
[0075]
A clamp circuit for clamping the node N2 to a predetermined potential is connected to the reference cell data line rDL. The clamp circuit has an operational amplifier OP2 in which the clamp potential Vclamp is input to the positive input terminal, the potential of the node N2 is input to the negative input terminal, and an output channel OUT that is output from the operational amplifier OP2 is input to the gate. MOS transistor QN2.
[0076]
The bias current supply circuit CS1 includes a P channel MOS transistor QP3, N channel MOS transistors QN3 and QN4, and a constant current source I1.
[0077]
The bias current I1 generated by the bias current supply circuit CS1 is supplied to the memory cell MC via the data line DL and the bit line BL <i> by the current mirror circuit including the P-channel MOS transistors QP1 and QP3. .
[0078]
The bias current I1 is passed through the reference data line rDL and the reference bit lines rBL <0>, rBL <1>,... RBL <7> by a current mirror circuit composed of P-channel MOS transistors QP1 and QP2. To the reference cell RC.
[0079]
FIG. 2 is an application example of the readout circuit of FIG. This read circuit is characterized in that a system for eliminating defective reference cells is mounted on the read circuit of FIG.
[0080]
The same number of address comparators 1 as the number of reference cells RC are provided. In the present embodiment, since the number of reference cells RC is 8, only eight address comparators 1 are provided corresponding to each address of the reference cell RC.
[0081]
The address comparator 1 compares the address of the defective reference cell stored in the storage element (eg, fuse, MTJ element, etc.) with the address for accessing the reference cell supplied to generate the reference current / voltage. To do.
[0082]
Then, the address comparator 1 sets the match signals MATCH <0>, MATCH <1>,... MATCH <7> to “H” when both addresses match.
[0083]
For example, consider a case where the reference cell (MTJ element) RC connected to the reference bit line rBL <3> is defective. In this case, the address designating the reference cell connected to the reference bit line rBL <3> is stored in the storage element corresponding to the address comparator <3>.
[0084]
When generating the reference current / voltage, the address comparator <3> compares the defective address stored in the storage element with the address supplied to generate the reference current / voltage. The address comparator <3> sets the match signal MATCH <3> to “H” when both addresses match.
[0085]
At this time, the P-channel MOS transistor P3 is turned off. The decoder <3> is in an inoperative state, and its output is always “L” regardless of the address signal. Therefore, N channel MOS transistor N3 is turned off.
[0086]
Therefore, the reference cell (MTJ element) connected to the reference bit line rBL <3> is eliminated and is not used when generating the reference current / voltage. At this time, the bias current I1 is supplied to the seven reference cells connected to the remaining reference bit lines rBL <0>,... RBL <2>, rBL <4>,. .
[0087]
The circuit in FIG. 2 is an example in which defective reference cells are simply eliminated. However, a redundant reference cell is provided separately as in a redundancy circuit, and the defective reference cell is replaced with a redundant reference cell. You may employ | adopt the technique of replacing with a cell.
[0088]
Further, an address that can be independently accessed to one reference cell may be assigned, and a monitor circuit that can monitor the current flowing through each reference cell from the outside may be added.
[0089]
FIG. 3 shows a circuit example of the address comparator of FIG.
The address comparators <j> (j = 0, 1,... 7) have k exclusive NOR circuits Ex-NOR <0>,... Ex-NOR <k> corresponding to the number of bits of the address. And an AND circuit AD1.
[0090]
The exclusive NOR circuit Ex-NOR <0>,... Ex-NOR <k> includes defective addresses Afuse <0>,... Afuse <k> stored in the storage element and an address Aref <for access. 0>,... Aref <k> is input.
[0091]
When all the bits of the defective address Afuse <0>,... Afuse <k> and the address Aref <0>,... Aref <k> for access completely match, all the exclusive NOR circuits Ex Since the output signal of -NOR <0>,... Ex-NOR <k> is “H”, the match signal MATCH <j> output from the AND circuit AD1 is “H”.
[0092]
On the other hand, if at least one bit of the defective address Afuse <0>,... Afuse <k> and the access address Aref <0>,. Since the output signal of the exclusive NOR circuit to which the bit is input is “L”, the coincidence signal MATCH <j> output from the AND circuit AD1 is “L”.
[0093]
4 and 5 show circuit examples of the decoder of FIG.
The decoder <j> (j = 0, 1,... 7) includes an inverter I1 and an AND circuit AD2.
[0094]
The coincidence signal MATCH <j> is input to the AND circuit AD2 after passing through the inverter I1. Further, the column address enable signal CDenable and the column address signal CD <j> are input to the AND circuit AD2.
[0095]
When the match signal MATCH <j> is “L”, the value of the output signal of the decoder <j> is determined based on the column address enable signal CDenable and the column address signal CD <j>. That is, when the column address enable signal CDenable is “H” and all the bits of the column address signal CD <j> are “H”, the output signal of the decoder <j> is “H”.
[0096]
On the other hand, when the match signal MATCH <j> is “H”, the output signal of the decoder <j> is always “L” regardless of the values of the column address enable signal CDenable and the column address signal CD <j>. It becomes.
[0097]
The decoder <BLi> is composed of an AND circuit AD3. A column address enable signal CDenable and a column address signal CD <BLi> are input to the AND circuit AD3.
[0098]
When the column address enable signal CDenable is “H”, if all bits of the column address signal CD <j> are “H”, the output signal of the decoder <BLi> is “H”. On the other hand, when the column address enable signal CDenable is “L”, the output signal of the decoder <BLi> is always “L” regardless of the column address signal CD <j>.
[0099]
FIG. 6 shows the address comparator of FIG. 3 more specifically.
[0100]
In this example, the address comparator <j> includes a storage element that stores a defective address. The memory element includes, for example, programmable MTJ elements MTJ (Afuse <0>), MTJ (bAfuse <0>),... MTJ (Afuse <k>), MTJ (bAfuse <k>).
[0101]
The program for MTJ elements MTJ (Afuse <0>), MTJ (bAfuse <0>), ... MTJ (Afuse <k>), MTJ (bAfuse <k>) is magnetized (parallel or antiparallel) Instead, it is determined by whether or not the tunnel insulating film is destroyed. Therefore, the memory element may be a laser blown fuse, an electrically programmable electric fuse (E-fuse), or the like.
[0102]
The exclusive NOR circuit Ex-NOR <0>,... Ex-NOR <k> is, for example, a number corresponding to the number of bits of an address necessary for selecting one reference cell RC, in this example, There are only (k + 1).
[0103]
Since the configurations of all the exclusive NOR circuits Ex-NOR <0>,... Ex-NOR <k> are the same, the configuration of the exclusive NOR circuit Ex-NOR <k> will be described below, for example. To do.
[0104]
One end of the MTJ elements MTJ (Afuse <k>), MTJ (bAfuse <k>) is connected to the power supply terminal Vdd via the P-channel MOS transistor QP4 and the N-channel MOS transistor QN5 '. Program signal PROG <k> is applied to the gate of MOS transistor QP4, and clamp signal Vclamp is applied to the gate of MOS transistor QN5 '.
[0105]
Also, one end of the MTJ elements MTJ (Afuse <k>), MTJ (bAfuse <k>) is connected to the power supply terminal Vdd via the P-channel MOS transistor QP5. An inverted signal bPROG <k> of program signal PROG <k> is applied to the gate of MOS transistor QP5.
[0106]
The other end of the MTJ element MTJ (Afuse <k>) is connected to the ground terminal Vss via the N-channel MOS transistor QN5. An address signal bAref <k> for selecting a reference cell is input to the gate of the MOS transistor QN5.
[0107]
The other end of the MTJ element MTJ (bAfuse <k>) is connected to the ground terminal Vss via the N-channel MOS transistor QN6. An address signal Aref <k> for selecting a reference cell is input to the gate of MOS transistor QN6. The address signal bAref <k> is an inverted signal of the address signal Aref <k>.
[0108]
The program signal bPROG <k> is a signal that becomes “L” when a defective address is written to the MTJ element MTJ (Afuse <k>), MTJ (bAfuse <k>).
[0109]
Note that the MTJ elements MTJ (Afuse <k>) and MTJ (bAfuse <k>) are all in the “1” state and the tunnel insulating film is not destroyed before the defective address is written.
[0110]
For example, when “0” is written in the MTJ element MTJ (Afuse <k>) and “1” is written in the MTJ element MTJ (bAfuse <k>), the address signal bAref <k> is “H” and the address signal Aref <k>. Is set to “L”, and the program signal bPROG <k> is set to “L”. At this time, an excessive voltage is applied to the MTJ element MTJ (Afuse <k>), the tunnel insulating film is destroyed, and “0” is written.
[0111]
Further, when “0” is written to the MTJ element MTJ (bAfuse <k>) and “1” is written to the MTJ element MTJ (Afuse <k>), the address signal Aref <k> is set to “H” and the address signal bAref <k>. Is set to “L”, and the program signal bPROG <k> is set to “L”. At this time, an excessive voltage is applied to the MTJ element MTJ (bAfuse <k>), the tunnel insulating film is broken, and “0” is written.
[0112]
When the thickness of the tunnel insulating film of the MTJ elements MTJ (Afuse <k>) and MTJ (bAfuse <k>) is 1 to 2 nm, the voltage required to destroy the tunnel insulating film is 1 to 5V. . In the current MOS type semiconductor memory, the value of the power supply voltage is about 2.5 V. In this case, the program operation can be executed without providing a dedicated internal booster circuit in the chip.
[0113]
The input terminal of the inverter I2 is connected to one end of the MTJ element MTJ (Afuse <k>), MTJ (bAfuse <k>), and the output signal OUT <of the exclusive NOR circuit Ex-NOR <k> is output from the output terminal. k> is obtained.
[0114]
Then, the output signals OUT <0>,... OUT <k> of the exclusive NOR circuits Ex-NOR <0>,... Ex-NOR <k> are input to the AND circuit AD1. The coincidence signal MATCH <j> is output from the AND circuit AD1.
[0115]
Note that the circuit of FIG. 6 can also be applied to a redundancy circuit for relieving a defective cell in a normal memory cell array. That is, it is detected by the circuit of FIG. 6 whether or not the input address and the defective address match. If they match, the defective cell is replaced with a redundant cell.
[0116]
FIG. 7 shows a circuit example of the operational amplifier of FIGS. 1 and 2.
The operational amplifiers OP1 and OP2 receive P-channel MOS transistors QP6 and QP7 for receiving input signals, N-channel MOS transistors QN7 and QN8 connected in a current mirror, and an enable signal Enable that determines activation / inactivation of the operational amplifier. N channel MOS and transistor QN9.
[0117]
The operational amplifiers OP1 and OP2 output an output signal Out corresponding to the difference between the two input signals (+, −). When the values of the two input signals (+, −) are equal, the output signals of the operational amplifiers OP1 and OP2 are zero.
[0118]
FIG. 8 shows a circuit example of the sense amplifier of FIGS. 1 and 2.
This sense amplifier S / A includes N-channel MOS transistors QN10 and QN11 for receiving an input signal, P-channel MOS transistors QP8 and QP10 connected to an output terminal, and P-channel MOS transistors QP9 and QP11 connected to each other. And an N channel MOS for receiving an enable signal Enable for determining activation / inactivation of the sense amplifier and a transistor QN12.
[0119]
The sense amplifier S / A increases the difference between the two input signals (+, −) and outputs it as output signals SAOUT and bSAOUT.
[0120]
  2. Second embodiment
  FIG.These show the principal parts of the read circuit of the magnetic random access memory according to the second embodiment of the present invention.
[0121]
The thickness of the tunnel insulating film of the MTJ element is about several nanometers, and is about several times the size of the molecule of the substance constituting the tunnel insulating film. For this reason, it is difficult to make the tunnel insulating film thinner than this.
[0122]
As the size of the MTJ element tends to be reduced with the progress of miniaturization of the memory cell, if the tunnel insulating film cannot be thinned, the resistance of the MTJ element is reduced along with the miniaturization of the memory cell. The value will increase.
[0123]
By the way, in the magnetic random access memory, a read potential appears on the bit line at the time of reading. This read potential is generated by the read current and the resistance value of the MTJ element. The time until the read potential is stabilized roughly increases in proportion to the product of the resistance value of the MTJ element and the parasitic capacitance of the wiring related to the read operation such as the bit line.
[0124]
This parasitic capacitance tends to increase with the miniaturization of memory cells. This is because the interval between wirings related to a read operation such as a bit line becomes narrow due to miniaturization of the memory cell. Assuming that the wiring width does not change, the capacity per unit length increases because the distance between the wirings becomes narrower.
[0125]
It is conceivable that the wiring related to the read operation such as the bit line is shortened due to the miniaturization of the memory cell. However, in the case of the magnetic random access memory, for example, the bit line is also used as a write line for flowing a write current. The That is, it is necessary to pass a current of several mA through the bit line in order to generate a magnetic field for writing. Considering this, the cross-sectional area of the wiring cannot be reduced in order to prevent electromigration.
[0126]
Therefore, for example, when the wiring width is reduced, it is important to increase the thickness and not reduce the cross-sectional area of the wiring instead. As a result, with the miniaturization of the memory cell, the parasitic capacitance per unit length of the wiring related to the read operation such as the bit line increases.
[0127]
From the above, in order to prevent the reading speed from decreasing, a plurality of dummy cells DC having the same structure as the selected cell MC are provided in the chip separately from the selected cell (MTJ element) MC. Then, the plurality of dummy cells DC are connected in parallel to the selected cell MC to increase the current drive capability of the bit line during the read operation.
[0128]
As with the reference cell RC, a circuit for writing is added to the dummy cell DC so that programming is possible. Thus, by combining the selected cell MC and the dummy cell DC, a balance with the reference cell RC can be ensured, so that an optimum input voltage for the sense amplifier S / A can be generated.
[0129]
A specific configuration of the reading circuit in FIG. 9 will be described.
Memory cell MC is connected to bit line BL <i>. Further, a dummy cell circuit 3 composed of (n−1) (n is a plurality) dummy cells DC having the same configuration as the memory cell MC is connected to the data line DL. A circuit necessary for writing is arranged in the dummy cell circuit 3A so that predetermined data can be individually written to each of the dummy cells DC.
[0130]
One end of each of the memory cell MC and the dummy cell DC is connected to the ground point via the read selection transistor RST.
[0131]
The gate of the read selection transistor RST is connected to the read word line WLn. The AND circuit AD <WLn> as a decoder controls on / off of the read selection transistor RST based on the row address signal RD <WLn> when the row address enable signal RDenable is “H”. That is, when the row address enable signal RDEnable is “H” and all the bits of the row address signal RD <WLn> are “H”, the read word line WLn is “H” and the read selection transistor RST is turned on. .
[0132]
One end of the bit line BL <i> is connected to the data line DL via the transfer transistor N <BLi>. On / off of the transfer transistor N <BLi> is controlled by an output signal of an AND circuit AD <BLi> as a decoder. For example, when the column address enable signal CDenable is “H” and the all bits of the column address signal CD <BLi> are “H”, the transfer transistor N <BLi> is turned on.
[0133]
A plurality of transfer transistors N <DL> are connected between the data line DL and the dummy cell DC. On / off of the transfer transistor N <DL> is controlled by a column address enable signal CDenable. When the column address enable signal CDenable is “H”, the transfer transistor N <DL> is turned on, and the dummy cell DC is connected in parallel to the memory cell MC.
[0134]
A clamp circuit for clamping the node N1 to a predetermined potential is connected to the data line DL. The clamp circuit has an operational amplifier OP1 to which the clamp potential Vclamp is input to the positive input terminal, the potential of the node N1 is input to the negative input terminal, and an N channel to which the output signal out output from the operational amplifier OP1 is input to the gate. MOS transistor QN1.
[0135]
The sense amplifier S / A compares the reference potential Vref output from the reference potential generation circuit 10 with the potential of the data line DL, and determines the data in the memory cell MC. The sense amplifier S / A outputs the data in the memory cell MC as read data SAOUT.
[0136]
The reference potential generation circuit 10 has n (n is a plurality) reference cells RC composed of the same MTJ elements as the memory cells MC. In each reference cell RC, circuits necessary for writing are arranged in the reference potential generation circuit 10 so that predetermined data can be individually written.
[0137]
One end of the reference cell RC is connected to the ground point via the read selection transistor RST. The gate of the read selection transistor RST is connected to the read word line WLn. The AND circuit AD <WLn> controls on / off of the read selection transistor RST based on the row address signal RD <WLn> when the row address enable signal RDEnable is “H”.
[0138]
For example, when the row address enable signal RDEnable is “H”, when all the bits of the row address signal RD <WLn> are “H”, the read word line WLn is “H” and the read selection transistor RST is turned on.
[0139]
One end of the reference cell bit lines rBL <0>, rBL <1>,... RBL <7> passes through the transfer transistors N <0>, N <1>,. Connected to the cell data line rDL. ON / OFF of the transfer transistors N <0>, N <1>,... N <7> is output signals of AND circuits AD <0>, AD <1>,. Controlled by
[0140]
For example, when the column address enable signal CDenable is “H”, when all the bits of the column address signals CD <0>, CD <1>,... CD <7> are “H”, the transfer transistor N <0>. , N <1>,... N <7> are turned on.
[0141]
A clamp circuit for clamping the node N2 to a predetermined potential is connected to the reference cell data line rDL. The clamp circuit has an operational amplifier OP2 in which the clamp potential Vclamp is input to the positive input terminal, the potential of the node N2 is input to the negative input terminal, and an output channel out that is output from the operational amplifier OP2 to the gate. MOS transistor QN2.
[0142]
The bias current supply circuit CS1 includes a P channel MOS transistor QP3, N channel MOS transistors QN3 and QN4, and a constant current source I1.
[0143]
The current I1 generated by the bias current supply circuit CS1 is supplied to the memory cell MC via the data line DL and the bit line BL <i> by the current mirror circuit including the P-channel MOS transistors QP1 and QP3.
[0144]
The current I1 is passed through the reference data line rDL and the reference bit lines rBL <0>, rBL <1>,... RBL <7> by a current mirror circuit composed of P-channel MOS transistors QP1 and QP2. Supplied to the reference cell RC.
[0145]
FIG. 10 shows a modification of the readout circuit of FIG.
In this modified example, as with the reference cell RC, addresses are assigned to the respective dummy cells DC, and the ON / OFF of the transfer transistor N <DL> in the dummy cell circuit 3A is turned on / off by column address signals CD <0>, CD <1>. ,... Individually controlled based on CD <7>.
[0146]
In the examples of FIGS. 9 and 10, the total number of memory cells MC and dummy cells DC is equal to the number of reference cells RC.
[0147]
In this case, the channel widths of the load P-channel MOS transistors QP1 and QP2, and the clamp N-channel MOS transistors N <0>, N <1>,... N <7>, N <BLi> , N <DL> may all be equal.
[0148]
In contrast, when the total number of memory cells MC and dummy cells DC is different from the number of reference cells RC, the channel widths of the load P-channel MOS transistors QP1 and QP2 and the clamping N-channel MOS transistor N The channel widths of <0>, N <1>,... N <7>, N <BLi>, N <DL> may be changed in accordance with the ratio of the number of cells.
[0149]
3. Third embodiment
FIG. 11 shows a constant current source used in the magnetic random access memory according to the third embodiment of the present invention.
[0150]
The constant current source I1 according to this embodiment can be applied to the magnetic random access memory in FIG. 1, FIG. 2, FIG. 9, and FIG.
[0151]
In the present embodiment, the constant current source I1 for applying a current bias to a memory cell, a reference cell or the like is also composed of a current source cell (MTJ element) RC2 having the same structure as the memory cell (MTJ element). This is because when the constant current source I1 is constituted by, for example, a BGR circuit, the BGR circuit does not have temperature characteristics, and therefore reflects the temperature characteristics of the MOS transistors and MTJ elements constituting the memory cell. Because it will not.
[0152]
The current source cell RC2 constituting the constant current source I1 has the same structure as the memory cell, and a plurality of cells are prepared. Further, a circuit for writing is provided in the constant current source I1 so that the current source cell RC2 constituting the constant current source I1 can be individually programmed.
[0153]
The current source cell RC2 is arranged in the same cell array as a normal memory cell array. In order to achieve early stabilization of the current value, the current source cell RC2 is accessed before the read operation to the memory cell, or in modes other than the write mode, standby mode, low power consumption mode, etc. It is desirable to always have an access state.
[0154]
In this case, with respect to the write word line, the memory cell in the normal memory cell array and the current source cell RC2 constituting the constant current source I1 may be shared, but with respect to the read word line, the memory cell The one for the reference cell and the one for the current source cell are separately provided.
[0155]
Further, for example, in the initial setting mode, an address may be allocated so that each current source cell can be individually selected.
[0156]
4). Fourth embodiment
FIG. 12 shows the main part of the read circuit of the magnetic random access memory according to the fourth embodiment of the present invention.
[0157]
The magnetic random access memory according to the present embodiment is characterized in that it has a mode for directly monitoring the cell current.
[0158]
In the mode in which the cell current is directly monitored, the bias current supply circuit CS1 is deactivated. For this purpose, N-channel MOS transistors QN3 'and QN4' for newly controlling the operation of the bias current supply circuit CS1 are arranged in the bias current supply circuit CS1. In the mode in which the cell current is directly monitored, the monitor control signal Imon becomes “H”, the inverted signal bImon becomes “L”, and the bias current supply circuit CS1 becomes inoperative.
[0159]
In a mode in which the cell current is directly monitored, a P-channel MOS transistor QP12 is provided for applying a bias voltage to the gates of P-channel MOS transistors QP1 and QP2 to keep these transistors in an off state. The MOS transistor QP12 is connected between the power supply terminal Vdd and the gates of the MOS transistors QP1 and QP2, and is controlled by the inverted signal bImon of the monitor control signal Imon.
[0160]
Further, a P-channel MOS transistor QN13 is connected between the power supply terminal Vdd and the gate of the MOS transistor QN1 (output terminal of the operational amplifier OP1). An inverted signal bImon of the monitor control signal Imon is input to the gate of the MOS transistor QP13. The positive input terminal of the sense amplifier S / A is connected to the output pin via an N-channel MOS transistor (transfer gate) QN13. The MOS transistor QN13 is controlled by a monitor control signal Imon.
[0161]
When the monitor control signal Imon is “H” and the N-channel MOS transistors N <BLi> and RST are turned on, the output pin connected to one end of the MOS transistor QN13 is connected to the tester, and the cell current is Can be monitored.
[0162]
Here, when the cell current is monitored after packaging, for example, the output pin connected to one end of the MOS transistor QN13 is not unique and also functions as a functional pin having a predetermined function during normal operation. As such, it may be shared. However, when there is a margin in the number of pins, the output pin may naturally be a pin used only for monitoring.
[0163]
When the cell current is monitored before packaging, the positive side input terminal of the sense amplifier S / A may be connected to the test dedicated pad via the MOS transistor QN13. In this case, at the time of packaging, the test dedicated pad is not connected to the output pin.
[0164]
According to the present embodiment, in the test mode, direct cell current monitoring and access to cells other than memory cells such as reference cells can be performed.
[0165]
Considering a NAND flash memory, for example, as shown in FIGS. 13 and 14, after receiving a test command, a cell current direct monitoring operation is entered based on a control signal CLE, or cells other than memory cells are entered. Enable access to. The address is taken into the chip from a normal address pin based on the control signal ALE, for example.
[0166]
In FIG. 13, # 77 (meaning 77 in hexadecimal) is a command code relating to direct monitoring of cell current, and in FIG. 14, # 55 (meaning 55 in hexadecimal) is other than the memory cell. This is a command code for fetching an address (extra address entry) for each cell.
[0167]
Further, for example, as shown in FIG. 15, in the case of an interface such as RDRAM, as a command code in an input packet, entry of direct monitoring of cell current, access to cells (extra cells) other than memory cells, and the like are entered. The extra address is designated by the address code in the packet.
[0168]
This technique can be applied to monitoring a cell current flowing in a cell other than a memory cell, for example, a reference cell.
[0169]
5). Fifth embodiment
As seen in Non-Patent Document 3 proposed by M Durlam et.al, the MR ratio decreases when the bias voltage is increased. Therefore, the bias voltage for the memory cell (MTJ element) is controlled by the control voltage Vclamp to obtain an optimum MR ratio.
[0170]
By the way, for example, as shown in Patent Document 1, there is a method of advantageously rewriting the magnetization direction of the MTJ element. For example, there is an optimum supply timing, current waveform, current value, etc. for the write current for generating a magnetic field that determines the magnetization direction of the MTJ element, and there is an optimum shape, etc. for the MTJ element. .
[0171]
In this embodiment, the write current control circuit for setting (programming) the write current supply timing, current waveform, current value, and the like to an optimum value, and the MTJ actually under a predetermined condition. A circuit for writing to perform a writing operation on the element is proposed.
[0172]
FIG. 16 shows an outline of a magnetic random access memory according to the fifth embodiment of the present invention.
[0173]
The magnetic random access memory (MRAM) 11 may itself constitute one memory chip, or may be one block in a chip having a specific function.
[0174]
The memory cell array (data cell) 12 and the reference cell array 13 have a configuration as shown in FIG. 17, for example. The memory cell array 12 actually has a function of storing data, and the reference cell array 13 has a function of determining a reference for determining the value of read data during a read operation.
[0175]
One of the two ends in the Y direction (Easy-Axis direction) of the cell array composed of the memory cell array 12 and the reference cell array 13 includes a row decoder & driver (row decoder & write word line driver, row decoder & read word). Line driver) 14 is arranged, and the write word line sinker 15 is arranged in the other one.
[0176]
For example, the row decoder & driver 14 selects one of a plurality of write word lines based on a row address signal and supplies a write current to the selected write word line during a write operation. It has the function to do. The write word line sinker 15 has a function of absorbing a write current supplied to, for example, one selected write word line during a write operation.
[0177]
The row decoder & driver 14 selects and selects one of a plurality of read word lines (may be integrated with a write word line) based on, for example, a row address signal during a read operation. The read word line has a function of causing a read current to flow. For example, the sense amplifier 20 detects the read current and determines read data.
[0178]
A column decoder & write bit line driver / sinker 16A is arranged at one of two ends in the X direction (Hard-Axis direction) of the memory cell array 12, and a column decoder & write is provided at the other end. A bit line driver / sinker (including a column transfer gate and a column decoder) 17A is arranged.
[0179]
The column decoder & write bit line driver / sinker 16A, 17A selects and selects one of a plurality of write bit lines (or data selection lines) based on, for example, a column address signal during a write operation. A function of flowing a write current having a direction corresponding to the write data to the one write bit line. The column transfer gate and the column decoder have a function of electrically connecting the data selection line selected by the column address signal to the sense amplifier 20 during the read operation.
[0180]
A reference cell column decoder & write bit line driver / sinker 16B is arranged at one of the two ends in the X direction of the reference cell array 13, and the other one is a reference cell column decoder & write. A bit line driver / sinker (including a column transfer gate and a column decoder) 17B is arranged.
[0181]
The reference cell column decoder & write bit line driver / sinkers 16B and 17B have a function of storing reference data in the reference cell array 13. The column transfer gate and the column decoder have a function of reading the reference data and transferring it to the sense amplifier 20 during the read operation.
[0182]
The address receiver 18 receives an address signal and transfers, for example, a row address signal to the row decoder & driver 14 and transfers a column address signal to the column decoder & write bit line drivers / sinkers 16A and 17A. The data input receiver 19 transfers the write data to the column decoder & write bit line driver / sinker 16A, 17A. The output driver 21 outputs the read data detected by the sense amplifier 20 to the outside of the magnetic random access memory 11.
[0183]
The control circuit 22 receives the / CE (Chip Enable) signal, the / WE (Write Enable) signal, and the / OE (Output Enable) signal, and controls the operation of the magnetic random access memory 11.
[0184]
For example, the control circuit 22 supplies the write signal WRITE to the write current control circuit 24 during the write operation. When the write current control circuit 24 receives the write signal WRITE, the write current control circuit 24 generates a write word line drive signal WWLDRV, a write word line sync signal WWLSNK, a write bit line drive signal WBLDRV, and a write bit line sync signal WBLSNK.
[0185]
The write word line drive signal WWLDRV is supplied to the row decoder & driver 14, and the write word line sync signal WWLSNK is supplied to the write word line sinker 15. The write bit line drive signal WBLDRV and the write bit line sync signal WBLSNK are supplied to the column decoder & write bit line drivers / sinkers 16A and 17A.
[0186]
The setting circuit 23 has a programming element, and setting data for determining the current waveform of the write word / bit line current is programmed in the programming element. As the programming element, for example, a laser blown fuse, an MTJ element (MTJ), an antifuse that breaks the tunnel barrier of the MTJ element, or the like can be used.
[0187]
The setting circuit 23 generates the write word line current waveform signals RP <0> to RP <3> and the write bit line current waveform signals CP <0> to CP <7> based on the setting data during the write operation. To do.
[0188]
The write word line current waveform signals RP <0> to RP <3> are supplied to the row decoder & driver 14 via the write current control circuit 24 (not necessarily via the write current control circuit 24).
[0189]
The write bit line current waveform signals CP <0> to CP <3> are given to the column decoder & write bit line driver / sinker 16A via the write current control circuit 24 or not, and the write bit line The current waveform signals CP <4> to CP <7> are supplied to the column decoder & write bit line driver / sinker 17A via the write current control circuit 24 or not.
[0190]
When the write word line drive signal WWLDRV is “H” and the write word line sink signal WWLSNK is “H”, the row decoder & driver 14 is based on the write word line current waveform signals RP <0> to RP <3>. The value (magnitude) of the write current flowing through the write word line selected by the row address signal is determined.
[0191]
Similarly, the write word line sinker 15 and the column decoder & write bit line drivers / sinkers 16A and 17A have the write bit line when the write bit line drive signal WBLDRV is “H” and the write bit line sink signal WBLSNK is “H”. Based on the current waveform signals CP <0> to CP <7>, the value (magnitude) of the write current flowing through the write bit line selected by the column address signal is determined.
[0192]
The write bit line current waveform signals CP <0> to CP <3> are written when a write current is passed from the column decoder & write bit line driver / sinker 16A to the column decoder & write bit line driver / sinker 17A. Determine the value of the line current.
[0193]
The write bit line current waveform signals CP <4> to CP <7> are written when a write current is passed from the column decoder & write bit line driver / sinker 17A to the column decoder & write bit line driver / sinker 16A. Determine the value of the line current.
[0194]
Regarding the current absorption timing of the write current, for example, the timing at which the sync signals WWLNK and WBLSNK change from “H” to “L” is delayed from the timing at which the drive signals WWLDRV and WBLDRV change from “H” to “L”. The effect of completely setting the write word / bit line potential to 0V can be obtained.
[0195]
In the test mode of the magnetic random access memory, for example, a write test for the MTJ element can be performed based on the setting data D <j> input from the data input / output terminal. By this write test, the write characteristics of the MTJ element in the memory cell array 12 are grasped, and the value of the write word / bit line current (the strength of the combined magnetic fields Hx and Hy) during the normal write operation is determined.
[0196]
In this test mode, the setting data D <j> may be input from the address terminal.
[0197]
After receiving the result of the test mode, the setting data programming operation is performed. This programming operation is an operation of programming the result of the test mode, that is, the value of the write word / bit line current to the programming element in the setting circuit 23.
[0198]
During the programming operation, the program signal PROG becomes “H”. Then, the value of the setting data D <j> input from the data input / output terminal or the address terminal is controlled, and the value of the write word / bit line current during the normal write operation is programmed in the programming element in the setting circuit 23. To do.
[0199]
(2) Row decoder & write word line driver / sinker
FIG. 18 shows a circuit example of the row decoder & write word line driver / sinker.
[0200]
The row decoder & write word line driver (for one row) 14 includes an AND gate circuit AD1, NAND gate circuits NDWS0 to NDWS3, and P channel MOS transistors WS0 to WS3. The gate of the P-channel MOS transistor WSi (i = 0, 1, 2, 3) is connected to the output terminal of the NAND gate circuit NDWSi, its source is connected to the power supply terminal VDD, and its drain is the write word line WWLi. (I = 1,...) Is connected to one end.
[0201]
The write word line current waveform signal RP <i> is input to one of the two input terminals of the NAND gate circuit NDWSi, and the output signal of the AND gate circuit AD1 is input to the other. To the AND gate circuit AD1, a write word line drive signal WWLDRV and a row address signal (different for each row i) composed of a plurality of bits are input.
[0202]
A write word line sinker (for one row) 15 is composed of an N-channel MOS transistor TN1. The source of the N-channel MOS transistor TN1 is connected to the ground terminal VSS, and the drain thereof is connected to the other end of the write word line WWLi. A write word line sync signal WWLSNK is input to the gate of the N-channel MOS transistor TN1.
[0203]
During the write operation, the write word line drive signal WWLDRV becomes “H” and all the bits of the row address signal become “H” in the selected row i. That is, in the selected row i, since the output signal of the AND circuit AD1 becomes “H”, a predetermined value (magnitude) is selected according to the values of the write word line current waveform signals RP <0> to RP <3>. ) Is supplied to the write word line WWLi.
[0204]
When the write word line sink signal WWLSNK becomes “H”, the N-channel MOS transistor TN1 is turned on, so that the write current flowing through the write word line WWLi is absorbed by the ground point VSS via the N-channel MOS transistor TN1. Is done.
[0205]
According to such a row decoder & write word line driver / sinker, the write word line WWLi in the selected row i is controlled by controlling the values of the write word line current waveform signals RP <0> to RP <3>. The magnitude of the write current (current waveform) can be controlled.
[0206]
Further, if the write word line sink signal WWLSNK is set to “L” after the write word line drive signal WWLDRV is set to “L”, the potential of the write word line WWLi after the write operation can be completely set to 0V. This is convenient for initialization.
[0207]
In controlling the value (magnitude) of the write word line current, first, the sizes (channel widths) of the plurality of P-channel MOS transistors WS0 to WS3, that is, the driving capability are all set to the same value. A control method of changing the number of P-channel MOS transistors WS0 to WS3 in the on state using the write word line current waveform signals RP <0> to RP <3> can be used.
[0208]
Second, the sizes (channel widths) of the plurality of P-channel MOS transistors WS0 to WS3, that is, the driving capability are set to different values, and the write word line current waveform signals RP <0> to RP <3> are used. Thus, a control method of selectively turning on one of the plurality of P-channel MOS transistors WS0 to WS3 can be used.
[0209]
Third, a control method combining these first and second methods, that is, changing the size of the P-channel MOS transistors WS0 to WS3 and changing the number of the P-channel MOS transistors WS0 to WS3 in the on state, A control method of controlling the value (magnitude) of write current can be used.
[0210]
(3) Column decoder & write bit line driver / sinker
FIG. 19 shows a circuit example of the column decoder & write bit line driver / sinker.
[0211]
The column decoder & write bit line driver / sinker (for one column) 16A includes NAND gate circuits NDBS0 to NDBS3, AND gate circuits AD2 and AD3, P channel MOS transistors BS0 to BS3, and N channel MOS transistor BN0.
[0212]
The gate of the P-channel MOS transistor BSi (i = 0, 1, 2, 3) is connected to the output terminal of the NAND gate circuit NDBSi, its source is connected to the power supply terminal VDD, and its drain is commonly used for writing. Connected to one end of the bit line WBLi (i = 1,...).
[0213]
The write word line current waveform signal CP <i> is input to one of two input terminals of the NAND gate circuit NDBSi (i = 0, 1, 2, 3), and the output signal of the AND gate circuit AD2 is input to the other. Is entered. A write bit line drive signal WBLDRV, a column address signal composed of a plurality of bits (different for each column i), and write data DATA are input to the AND gate circuit AD2.
[0214]
The gate of the N-channel MOS transistor BN0 is connected to the output terminal of the AND gate circuit AD3, the source is connected to the ground terminal VSS, and the drain is one end of the write bit line WBLi (i = 1,...). Connected to. To the AND gate circuit AD3, a write bit line sync signal WBLSNK, a column address signal composed of a plurality of bits (different for each column i), and an inverted signal bDATA of write data are input.
[0215]
Similarly, the column decoder & write bit line driver / sinker (for one column) 17A includes NAND gate circuits NDBS4 to NDBS7, AND gate circuits AD4 and AD5, P channel MOS transistors BS4 to BS7, and N channel MOS transistor BN1. The
[0216]
The gate of the P-channel MOS transistor BSi (i = 4, 5, 6, 7) is connected to the output terminal of the NAND gate circuit NDBSi, its source is connected to the power supply terminal VDD, and its drain is commonly used for writing. Connected to the other end of bit line WBLi (i = 1,...)
[0217]
The write word line current waveform signal CP <i> is input to one of two input terminals of the NAND gate circuit NDBSi (i = 4, 5, 6, 7), and the output signal of the AND gate circuit AD4 is input to the other. Is entered. The AND gate circuit AD4 receives a write bit line drive signal WBLDRV, a column address signal composed of a plurality of bits (different for each column i), and an inverted signal bDATA of write data.
[0218]
The gate of the N-channel MOS transistor BN1 is connected to the output terminal of the AND gate circuit AD5, its source is connected to the ground terminal VSS, and its drain is in addition to the write bit line WBLi (i = 1,...). Connected to the end. A write bit line sync signal WBLSNK, a column address signal composed of a plurality of bits (different for each column i), and write data DATA are input to the AND gate circuit AD5.
[0219]
During the write operation, both the write bit line drive signal WBLDRV and the write bit line sink signal WBLSNK are “H”, and all the bits of the column address signal are “H” in the selected column i.
[0220]
Accordingly, in the selected column i, the column decoder & write bit line driver / sinker 16A is directed to the column decoder & write bit line driver / sinker 17A by the write bit line current waveform signals CP <0> to CP <3>. The value (magnitude) of the flowing write current is determined.
[0221]
In addition, the value (large) of the write current that flows from the column decoder & write bit line driver / sinker 17A to the column decoder & write bit line driver / sinker 16A according to the write bit line current waveform signals CP <4> to CP <7>. Is determined.
[0222]
The direction of the write current flowing through the write bit line WBLi is determined by the value of the write data DATA.
[0223]
For example, when the write data DATA is “1” (= “H”), at least one P-channel MOS transistor BS0 to BS3 is turned on by the write bit line current waveform signals CP <0> to CP <3>. The N channel MOS transistor BN1 is also turned on. Therefore, a write current flows from the column decoder & write bit line driver / sinker 16A to the column decoder & write bit line driver / sinker 17A.
[0224]
When the write data DATA is “0” (= “L”), at least one P channel MOS transistor BS4 to BS7 is turned on by the write bit line current waveform signals CP <4> to CP <7> In addition, N channel MOS transistor BN0 is turned on. Therefore, a write current flows from the column decoder & write bit line driver / sinker 17A to the column decoder & write bit line driver / sinker 16A.
[0225]
According to such a column decoder & write bit line driver / sinker, the write bit line WBLi in the selected column i is controlled by controlling the values of the write bit line current waveform signals CP <0> to CP <7>. The magnitude of the write current (current waveform) can be controlled.
[0226]
Further, if the write bit line sink signal WBLSNK is set to “L” after the write bit line drive signal WBLDRV is set to “L”, the potential of the write bit line WBLi after the write operation can be completely set to 0V. This is convenient for initialization.
[0227]
In controlling the value (magnitude) of the write bit line current, first, the sizes (channel widths) of the plurality of P channel MOS transistors BS0 to BS7, that is, the driving capability are all set to the same value. A control method of changing the number of P-channel MOS transistors BS0 to BS7 in the on state using the write bit line current waveform signals CP <0> to CP <7> can be used.
[0228]
Second, the sizes (channel widths) of the plurality of P-channel MOS transistors BS0 to BS7, that is, the driving capability are set to different values, and the write bit line current waveform signals CP <0> to CP <7> are used. Thus, a control method of selectively turning on one of the plurality of P-channel MOS transistors BS0 to BS7 can be used.
[0229]
Third, a control method combining these first and second methods, that is, changing the size of the P-channel MOS transistors BS0 to BS7 and changing the number of the P-channel MOS transistors BS0 to BS7 in the on state, A control method of controlling the value (magnitude) of write current can be used.
[0230]
(4) Write current control circuit
Next, an example of a write current control circuit that generates the write word line drive signal WWLDRV, the write word line sync signal WWLSNK, the write bit line drive signal WBLDRV, and the write bit line sync signal WBLSNK will be described.
[0231]
20 and 21 show examples of the write current control circuit.
[0232]
The write current control circuit (part 1) 24 generates a write word line drive signal WWLDRV and a write word line sink signal WWLSNK based on the write signal WRITE. The write current control circuit (part 1) 24 includes inverter circuits IV0 and IV1, a NAND circuit NAND1, delay circuits WDL0,... WDL4, and a plurality of transfer gate circuits.
[0233]
Each of the plurality of transfer gate circuits includes an N channel MOS transistor and a P channel MOS transistor, and control signals WS <0>,... WS <3>, / WS <0>,. 3>. Control signals / WS <0>,... / WS <3> are inverted signals of control signals WS <0>,.
[0234]
The write current control circuit (part 2) 24 generates a write bit line drive signal WBLDRV and a write bit line sink signal WBLSNK based on the write signal WRITE. The write current control circuit (part 2) 24 includes inverter circuits IV2 and IV3, a NAND circuit NAND2, delay circuits BDL0,... BDL4, and a plurality of transfer gate circuits.
[0235]
Each of the plurality of transfer gate circuits includes an N channel MOS transistor and a P channel MOS transistor, and control signals BS <0>,... BS <3>, / BS <0>,. 3>. Control signals / BS <0>,... / BS <3> are inverted signals of control signals BS <0>,.
[0236]
(5) Setting circuit
Next, a setting circuit that generates the write word line current waveform signals RP <0> to RP <3> and the write bit line current waveform signals CP <0> to CP <3> will be described.
[0237]
FIG. 22 shows an example of the setting circuit.
The setting circuit 23 includes a first portion that generates write word line current waveform signals RP <0> to RP <3>, and a second portion that generates write bit line current waveform signals CP <0> to CP <3>. Consists of
[0238]
The first part is a register <0>, <1> in which setting data for determining a current waveform (magnitude) of a write word line current is programmed, and an output signal TD <0> of the registers <0>, <1>. , TD <1>, bTD <0>, bTD <1> are decoded to output write word line current waveform signals RP <0> to RP <3>. Have.
[0239]
The second part is a register <2> to <4> in which setting data for determining a current waveform (magnitude) of the write bit line current is programmed, and an output signal TD <2> of the registers <2> to <4>. Decoder CP <0> to CP <7> for decoding write bit line current waveform signals CP <0> to CP <7> by decoding ~ TD <4>, bTD <2> to bTD <4> Have.
[0240]
In this example, it is assumed that the write word line / bit line current is set for each chip or for each cell array. When the write word line / bit line current is set for each chip, only one setting circuit 23 is provided in the chip. When there are a plurality of cell arrays in a chip and the write word line / bit line current is set for each cell array, the same number of setting circuits 23 as the number of cell arrays are provided in the chip.
[0241]
Registers <0> and <1> are programmed with setting data for determining the current waveform of the write word line current. The current waveform of the write word line current is controlled by write word line current waveform signals RP <0> to RP <3> as shown in FIG. In this example, one of the write word line current waveform signals RP <0> to RP <3> is set to “H” by 2-bit setting data registered in the registers <0> and <1>.
[0242]
In other words, four current waveforms can be realized by changing the sizes of the P-channel MOS transistors WS0 to WS3 in FIG.
[0243]
It should be noted that the number of write word line current waveform signals RP <0> to RP <3> that become “H” may be controlled by 2-bit setting data registered in the registers <0> and <1>. Good. In this case, even if the sizes of the P-channel MOS transistors WS0 to WS3 in FIG. 18 are the same, four current waveforms can be realized.
[0244]
D <0> and D <1> are setting data input from the outside of the magnetic random access memory (chip) in the test mode. In the test mode, the current waveform of the write word line current can be determined based on the setting data, and the characteristics of the MTJ element can be tested.
[0245]
D <0> and D <1> are also setting data input from the outside of the magnetic random access memory (chip) when setting data is registered. At the time of registration of the setting data, the setting data can be electrically programmed into the storage elements in the registers <0> and <1> based on the setting data.
[0246]
Registers <2> to <4> are programmed with setting data for determining the current waveform of the write bit line current. The current waveform of the write bit line current is controlled by write bit line current waveform signals CP <0> to CP <3> as shown in FIG. In this example, one of the write bit line current waveform signals CP <0> to CP <7> is set to H ”according to the 3-bit setting data registered in the registers <2> to <4>.
[0247]
That is, by changing the sizes of the P-channel MOS transistors BS0 to BS3 in FIG. 19, only four current waveforms of the write bit line current from the write bit line driver 16A toward the write bit line sinker 17A can be prepared. Further, by changing the sizes of the P-channel MOS transistors BS4 to BS7, only four kinds of current waveforms of the write bit line current from the write bit line driver 17A toward the write bit line sinker 16A can be prepared.
[0248]
The number of write bit line current waveform signals CP <0> to CP <7> that become “H” may be controlled by 3-bit setting data registered in registers <2> to <4>. Good. In this case, even if the sizes of the P-channel MOS transistors BS0 to BS7 in FIG. 19 are the same, four current waveforms can be realized for each direction of the write bit line current.
[0249]
D <2> to D <4> are setting data input from the outside of the magnetic random access memory (chip) in the test mode. In the test mode, the current waveform of the write bit line current can be determined based on this setting data, and the characteristics of the MTJ element can be tested.
[0250]
D <2> to D <4> are also setting data input from the outside of the magnetic random access memory (chip) when setting data is registered. At the time of registration of the setting data, the setting data can be electrically programmed into the storage elements in the registers <2> to <4> based on the setting data.
[0251]
(6) Register <j>
A circuit example of the register <j> in the setting circuit 23 in FIG. 22 will be described.
[0252]
FIG. 23 illustrates a circuit example of the register.
In the register <j> of this example, an MTJ element is used as an element for storing setting data.
[0253]
The program data output circuit 29 has an MTJ element MTJ for storing setting data. Here, in the MTJ element MTJ, setting data can be stored in the magnetization state of the MTJ element, that is, the relationship between the magnetization direction of the fixed layer and the magnetization direction of the storage layer (parallel or antiparallel). The example does not use such a method.
[0254]
This is because the value of the setting data is not rewritten again after it is once written in the MTJ element MTJ.
[0255]
In consideration of the fact that the MR ratio of the MTJ element MTJ is 20 to 40%, in the setting circuit that outputs the data of the MTJ element MTJ at the same time as the power is turned on, the MTJ element MTJ has large This is because a voltage may be applied to cause erroneous reading.
[0256]
The MTJ element MTJ has a characteristic that the MR ratio decreases as the bias voltage applied to both ends of the MTJ element MTJ increases. For this reason, when the setting data is stored in the magnetization state of the MTJ element, the MR ratio (the difference between the read signals of “1” data and “0” data) decreases when the bias voltage is increased to obtain a large read signal amount. This increases the possibility of erroneous reading.
[0257]
Therefore, for the MTJ element MTJ for storing the setting data, the setting data is programmed not by the relationship between the magnetization direction of the fixed layer and the magnetization direction of the storage layer but by whether or not the tunnel barrier is broken down. .
[0258]
In the setting data programming method using the dielectric breakdown of the MTJ element MTJ, the setting data can be stored semi-permanently.
[0259]
One end of the MTJ element MTJ is connected to the power supply terminal VDD via the P-channel MOS transistor P1 and the N-channel MOS transistor N1, and the other end is connected to the ground terminal VSS via the N-channel MOS transistor N2.
[0260]
Since the gate of the P-channel MOS transistor P1 is connected to the ground terminal VSS and the gate of the N-channel MOS transistor N2 is connected to the power supply terminal VDD, these MOS transistors P1 and N2 are always in the on state. .
[0261]
The clamp potential Vclamp is input to the gate of the N-channel MOS transistor N1. By setting the clamp potential Vclamp to an appropriate value, it is possible to prevent a high voltage from being applied between the electrodes of the MTJ element MTJ when setting data is read.
[0262]
An example of a Vclamp generation circuit that generates the clamp potential Vclamp is shown in FIG. In the Vclamp generation circuit 31 of this example, the clamp potential Vclamp is obtained by dividing the output voltage of the BGR circuit by resistance. The clamp potential Vclamp is 0.3 to 0.5V.
[0263]
The NAND gate circuit ND4 and the P-channel MOS transistor P2 are elements required when a setting data programming method using dielectric breakdown of the MTJ element MTJ is employed.
[0264]
When the setting data is programmed, the program signal PROG becomes “H”. For example, when setting data “1” is written to the MTJ element MTJ, “1” (= “H”) is set as setting data D <j> from an external terminal (data input terminal, address terminal, dedicated terminal, etc.). )).
[0265]
At this time, the output signal of the NAND gate circuit ND4 becomes “L”, and the P-channel MOS transistor P2 is turned on. Therefore, a large voltage is applied to both ends of the MTJ element MTJ, the tunnel barrier of the MTJ element MTJ is broken, and as a result, setting data “1” is programmed in the MTJ element MTJ. In this case, TD <j> is “L” and bTD <j> is “H”.
[0266]
On the other hand, for example, when setting data “0” is written to the MTJ element MTJ, “0” (= “L”) is set as setting data D <j> from an external terminal (data input terminal, address terminal, dedicated terminal, etc.). )).
[0267]
At this time, the output signal of the NAND gate circuit ND4 becomes “H”, and the P-channel MOS transistor P2 is turned off. Therefore, since a large voltage is not applied to both ends of the MTJ element MTJ, the tunnel barrier of the MTJ element MTJ is not broken, and as a result, the setting data “0” is programmed in the MTJ element MTJ. . In this case, TD <j> is “H” and bTD <j> is “L”.
[0268]
A connection point between the P-channel MOS transistor P1 and the N-channel MOS transistor N1 is connected to the input terminal of the inverter I7 via the inverter I9 and the transfer gate TG4. The output signal of the inverter I7 is bTD <j>, and the output signal of the inverter I8 is TD <j>.
[0269]
An example of the Vclamp generation circuit 31 is shown in FIG. In this example, by dividing the output voltage of the BGR circuit by resistance, Vclamp = 0.3 to 0.5 V is obtained as a clamp potential.
[0270]
(7) Decoders RP <0> to RP <3>, CP <0> to CP <7>
A circuit example of the decoders RP <0> to RP <3> and CP <0> to CP <7> in the setting circuit 23 of FIG. 22 will be described.
[0271]
FIG. 25 shows a circuit example of the decoder.
Each of the decoders RP <0> to RP <3> and CP <0> to CP <7> includes a NAND gate circuit ND3 and an inverter I10.
[0272]
Three input signals A, B, and C are input to the NAND gate circuit ND3, and the output signals are input to the inverter I10. The output signal D of the inverter I10 becomes the write word / bit line current waveform signals RP <0> to RP <3>, CP <0> to CP <7>.
[0273]
Table 1 shows a decoding table (relationship between input signals and output signals) of the decoders RP <0> to RP <3> and CP <0> to CP <7>.
[0274]
[Table 1]

[0275]
(8) Example of operation waveform
FIG. 26 shows an example of operation waveforms of the write word line driver / sinker of FIG.
[0276]
When the write signal WRITE becomes “H”, the write word line drive signal WWLDRV and the write word line sink signal WWLSNK become “H”. Timings at which the write word line drive signal WWLDRV and the write word line sync signal WWLNK are set to “H” are controlled by control signals WS <0> to WS <3>, / WS <0> to / WS <3>.
[0277]
When the write signal WRITE becomes “L”, first, the write word line drive signal WWLDRV becomes “L”. Then, after a certain period determined by the delay time of the delay circuit WDL4 in FIG. 20, the write word line sync signal WWLSNK becomes “L”. This fixed period is a period for setting the potential of the write word line WWLi to 0 V after the write operation is completed.
[0278]
FIG. 27 shows an example of operation waveforms of the write bit line driver / sinker of FIG.
[0279]
When the write signal WRITE becomes “H”, the write bit line drive signal WBLDRV and the write bit line sink signal WBLSNK become “H”. The timing when the write bit line drive signal WBLDRV and the write bit line sync signal WBLSNK are set to “H” is controlled by the control signals BS <0> to BS <3>, / BS <0> to / BS <3>.
[0280]
When the write signal WRITE becomes “L”, first, the write bit line drive signal WBLDRV becomes “L”. Then, after a certain period determined by the delay time of the delay circuit BDL4 in FIG. 21, the write bit line sync signal WBLSNK becomes “L”. This fixed period is a period for setting the potential of the write bit line WBLi to 0 V after the write operation is completed.
[0281]
▲ 9 ▼ Summary
As described above, according to the magnetic random access memory of this example, the current waveform (magnitude) of the write current for the write word / bit line can be set by programming for each chip or for each memory cell array. Further, the current waveform of the write word line current and the current waveform of the write bit line current can be determined independently of each other. Further, with regard to the write bit line current, the current waveform of the write bit line current can be individually determined for the write data value (write current direction).
[0282]
6). Sixth embodiment
Next, a data reading method according to the sixth embodiment of the present invention will be described.
[0283]
FIG. 28 shows an example of a read method using the read circuit according to the first embodiment of the present invention.
[0284]
In this reading method, first, characteristics of a plurality of MTJ elements constituting a memory cell and a plurality of reference cells are inspected (step ST1). Next, “0” data or “1” data is individually written into each of the plurality of reference cells based on the characteristics of the plurality of MTJ elements (step ST2).
[0285]
Here, for example, among the plurality of reference cells, the number of cells to which “0” data is written may be the same as or different from the number of cells to which “1” data is written.
[0286]
When reading the data of the selected memory cell, a reference current / potential is generated using the plurality of reference cells and used as a reference for determining the data value (step ST3).
[0287]
As shown in FIG. 29, when reading data from a memory cell, access is made by accessing at least one cell (may be a plurality or all cells) from among a plurality of reference cells based on an address signal. The reference current / potential may be generated based on the reference cell (step ST2 ′).
[0288]
FIG. 30 shows an example of a read method using the read circuit according to the second embodiment of the present invention.
[0289]
In this reading method, first, characteristics of a plurality of MTJ elements constituting a memory cell, a plurality of reference cells, and a plurality of dummy cells are inspected (step ST1). Next, “0” data or “1” data is individually written in each of the plurality of reference cells and the plurality of dummy cells based on the characteristics of the plurality of MTJ elements (step ST2).
[0290]
Thereafter, based on the address signal, at least one cell (may be a plurality or all of the cells) is accessed from among the plurality of reference cells, and a reference current / potential is generated based on the accessed reference cell ( Step ST2 ′).
[0291]
At this time, in order to match the current flowing in each MTJ element on the reference cell side with the current flowing in each MTJ element on the memory cell side, an access operation is performed on the dummy cell, and the current driving force on the reference cell side and the current driving on the memory cell side are performed. Adjustment with force is attempted (step ST2 ″).
[0292]
The reference current / potential generated in this way is used as a reference when determining the data value of the memory cell (step ST3).
[0293]
In the case of the read method of this example, in order to make the current values flowing through the MTJ elements substantially equal, the total number of memory cells and dummy cells connected in parallel to the number of cells to be accessed among the plurality of reference cells. To be equal.
[0294]
FIG. 31 shows an example of a read method using the read circuit according to the third embodiment of the present invention.
[0295]
In this reading method, first, characteristics of a plurality of MTJ elements constituting a memory cell, a plurality of reference cells, and a plurality of dummy cells are inspected (step ST1). Next, based on the characteristics of the plurality of MTJ elements, “0” data or “1” data is individually written to each of the plurality of reference cells, the plurality of dummy cells, and the plurality of MTJ elements in the current source ( Step ST2).
[0296]
Thereafter, an access operation for a plurality of MTJ elements in the current source is performed based on the address signal (step ST2a).
[0297]
Further, at least one cell is accessed from among the plurality of reference cells, and a reference current / potential is generated based on the accessed reference cell (step ST2 '). In addition, the dummy cell is accessed to adjust the current driving force on the reference cell side and the current driving force on the memory cell side (step ST2 ″).
[0298]
The reference current / potential generated in this way is used as a reference when determining the data value of the memory cell (step ST3).
[0299]
7. Other
Thus, according to the magnetic random access memory according to the example of the present invention, at the time of access, a cell other than the selected memory cell (data cell), for example, a reference cell is accessed, and a write operation, a read operation, Monitor operation can be performed.
[0300]
In addition, regarding the plurality of reference cells from which the reference current / voltage used as a reference for determining the data value during the read operation is the same, it is necessary that the number in the “1” state and the number in the “0” state are the same. For example, the ratio between the “1” state and the “0” state can be arbitrarily determined so that the optimum reference current / voltage can be generated according to the variation in the resistance value of the MTJ element.
[0301]
Further, even if the resistance value of the MTJ element increases due to the miniaturization of the element, the driving capability for the bit line and the data line is increased by driving a dummy cell (MTJ element) different from the memory cell (MTJ element). Can do.
[0302]
In addition, since the monitor circuit for monitoring the cell current is provided in the readout circuit, the cell current of the memory cell can be monitored in advance. A current source that generates a read current to be applied to the MTJ element can also be configured from the MTJ element. Data can be written independently for each MTJ element in the current source.
[0303]
In addition, this invention is not limited to the said embodiment, In the range which does not deviate from the summary, it can actualize by deform | transforming a component. In addition, various inventions can be configured by appropriately combining a plurality of components disclosed in the embodiment. For example, some constituent elements may be deleted from all the constituent elements disclosed in the above embodiments, or constituent elements of different embodiments may be appropriately combined.
[0304]
【The invention's effect】
As described above, according to the magnetic random access memory of the present invention, an optimum reference voltage can be generated even if the thickness of the tunnel insulating film of the MTJ element varies, and the MTJ element can be miniaturized. Even if the resistance value increases, the reading speed does not decrease, and the optimum write current value and supply timing for the MTJ element can be found.
[Brief description of the drawings]
FIG. 1 is a diagram showing a main part of a read circuit according to a first embodiment of the present invention.
FIG. 2 is a diagram showing an application example of the reading circuit in FIG. 1;
FIG. 3 is a diagram illustrating an example of an address comparator.
FIG. 4 is a diagram showing an example of a decoder <j>.
FIG. 5 is a diagram showing an example of a decoder <BLi>.
6 is a diagram showing a circuit example of the address comparator in FIG. 3;
FIG. 7 is a diagram illustrating a circuit example of an operational amplifier.
FIG. 8 is a diagram illustrating a circuit example of a sense amplifier.
FIG. 9 is a diagram showing a main part of a read circuit according to a second embodiment of the present invention.
10 is a diagram showing a modification of the reading circuit in FIG. 9;
FIG. 11 is a diagram showing a current source according to a third embodiment of the present invention.
FIG. 12 is a diagram showing a main part of a read circuit according to a fourth embodiment of the present invention.
FIG. 13 is a diagram showing an operation example of a NAND flash memory.
FIG. 14 is a diagram showing an operation example of a NAND flash memory.
FIG. 15 is a diagram showing an operation example of an RDRAM;
FIG. 16 is a diagram showing an outline of an MRAM according to a fifth embodiment of the present invention.
FIG. 17 illustrates a circuit example of a memory cell array.
FIG. 18 is a diagram showing a circuit example of a write word line driver.
FIG. 19 is a diagram showing a circuit example of a write bit line driver / sinker;
FIG. 20 is a diagram showing a circuit example 1 of a write current control circuit;
FIG. 21 is a diagram showing a second example of the write current control circuit;
FIG. 22 is a diagram showing a circuit example of a setting circuit.
FIG. 23 is a diagram showing a circuit example of a register <j>.
FIG. 24 is a diagram showing a circuit example of a Vclamp generation circuit.
FIG. 25 is a diagram showing a circuit example of decoders RP <0> to RP <3> and CP <0> to CP <7>.
FIG. 26 is a view showing an example of operation waveforms of the MRAM in FIG. 16;
FIG. 27 is a diagram showing an example of operation waveforms of the MRAM in FIG. 16;
FIG. 28 is a diagram showing a reading method according to the sixth embodiment of the present invention.
FIG. 29 is a diagram showing a reading method according to the sixth embodiment of the present invention.
FIG. 30 is a diagram showing a reading method according to the sixth embodiment of the present invention.
FIG. 31 is a diagram showing a reading method according to the sixth embodiment of the present invention.
FIG. 32 is a diagram modeling a sense circuit.
[Explanation of symbols]
1: address comparator, 2: decoder, 10: reference potential generation circuit, 11: MRAM, 12: memory cell array, 13: reference cell array: 14: row decoder & word line driver, 15: row decoder & word line driver / sinker, 16A, 16B, 17A, 17B: column decoder & bit line driver / sinker, 18: address receiver, 19: data input receiver, 20: sense amplifier, 21: data output driver, 22: control circuit, 23: setting circuit, 24 : Write current control circuit, CS1: Bias current supply circuit, OP1, OP2: Operational amplifier, S / A: Sense amplifier, QP1,... QP10: P channel MOS transistor, QN1,. : N-channel MOS transistor, MC: Memory cell, RC: Reference cell, I1: Current source, AD <BLi>, AD <0>,... AD <7>: AND circuit, RST: Read selection transistor.

Claims (5)

Consists magnetoresistive element may take the first and second states, and the memory cells that will be connected between the first node and the first power supply terminal,
To make a reference for judging data of the memory cell, which is composed of a magnetoresistive effect element, can take the first and second states, is connected in parallel between the second node and the first power supply terminal. N (n is a plurality) reference cells ,
A first clamping circuit for clamping the first node to a predetermined potential;
A second clamping circuit for clamping the second node to a predetermined potential;
A first MOS transistor connected between the first node and a second power supply terminal;
A second MOS transistor connected between the second node and a second power supply terminal;
A bias current supply circuit configured to form a current mirror circuit with the first and second MOS transistors, and to supply a bias current to the memory cell and the n reference cells based on a constant current generated by a constant current source;
A sense amplifier that compares the potential of the drain of the first MOS transistor and the drain of the second MOS transistor to determine data of the memory cell ;
Data writing / reading can be independently performed on the plurality of reference cells, and the ratio between the number of reference cells in the first state and the number of reference cells in the second state is arbitrary. A magnetic random access memory characterized in that the current driving capability of the second MOS transistor is n times the current driving capability of the first MOS transistor . Further comprising a system for eliminating or relieving the defective reference cell among the plurality of reference cells,
The second MOS transistor is composed of n MOS transistors connected in parallel,
When the number of defective reference cells is k (k is a number of 1 or more), among the n MOS transistors, a MOS transistor that supplies a bias current to the defective reference cell is turned off, 2. The magnetic random access memory according to claim 1 , wherein the current driving capability of the 2MOS transistor is n−k times the current driving capability of the first MOS transistor . The constant current source is:
N current source cells that are composed of magnetoresistive elements, can take the first and second states, and are connected in parallel between a third node and the first power supply terminal;
A third clamping circuit for clamping the third node to a predetermined potential;
A third MOS transistor connected between the third node and the second power supply terminal;
A third MOS transistor and a fourth MOS transistor constituting a current mirror circuit;
Data writing / reading can be independently performed on each of the plurality of current source cells, and the number of current source cells in the first state and the number of current source cells in the second state is different Ri, the current driving capability of the 3MOS transistor is a magnetic random access memory according to claim 1 or 2, characterized in that n times the current driving capability of the first 4MOS transistor. 4. The magnetic random access memory according to claim 3 , wherein the access to the n current source cells is started before the access to the memory cell. A memory cell that is composed of a magnetoresistive element and can take a first state and a second state, and is connected between a first node and a first power supply terminal;
In order to make a reference for judging data of the memory cell, which is composed of a magnetoresistive effect element, can take the first and second states, is connected in parallel between the second node and the first power supply terminal. N (n is a plurality) reference cells,
N-1 dummy cells that are composed of magnetoresistive elements, can take the first and second states, and are connected in parallel between the first node and the first power supply terminal;
A first clamping circuit for clamping the first node to a predetermined potential;
A second clamping circuit for clamping the second node to a predetermined potential;
A first MOS transistor connected between the first node and a second power supply terminal;
A second MOS transistor connected between the second node and a second power supply terminal;
A bias current supply circuit configured to form a current mirror circuit with the first and second MOS transistors, and to supply a bias current to the memory cell and the n reference cells based on a constant current generated by a constant current source;
A sense amplifier that compares the potential of the drain of the first MOS transistor and the drain of the second MOS transistor to determine data of the memory cell;
For the plurality of reference cells and the n−1 dummy cells, data can be written / read independently, and the number of reference cells in the first state and the reference cells in the second state The ratio between the number of dummy cells in the first state and the number of dummy cells in the second state can be arbitrarily set, and the current driving capability of the second MOS transistor and the first The current drive capability of 1MOS transistor is equal
Magnetic random access memory characterized by that.

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