JP2012027974A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of reading data accurately even if individual difference is generated between variable resistance elements that store data and variable resistance elements for reference while preventing an increase in area.SOLUTION: A semiconductor memory device includes a memory cell array in which memory cells are arranged in a matrix and a reference resistance circuit that generates a reference resistance value. The memory cells have data storage resistance elements that are variable resistance elements, and the reference resistance circuit has first reference resistance elements Rr1 and second reference resistance elements Rr2 that are variable resistance elements each having the same structure as the data storage resistance elements. The first reference resistance elements Rr1 are set at a first resistance value, the second reference resistance elements Rr2 are set at a second resistance value lower than the first resistance value, and the reference resistance value is a resistance value between the first resistance value and the second resistance value generated by connecting the first reference resistance elements and the second reference resistance elements.

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device including a variable resistance element and a reference variable resistance element.

  In recent years, a nonvolatile semiconductor memory device using a variable resistance element made of a ferromagnetic tunnel junction element as a storage medium has been devised. The ferromagnetic tunnel junction element has a stacked free magnetic layer and a fixed magnetic layer. By applying a voltage lower or higher than the threshold voltage to the ferromagnetic tunnel junction element, the state of the magnetic layer changes. When the free magnetic layer and the fixed magnetic layer are magnetized in the same direction, the resistance value is low and the resistance value is low.When the free magnetic layer and the fixed magnetization layer are magnetized in the opposite direction, the resistance value is high. It becomes. Therefore, data can be stored in the ferromagnetic tunnel junction device by making the high resistance state and the low resistance state correspond to the data of “0” and “1”, respectively.

  One bit of memory cell for storing data is formed by two variable resistance elements, complementary data is stored in the two variable resistance elements, and the resistance values of the two variable resistance elements are compared with each other. Thus, it is possible to determine which variable resistance element is in the low resistance state. Thereby, data stored in the memory cell can be read. However, in this method, two variable resistance elements are required for one memory cell. Therefore, if the memory capacity is increased, an increase in occupied area and manufacturing cost cannot be ignored.

  For this reason, a method of forming one bit of a memory cell with one variable resistance element has been studied. In this case, data is generally read out by comparing the resistance value of the memory cell with some reference resistance value. For example, a semiconductor memory device provided with a memory cell and a reference cell that generates a reference resistance value has been reported (see, for example, Patent Document 1). As shown in FIG. 26, there are a memory cell 507 in which a fixed resistance element 505 and a storage variable resistance element 506 are connected in series between a power supply VDD and a ground GND, and a fixed resistance element 502 and a variable resistance element. A reference cell 504 in which a reference resistance element 503 is connected in series is provided. The reference resistance element 503 is set to a resistance value between the resistance value in the high resistance state and the resistance value in the low resistance state of the variable resistance element 506 for storage.

JP 2003-317466 A

  However, the conventional semiconductor memory device may not be able to read the stored data accurately due to variations in characteristics of the variable resistance element for storage, the reference resistance element, and the fixed resistance element. The variable resistance element and the fixed resistance element are formed by a micro process of micron order or submicron order. For this reason, the resistance value tends to vary. In particular, a variable resistance element that is a ferromagnetic tunnel junction element uses a material that is not often used in conventional semiconductor devices. For this reason, compared with a general dynamic access ram etc., the characteristic change in the manufacturing process is likely to occur.

  In addition, when the variable resistance elements are arranged in a matrix, the resistance value may vary depending on the position where the variable resistance elements are arranged. In addition, when a plurality of chips are formed in a wafer, there is a possibility that the variation from chip to chip becomes large.

  When the difference between the resistance value in the high resistance state and the resistance value in the low resistance state of the variable resistance element is large, the variation can be ignored, but the difference in resistance value tends to become smaller due to miniaturization of the semiconductor memory device.

  In the conventional semiconductor memory device, the reference resistance element is made variable so as to cope with the variation in resistance value. However, when the resistance value variation between memory cells becomes large, the reference resistance element can be made variable. However, it becomes difficult to read data accurately.

  The present invention can realize a semiconductor memory device capable of accurately reading data even when individual differences occur between a variable resistance element that stores data and a reference variable resistance element while suppressing an increase in area. The purpose is to do so.

  In order to achieve the above object, the present invention provides a semiconductor memory device including a reference resistance element composed of a variable resistance element having the same structure as that of a data storage resistance element, and a reference resistance element in a high resistance state and a reference in a low resistance state. A reference resistance value is generated by a resistance element.

  Specifically, a semiconductor memory device according to the present invention is formed in a memory cell region of a substrate, a plurality of memory cells are formed in a matrix array of memory cells and a reference circuit region of the substrate, and a reference resistance value And a comparison circuit that compares the resistance value of the memory cell with the reference resistance value, and the memory cell corresponds to the first data resistance value or the first data corresponding to the stored data. The data storage resistance element is a variable resistance element having a second data resistance value lower than the resistance value, and the reference resistance circuit is a variable resistance element that has the same structure as each of the data storage resistance elements. The first reference resistance element is set to a first resistance value, and the second reference resistance element has a second resistance value lower than the first resistance value. The resistance value is set and Resistance is the resistance between the first resistance and a second resistance value generated by connecting a first reference resistance element and a second reference resistance element.

  The semiconductor memory device of the present invention includes a first reference resistance element and a second reference resistance element, each of which is a variable resistance element in which the reference resistance circuit has the same structure as the data storage resistance element. A reference resistance value between the first resistance value and the second resistance value is generated. For this reason, the dispersion | variation in the resistance characteristic of a data storage resistive element and the dispersion | variation in the resistance characteristic of a reference resistive element can be linked. Therefore, the reference resistance value between the first data resistance value and the second data resistance value can be easily generated even when the resistance characteristics of the data storage resistance element and the reference resistance element vary. As a result, accurate data can be read out.

  In the semiconductor memory device of the present invention, the first reference resistance element and the second reference resistance element may be plural.

  In this case, the number of first reference resistance elements may be equal to the number of second reference resistance elements.

  Further, the number of first reference resistance elements and the number of second reference resistance elements may be different. In this case, the number of first reference resistance elements may be larger than the number of second reference resistance elements.

  In the semiconductor memory device of the present invention, it is preferable that the distribution of the first reference resistance elements and the distribution of the second reference resistance elements in the reference circuit region are uniform. In this case, the first reference resistance element and the second reference resistance element may be alternately arranged in the reference circuit region.

  In the semiconductor memory device of the present invention, the memory cell region and the reference circuit region may be disposed adjacent to each other on the substrate.

  In the semiconductor memory device of the present invention, the reference resistance circuit collectively sets two or more of the first reference resistance elements to the first resistance value and collectively sets two or more of the second reference resistance elements. You may have the reference resistive element setting circuit set to a 2nd resistance value.

  In the semiconductor memory device of the present invention, the reference resistance circuit sets the first resistance value to a resistance value lower than the highest resistance value that can be set in the variable resistance element and higher than the lowest resistance value. A resistance value changing circuit for setting the resistance value to be higher than the lowest resistance value that can be set in the variable resistance element and lower than the first resistance value; The voltage or current value applied to at least one of the reference resistance element and the second reference resistance element or the time for applying the voltage or current may be adjusted.

  In the semiconductor memory device of the present invention, the reference resistance circuit includes a first reference resistance element and a second reference resistance element for generating a reference resistance value for at least part of the first reference resistance element and the second reference resistance element. You may have the reference resistive element selection circuit selected as a reference resistive element.

  In this case, the reference resistance element selection circuit may include a register or a nonvolatile memory that stores the number of first reference resistance elements to be selected and the number of second reference resistance elements to be selected.

  The reference resistance circuit detects status information indicating the usage status of the memory cell array, and outputs a status information signal based on the status information, and generates an optimal number information signal based on the status information signal. And the status information includes information on at least one of use time, number of accesses, applied voltage, current, and use temperature, and the optimum number information signal generation circuit includes: Conversion from the status information signal to the optimum number information signal based on the correspondence information between the number of first reference resistance elements and the number of second reference resistance elements used for generating the reference resistance value stored in advance and the status information signal The reference resistance element selection circuit may be configured to select the first reference resistance element and the second reference resistance element used for generating the reference resistance value based on the optimum number information signal.

  Further, the reference resistance circuit uses at least a part of the data storage resistance element as the first distribution detection element, and detects the first distribution information that is the distribution information of the resistance value of the first distribution detection element. The reference resistance element selection circuit may include a distribution information detection circuit, and may select the first reference resistance element and the second reference resistance element used for generating the reference resistance value based on the first distribution information. . Further, at least a part of the first reference resistance element and the second reference resistance element is used as the second distribution detection element, and second distribution information that is distribution information of the resistance value of the second distribution detection element is detected. The reference resistance element selection circuit selects the first reference resistance element and the second reference resistance element used for generating the reference resistance value based on the second distribution information. May be.

  In the semiconductor memory device of the present invention, the reference resistance circuit is a part of the variable resistance element formed in the reference circuit region, and is applied by applying stress to the first reference resistance element and the second reference resistance element. The reference resistance element selection circuit is a first reference resistance element used for generating a reference resistance value based on the resistance characteristic of the deterioration detection element. The second reference resistance element may be selected.

  In this case, the stress may include at least one of the stress due to the use environment temperature, the stress due to the access count, the stress due to the data inversion count, the stress due to the applied voltage, the stress due to the applied current, and the stress due to the applied time.

  In the semiconductor memory device of the present invention, the data storage resistance element, the first reference resistance element, and the second reference resistance element may be formed on the substrate with the same planar pattern.

  A semiconductor memory device of the present invention is connected to a memory cell, connected to a bit line that outputs a first electrical signal corresponding to information stored in the memory cell, and a reference resistance circuit, and corresponds to a reference resistance value A reference bit line from which the second electric signal is output may be further provided, and each circuit compared with the previous period may be a sense amplifier circuit connected to the bit line and the reference bit line.

  In the semiconductor memory device of the present invention, a plurality of bit lines may be provided, and the sense amplifier circuit may include a selection circuit that selectively connects one of the bit lines.

  In the semiconductor memory device of the present invention, at least one of the memory cell and the reference resistance circuit may be a variable resistance element only, may include a variable resistance element and a selection transistor, and includes a variable resistance element and a diode element. You may go out.

  According to the semiconductor memory device of the present invention, even if an individual difference occurs between the variable resistance element for storing data and the reference variable resistance element by the manufacturing process while suppressing an increase in area, the data is accurately read out. It becomes possible.

1 is a plan view showing a semiconductor memory device according to one embodiment. It is a top view which shows the example of arrangement | positioning at the time of forming the semiconductor memory device concerning one Embodiment on a wafer. FIG. 3 is a plan view showing an arrangement example of the memory cell array of the semiconductor memory device according to the embodiment. (A)-(d) is a circuit diagram which shows the structural example of the memory cell of the semiconductor memory device based on one Embodiment. (A)-(d) is a circuit diagram which shows the structural example of the reference resistance circuit of the semiconductor memory device based on one Embodiment. It is a circuit diagram which shows the structural example of the reference resistive element array of the semiconductor memory device which concerns on one Embodiment. It is a circuit diagram which shows the structural example of the reference resistive element array of the semiconductor memory device which concerns on one Embodiment. It is a graph which shows distribution of the resistance value of the reference resistive element of the semiconductor memory device which concerns on one Embodiment. It is a circuit diagram which shows the structural example of the reference resistive element array of the semiconductor memory device which concerns on one Embodiment. It is a graph which shows distribution of the resistance value of the reference resistive element of the semiconductor memory device which concerns on one Embodiment. It is a circuit diagram which shows the structural example of the reference resistive element array of the semiconductor memory device which concerns on one Embodiment. It is a top view which shows the example of arrangement | positioning of the reference resistive element array of the semiconductor memory device which concerns on one Embodiment. It is a circuit diagram showing an example of composition of a reference resistance setting circuit of a semiconductor memory device concerning one embodiment. 6 is a table showing a driving example of a reference resistance setting circuit of the semiconductor memory device according to the embodiment. 6 is a table showing a driving example of a reference resistance setting circuit of the semiconductor memory device according to the embodiment. It is a circuit diagram showing an example of composition of a reference resistance setting circuit of a semiconductor memory device concerning one embodiment. It is a graph which shows distribution of the resistance value of the reference resistive element of the semiconductor memory device which concerns on one Embodiment. It is a block diagram which shows the structural example of the reference resistive element selection circuit of the semiconductor memory device which concerns on one Embodiment. It is a block diagram which shows the structural example of the reference resistive element selection circuit of the semiconductor memory device which concerns on one Embodiment. (A) And (b) is a graph which shows distribution of the resistance value of the reference resistive element of the semiconductor memory device based on one Embodiment, (a) shows the state immediately after manufacture, (b) is the state after degradation Indicates. It is a block diagram which shows the example of a structure of the condition information detection circuit and optimal number information generation circuit of the semiconductor memory device concerning one Embodiment. It is a block diagram which shows the structural example of the distribution information detection circuit of the semiconductor memory device which concerns on one Embodiment. 1 is a block diagram illustrating a configuration example of a sense amplifier circuit of a semiconductor memory device according to an embodiment. 1 is a block diagram illustrating a configuration example of a sense amplifier circuit of a semiconductor memory device according to an embodiment. 1 is a block diagram illustrating a configuration example of a sense amplifier circuit of a semiconductor memory device according to an embodiment. It is a circuit diagram which shows a memory cell and a reference cell of the semiconductor memory device concerning a prior art example.

(One embodiment)
FIG. 1 shows a planar configuration of a semiconductor memory device according to an embodiment. As shown in FIG. 1, a reference resistance circuit 121 formed in the reference circuit formation region 102 of the substrate 101 and a memory cell array 131 formed in the memory cell formation region 103 are provided. The reference resistance circuit 121 has a reference resistance element array 124 in which a plurality of reference resistance elements Rr are arranged in a matrix. The memory cell array 131 has a plurality of memory cells 136 arranged in a matrix. The memory cell 136 has a data storage resistive element Rd. In FIG. 1, four reference resistance elements Rr are included in the reference resistance element array 124 and 16 memory cells 136 are included in the memory cell array 131. However, the number of reference resistance elements Rr and memory cells 136 is as follows. Not exclusively.

  In the case of manufacturing a semiconductor memory device, a plurality of semiconductor chips 201 are formed on one wafer 200 as shown in FIG. Variations in the manufacturing process cause microscopic variations in pattern dimensions, shape, film thickness, film quality, and the like. For example, in the case of a variable resistance element having a 1 μm square film thickness of 100 nm designed so that the resistance value in the high resistance state is 500 kΩ and the resistance value in the low resistance state is 50 kΩ, the resistance value varies depending on variations in dimensions and film thickness. Vary by more than 10%. In particular, resistance values are likely to vary between the semiconductor chip 201 formed almost at the center of the wafer 200 in FIG. 2 and the semiconductor chip 201 formed on the outer edge of the wafer. Generally, this is smaller than the variation between the semiconductor chips, but the resistance value also varies within the same semiconductor chip. For example, when a plurality of memory cell arrays 131 are formed at distant positions in the semiconductor chip 201 as shown in FIG. 3, resistance values are likely to vary among the memory cell arrays. Therefore, as shown in FIG. 1, the reference circuit formation region 102 and the memory cell formation region 103 are preferably arranged adjacent to each other on the substrate 101. By disposing the reference resistor circuit 121 and the memory cell array 131 adjacent to each other, variation in characteristics between the reference resistor element Rr constituting the reference resistor circuit 121 and the data storage resistor element Rd constituting the memory cell can be suppressed to be small. It becomes possible.

  As shown in FIG. 4A, the memory cell 136 has a data storage resistance element Rd which is a variable resistance element made of a ferromagnetic tunnel junction element. In FIG. 4A, the data storage resistive element Rd is connected between the power supply line DL and the bit line BL. A high resistance state having a first data resistance value and a low resistance state having a second data resistance value lower than the first data resistance value by applying a predetermined voltage or current to the data storage resistance element Rd And can be switched. If the memory cell 136 is configured only by the data storage resistive element Rd, the configuration of the memory cell 136 can be simplified and the area occupied by the memory cell 136 can be reduced. As shown in FIGS. 4B and 4C, the memory cell 136 may be a combination of the data storage resistance element Rd and the selection transistor Tr1 controlled by the word line WL. By using the selection transistor Tr1, a stable cell selection operation can be performed. Further, as shown in FIG. 4D, the memory cell 136 may be a combination of a data storage resistance element Rd and a diode D1. By connecting the diode D1 and the data storage resistive element Rd in series, the sensitivity for detecting the resistance change of the data storage resistive element Rd can be increased, and the operation margin can be expanded.

  As shown in FIG. 5A, the reference resistance circuit 121 includes a reference resistance element array 124 including a plurality of reference resistance elements Rr. In FIG. 5A, the reference resistive element array 124 is connected between the power supply line DL and the reference bit line / BL. As shown in FIGS. 5B and 5C, a combination of the reference resistance element array 124 and the selection transistor Tr2 controlled by the word line WL may be used. Further, as shown in FIG. 5D, a combination of the reference resistance element array 124 and the diode D2 may be used.

  As shown in FIG. 6, the reference resistance element array 124 includes a plurality of reference resistance elements Rr connected between the terminal Rai and the terminal Rao. The reference resistance element Rr is a variable resistance element composed of a ferromagnetic tunnel junction element having the same structure as the data storage resistance element Rd. The reference resistance element Rr includes a first reference resistance element Rr1 set to a first resistance value and a second reference resistance element Rr2 set to a second resistance value lower than the first resistance value. Including. In FIG. 6, two pairs of reference resistance element pairs 126 each having a first reference resistance element Rr1 and a second reference resistance element Rr2 connected in series are connected in parallel. The reference resistance element Rr is a variable resistance element having the same structure as the data storage resistance element Rd. Here, the same structure means that they are made of the same material and are formed of films having substantially the same film thickness, plane pattern, and the like. Usually, the data storage resistive element Rd and the reference resistive element Rr are formed substantially simultaneously by the same manufacturing process, and patterning of the formed film is also performed substantially simultaneously by the same manufacturing process. As a result, the same structure referred to here includes variations in film thickness and patterning dimensions that occur in the film formation process or patterning process as allowable ranges. Therefore, the variation in resistance characteristic of the reference resistance element Rr in the reference resistance circuit 121 and the variation in resistance characteristic of the data storage resistance element in the memory cell array 131 are linked to each other.

When the resistance value of the first reference resistance element Rr1 is R _H and the resistance value of the second reference resistance element Rr2 set to the low resistance state is R _L , the resistance value of the reference resistance element array 124 is the resistance value R _H and the resistance value R _L are averaged (R _H + R _L ) / 2. The data storage resistance element Rd and the reference resistance element Rr basically have the same resistance characteristics. For this reason, the resistance value of the reference resistance element array 124 is approximately halfway between the first data resistance value in the high resistance state of the data storage resistance element Rd and the second data resistance value in the low resistance state. Become. Therefore, by comparing the resistance value of the data storage resistance element Rd with the reference resistance value that is the resistance value of the reference resistance element array 124, the data stored in the data storage resistance element Rd can be read.

  In FIG. 6, the node A and the node A 'are not connected, but the same effect can be obtained even if they are connected. In FIG. 6, two first reference resistance elements Rr1 are connected to the terminal Rai, and two second reference resistance elements Rr2 are connected to the terminal Rao. However, the first reference resistance element Rr2 is connected to the terminal Rai. The same applies to a configuration in which the reference resistance element Rr1 and the second reference resistance element Rr2 are connected one by one, and the first reference resistance element Rr1 and the second reference resistance element Rr2 are connected to the terminal Rao one by one. The effect is obtained.

  The reference resistance element array 124 may be configured as shown in FIG. In FIG. 7, a first reference resistance element array 124A in which a plurality of first reference resistance elements Rr1 are arranged between a terminal Rai and a terminal Rao connected in series, and a second reference resistance element Rr2 are A plurality of second reference resistor element arrays 124B are connected. Specifically, in the first reference resistance element array 124A, n first reference resistance elements Rr1 set in a high resistance state indicating the first resistance value are connected in series, and further, n sets are connected in parallel. ing. In the second reference resistance element array 124B, n second reference resistance elements Rr2 set in a low resistance state are connected in series, and n sets are connected in parallel. Two pairs of reference resistance element arrays in which the first reference resistance element array 124A and the second reference resistance element array 124B are connected in series one by one are connected in parallel. Therefore, n × n × 2 (where n is an integer of 1 or more) is provided as the first reference resistance element Rr1 and the second reference resistance element Rr2. When n is 1, the configuration is the same as in FIG.

The reference resistance value of the reference resistance element array 124 is (R _H + R _L ) / n obtained by averaging the first resistance value R _H and the second resistance value R _L. Therefore, it is possible to easily set the reference resistance value of the reference resistance element array 124 to a resistance value approximately in the middle between the first data resistance value and the second data resistance value of the data storage resistance element Rd of the memory cell 136. it can.

  By increasing n, the following effects can be obtained. FIG. 8 shows an example of the distribution of resistance values of the reference resistance element Rr. In FIG. 8, the horizontal axis represents the resistance value, and the vertical axis represents the number of reference resistance elements.

  Due to variations in the manufacturing process and the like, there are some individual differences in the resistance value of the reference resistance element Rr. The distribution of the resistance value of the reference resistance element Rr set in the high resistance state is D1, and the distribution of the resistance value of the reference resistance element Rr2 set in the low resistance state is D2. The distribution D1 and the distribution D2 are considered to be statistically almost normal distribution. Therefore, in the reference resistance element array 124 shown in FIG. 7, if the number of the first reference resistance elements Rr1 and the second reference resistance elements Rr2 used for generating the reference resistance value is sufficiently large, the reference resistance value is The median value ArM of the average value Ar1 of the distribution D1 and the average value Ar2 of the distribution D2 is substantially equal. For this reason, a sufficient difference between the lower limit of the distribution D1 and the upper limit of the distribution D2 can be secured.

  On the other hand, when n is small, the resistance values of the first reference resistance element array 124A and the second reference resistance element array 124B may be shifted from the average value Ar1 of the distribution D1 and the average value Ar2 of the distribution D2. is there. For example, the resistance value of the first reference resistance element array 124A may be F3R1H higher than Ar1, and the resistance value of the second reference resistance element array 124B may be F3R1L higher than Ar2. In this case, the reference resistance value is F3R1M higher than ArM, and the difference between the reference resistance value and the lower limit of the distribution D1 is smaller than the difference between the upper limit of the distribution D2. For this reason, there is a possibility that data of the data storage resistive element Rd cannot be read stably. Further, when the resistance value of the first reference resistive element array 124A is F3R2H near the lower limit of the distribution D1, and the resistance value of the second reference resistive element array 124B is F3R2L near the lower limit of the distribution D2, the reference resistance value is distributed. It becomes lower than the upper limit of D2. In such a case, memory cells that cannot read data are generated.

  By increasing the number of n in this way, the possibility of erroneous data reading can be further reduced. The value of n is preferably as large as possible, but is preferably at least 8 or more.

  In FIG. 7, the reference resistance elements may be connected in parallel within the first reference resistance element array 124A and the second reference resistance element array 124B. Further, the n first reference resistance elements Rr1 and the n second reference resistance elements Rr2 are connected in series without being divided into the first reference resistance element array 124A and the second reference resistance element array 124B. 2n sets may be connected in parallel. Alternatively, the second reference resistance element array 124B may be disposed on the terminal Rai side, and the first reference resistance element array 124A may be disposed on the terminal Rao side.

  Further, the number of first reference resistance elements Rr1 included in the first reference resistance element array 124A and the number of second reference resistance elements Rr2 included in the second reference resistance element array 124B are each n. The number of first reference resistance elements Rr1 constituting the first reference resistance element array 124A may be different from the number of second reference resistance elements Rr2 constituting the second reference resistance element array 124B.

Furthermore, as shown in FIG. 9, the first reference resistance element array 124A has a configuration in which n1 first reference resistance elements Rr1 are connected in series, and n2 sets are connected in parallel, and the second reference resistance elements The element array 124B may have a configuration in which m1 second reference resistance elements Rr2 are connected in series and m2 sets are connected in parallel (where n1, n2, m1, and m2 are integers of 1 or more, n1 ≠ n2, m1 ≠ m2, and n1 × n2 ≠ m1 × m2.) In this case, the resistance value of the first reference resistance element array 124A is (n1 × R _H ) / n2, and the resistance value of the second reference resistance element array 124B is (m1 × R _L ) / m2. . Therefore, the reference resistance value of the reference resistive element array 124 is ((n1 × m2 × R _H ) + (n2 × m1 × R _L )) / (2 × n2 × m2).

  By adopting such a configuration, the following effects can be obtained. FIG. 10 shows an example of the distribution of resistance values of the reference resistance element Rr. In FIG. 10, the horizontal axis represents the resistance value, and the vertical axis represents the number of reference resistance elements.

  The variation in the resistance value of the reference resistance element Rr may differ depending on the resistance value to be set. For example, as shown in FIG. 10, the variation in the distribution D1 may be larger than the variation in the distribution D2. In this case, the optimum number and the second reference resistance element Rr2 set to a relatively low resistance value having a small variation in distribution and the optimum number and distribution for the first reference resistance element Rr1 set to a relatively high resistance value having a large dispersion. It is a different value from the correct number. For this reason, it is preferable to set the number of each of the first reference resistance element Rr1 and the second reference resistance element Rr2 according to the distribution variation.

  Furthermore, when the resistance value of the first reference resistive element array 124A is the average value Ar1 of the distribution D1, and the resistance value of the second reference resistive element array 124B is the average value Ar2 of the distribution D2, the reference shown in FIG. In the case of the resistance element array 124, the reference resistance value is the median value ArM between Ar1 and Ar2, and when the variation of the distribution D1 is large, the reference resistance value may fall within the range of the distribution D1. By configuring the reference resistance element array 124 as shown in FIG. 10, the resistance values of the first reference resistance element array 124A and the second reference resistance element array 124B are changed to the average values Ar1 and D2 of the distribution D1. It can be shifted from the average value Ar2. Thereby, the reference resistance value can be set to ArN near the center between the lower limit of the distribution D1 and the upper limit of the distribution D2.

  n1, n2, m1, and m2 may be determined according to the distribution of variations in resistance characteristics of the reference resistance element Rr. In general, the number of first reference resistance elements Rr1 (n1 × n2) is preferably larger than the number of second reference resistance elements Rr2 (m1 × m2).

  In general, the variation in resistance value of the reference resistance element Rr tends to be larger in the first resistance value having a higher resistance value than in the second resistance value having a lower resistance value as shown in FIG. By making (n1 × n2) larger than (m1 × m2), the number of the first reference resistance elements Rr1 in the high resistance state is averaged over the second reference resistance elements Rr2 in the low resistance state. More than the number. For this reason, the first reference resistive element array 124A in the high resistance state can be brought into an averaged state with higher accuracy.

  Also in FIG. 9, the reference resistance elements may be connected in parallel as in FIG. Alternatively, the second reference resistance element array 124B may be disposed on the terminal Rai side, and the first reference resistance element array 124A may be disposed on the terminal Rao side.

Further, as shown in FIG. 11, n unit arrays 127 each composed of two first reference resistance elements Rr1 and two second reference resistance elements Rr2 shown in FIG. 6 are connected in series. (N is an integer greater than or equal to 1.) It is good also as a structure which connected this in m sets (m is an integer greater than or equal to 1). In this case, the resistance value of the reference resistive element array 124 is (n × (R _H + R _L )) / (2 × m). Even in such a configuration, similarly to the reference resistance element array shown in FIG. 9, by adjusting the values of n and m, the reference resistance value is centered between the lower limit of the distribution D1 and the upper limit of the distribution D2. Can easily be in the vicinity. In this case, the values of n and m may be determined according to the distribution of resistance values of the reference resistance element Rr, but it is generally preferable that n is larger than m. If n is larger than m, the number of unit arrays 127 connected in series becomes larger than the number connected in parallel, and the reference resistance value can be shifted to the Ar2 side. However, n and m may be equal. When both n and m are 1, the configuration shown in FIG. 6 is obtained.

  The first reference resistance element Rr1 and the second reference resistance element Rr2 may be arranged in any manner. However, when attention is paid to a region having a constant area in the reference circuit formation region, it is preferable that the reference circuit is disposed in the region on average. For example, when the number of first reference resistance elements Rr1 is equal to the number of second reference resistance elements Rr2, as shown in FIG. 12A, the first reference resistance element Rr1 and the second reference resistance element Rr1 It is preferable to arrange the resistance elements Rr2 alternately. Even when the number of the first reference resistance elements Rr1 and the number of the second reference resistance elements Rr2 are different, for example, as shown in FIG. It is preferable that the ratio between the number of first reference resistance elements Rr1 and the number of second reference resistance elements Rr2 in the unit region is constant. FIG. 12B shows a case where the ratio of the number of first reference resistance elements Rr1 to the number of second reference resistance elements Rr2 in the 4 × 4 unit region is 3: 1. Any arrangement may be used as long as the ratio in the region is constant.

  When the first reference resistance element Rr1 and the second reference resistance element Rr2 are arranged in a biased manner, the resistance value distribution D1 of the first reference resistance element Rr1 and the resistance value distribution D2 of the second reference resistance element Rr2 are arranged. Deviation from is increased. For this reason, the deviation between the resistance value of the reference resistive element array 124 and the median value between the lower limit of the distribution D1 and the upper limit of the distribution D2 becomes large. If the first reference resistance element Rr1 and the second reference resistance element Rr2 are arranged alternately or so that the ratios in a certain range are equal, the variation in the resistance value distribution D1 of the first reference resistance element Rr1. And the dispersion | variation in resistance value distribution D2 of 2nd reference resistive element Rr2 can be made small, and the shift | offset | difference with the median value of the minimum of distribution D1 and the upper limit of distribution D2 and a reference resistance value can be made small.

  The resistance value of the first reference resistance element Rr1 and the resistance value of the second reference resistance element Rr2 may be set using a reference resistance element setting circuit 141 as shown in FIG. The reference resistance element setting circuit 141 has a plurality of transfer gates connected to both ends of the reference resistance element Rr. In FIG. 13, a second reference resistance element Rr2 is connected in series between two first reference resistance elements Rr1, and three sets of reference resistance elements array 124 are connected in parallel. Shows the case. The reference resistance element setting circuit 141 includes a first transfer gate TG1 that is connected to a terminal of the first first reference resistance element Rr1 that is not connected to the second reference resistance element Rr2, and the first first reference resistance element Rr1. A second transfer gate TG2 connected to a connection node between the first reference resistance element Rr1 and the second reference resistance element Rr2, and the second reference resistance element Rr2 and the second first reference resistance element Rr1. A third transfer gate TG3 connected to the connection node, and a fourth transfer gate TG4 connected to a terminal of the second first reference resistance element Rr1 not connected to the second reference resistance element; have. The first transfer gate TG1 to the fourth transfer gate TG4 are connected to the control terminal CTR1 to the control terminal CTR4, respectively, and connect and disconnect the terminal RDL1 to the power supply terminal RDL4 and the terminal of the reference resistance element Rr, respectively. Can be switched.

  The operation of the reference resistance element setting circuit 141 will be described below. As shown in FIG. 14, in step 1, all transfer gates are turned off. Next, in step 2, the third transfer gate TG3 and the fourth transfer gate TG4 are turned off, and the first transfer gate TG1 and the second transfer gate TG2 are turned on, so that the terminal RDL1 and the terminal A voltage or current is applied from the terminal RDL1 and the terminal RDL2 to the three first reference resistance elements Rr1 connected to the RDL2. Next, in step 3, the first transfer gate TG1 and the fourth transfer gate TG4 are turned off, and the second transfer gate TG2 and the third transfer gate TG3 are turned on, so that the terminal RDL2 and the terminal A voltage or a current is applied from the terminal RDL2 and the terminal RDL3 to the three second reference resistance elements Rr2 connected to the RDL3. Next, in step 4, the first transfer gate TG1 and the second transfer gate TG2 are turned off, and the third transfer gate TG3 and the fourth transfer gate TG4 are turned on, whereby the terminals RDL3 and RDL4 A voltage or current is applied from the terminal RDL3 and the terminal RDL4 to the three first reference resistance elements Rr1 connected between the terminals RDL1 and RDL4. Next, in step 5, all transfer gates are turned off.

  In this way, the resistance values of a plurality of reference resistance elements Rr can be set at a time. By setting the resistance value of the reference resistance element Rr under the same conditions, it is possible to reduce variations in the resistance value of the reference resistance element Rr. Further, since the time required for setting can be greatly shortened, it is possible to achieve cost reduction by shortening the time. In addition, the electrical inspection of the reference resistive element Rr constituting the reference resistive element array 124 can be performed at the same time, and the time for electrical inspection of the semiconductor memory device can be shortened.

  Further, the resistance value of the reference resistance element Rr may be set by steps as shown in FIG. In this case, the resistance value can be set for all the first reference resistance elements Rr1 at once. For this reason, the variation of the resistance value can be further reduced, and the set time can be shortened.

  As an example, the reference resistance element array 124 including six first reference resistance elements Rr1 and three second reference resistance elements Rr2 is shown, but the first reference resistance elements are arranged in the column direction. In the case of a matrix-like reference resistance element array 124 in which Rr1 and second reference resistance elements Rr2 are alternately arranged and the same type of reference resistance elements Rr are arranged in the row direction, the number of reference resistance elements Rr is as follows. It can be set in any way.

  Further, it is not necessary that the first reference resistance element Rr1 and the second reference resistance element Rr2 are alternately arranged in the column direction. As shown in FIG. 16, two first reference resistance elements Rr1 and In the case of the reference resistor element array 124 in which one second reference resistor element Rr2 is alternately arranged, both ends of the reference resistor element array 124, the first reference resistor element Rr1 and the second reference resistor are arranged. What is necessary is just to connect the output of a transfer gate to the node to which element Rr2 was connected. FIG. 16 shows an example in which the number n of the first reference resistance elements Rr1 arranged continuously is 2 and the number m of the second reference resistance elements Rr2 arranged continuously is 1. , N and m can be set in any way. In addition, the number of first reference resistance elements Rr1 or the number of second reference resistance elements Rr2 arranged in succession does not always have to be the same, and may differ from place to place. Further, a configuration in which one block of the first reference resistance element Rr1 and one block of the second reference resistance element Rr2 are arranged one by one is possible. In FIG. 16, nodes in which Rr1 are connected in series are connected to each other, but a configuration in which the nodes are not connected may be employed.

  Although an example in which the reference resistor element setting circuit 141 is configured by a transfer gate has been shown, it is only necessary to selectively apply a voltage or current, and other switch elements may be used, or a circuit such as an inverter may be used.

  The resistance values of the first reference resistance element Rr1 and the second reference resistance element Rr2 are changed by changing the voltage or current value applied by the reference resistance element setting circuit 141 or the time during which the voltage or current is applied. be able to. For example, in the reference resistance element setting circuit 141 illustrated in FIG. 13 or FIG. 16, the voltage or current applied to the terminals RDL1 to RDL4 is adjusted, or the first transfer gate TG1 to the fourth transfer gate TG4 are turned on. The resistance value of at least a part of the first reference resistance element Rr1 or at least a part of the second reference resistance element Rr2 is set in the reference resistance element Rr by adjusting the time for turning on or turning off. It can be set to a resistance value between the highest possible resistance value and the lowest possible resistance value.

  Depending on the material, the reference resistance element Rr may have a higher resistance value stability than the highest resistance value or the lowest resistance value that can be set depending on the material. In this case, as shown in FIG. 17, the distribution D3 of the resistance value of the first reference resistance element Rr1 set to a resistance value between the highest resistance value and the lowest resistance value that can be set is the highest that can be set. The variation is smaller than the resistance value distribution D1 of the first reference resistance element Rr1 set to a high resistance value. Further, the distribution D2 of the resistance value of the second reference resistance element Rr2 set to a resistance value between the highest and lowest settable resistance value is the second set to the lowest settable resistance value. The variation is smaller than the resistance value distribution D2 of the reference resistance element Rr2. Therefore, the number of first reference resistance elements Rr1 and the number of second reference resistance elements Rr2 required to stabilize the resistance value of the first reference resistance element array 124A and the resistance value of the second reference resistance element array 124B. The number can be reduced. Therefore, the area occupied by the reference resistive element array 124 can be reduced, and further, the price of the semiconductor memory device can be reduced.

  The optimum number of the first reference resistor elements Rr1 and the optimum number of the second reference resistor elements Rr2 constituting the reference resistor element array 124 are mainly determined by the resistance of the data storage resistor element and the reference resistor element Rr due to the manufacturing process or the like. It depends on the variation of characteristics. For this reason, after measuring the resistance characteristics of the data storage resistance element Rd and the reference resistance element Rr after the manufacturing process, the first reference resistance element Rr1 and the second reference resistance element Rr1 constituting the reference resistance element array 124 according to the measured resistance characteristics. If the number of reference resistance elements Rr2 can be set, the possibility of erroneous data reading can be further reduced.

  As shown in FIG. 18, by providing the reference resistance element control circuit 143, the number of first reference resistance elements Rr1 and second reference resistance elements Rr2 constituting the reference resistance element array 124 can be arbitrarily set. It becomes possible. The reference resistance element control circuit 143 includes a register 144 configured by a latch circuit or the like. The register 144 includes the number of reference resistance elements Rr that are set to the first reference resistance element Rr1 in the high resistance state by the reference resistance element setting circuit 141 and the reference resistance that is set to the second reference resistance element Rr2 in the low resistance state. The number of elements Rr is stored. Based on the information stored in the register 144, the reference resistor element setting circuit 141 sets only the required number of reference resistor elements Rr as the first reference resistor element Rr1 and the second reference resistor element Rr2.

  By storing information in the register, setting of the first reference resistance element Rr1 and the second reference resistance element Rr2 can be completed in a short time. In addition, since the optimum number can be set for each semiconductor memory device, the yield of the semiconductor memory device can be improved and the manufacturing cost of the semiconductor memory device can be reduced.

  The reference resistance element control circuit 143 may use a nonvolatile memory 145 such as a flash memory instead of the register 144 as shown in FIG. Once the number information is set by using a non-volatile memory, the number information is retained even when the power is turned off and then turned on again. Therefore, it is necessary to reset the number information when the power is turned on again. There is no. Therefore, it is possible to increase the speed, reduce power consumption, and improve the function of the semiconductor memory device.

  The data storage resistance element Rd and the reference resistance element Rr are gradually deteriorated after manufacture. For this reason, even if the resistance characteristics are confirmed immediately after manufacturing and the optimum number of the first reference resistance element Rr1 and the second reference resistance element Rr2 constituting the reference resistance element array 124 is determined, the continuous use is continued. As a result, the optimum number may vary. For example, immediately after manufacturing, as shown in FIG. 20A, the first resistance value has a distribution D1, the second resistance value has a distribution D2, and the average value of the distribution D1 is Ar1. Assume that the average value of D2 is Ar2. When stress due to use is applied, the distribution of the resistance characteristic of the reference resistance element Rr changes, and as shown in FIG. 20B, the distribution of the first resistance value becomes D3 and the average value becomes Ar3, and the second resistance value. The distribution of D4 becomes D4 and the average value becomes Ar4. In this case, when the optimum number of the first reference resistance element Rr1 and the second reference resistance element Rr2 determined based on the distribution D1 and the distribution D2 is applied, the reference resistance value is set to the lower limit of the distribution D3 and the upper limit of the distribution D4. And can't be in the middle. Therefore, a part of the reference resistance element Rr is deteriorated in advance, the resistance characteristics in the deteriorated state are measured, and the first reference resistance element Rr1 and the second reference resistance element Rr2 are measured based on the resistance characteristics in the deteriorated state. An optimal number may be determined. In this case, the predetermined reference resistance element Rr is used as the degradation characteristic detection element, and after applying stress to the degradation characteristic detection element, the reference resistance element array 124 is configured based on the resistance characteristic of the degradation characteristic detection element. The optimum number of reference resistance elements Rr1 and second reference resistance elements Rr2 may be determined. In this case, the reference resistance element array 124 may be configured by the reference resistance elements Rr excluding the reference resistance element Rr used as the deterioration characteristic detection element.

  The stress applied to the degradation characteristic detecting element may be temperature application, voltage application including data writing and reading, or current application, or a combination of these. Moreover, these may be applied continuously and may be applied intermittently on and off.

  The optimum number of the first reference resistor elements Rr1 and the optimum number of the second reference resistor elements Rr2 constituting the reference resistor element array 124 are the use time, the number of accesses, the applied voltage, the applied current, and the use of the semiconductor memory device. It also changes depending on usage conditions such as temperature. For this reason, as shown in FIG. 21, a usage status detection circuit 147 and an optimum number information signal generation circuit 148 are provided, and the set number of the first reference resistance element Rr1 and the second reference resistance element Rr2 is changed depending on the usage status. do it.

  The usage status detection circuit 147 detects a usage status index including at least one of the usage time, the number of accesses, the applied voltage, the applied current, and the usage temperature of the semiconductor memory device, and the status based on the detected usage status index. An information signal Ssi is output. The optimum number information signal generation circuit 148 converts the situation information signal Ssi into optimum number information Sbsi and outputs it to the reference resistance element control circuit 143. The reference resistance element control circuit 143 controls the reference resistance element setting circuit 141 based on the optimum number information Sbsi.

  The optimum number information signal generation circuit 148, for example, table data that associates the optimum number of the first reference resistance element Rr1 and the second reference resistance element Rr2 constituting the reference resistance element array 124 with the status information signal Ssi. As the number selection information, and the situation information signal Ssi may be converted into the optimum number information signal Sbsi using the table data.

  In this way, it is possible to automatically set the reference resistive element array 124 to the optimum state at all times, and to improve the characteristics of the semiconductor memory device. In addition, it is possible to extend the life and guaranteed durability of the semiconductor memory device.

  Variations in the resistance characteristics of the data storage resistance element Rd and the reference resistance element Rr not only change depending on the use situation, but may change even when left unused. Therefore, based on the distribution of resistance values of the reference resistance element Rr and the distribution of resistance values of the data storage resistance element Rd, the first reference resistance element Rr1 and the second reference resistance element Rr2 constituting the reference resistance element array 124. By determining the number of semiconductor memory devices, the characteristics of the semiconductor memory device can be further stabilized.

  For example, as shown in FIG. 22, a distribution information detection circuit 151 for detecting a distribution state of at least one resistance value of the data storage resistance element Rd and the reference resistance element Rr is provided, and the distribution information detection circuit 151 uses the reference resistance element control circuit. 143 may be controlled.

  The distribution information detection circuit 151 may be configured to include, for example, a power-on detection circuit 152, a resistance element readout circuit 153, a resistance distribution information storage circuit 154, and a resistance element distribution control circuit 155. The power-on detection circuit 152 detects whether or not the semiconductor memory device is in an operating state, and outputs a power-on signal Spo when the power is turned on. When the power-on signal Spo is input, the resistance element reading circuit 153 reads the resistance value in the low resistance state and the resistance value in the high resistance state for at least one of the data storage resistance element Rd and the reference resistance element Rr, The resistance value is output as resistance value information Sr. The reading of the resistance value and the output of the resistance value information Sr are performed for all of the preset distribution detection elements. The resistance distribution information accumulation circuit 154 sequentially accumulates the resistance information Sr output from the resistance element readout circuit 153, and outputs the accumulated signal as resistance distribution information Sctr. The resistance element distribution control circuit 155 determines the optimal number of first reference resistance elements Rr1 and second reference resistance elements Rr2 constituting the reference resistance element array 124 based on the resistance distribution information Sctr, and optimal man-hour information Output as signal Sbcsr.

  The number of data storage resistance elements Rd and reference resistance elements Rr used as distribution detection elements may be set in any manner as long as statistically reliable distribution information can be obtained. Moreover, it is good also as a state which applied stress to the distribution detection element previously, and deteriorated more. In this way, the margin for deterioration can be increased. In addition, at least a part of the data storage resistance element Rd and the reference resistance element Rr is not used as a distribution detection element, but a dedicated variable resistance element having the same structure as the data storage resistance element Rd and the reference resistance element Rd is distributed. You may provide separately as an element.

  The resistance value of the reference resistance element array 124 and the resistance value of the memory cell 136 may be compared using, for example, a sense amplifier circuit. Specifically, as shown in FIG. 23, the bit line BL from the memory cell 136 and the reference bit line / BL from the reference resistor circuit 121 may be input to the sense amplifier circuit 161.

  As shown in FIG. 24, the bit lines BL of the memory cells 136 included in the memory cell array 131 may be collectively input to the sense amplifier circuit 161. In this way, the information stored in the plurality of memory cells 136 can be discriminated by the same sense amplifier circuit 161, so that the capacity of the semiconductor memory device can be increased. In addition, an effect of downsizing the semiconductor memory device can be obtained.

  Further, as shown in FIG. 25, the memory cell 136 is divided into a plurality of memory cell units 138, the bit lines BL are grouped for each memory cell unit 138, and the grouped bit lines BL are selected by the bit line selection circuit 165. May be input to the sense amplifier circuit 161. In this way, the capacity can be further increased.

  In the present embodiment, the field-induced resistance change memory (RRAM) has been described. However, the present invention can also be applied to other resistance change type semiconductor memory devices such as a phase change memory (PRAM) and a magnetoresistive memory (MRAM). .

  The semiconductor memory device according to the present invention can accurately read out data even if individual differences occur between the variable resistance element for storing data and the reference variable resistance element, while suppressing an increase in area. In particular, it is useful in a semiconductor memory device or the like provided with a variable resistance element and a reference constant resistance element.

DESCRIPTION OF SYMBOLS 101 Substrate 102 Reference circuit formation area 103 Memory cell formation area 121 Reference resistance circuit 124 Reference resistance element array 124A First reference resistance element array 124B Second reference resistance element array 126 Reference resistance element pair 127 Unit array 131 Memory cell array 136 Memory Cell 138 Memory cell unit 141 Reference resistance element setting circuit 143 Reference resistance element control circuit 144 Register 145 Non-volatile memory 147 Usage state detection circuit 148 Optimal number information signal generation circuit 151 Distribution information detection circuit 152 Power-on detection circuit 153 Resistance element read circuit 154 Resistance distribution information storage circuit 155 Resistance element distribution control circuit 161 Sense amplifier circuit 165 Bit line selection circuit 200 Wafer 201 Semiconductor chip

Claims (23)

A memory cell array formed in a memory cell region of a substrate, and a plurality of memory cells arranged in a matrix;
A reference resistance circuit formed in a reference circuit region of the substrate and generating a reference resistance value;
A comparison circuit for comparing the resistance value of the memory cell and the reference resistance value;
The memory cell has a data storage resistance element which is a variable resistance element having a first data resistance value or a second data resistance value lower than the first data resistance value corresponding to stored data,
The reference resistance circuit includes a first reference resistance element and a second reference resistance element, each of which is a variable resistance element having the same structure as the data storage resistance element,
The first reference resistance element is set to a first resistance value;
The second reference resistance element is set to a second resistance value lower than the first resistance value;
The reference resistance value is a resistance value between the first resistance value and the second resistance value generated by connecting the first reference resistance element and the second reference resistance element. A semiconductor memory device.   The semiconductor memory device according to claim 1, wherein the first reference resistance element and the second reference resistance element are plural.   The semiconductor memory device according to claim 2, wherein the number of the first reference resistance elements is equal to the number of the second reference resistance elements.   3. The semiconductor memory device according to claim 2, wherein the number of the first reference resistance elements is different from the number of the second reference resistance elements.   The semiconductor memory device according to claim 4, wherein the number of the first reference resistance elements is larger than the number of the second reference resistance elements.   3. The semiconductor memory device according to claim 2, wherein a distribution of the first reference resistance element and a distribution of the second reference resistance element in the reference circuit region are uniform.   7. The semiconductor memory device according to claim 6, wherein in the reference circuit region, the first reference resistance elements and the second reference resistance elements are alternately arranged.   The semiconductor memory device according to claim 2, wherein the memory cell region and the reference circuit region are arranged adjacent to each other on the substrate.   The reference resistance circuit collectively sets two or more of the first reference resistance elements to the first resistance value, and collectively sets two or more of the second reference resistance elements to the second resistance element. The semiconductor memory device according to claim 2, further comprising a reference resistance element setting circuit that sets the resistance value. The reference resistance circuit sets the first resistance value to a resistance value lower than the highest resistance value that can be set in the variable resistance element and higher than the lowest resistance value, and sets the second resistance value to the second resistance value. A resistance value changing circuit for setting a resistance value higher than the lowest resistance value that can be set in the variable resistance element and lower than the first resistance value;
The resistance value changing circuit adjusts a voltage or a current value applied to at least one of the first reference resistance element and the second reference resistance element, or a time for applying the voltage or current. 2. The semiconductor memory device according to 2.   The reference resistance circuit selects at least a part of the first reference resistance element and the second reference resistance element as a first reference resistance element and a second reference resistance element for generating the reference resistance value. The semiconductor memory device according to claim 2, further comprising a reference resistance element selection circuit that performs the selection.   The reference resistance element selection circuit includes a register or a nonvolatile memory that stores the number of the first reference resistance elements to be selected and the number of the second reference resistance elements to be selected. Item 12. The semiconductor memory device according to Item 11. The reference resistance circuit is:
A status information detection circuit that detects status information indicating a usage status of the memory cell array and outputs a status information signal based on the status information;
An optimum number information signal generating circuit for generating and outputting an optimum number information signal based on the situation information signal,
The status information includes information on at least one of use time, number of accesses, applied voltage, current, and use temperature,
The optimum number information signal generation circuit uses correspondence information between the number of the first reference resistance elements and the number of the second reference resistance elements used to generate the reference resistance value stored in advance and the status information signal. Conversion from the status information signal to the optimum number information signal based on,
12. The reference resistance element selection circuit selects the first reference resistance element and the second reference resistance element used for generating the reference resistance value based on the optimum number information signal. The semiconductor memory device described in 1. The reference resistance circuit uses at least a part of the data storage resistance element as a first distribution detection element, and detects first distribution information that is distribution information of resistance values of the first distribution detection element. Distribution information detection circuit
The reference resistance element selection circuit selects the first reference resistance element and the second reference resistance element used for generating the reference resistance value based on the first distribution information. 11. The semiconductor memory device according to 11. The reference resistance circuit uses at least a part of the first reference resistance element and the second reference resistance element as a second distribution detection element, and is a distribution information of a resistance value of the second distribution detection element. A second distribution information detection circuit for detecting the distribution information of 2;
The reference resistance element selection circuit selects the first reference resistance element and the second reference resistance element to be used for generating the reference resistance value based on the second distribution information. 11. The semiconductor memory device according to 11. The reference resistance circuit is a part of the variable resistance element formed in the reference circuit region, and has a resistance characteristic higher than that of the first reference resistance element and the second reference resistance element by applying stress. It has a deterioration detecting element that is a deteriorated variable resistance element,
The reference resistance element selection circuit selects the first reference resistance element and the second reference resistance element used to generate the reference resistance value based on a resistance characteristic of the deterioration detection element. Item 12. The semiconductor memory device according to Item 11.   17. The stress according to claim 16, wherein the stress includes at least one of a stress due to a use environment temperature, a stress due to an access count, a stress due to a data inversion count, a stress due to an applied voltage, a stress due to an applied current, and a stress due to an application time. The semiconductor memory device described.   3. The semiconductor memory device according to claim 2, wherein the data storage resistive element, the first reference resistive element, and the second reference resistive element are formed on the substrate with the same planar pattern. A bit line connected to the memory cell and outputting a first electrical signal corresponding to information stored in the memory cell;
A reference bit line connected to the reference resistance circuit and outputting a second electrical signal corresponding to the reference resistance value;
3. The semiconductor memory device according to claim 2, wherein each circuit of the previous period is a sense amplifier circuit connected to the bit line and the reference bit line. A plurality of the bit lines;
The semiconductor memory device according to claim 19, wherein the sense amplifier circuit includes a selection circuit that selectively connects one of the bit lines.   The semiconductor memory device according to claim 19, wherein at least one of the memory cell and the reference resistance circuit includes only a variable resistance element.   20. The semiconductor memory device according to claim 19, wherein at least one of the memory cell and the reference resistance circuit includes a variable resistance element and a selection transistor.   The semiconductor memory device according to claim 19, wherein at least one of the memory cell and the reference resistance circuit includes a variable resistance element and a diode element.

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