JP5828480B2 - Piezoelectric device - Google Patents

Description

  The present invention relates to a piezoelectric device used in electronic equipment and the like.

  Conventionally, a signal source such as a reference signal source or a clock signal source is mounted on an electronic device such as a mobile phone, and a piezoelectric device is known as such a signal source.

  The piezoelectric device includes an element mounting member, and a piezoelectric element and an integrated circuit element mounted on the element mounting member. The integrated circuit element is cut out from an aggregate (that is, a wafer) of a plurality of integrated circuit elements. For example, a metal pattern may be provided on each edge of a plurality of integrated circuit elements in order to reduce the deflection of the wafer as the size of the wafer increases.

JP 2011-234203 A

  However, since the metal pattern is provided on the edge of the integrated circuit element, when the integrated circuit element is mounted on the element mounting member by solder, the solder contacts the metal pattern, and a plurality of integrated circuit elements There is a possibility that the electrode is short-circuited through the metal pattern.

A piezoelectric device according to one aspect of the present invention includes an element mounting member, a piezoelectric element mounted on the element mounting member, and a conductor pattern provided on the surface of the element mounting member and including a pad region and a wiring region. And an integrated circuit component electrically connected to the pad area of the conductor pattern by a solder bump, and an integrated circuit element and a metal pattern provided at an edge of the surface connected by the solder bump of the integrated circuit element Including. The conductor pattern further includes a solder flow prevention region provided between the pad region and the wiring region. The solder flow prevention region is provided at a position overlapping the metal pattern of the integrated circuit component or inside the metal pattern in plan view.

  In the piezoelectric device according to one aspect of the present invention, the solder flow prevention region is provided at a position overlapping the metal pattern of the integrated circuit component in a plan view or inside the metal pattern, so that the solder can contact the metal pattern. The possibility that the plurality of electrodes of the integrated circuit element are short-circuited is reduced.

It is a longitudinal section showing a piezoelectric device in an embodiment of the present invention. It is a top view which shows the state which removed the integrated circuit element in the piezoelectric apparatus shown by FIG. It is a top view which shows the integrated circuit element in the piezoelectric apparatus shown by FIG. FIG. 2 is a plan view showing an example of electrical connection of integrated circuit elements in the piezoelectric device shown in FIG. 1. It is a longitudinal cross-sectional view which shows the joining state of the connection part in the piezoelectric apparatus shown by FIG.

  Hereinafter, exemplary embodiments of the present invention will be described with reference to the drawings.

  As shown in FIGS. 1 and 2, the piezoelectric device 100 according to the embodiment of the present invention is mounted on the element mounting member 110, the integrated circuit component 120 mounted on the element mounting member 110, and the element mounting member 110. And a piezoelectric element 130 electrically connected to the integrated circuit component 120. FIG. 1 is a longitudinal sectional view taken along line AA of the piezoelectric device 100 shown in FIG.

  The element mounting member 110 includes an insulating base 111 including a substrate portion 111a, a first frame portion 111b provided on the upper surface of the substrate portion 111a, and a second frame portion 111c provided on the lower surface of the substrate portion 111a. It includes a plurality of conductor patterns 113 and a pair of monitoring terminals 114a and 114b provided on the upper surface of the portion 111a, and a plurality of external terminals 116 provided on the upper surface of the first frame portion 111b. Here, the recess on the upper surface of the element mounting member 110 is defined as a first recess K1, and the recess on the lower surface is defined as a second recess K2.

In FIG. 2, the plurality of conductor patterns 113 are indicated as 113 a to 113 f by adding alphabet letters a to f after the reference numeral 113. The plurality of conductor patterns 113a to 113f are, for example, an output pattern 113a, a ground pattern 113b, a control pattern 113c, a power supply pattern 113d, a first input pattern 113e, and a second input pattern 113f. Further, in FIG. 2, for example, the output pattern 113a includes an output pad areas 113a ₁ and the output wiring region 113a _2, and the output pad region 113a ₁ and a solder flow preventing region 113a ₃ provided between the output wiring region 113a ₂ Is included. For example, the ground pattern 113b includes a ground pad region 113b ₁ and the ground line area 113b _2, and a solder flow preventing region 113b ₃ provided between the ground pad region 113b ₁ and the ground wiring region 113b _2. For example, the control pattern 113c includes a control pad region 113c ₁ and the control line region 113c _2, and a solder flow preventing region 113c ₃ provided between the control pad area 113c ₁ and the control wiring region 113c _2. For example, the power supply pattern 113d includes a power supply pad region 113d ₁ and a power supply wiring region 113d _2, and a solder flow preventing region 113d ₃ provided between the power supply pad region 113d ₁ and the power supply wiring region 113d _2. For example, the first input pattern 113e is provided first between the input pad region 113e ₁ and a first input wiring region 113e _2, between the first input pad area 113e ₁ and a first input wiring region 113e ₂ was and a solder flow preventing region 113e _3. For example, the second input pattern 113f is provided second to the input pad region 113f ₁ and the second input wiring region 113f _2, to the second input pad area 113f ₁ and the second between the input wiring region 113f ₂ It was and a solder flow preventing region 113f _3.

  In FIG. 2, the external terminals 116 are indicated as 116 a to 116 d by adding alphabet letters a to d after the reference numeral 116. The plurality of external terminals 116a to 116d are, for example, an output external terminal 116a, a ground external terminal 116b, a control external terminal 116c, and a power supply external terminal 116d.

  The substrate portion 111a, the first frame portion 111b, and the second frame portion 111c are made of a ceramic material such as alumina ceramics or glass-ceramics. Moreover, the board | substrate part 111a is a rectangular flat plate shape in planar view, for example, as FIG.1 and FIG.2 shows. The first frame portion 111b is provided along the edge portion of the upper surface of the substrate portion 111a. The second frame portion 111c is provided along the edge portion of the lower surface of the substrate portion 111a.

  Of the plurality of conductor patterns 113a to 113f, the first input pattern 113e is electrically connected to the monitor terminal 114a via an inner layer wiring (not shown) of the substrate portion 111a. The second input pattern 113f is electrically connected to the monitor terminal 114b via an inner layer wiring (not shown) of the substrate portion 111a.

  The output pattern 113a is applied with a signal output from the integrated circuit component 120 and is electrically connected to the output external terminal 116a. The ground pattern 113b is electrically connected to the ground external terminal 116b, and a ground voltage is applied. The control pattern 113c is electrically connected to the control external terminal 116c, and a signal (that is, a control signal) for controlling the output state of the integrated circuit component 120 is applied. The power supply pattern 113d is electrically connected to the power supply external terminal 116d, and a power supply voltage is applied. The first input pattern 113e and the second input pattern 113f are electrically connected to the piezoelectric element 130, and an output signal of the piezoelectric element 130 input to the integrated circuit component 120 is applied.

  As shown in FIG. 2, the pair of monitoring terminals 114a and 114b have a quadrangular shape parallel to the short side and the long side of the first recess K1. The pair of monitoring terminals 114 a and 114 b are terminals for measuring an output signal of the piezoelectric element 130.

The integrated circuit component 120 is provided in the first recess K <b> 1 and is electrically connected to the plurality of conductor patterns 113 of the element mounting member 110 by solder bumps 125. As shown in FIG. 3, the integrated circuit component 120 has a metal pattern 124 provided on the edge of the surface connected to the integrated circuit element 121 by the solder bump 125 of the integrated circuit element 121. . Further, the integrated circuit element 121 has a plurality of electrodes 122. In FIG. 3, the plurality of electrodes 122 and the metal pattern 124 are indicated by broken lines through a part of the integrated circuit element 120. In FIG. 3, the plurality of electrodes 122 are indicated as 122 a to 122 f by adding alphabet letters a to f after the reference numeral 122.

  Here, an example of the plurality of electrodes 122a to 122f of the integrated circuit element 121 will be described. The plurality of electrodes 122a to 122f are, for example, an output electrode 122a, a ground electrode 122b, a control electrode 122c, a power supply electrode 122d, a first input electrode 122e, and a second input electrode 122f.

  As shown in FIG. 4, the output electrode 122a is electrically connected to the output pattern 113a via the solder bump 125, and an output signal is output. The ground electrode 122b is electrically connected to the ground pattern 113b via the solder bump 125, and a ground voltage is applied. The control electrode 122c is electrically connected to the control pattern 113c, and a signal for controlling the output state of the signal from the control electrode 122c is input. The power supply electrode 122d is electrically connected to the power supply pattern 113d, and a power supply voltage is applied thereto. The first input electrode 122e and the second input electrode 122f are electrically connected to the piezoelectric element 130 via the first input pattern 113e and the second input pattern 113f.

  The piezoelectric element 130 is provided in the second recess K2, and is connected to the first input electrode 122e and the second input electrode 122f of the integrated circuit element 121 via the first and second input patterns 113e and 113f. Electrically connected. The piezoelectric element 130 includes a piezoelectric element plate cut along a predetermined crystal axis, and a connection electrode and an excitation electrode formed on the piezoelectric element plate. The piezoelectric element 130 causes a thickness shear vibration at a predetermined frequency when a varying voltage from the outside is applied to the piezoelectric element plate via the connection electrode and the excitation electrode. As the piezoelectric element plate, for example, AT-cut quartz is used. The second recess K2 of the element mounting member 110 in which the piezoelectric element 130 is accommodated is hermetically sealed by the lid member 140.

Here, the solder flow prevention regions 113a ₃ to 113a of the plurality of electrodes 122a to 122f and the metal pattern 124 of the integrated circuit element 121 and the conductor patterns 113a to 113f provided on the upper surface of the substrate portion 111a in the piezoelectric device 100 of this embodiment. 4 positional relationship between the 113f _3, will be described with reference to FIG.

As shown in FIG. 4, the integrated circuit component 120 is provided in the first recess K1. The plurality of electrodes 122a to 122f of the integrated circuit element 121 are located in a region near the long side of the first recess K1. The metal pattern 124 provided on the edge of the surface connected by the solder bump 125 of the integrated circuit element 121 is provided outside the plurality of electrodes 122a to 122f so as to surround the plurality of electrodes 122a to 122f.

In addition, the conductor patterns 113a to 113f provided on the upper surface of the substrate portion 111a include solder flow prevention regions 113a _{3 to} 113f ₃ provided between the pad regions 113a _{1 to} 113f ₁ and the wiring regions 113a _{2 to} 113f _2. It is configured to be equipped. The conductor patterns 113a to 113f have a three-layer structure. For example, molybdenum (Mo) is formed in the lower layer, nickel (Ni) is formed in the intermediate layer, and gold (Au) is formed in the upper layer, for example.

The solder flow prevention regions 113a _{3 to} 113f ₃ are for hindering the flow of solder, for example, a convex portion having a height difference that hinders the flow of solder, or a portion made of a metal oxide having relatively low wettability with the solder. Or it is the recessed part etc. which a solder tends to collect. The convex portion is formed, for example, by irradiating the conductor patterns 113a to 113f with a laser. Further, the portion made of the metal oxide is generated by reacting with air by, for example, nickel (Ni) in the intermediate layer of the conductor patterns 113a to 113f being scraped with a laser and generating heat. The recess is formed by cutting an intermediate layer such as nickel (Ni) and an upper layer such as gold (Au). As described above, the convex portion, the metal oxide, and the concave portion are formed at a time by irradiating the conductor patterns 113a to 113f with laser.

As described above, the solder flow prevention regions 113a _{3 to} 113f ₃ of the piezoelectric device 100 according to the present embodiment, for example, irradiate the laser to the conductor patterns 113a to 113f, and for example, nickel (Ni ) And an upper layer such as gold (Au). As the laser, for example, a carbon dioxide laser, a YAG laser, a YVO ₄ laser, a semiconductor laser, an excimer laser, or the like is used.

Here, the solder flow prevention regions 113a _{3 to} 113f _{3 of the} conductor patterns 113a to 113f provided on the upper surface of the substrate portion 111a and the metal pattern 124 provided on the edge of the integrated circuit element 121 are shown in FIGS. As shown in FIG. 5, the solder flow prevention regions 113 a _{3 to} 113 f ₃ are formed so as to overlap the metal pattern 124 formed in the integrated circuit element 121 or inside the metal pattern 124.

In the piezoelectric device 100 of the present embodiment, for example, as shown in FIG. 5, at least the edge of the solder flow prevention region 113b ₃ facing the inside of the element mounting member 110 is formed inside the metal pattern 124. . Therefore, the piezoelectric device 100 of this embodiment, in the inside than the metal pattern 124 of the integrated circuit device 121, since the solder flow preventing region 113b ₃ of the conductor pattern 113, is stopped solder flow, integrated circuit element by metal patterns 124 The possibility that the plurality of electrodes 122a to 122f of 121 are short-circuited is reduced.

In addition, the solder flow prevention regions 113a _{3 to} 113f ₃ irradiate the conductor patterns 113a to 113f with laser to remove the plating layer on the surface layer portion, and the bulge of the plating removed in the vicinity of the portion where the plating layer is removed. It is formed. Since at least the surface portion of the plating bulge is made of a metal oxide having low solder wettability such as nickel (Ni), for example, the expansion of the solder bumps 125 in the pad regions 113a _{1 to} 113f ₁ can be stopped.

Therefore, the piezoelectric device 100 according to this embodiment includes solder bumps that electrically connect the pad regions 113a _{1 to} 113f ₁ provided on the upper surface of the substrate portion 111a and the plurality of electrodes 122a to 122f of the integrated circuit element 121. 125 can be prevented from spreading to the metal pattern 124 formed on the edge of the integrated circuit element 121. Therefore, the piezoelectric device 100 of this embodiment can reduce the possibility that the plurality of electrodes 122a to 122f of the integrated circuit element 121 are short-circuited via the metal pattern 124.

In addition, the solder flow prevention regions 113a _{3 to} 113f ₃ provided on the upper surface of the substrate portion 111a of the piezoelectric device 100 of the present embodiment are insulated on the conductor patterns 113a to 113f, for example, besides being formed by laser irradiation. A layer or a metal layer may be formed and a convex part may be provided.

  Examples of the insulating layer include a ceramic coat (for example, alumina coat) or a resin. The ceramic coat or resin is provided on the conductor patterns 113a to 113f by screen printing. The ceramic coat or the resin can be formed simultaneously by screen printing with a plurality of insulating layers, so that the manufacturing cost can be reduced. Since the insulating layer has lower wettability with the solder than the conductor pattern, it is possible to further reduce the flow of solder.

  Further, the metal layer is, for example, an Al film or a Cr film, and is formed by a vacuum printing method such as sputtering. Since an Al film, a Cr film, or the like can be formed by sputtering a plurality of metal layers at the same time, the manufacturing cost can be reduced.

In the laser forming method, since the convex portions can be formed by cutting the conductor patterns 113a to 113f with a laser, it is not necessary to separately prepare a material for forming the convex portions, and the productivity can be improved by reducing the members. It becomes possible. Further, in the laser forming method, since the element mounting member 110 on which the conductor pattern 113 is formed is formed by post-processing, for example, the solder flow prevention regions 113a _{3 to} 113f corresponding to the size of the integrated circuit component 120. _{Thus, the} degree of freedom in manufacturing is increased.

  In the above-described embodiment, various changes and improvements can be made without departing from the scope of the present invention. For example, in the above-described embodiment, the AT-cut piezoelectric element 130 is shown as the piezoelectric element plate mounted in the second recessed space K2 of the piezoelectric device 100. However, the present invention is not limited to this, and for example, a tuning-fork type vibration element or elastic A surface wave element may be used.

DESCRIPTION OF SYMBOLS 100 ... Piezoelectric device 110 ... Element mounting member 111 ... Insulation base | substrate 111a ... Substrate part 111b ... 1st frame part 111c ... 2nd frame part 113 ... Conductor pattern 113a _{1 ~113f 1} ··· pad area 113a ₂ ~113f ₂ ··· wiring region 113a ₃ ~113f ₃ ··· terminal solder flow prevention region 114 ... monitor 116 ... external terminals 120 ... integrated circuits Component 121 ... Integrated circuit element 122 ... Electrode 124 ... Metal pattern 125 ... Solder bump 130 ... Piezoelectric element 140 ... Lid member K1 ... First recess K2 ... First 2 recesses

Claims (1)

An element mounting member;
A piezoelectric element mounted on the element mounting member;
A conductor pattern provided on the surface of the element mounting member, including a pad region and a wiring region;
An integrated circuit that is electrically connected to the pad region of the conductor pattern by a solder bump, and includes an integrated circuit element and a metal pattern provided at an edge of the surface connected by the solder bump of the integrated circuit element. Circuit components and
The conductor pattern further includes a solder flow prevention region provided between the pad region and the wiring region;
The piezoelectric device, wherein the solder flow prevention region is provided at a position overlapping the metal pattern of the integrated circuit component or inside the metal pattern in plan view.

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