JP5813485B2 - A / D converter - Google Patents

Description

The present invention relates to A / D converter for converting a digital signal to one of the multiple input signals.

As this type of A / D converter , a ΔΣ A / D converter disclosed in Patent Document 1 below is known. This ΔΣ A / D converter is configured to include a multiplexer and a setting circuit. In this ΔΣ A / D converter , the setting circuit generates and outputs a signal for controlling the switching state of the multiplexer based on a signal input from the outside, and the multiplexer is based on the signal output from the setting circuit. Thus, one of the plurality of analog input signals is switched and output as an output signal.

  For example, when the number of analog input signals input to the multiplexer is four, the setting circuit decodes the signal contents of the two signals based on the signal contents of the two signals input from the outside. ) Generates and outputs four signals (signals corresponding to four analog input signals on a one-to-one basis) in which only one signal is valid, and the multiplexer becomes valid among the signals input from the setting circuit. The analog input signal corresponding to the existing signal is switched and output as an output signal.

JP 2008-35039 A (page 5-6, FIG. 1)

However, the above-mentioned ΔΣ A / D converter has the following problems to be solved. That is, in this ΔΣ A / D converter, the number of signals input from the outside to the setting circuit in order to switch one of a plurality of analog input signals input to the multiplexer as an output signal is the analog input signal When the number of analog input signals is 3 or more, the number is always plural, and increases step by step as the number of analog input signals increases. For example, when the number of analog input signals is 3 or more and 4 or less, the number of signals is 2, and when the number of analog input signals is 5 or more and 8 or less, the number of signals is 3, When the number of signals is 9 or more and 16 or less, the number of signals increases stepwise, such as four.

For this reason, in this ΔΣ A / D converter, when the number of analog input signals is large (in the case of 3 or more), the number of signals input from the outside to the setting circuit is always plural. Since there are always a plurality of wirings for transmitting the cable, there is a problem to be solved that the cost of the connection cable including the wirings increases.

The present invention has been made to solve the above problems, a main object thereof is to provide a switching resulting Ru A / D converter a plurality of input signals in one signal.

A / D converter according to claim 1, wherein to achieve the above object, a multiplexer for outputting an output signal by switching the one according to the switching signal of the multiple input signals, based on the clock signal of one system has a sequential circuit for outputting a state signal indicating the current the state while sequentially transitions to predefined plurality of states, the switching which generates and outputs the switching signal based on the state signal and the clock signal A signal output circuit; an insulation input circuit; and an A / D conversion circuit that converts the output signal into a digital signal and outputs the digital signal, and the plurality of input signals and the clock signal are input from the outside, and the insulation input The circuit is an A / D conversion device that electrically insulates the input clock signal and outputs the clock signal to the switching signal output circuit. The sequential circuit includes a combinational circuit together with a sequential circuit, and the sequential circuit includes one flip-flop that sequentially transitions to two states based on a clock signal output from the isolated input circuit and outputs one state signal. The combinational circuit is composed of one AND element, outputs the state signal output from the flip-flop as one of the switching signals, and the AND element is output from the insulation input circuit. The logical product of the clock signal and the state signal is calculated and output as another one of the switching signals.

The A / D conversion device according to claim 2 is a plurality of states defined in advance based on a multiplexer that switches one of a plurality of input signals according to a switching signal and outputs the same as an output signal, and a single clock signal. And a switching signal output circuit for generating and outputting the switching signal based on the state signal and the clock signal, and an insulating input circuit. And an A / D conversion circuit that converts the output signal into a digital signal and outputs the digital signal, the plurality of input signals and the clock signal are input from the outside, and the isolated input circuit An A / D converter that electrically isolates a signal and outputs the signal to the switching signal output circuit, wherein the switching signal output circuit is combined with the sequential circuit. The sequential circuit is configured to output one of the two state signals, one of which is an inverted signal of the other, sequentially transitioning to two states based on a clock signal output from the isolated input circuit. The combinational circuit is composed of two AND elements and one OR element, and one of the two state signals output from the flip-flop is directly used as one of the switching signals. One AND element of the two AND elements calculates and outputs the logical product of the one state signal and the clock signal output from the insulation input circuit, and the two AND elements The other AND element calculates and outputs the logical product of the other of the two state signals and the clock signal, and the OR element outputs the two AND signals. Calculates the logical sum of the outputs of the de-element output as the other one of said switching signal.

According to the A / D conversion device described in claims 1 and 2 , even if the number of input signals is three or more, these input signals are converted based on a single clock signal input from the outside. It can be output to the A / D conversion circuit as an output signal while sequentially switching. Further, it is possible to avoid an increase in cost of the connection cable including a wiring for transmitting a clock signal.

Moreover, since it is possible to dispense a number of circuits insulation input circuit in one, it is possible to avoid a cost increase of about isolated input circuit.

It is a block diagram which shows the structure of A / D conversion apparatus 1 and 1A. 3 is a circuit diagram of a switching signal output circuit 12. FIG. 4 is a truth table of the multiplexer 13; 3 is a timing chart for explaining the operation of the A / D conversion device 1. FIG. 12 is a circuit diagram of another switching signal output circuit 12A. It is a truth table of the multiplexer 13A. It is a timing chart for demonstrating operation | movement of A / D converter 1A.

Hereinafter , embodiments of the A / D conversion device will be described with reference to the accompanying drawings.

  First, the configuration of the A / D conversion apparatus 1 will be described with reference to the drawings.

  As shown in FIG. 1, the A / D conversion apparatus 1 includes a signal switching circuit 2, an A / D conversion circuit 3, and an insulation output circuit 4, and a plurality of (three in this example) input signals input from the outside. (Analog signals) Si1, Si2, Si3 (hereinafter also referred to as “input signal Si” unless otherwise distinguished) in this order, a predetermined number of bits indicating the respective amplitudes (in this example, 8 bits as an example) The digital signal Dv is repeatedly converted into a parallel digital signal Dv, and the digital signal Dv is electrically insulated and output as a digital signal Dvo.

  The signal switching circuit 2 includes an insulation input circuit 11, a switching signal output circuit 12, and a multiplexer 13. The insulation input circuit 11 electrically insulates one (one system) clock signal (digital signal) CK inputted from the outside, and outputs it as another one (one system) clock signal (digital signal) CK1. To do. In the present example, the isolated input circuit 11 is configured using a digital isolator as an example, but may be configured using a photocoupler, a pulse transformer (insulated transformer), or the like.

  As shown in FIG. 2, the switching signal output circuit 12 includes a sequential circuit 21 and a combinational circuit 22, and is used for the multiplexer 13 based on the clock signal CK <b> 1 (clock signal CK input via the insulating input circuit 11). Switch signal Sc is generated and output. In this example, as will be described later, the multiplexer 13 is configured to switch the three input signals Si to be input and output one of them as the output signal So, as shown in the truth table shown in FIG. In addition, two switching signals Sc1 and Sc2 (hereinafter also referred to as “switching signal Sc” unless otherwise distinguished) are required. For this reason, the switching signal output circuit 12 generates and outputs these two switching signals Sc1 and Sc2.

  In this example, the sequential circuit 21 includes, as an example, one flip-flop (as an example, a synchronous D flip-flop) 21a. In the sequential circuit 21, the flip-flop 21 a sequentially transitions to two states (first state and second state) based on (synchronously with) the clock signal CK 1, and outputs a state signal Ss 1 indicating the current state. Generate and output. In this case, the state signal Ss1 is inverted in every cycle of the clock signal CK1, and indicates the first state when it is at a high level (H) and indicates the second state when it is at a low level (L).

  As an example, the combinational circuit 22 includes one AND element 22a. The combinational circuit 22 receives the state signal Ss1 and the clock signal CK1, and outputs the state signal Ss1 as it is as the switching signal Sc1. In the combinational circuit 22, the AND element 22a calculates a logical product of the state signal Ss1 and the clock signal CK1, and outputs the logical product as the switching signal Sc2.

  With the above configuration, the switching signal output circuit 12 has two switching signals Sc1 and Sc2 that change in synchronization with the clock signal CK1, as shown in FIG. 4, based on the clock signal CK1 (in this example, in synchronization). And output to the multiplexer 13.

  In this example, the multiplexer 13 inputs the above-described three input signals Si1, Si2, and Si3 from the outside, and converts one of these input signals Si into two switching signals as shown in FIG. The signals are switched according to the signal contents of Sc1 and Sc2 (high level (H) or low level (L)) and output as an output signal So.

  The A / D conversion circuit 3 receives the output signal So output from the multiplexer 13, and, as shown in FIG. 4, outputs the output signal So in synchronization with the sampling clock CKi synchronized with the rising and falling edges of the clock signal CK1. Is converted into an 8-bit parallel digital signal Dv indicating the amplitude of the output signal So and output. In this case, the sampling clock CKi, although not shown, receives a known differentiation circuit (for example, a delay element that delays the sampling clock CKi for a certain time, a sampling clock CKi, and a sampling clock CKi that is delayed for a certain time by the delay element). An exclusive OR element and an inverting (knot) element that inverts the output of the exclusive OR element are generated. In FIG. 4, since the number of input signals Si is three, the fourth sampling clock CKi is not shown.

  The insulation output circuit 4 receives the 8-bit digital signal Dv and electrically insulates it, and outputs it as an 8-bit digital signal Dvo. In the present example, the insulated output circuit 4 is configured using a digital isolator as an example, but may be configured using a photocoupler, a pulse transformer (insulated transformer), or the like.

  Next, operations of the signal switching circuit 2 and the A / D converter 1 will be described with reference to the drawings. The A / D converter 1 includes three input signals Si1, Si2, and Si3 whose waveforms (for example, amplitude and period) independently change with time, and a clock signal CK having a constant period. Are continuously input from the outside.

  In this state, in the signal switching circuit 2 of the A / D converter 1, the isolated input circuit 11 inputs the clock signal CK and generates and outputs the electrically isolated clock signal CK1. The switching signal output circuit 12 generates the two switching signals Sc1 and Sc2 based on (in synchronization with) the clock signal CK1, and outputs the two switching signals Sc1 and Sc2 to the multiplexer 13.

  The multiplexer 13 switches the three input signals Si1, Si2, Si3 as shown in FIG. 3 according to the signal contents of the switching signals Sc1, Sc2 output from the switching signal output circuit 12, and as shown in FIG. The input signals Si1, Si2, and Si3 are output as the output signal So repeatedly every two cycles of the clock signal CK1 as a whole, in this order for each half cycle of the clock signal CK1.

  Next, as shown in FIG. 4, the A / D conversion circuit 3 is synchronized with the rise and fall of the clock signal CK1 (that is, synchronized with the switching timing of the input signals Si1, Si2, Si3 by the multiplexer 13). In synchronization with the clock CKi, the output signal So output from the multiplexer 13 is sampled, converted into a digital signal Dv, and output. Subsequently, the insulation output circuit 4 electrically insulates the digital signal Dv and outputs it as the digital signal Dvo to the outside of the A / D conversion device 1.

  As described above, in the signal switching circuit 2 of the A / D converter 1, the switching signal output circuit 12 has a plurality of states defined in advance (synchronously) based on one system of clock signals CK input from the outside. And a switching circuit Sc1 to the multiplexer 13 based on the state signal Ss1 and the clock signal CK (specifically, the clock signal CK1). , Sc2 is generated and output.

  Therefore, according to this signal switching circuit 2, even when the number of input signals Si is three (an example of three or more), based on one clock signal CK input from the outside (synchronized). The input signal Si can be output as the output signal So while being sequentially switched. Further, with this configuration, according to the signal switching circuit 2, it is possible to avoid an increase in cost for the connection cable including the wiring for transmitting the clock signal CK.

  Further, according to the signal switching circuit 2, even if the configuration in which the clock signal CK is electrically insulated in the insulation input circuit 11 is adopted, the number of the insulation input circuits 11 can be reduced regardless of the number of the input signals Si. Since only one can be used, an increase in cost related to the isolated input circuit 11 can be avoided.

  Further, according to the A / D conversion device 1 provided with the signal switching circuit 2, the connection cable including the wiring for transmitting the clock signal CK even when the number of the input signals Si is large (in the case of 3 or more). The input signal Si can be converted into the digital signal Dvo and output to the outside while avoiding an increase in cost.

  In addition, although the number of input signals Si has been described above for three examples, as indicated by a broken line in FIG. 1, the input signal Si4 is added, and the signal switching circuit 2 has four input signals Si1 to Si4 (hereinafter not distinguished). (Sometimes referred to as “input signal Si”) are sequentially switched and output as an output signal So, and the A / D conversion circuit 3 and the insulation output circuit 4 sequentially convert the output signal So into a digital signal Dv, and the digital signal Dvo It is also possible to adopt a configuration that outputs to the outside.

  An A / D converter 1A employing this configuration includes a signal switching circuit 2A, an A / D converter circuit 3, and an insulated output circuit 4, as shown in FIG. Since the configuration other than the switching signal output circuit 12A and the multiplexer 13A constituting the signal switching circuit 2A is the same as that of the A / D converter 1, the same components are denoted by the same reference numerals and overlapped. The description will be omitted, and different configurations will be mainly described.

As shown in FIG. 5, the switching signal output circuit 12A includes a sequential circuit 21 and a combinational circuit 32. The sequential circuit 21 is configured in the same manner as the switching signal output circuit 12, and the state signal Ss1 and its inverted signal are used as the switching signal output circuit 12A. The status signal Ss1 ′ is output. On the other hand, the combinational circuit 32 includes two AND elements 32a and 32b and one OR element 32c as an example. The combinational circuit 32 receives the state signals Ss1, Ss1 ′ and the clock signal CK1, and outputs the state signal Ss1 as it is as the switching signal Sc1. In the combinational circuit 32, the AND element 32a calculates the logical product of the state signal Ss1 and the clock signal CK1, and the AND element 32b calculates the logical product of the state signal Ss1 ′ and the clock signal CK1, and the OR element 32c. Calculates the logical sum of the outputs of both AND elements 32a and 32b, and outputs it as the switching signal Sc2.

  With the above configuration, the switching signal output circuit 12A receives two switching signals Sc1 and Sc2 that change in synchronization with the clock signal CK1, as shown in FIG. 7, based on the status signals Ss1 and Ss1 ′ and the clock signal CK1. Generate and output to the multiplexer 13A. As shown in FIG. 7, in this example, the switching signal Sc2 is the same signal as the clock signal CK1 unless the delay time in each element is taken into consideration, and therefore the clock signal CK1 is output as it is as the switching signal Sc2. It is also possible to adopt a configuration that does this.

  The multiplexer 13A receives the above four input signals Si1, Si2, Si3, Si4 from the outside, and converts one of the input signals Si into two switching signals Sc1, as shown in FIG. The signal is switched according to the signal content of Sc2 (high level (H) or low level (L)) and output as an output signal So.

  Next, operations of the signal switching circuit 2A and the A / D conversion device 1A will be described with reference to the drawings. The A / D converter 1A includes four input signals Si1, Si2, Si3, Si4 whose waveforms (for example, amplitude and period) independently change with time, and one of a constant period. It is assumed that (one system) of clock signals CK are continuously input from the outside.

  In this state, in the signal switching circuit 2A of the A / D converter 1A, the insulating input circuit 11 receives the clock signal CK, generates the clock signal CK1, and outputs it. The switching signal output circuit 12A generates the two switching signals Sc1 and Sc2 based on (in synchronization with) the clock signal CK1, and outputs the two switching signals Sc1 and Sc2 to the multiplexer 13A.

  As shown in FIG. 7, the multiplexer 13A switches the four input signals Si1, Si2, Si3, Si4 as shown in FIG. 6 according to the signal contents of the switching signals Sc1, Sc2 output from the switching signal output circuit 12A. In addition, the input signals Si1, Si2, Si3, and Si4 are repeatedly output in this order for every half cycle of the clock signal CK1, and as a whole, every two cycles of the clock signal CK1.

  Next, as shown in FIG. 7, the A / D conversion circuit 3 samples the output signal So output from the multiplexer 13A in synchronization with the sampling clock CKi, converts it into a digital signal Dv, and outputs it. Subsequently, the insulation output circuit 4 electrically insulates the digital signal Dv and outputs it as a digital signal Dvo to the outside of the A / D converter 1A.

  Also in this A / D conversion device 1A, the signal switching circuit 2A has four input signals Si1, Si2, Si3 inputted from the outside based on (synchronously) one clock signal CK inputted from the outside. The output signal So is output while sequentially switching Si4, the A / D conversion circuit 3 sequentially converts the output signal So into a digital signal Dv, and the insulation output circuit 4 electrically insulates the digital signal Dv. And output to the outside as a digital signal Dvo.

  Therefore, according to the signal switching circuit 2A and the A / D converter 1A, even if the number of input signals Si is four (an example in the case of three or more), one clock signal input from the outside Based on (in synchronization with) CK, these input signals Si can be output as the output signal So while being sequentially switched. As a result, according to the signal switching circuit 2A, it is possible to avoid an increase in the cost of the connection cable including the wiring for transmitting the clock signal CK.

  In the signal switching circuit 2 (2A), the clock signal CK from the outside is electrically insulated by the insulation input circuit 11 and inputted into the circuit as the clock signal CK1, and the digital signal Dv generated in the circuit is used. Is isolated by the insulated output circuit 4 and output to the outside as a digital signal Dvo. However, when it is not necessary to electrically isolate these signals, the insulated output circuit 4 and the insulated input circuit are used. 11 may be omitted, and the clock signal CK may be directly input (as it is) and used, and the digital signal Dv may be directly output (as it is).

  In the signal switching circuit 2 (2A), the number of input signals Si is defined as three or four. However, a configuration in which the number of input signals Si is defined as five or more may be employed. . In this case, when the number of input signals Si is 5 or more and 8 or less, the number of switching signals Sc is defined as three, and when the number of input signals Si is 9 or more and 16 or less, the number of switching signals Sc is four. As specified, the number of switching signals Sc needs to be increased stepwise as the number of input signals Si increases. Even in this case, the number of clock signals CK input from the outside is one. By increasing the number of flip-flops constituting the sequential circuit of the switching signal output circuit, the required number of switching signals Sc can be generated and output to the multiplexer.

  In the switching signal output circuit 12 (12A), the combinational circuit 22 is based on the state signal (the state signal Ss1 or the state signal Ss1 ′ that is an inverted signal thereof) generated by the sequential circuit 21 and the clock signal CK1. (32) employs a configuration in which the switching signals Sc1 and Sc2 are generated and output, but the sequential circuit of the switching signal output circuit is configured by the same number of flip-flops as the number of switching signals Sc required in the multiplexer. Thus, it is possible to generate the switching signal Sc using only the state signal (output of each flip-flop) output from the sequential circuit.

  Moreover, although the example which applied the signal switching circuit 2 (2A) to the A / D converter 1 (1A) was demonstrated, the signal switching circuit 2 (2A) can also be used independently, or an A / D conversion circuit It can also be combined with circuits other than 3.

DESCRIPTION OF SYMBOLS 1,1A A / D converter 2, 2A Signal switching circuit 3 A / D conversion circuit 11 Insulation input circuit 12, 12A Switching signal output circuit 13, 13A Multiplexer CK, CK1 Clock signal Sc1, Sc2 Switching signal Si1, Si2, Si3 , Si4 input signal Ss1, Ss1 'Status signal So output signal

Claims (2)

It shows a multiplexer for outputting an output signal by switching according to one of the switching signals of the multiple input signals, the current of the condition while sequentially transitions to a plurality of states defined in advance based on the clock signal of one system has a sequence circuit for outputting a status signal, converts a switching signal output circuit that generates and outputs the switching signal based on the state signals and said clock signal, an insulating input circuit, the output signal to a digital signal And the A / D conversion circuit for outputting, the plurality of input signals and the clock signal are inputted from the outside, and the insulation input circuit electrically insulates the inputted clock signal and performs the switching. An A / D converter that outputs to a signal output circuit,
The switching signal output circuit has a combinational circuit together with the sequential circuit,
The sequential circuit is composed of one flip-flop that sequentially changes to two states based on a clock signal output from the insulation input circuit and outputs one state signal,
The combinational circuit is configured by one AND element and outputs the state signal output from the flip-flop as it is as one of the switching signals, and the AND element is output from the insulation input circuit. An A / D conversion device that calculates a logical product of the clock signal and the state signal and outputs it as another one of the switching signals. A multiplexer that switches one of a plurality of input signals according to a switching signal and outputs it as an output signal, and a state that sequentially transitions to a plurality of states that are defined in advance based on one system of clock signals and that indicates the current state A sequential circuit for outputting a signal, a switching signal output circuit for generating and outputting the switching signal based on the state signal and the clock signal, an insulating input circuit, and converting the output signal into a digital signal A plurality of input signals and the clock signal are input from the outside, and the isolated input circuit electrically isolates the input clock signal and outputs the switching signal. An A / D converter that outputs to a circuit,
The switching signal output circuit has a combinational circuit together with the sequential circuit,
The sequential circuit is configured by one flip-flop that sequentially changes to two states based on a clock signal output from the insulation input circuit and outputs two state signals, one of which is an inverted signal of the other,
The combinational circuit is composed of two AND elements and one OR element and outputs one of the two state signals output from the flip-flop as one of the switching signals as it is. One AND element of the AND elements calculates and outputs a logical product of the one state signal and the clock signal output from the insulation input circuit, and the other AND element of the two AND elements The logical product of the other of the two status signals and the clock signal is calculated and output, and the OR element calculates the logical sum of the outputs of the two AND elements and outputs the other one of the switching signals. As an A / D converter.

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