JP5491454B2 - Parallel-serial conversion circuit - Google Patents

Description

  The present invention relates to a parallel-serial conversion circuit.

A parallel-serial conversion circuit for converting a parallel signal into a serial signal is in demand for low-frequency and high-speed parallel-serial conversion. As a prior art of a low-frequency, high-speed parallel-serial conversion circuit, for example, there is a parallel-serial conversion circuit described in Patent Document 1.
FIG. 7 is a diagram for explaining the parallel-serial conversion circuit described in Patent Document 1. In FIG. The parallel-serial conversion circuit shown in FIG. 7 controls a flip-flop circuit 1 that takes in parallel data, a selector circuit 2 that receives a signal output from the flip-flop circuit 1 and outputs serial data, and a selector circuit 2. And a selector control circuit 4 that controls selection of serial data output from the selector circuit 2, and a PLL circuit 3 that receives a clock signal and generates a multi-phase clock having the same frequency as the clock signal. .

  The selector circuit 2 is generally configured by connecting three-state buffers 5a and 5b in parallel in the number of necessary conversion bits. In such a selector circuit 2, the control signal generated using the multiphase clock signal output from the PLL circuit 3 converts the parallel data into serial data by sequentially selecting the buffers 5a and 5b. .

Patent No. 4412788

  In the prior art described in Patent Document 1 described above, if the rise and fall times of the signals output from the buffers 5a and 5b are slow, the influence of external noise such as power supply noise on the characteristics increases, or There is a problem that the influence of manufacturing variation becomes large. Furthermore, the width of the Eye (Eye Diagram) of serial data after serial conversion is narrowed. For this reason, in the prior art, the rise and fall of the signal described above are made steep by increasing the size of the buffers 5a and 5b.

However, when the size of the buffer is increased, the size of all the buffers 5a and 5b connected in parallel is increased, and the load on the selector circuit 2 is increased. For this reason, in a parallel-serial conversion circuit applied to a high-speed parallel-serial of several hundred MHz or more, it is impossible to improve the slope of the rising and falling edges of the signal by increasing the buffer size.
The present invention has been made in view of the above points, and an object of the present invention is to provide a parallel-serial conversion circuit that is resistant to power supply noise and capable of high-speed parallel-serial conversion at a low frequency.

In order to solve the above problems, a parallel-serial conversion circuit of the present invention (for example, the parallel-serial conversion circuit shown in FIG. 1) includes a clock signal and a multi-phase pulse signal having the same frequency as the clock signal. A parallel-serial conversion circuit for converting parallel data into serial data, which are connected in parallel to each other, and each of the first buffer circuits (for example, a number corresponding to the number of bits of the parallel data to which the parallel data is input) A first selector circuit (for example, the selector circuit 103 shown in FIG. 1) that sequentially selects the buffer circuits based on the pulse signal and outputs first internal serial data. Are connected in parallel with each other and input inverted parallel data obtained by inverting the parallel data. The number of second buffer circuits corresponding to the number of bits of the inverted parallel data is included, the second buffer circuit (for example, the buffer circuit 105 shown in FIG. 1) is included based on the pulse signal, and the number of second buffer circuits is determined based on the pulse signal. A second selector circuit (for example, the selector circuit 104 shown in FIG. 1) for sequentially selecting the second buffer circuit and outputting second internal serial data; and a rising edge and a falling edge of the first internal serial data A first edge detection circuit (for example, the edge detection circuit shown in FIG. 1) that outputs a first pulse signal whose output level is switched in synchronization with one of the detected rising edge and falling edge. 106), and the rising edge of the first internal serial data is detected by the first edge detection circuit. When the rising edge of the second internal serial data is detected and the falling edge of the first internal serial data is detected by the first edge detection circuit, the falling edge of the second internal serial data And a second edge detection circuit (for example, the edge detection circuit 107 shown in FIG. 1) that outputs a second pulse signal whose output level is switched in synchronization with one of the detected rising edge and falling edge. And a latch circuit that outputs the serial data whose output level is switched in synchronization with one of the rising and falling edges of the first pulse signal and one of the rising and falling edges of the second pulse signal (for example, FIG. and SR latch circuit 110) shown, only contains the first rising edge of the internal serial data, said first The first edge detection circuit detects a steeper side of the rising edge and the falling edge of the first internal serial data, and is steeper or gentler than the falling edge of the internal serial data. The rising edge of the second internal serial data is steeper or gentler than the falling edge of the second internal serial data, and the second edge detection circuit detects the rising edge and the falling edge of the second internal serial data. Among the edges, a steeper side is detected .

  In the parallel-serial conversion circuit according to the present invention, in the above-described invention, a first synchronization circuit (for example, as shown in FIG. 1) that synchronizes the parallel data and outputs it to the first selector circuit based on the clock signal. And a second synchronization circuit (for example, the flip-flop circuit 102 shown in FIG. 1) that synchronizes the parallel data and outputs it to the second selector circuit based on the clock signal. It is desirable to further include.

  The parallel-serial conversion circuit according to the present invention is the parallel-serial conversion circuit according to the present invention, wherein the multi-phase pulse signal having the same frequency as the clock signal and corresponding to each of the first selector circuit and the second selector circuit is provided. The first selector circuit further sequentially selects the first internal serial data based on the corresponding multiphase pulse signal, and further includes a PLL circuit to be generated (for example, the PLL circuit 108 shown in FIG. 1). It is desirable that the 2-selector circuit sequentially selects the second internal serial data based on the corresponding multiphase pulse signal.

  In the parallel-serial conversion circuit according to the present invention, the latch circuit includes a first OR circuit (for example, an OR circuit 501 shown in FIG. 5) to which the first pulse signal is input; A second logical sum circuit (for example, the logical sum circuit 502 shown in FIG. 5) that receives the signal output from the first logical sum circuit and outputs a signal to the first logical sum circuit, and the first logical sum circuit. A first buffer circuit (for example, inverter elements 503 and 504 shown in FIG. 5) which is connected to an output node of the circuit and buffers the signal output from the first OR circuit; and an output node of the second OR circuit And a second buffer circuit (for example, inverter elements 505 and 506 shown in FIG. 5) that buffers the signal output from the second OR circuit.

  In the parallel-serial conversion circuit of the present invention, in the above-described invention, the latch circuit is configured by the first buffer circuit connecting a plurality of first inverter elements in series, and the plurality of second buffer circuits. The second inverter elements are connected in series and connected to a first node between the plurality of first inverter elements and to a second node between the plurality of second inverter elements. A fourth inverter having a third inverter element having an output terminal (for example, the inverter element 602 shown in FIG. 6), an output terminal connected to the first node, and an input terminal connected to the second node It is desirable to further include an element (for example, the inverter element 601 shown in FIG. 6).

In the parallel-serial conversion circuit of the present invention, in the above-described invention, it is preferable that the latch circuit differentially outputs the serial data and inverted serial data obtained by inverting the serial data .

The present invention uses two similar selector circuits, and inputs positive parallel data to one and negative parallel data to the other. A pulse in which one edge is detected is generated for each of the two selector circuits through an edge detection circuit that detects a rising edge or a falling edge and generates a pulse for the output data of each selector circuit. . A parallel-serial conversion signal can be obtained by inputting the output of each edge detection circuit to each of the set input and reset input of the SR latch circuit.
According to the present invention, it is possible to provide a parallel-serial conversion circuit that is resistant to power supply noise and can perform high-speed parallel-serial conversion at a low frequency.

It is a figure for demonstrating the parallel-serial conversion circuit of one Embodiment of this invention. FIG. 2 is a diagram illustrating an input clock signal CKI, a clock signal PH [6: 0], and a control signal SEL [6: 0] illustrated in FIG. 2 is a timing chart for explaining the parallel-serial conversion timing of the parallel-serial conversion circuit shown in FIG. 1. It is a figure for demonstrating the structure of the edge detection circuit shown in FIG. FIG. 2 is a diagram for explaining the SR latch circuit shown in FIG. 1. It is a figure for demonstrating the other SR latch circuit of one Embodiment of this invention. It is a figure for demonstrating the parallel-serial conversion circuit of a prior art.

Hereinafter, a parallel-serial conversion circuit according to an embodiment of the present invention will be described.
Circuit Configuration FIG. 1 is a diagram for explaining a parallel-serial conversion circuit of the present embodiment. In this embodiment, in order to simplify the description, a parallel-serial conversion circuit that performs parallel-serial conversion of a 7-bit parallel signal into a 1-bit serial signal will be described as an example. However, the parallel-serial conversion circuit of the present embodiment is not limited to the configuration for converting a 7-bit parallel signal into a serial signal, and can be applied regardless of the number of bits of the parallel signal.

  The parallel-serial conversion circuit 10 shown in FIG. 1 includes an input clock signal CKI and a flip-flop circuit 101 that inputs positive parallel data Din [6: 0], an input clock signal CKI, And a flip-flop circuit 102 for inputting parallel data Din_n [6: 0]. The parallel data Din_n [6: 0] is a signal generated by inverting Din [6: 0] of the parallel data by the inverter element 111. The flip-flop circuits 101 and 102 output data Dinx [6: 0] (n) and data Dinx_n [6: 0] (n), respectively.

The parallel-serial conversion circuit 10 receives the data Dinx [6: 0] (n) output from the flip-flop circuit 101, performs serial conversion and outputs serial data SDP, and the flip-flop circuit 102 includes It includes a selector circuit 104 that inputs the output data Dinx_n [6: 0] (n), converts the data serially, and outputs serial data SDN.
The selector circuits 103 and 104 each include seven buffers 105 (only the zeroth buffer 105 and the sixth buffer 105 are shown in the figure) in accordance with the number of bits of parallel data 7. The buffers 105 are all 3-state buffers.

  The parallel-serial conversion circuit 10 receives the serial data SDP output from the selector circuit 103, detects the rising edge of the serial data SDP, and outputs a pulse signal SDS. And an edge detection circuit 107 that receives the output serial data SDN, detects a rising edge of the serial data SDN, and outputs a pulse signal SDR. The parallel-serial conversion circuit 10 includes an SR latch circuit 110 having a set input terminal S for inputting a pulse signal SDS and a reset input terminal R for inputting a pulse signal SDR.

The SR latch circuit 110 receives the pulse signals SDS and SDR and outputs signals latched at the rising or falling timing of the pulse signals SDS and SDR as serial data SDATAT and SDATA.
Further, the parallel-serial conversion circuit 10 receives the input clock signal CKI, and generates seven clock signals (seven-phase clock signals) PH [6: 0] having the same frequency and different phases from the input clock signal CKI. The selector circuit 103 and 104 are selected by using the PLL circuit 108 that performs this operation and the seven-phase clock signal PH [6: 0], and the control signal SEL [6: is used for sequentially selecting the data Dinx [6: 0]. 0] is output.

  The parallel data Din [6: 0] and parallel data Din_n [6: 0] are synchronized with the input clock signal CKI by the flip-flop circuits 101 and 102 and output. The PLL circuit 108 outputs a 7-phase clock signal PH [6: 0] synchronized with the phase of the signal synchronized with the input clock signal CKI, and the control circuit 109 outputs a 7-phase clock signal PH [6: 0]. ], The control signal SEL [6: 0] for controlling the selector circuits 103 and 104 is output. The control signal SEL [6: 0] is seven pulse signals.

Operation FIG. 2 is a diagram illustrating the input clock signal CKI, the clock signal PH [6: 0], and the control signal SEL [6: 0] illustrated in FIG. The vertical axis in FIG. 2 indicates the rise and fall of the signal, and the horizontal axis indicates time. According to FIG. 2, it can be seen that the seven-phase clock signals PH [6: 0] are all signals having a constant duty ratio of 50% and different phases by 1/7 of one cycle. The clock signal PH [6] is a signal having the same rising edge phase as the input clock signal CKI. The control signal SEL [6: 0] is a signal whose High pulse width is 1/7 of one cycle and whose phase is different by 1/7 phase of one cycle.

  FIG. 3 is a timing chart for explaining the parallel-serial conversion timing of the parallel-serial conversion circuit 10 shown in FIG. The vertical axis in FIG. 3 indicates the rising and falling edges of the serial data SDP, SDN, the pulse signals SDS, SDR, and the output signals SDATAP, SDATA, and the horizontal axis indicates time. The illustrated Dinx [6: 0] (n) and data Dinx [6: 0] (n + 1) indicate continuous phases.

The control signal SEL [6: 0] output from the control circuit 109 alternately selects the selector circuits 103 and 104, and further sequentially selects seven signals output from the selected selector circuit. The selected signal becomes serial data SDP and SDN, and parallel-serial conversion is performed.
That is, the selector circuit 103 outputs serial data SDP obtained by serially converting positive parallel data Din [6: 0], and the selector circuit 4 serially converts negative parallel data Din_n [6: 0]. The serial data SDN is output. Buffer timings of the buffers 105 in the selector circuits 103 and 104 are optimized so that the rising edges of the serial data SDP and SDN at this time are steep.

In the present embodiment, since the rising edges of the serial data SDP and SDN are detected, the falling edges of the serial data SDP and SDN may be determined so that the transition ends within the buffer selection period. However, the present embodiment is not limited to the configuration for detecting the rising edges of the serial data SDP and SDN, and the falling edges may be detected.
The serial data SDP and SDN output from the selector circuits 103 and 104 are input to the edge detection circuits 106 and 107, respectively. The edge detection circuits 106 and 107 detect rising edges of the serial data SDP and SDN, and output pulse signals SDS and SDR that rise at the timing when the edges are detected.

  FIG. 4 is a diagram for explaining the configuration of the edge detection circuits 106 and 107. The edge detection circuits 106 and 107 are an inverter circuit 402 that inverts input serial data SDP and SDN, a plurality of delay buffer circuits 401 that delay an output signal that is inverted and output, and an input signal that is inverted and delayed. And a 2-input AND circuit 403 that inputs the received signal and outputs pulse signals SDS and SDR. The 2-input AND circuit 403 has two input terminals A and B. Thereafter, serial data SDP and SDN input from the input terminal A are input to the A input, and serial input from the input terminal B is input. Data SDP and SDN are described as B input.

  When the serial data SDP and SDN shown in FIG. 3 are low level signals, the 2-input AND circuit 403 outputs low level signals SDS and SDR. Further, when the serial data SDP and SDN transition from the low level to the high level, the A input also transitions from the low level to the high level. At this time, since the B input transitions from the High level to the Low level with a delay of a certain time, there is a period in which both the A input and the B input are input to the 2-input AND circuit 403 as high level signals. The 2-input AND circuit 403 outputs high-level SDS and SDR for that period.

  When the A input to the 2-input AND circuit 403 is at a high level, a low level signal is input to the B input. At this time, the 2-input AND circuit 403 always outputs a Low level signal. When the A input transitions from the High level to the Low level, the B input transitions from the Low level to the High level with a certain time delay. For this reason, since either the A input or the B input is always at the Low level, the 2-input AND circuit 403 outputs a Low level signal.

As described above, the edge detection circuits 106 and 107 detect the rising edges of the input serial data SDP and SDN, and the pulse signals SDS and SDR having pulse widths corresponding to the delays of the plurality of delay buffer circuits 401 are detected. Is output.
The pulse signals SDS and SDR output from the edge detection circuits 106 and 107 are input to the set input terminal S and the reset input terminal R of the SR latch circuit 110, respectively. The SR latch circuit 110 outputs a high level signal when a high level signal is input to the set input terminal S, and outputs a low level signal when a high level signal is input to the reset input terminal R. When the signals input to the set input terminal S and the reset input terminal R are both at the low level, the high and low states of the output pulse signal are maintained.

  FIG. 5 is a diagram for explaining the SR latch circuit 110. The SR latch circuit 110 includes two OR circuits 501 and 502, a buffer circuit 507 including two stages of inverter elements 503 and 504, and a buffer circuit 508 including two stages of inverter elements 505 and 506. Yes. Each of the OR circuits 501 and 502 has two input terminals A and B, and a set signal is input to the input terminal A of the OR circuit 501. A reset signal is input to the input terminal A of the OR circuit 502. In addition, the signal output from the other is input to the input terminal B of the OR circuits 501 and 502.

  The signals output by the OR circuits 501 and 502 are buffered by the buffer circuits 507 and 508. If the output of the SR latch circuit 110 is single, only the output signal VO + output from the buffer circuit 508 may be output. However, in general, in a parallel-serial conversion circuit used for applications such as LVDS (Low voltage differential signaling), it is often desired to output a differential output signal. In such a parallel-serial conversion circuit, the output signal VO + and the output signal VO− of the SR latch circuit 110 may be used.

  Further, in the SR latch circuit 110 shown in FIG. 5, when the set signal transits from the Low level to the High level, the transition of the output signal VO + from the Low level to the High level changes from the High level to the Low level of the output signal VO−. Compared with the transition to, a delay of one logical sum is generated. Further, when the reset signal transitions from the low level to the high level, the transition of the output signal VO− from the low level to the high level is one logical sum compared to the transition from the high level to the low level of the VO + terminal. Incurs a minute delay.

  FIG. 6 is a diagram for explaining an SR latch circuit that can eliminate the delay described above. Among the configurations shown in FIG. 6, configurations similar to those shown in FIG. 5 are denoted by the same reference numerals, and description thereof is partially omitted. In the SR latch circuit shown in FIG. 6, the inverter element 601 is inserted between the output node of the first-stage inverter element 503 and the output node of the inverter element 505, and the input node of the second-stage inverter element 504 and the inverter element An inverter element 602 is inserted between the input nodes 506.

  As illustrated, the input terminal 601a of the inverter element 601 is connected to a node between the inverter element 503 and the inverter element 504, and the output terminal 601b of the inverter element 601 is connected to the inverter element 505 and the inverter element 506. Connected to nodes between. The input terminal 602a of the inverter element 602 is connected to a node between the inverter element 505 and the inverter element 506, and the output terminal 602b of the inverter element 602 is connected to a node between the inverter element 503 and the inverter element 504. Has been.

With such a configuration, the inverter elements 601 and 602 can cross each other's input and output and latch the other output signal. For this reason, according to the SR latch circuit shown in FIG. 6, the zero cross points (timing when the amplitude becomes 0) of the differentially outputted output signals VO + and VO− can be made uniform.
As described above, according to the present embodiment, an input parallel signal can be converted into a differential serial signal having zero cross points. Furthermore, since only one edge of the output signal needs to be steep in the selector circuits 103 and 104, the selector circuits 103 and 104 are more resistant to external noise such as power supply noise and more resistant to manufacturing variations than the prior art, and further increase the EYE width It can be taken widely.

  The parallel-serial conversion circuit of the present invention can be applied to general parallel-serial conversion that is resistant to power supply noise and requires high-speed characteristics at a low frequency.

DESCRIPTION OF SYMBOLS 10 Parallel-serial conversion circuit 101,102 Flip-flop circuit 103,104 Selector circuit 105 Buffer 106,107 Edge detection circuit 108 PLL circuit 109 Control circuit 110 SR latch circuit 111,503,504,505,506,601,602 Inverter element 401 Buffer circuit for delay 402 Inverter circuit 403 Input AND circuit 501 and 502 OR circuit 507 and 508 Buffer circuit

Claims (6)

A parallel-serial conversion circuit that converts parallel data into serial data using a clock signal and a multi-phase pulse signal having the same frequency as the clock signal,
A plurality of first buffer circuits connected in parallel to each other, each having a number corresponding to the number of bits of the parallel data to which the parallel data is input, and sequentially selecting the buffer circuits based on the pulse signal, A first selector circuit for outputting data;
A plurality of second buffer circuits connected in parallel to each other, each having a number corresponding to the number of bits of the inverted parallel data to which the inverted parallel data obtained by inverting the parallel data is input, and the second buffer circuit is configured based on the pulse signal. A second selector circuit for sequentially selecting and outputting second internal serial data;
Detecting one of a rising edge and a falling edge of the first internal serial data;
A first edge detection circuit that outputs a first pulse signal whose output level is switched in synchronization with one of the detected rising edge and falling edge;
When the rising edge of the first internal serial data is detected by the first edge detection circuit, the rising edge of the second internal serial data is detected, and the first internal detection data is detected by the first edge detection circuit. When the falling edge of the serial data is detected, the falling edge of the second internal serial data is detected, and the output level is switched in synchronization with one of the detected rising edge and falling edge. A second edge detection circuit for outputting a second pulse signal;
Viewed including the one of the rising and falling of the first pulse signal, a latch circuit for outputting the serial data is synchronized with the output level is switched to the one of the rising and falling of the second pulse signal, and
The rising edge of the first internal serial data is steeper or gradual than the falling edge of the first internal serial data, and the first edge detection circuit includes a rising edge of the first internal serial data A steep side of the falling edge is detected, the rising edge of the second internal serial data is steeper or gentler than the falling edge of the second internal serial data, and the second edge detection The circuit detects a steeper side of rising edges and falling edges of the second internal serial data . A first synchronization circuit that synchronizes the parallel data and outputs to the first selector circuit based on the clock signal;
A second synchronization circuit that synchronizes the parallel data and outputs to the second selector circuit based on the clock signal;
The parallel-serial conversion circuit according to claim 1, further comprising: A PLL circuit having the same frequency as the clock signal and generating a plurality of multi-phase pulse signals corresponding to each of the first selector circuit and the second selector circuit;
The first selector circuit sequentially selects the first internal serial data based on the corresponding multi-phase pulse signal, and the second selector circuit selects the second internal circuit based on the corresponding multi-phase pulse signal. 3. The parallel-serial conversion circuit according to claim 1, wherein the internal serial data is sequentially selected. The latch circuit is
A first OR circuit to which the first pulse signal is input;
A second OR circuit that receives a signal output from the first OR circuit and outputs a signal to the first OR circuit;
A first buffer circuit connected to an output node of the first OR circuit and buffering a signal output from the first OR circuit;
A second buffer circuit connected to an output node of the second OR circuit and buffering a signal output from the second OR circuit;
The parallel-serial conversion circuit according to claim 1, further comprising: The latch circuit is
The first buffer circuit is configured by connecting a plurality of first inverter elements in series, and the second buffer circuit is configured by connecting a plurality of second inverter elements in series,
A third inverter element having an input terminal connected to a first node between the plurality of first inverter elements and an output terminal connected to a second node between the plurality of second inverter elements; A fourth inverter element having an output terminal connected to the node and an input terminal connected to the second node;
The parallel-serial conversion circuit according to claim 4, further comprising: The latch circuit is
6. The parallel-serial conversion circuit according to claim 1, wherein the serial data and inverted serial data obtained by inverting the serial data are differentially output.

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