TWI495266B - Ring oscillator - Google Patents

Description

Ring oscillator circuit

This invention relates to a ring oscillator circuit and, more particularly, to a digitally controlled ring oscillator circuit having a clock count delay line circuit.

Many electronic devices require an oscillating signal or a clock signal for the clock program to achieve synchronization within the device. As electronic devices become more complex, there is a need to be able to use low cost clock signal generating devices within low cost electronic devices. Most electronic devices use a phase locked loop to generate an internal clock signal.

In general, a phase lock loop (PLL) consists of a phase comparator, a loop filter, and a voltage control oscillator (VOC). A phase locked loop or a digital phase lock loop (DPLL) requires an oscillator to generate a clock signal. Among them, the ring oscillator is a simple and common clock signal generator, and the conventional ring oscillator can realize the time delay function by combining the logic gate delay line circuit. For example, the conventional ring oscillator 100 shown in FIG. The ring oscillator 100 includes a delay line circuit in which an odd number of delay acting inverters INV1 are connected in series. If a set of control signals is used to set the number of cascaded delay line inverters, that is, the number of delay units is set, the delay time can be changed, and then the oscillation frequency can be controlled. In general, when the delay line contains more than a number of delay units, it can provide a wide range of oscillation frequencies of the clock signal, but it also Due to the inclusion of more delay units, the larger the circuit and the higher the cost.

The present invention proposes a plurality of ring oscillator circuits to effectively increase the frequency range in which they oscillate.

The present invention provides a ring oscillator comprising a clock count delay, a signal transfer synchronizer, and a combined logic gate delay circuit. The clock count delayer receives the input signal, the clock signal and the first delay control signal, and delays the input signal according to the first delay control signal and the pulse signal to generate the first delayed signal. The signal transmission synchronizer is coupled to the clock count delay device, receives the input signal, and generates a second delayed signal according to the transition point of the input signal. The combination logic gate delay circuit is coupled to the signal transfer synchronizer, receives the second delay signal, and delays the second delay signal to generate an output signal according to the second delay control signal, wherein the clock count delay device receives the end point coupling of the input signal The combination logic gate delay circuit produces an endpoint of the output signal.

The present invention further provides a ring oscillator comprising a synchronous clock count delay and a combined logic gate delay circuit. The synchronous clock count delayer receives the input signal and the delay control signal, and delays the input signal according to the first delay control signal and the pulse signal to generate the first delayed signal. The combined logic gate delay circuit receives the first delayed signal and delays the delayed signal to generate an output signal according to the second delay control signal, wherein the end of the synchronous clock count delay receiving input signal is coupled to the combined logic gate delay circuit to generate The endpoint of the output signal.

The present invention further provides a ring oscillator circuit including a clock count delay and a combined logic gate delay circuit. The clock counting delay device receives the input signal, the clock signal and the delay control signal, and delays the input signal according to the delay control signal and the pulse signal to generate a delayed signal. The combined logic gate delay circuit is coupled to the clock count delay device, receives the delay signal, and delays the delay signal according to the delay control signal to generate an output signal, wherein the end of the clock count delay receiver receiving the input signal is coupled to the combined logic gate The delay circuit produces an endpoint of the output signal.

In summary, the ring oscillator circuit proposed by the present invention has a combined logic gate delay circuit. The combined logic gate delay circuit delay line circuit has a function of counting the amount of delay using the clock. The delay time generated by the combined logic gate delay circuit delay line circuit is set by using the period of the clock signal as a unit. Thereby, the frequency range of the oscillation can be easily increased without using too many combined logic gate delay units.

The above described features and advantages of the present invention will be more apparent from the following description.

Please refer to FIG. 2. FIG. 2 is a schematic diagram of a ring oscillator circuit 200 according to an embodiment of the present invention. The ring oscillator 200 includes three parts, a clock count delay 210, a signal transfer synchronizer 220, and a combined logic gate delay circuit 230.

The clock count delay unit 210 is configured to receive the input signal In, the clock signal Tune_clk, and the delay control signal CK_delay[19:0], and according to the delay control The signal CK_delay[19:0] delays the input signal In, and the clock count delay 210 delays the delay of the input signal In by one or more cycles of the clock signal Tune_clk to generate the delayed signal In_ck_d. The delay amount is determined by the delay control signal CK_delay[19:0]. In an embodiment of the invention, the delay control signal CK_delay[19:0] is a digital signal of length 20 bits such that the set value ranges from 0 to (220-1). It should be noted that the length of the delay control signal CK_delay is not limited thereto. It should be understood by those skilled in the art that the length can be adjusted according to different requirements. In practical applications, for example, when the ring oscillator 200 of the present embodiment is applied to a digital phase lock loop (DPLL) circuit, the designer can first estimate a delay control signal CK_delay according to the target frequency. The value of 19:0] is taken as the initial value of CK_delay[19:0], so that the DPLL's tracking time/lock time can be accelerated.

3 is an example of a timing chart of an input signal In, a clock signal Tune_clk, and a delay signal In_ck_d according to an embodiment of the present invention. In this embodiment, the clock count delayer delays the period of, for example, eight delay clock Tune_clk signals for the input signal In to generate the delayed signal In_ck_d.

4 is a schematic diagram of an embodiment of a signal transfer synchronizer 220 that is formed by concatenating a plurality of signal transfer synchronizer units 410~4N0. Each of the signal passing synchronizer units receives the input signal I, the delayed signal In_ck_d, and outputs the output signal OUT. Each signal passing synchronizer unit includes (with the signal passing synchronizer unit 410 as an example) a delay The logic gate 411, the multiplexer 413, and the phase comparator 412. The delay logic gate 411 gate delays the received input signal I and outputs it to the input signal terminal I2 of the multiplexer 413, and the other input signal terminal I1 of the multiplexer 413 receives the signal In_ck_d. The multiplexer 413 is selected between the input signal I1 and the input signal I2 to generate an output signal OUT. And the selection signal sel[0] received by the multiplexer 413 is generated by the output of the phase comparator 412. The phase comparator 412 compares the phases of the input signal I and the output signal OUT. If the input signal I and the output signal OUT are in phase, the multiplexer selects the input signal I as the output signal OUT. Conversely, if the phases of the input signal I and the output signal OUT are different, the multiplexer 413 selects the delay signal In_ck_d as the output signal OUT. In an embodiment of the present invention, the signal transmission synchronizer 220 is formed by concatenating 64 signal transmission synchronizer units 410~4N0. Notably, the number of signal transmission synchronizer units 410~4N0 is not limited thereto. Those having ordinary knowledge in the technical field of the present invention should understand that this length can be adjusted according to different needs. The timing chart of this embodiment will be exemplified below.

As shown in FIG. 5, the timing chart described in FIG. 3 is extended. The input signal In is sampled by using the timing signal Tune_clk as the sampling clock. Similarly, the signal synchronizing unit 410 is used as an example. When the input signal In transitions from a logic high level to a logic low level or from a logic low level to At the logic high level, phase comparator 412 compares the phase of input signal I and output signal OUT. If the input signal I and the output signal OUT are in phase, the phase comparator 412 outputs a logic low level selection signal sel[0] to control the multiplexer 413 to select the input signal I as the output signal OUT. Conversely, if the input signal The phase of the I and the output signal OUT are different, and the phase comparator outputs a logic high level selection signal sel[0] to control the multiplexer 413 to select the delay signal In_ck_d as the output signal OUT. In principle, each time the phase of the input signal In changes, only the selection control signal of the multiplexer of the signal transmission synchronizer unit will be at a logic high level. At this time, the delay signal In_clk_d is inserted by the set of multiplexers whose selection control signal is equal to the logic high level, and the delay signal In_clk_d is transmitted backward until the number of cycles in which the delay signal In_clk_d is delayed is sufficient, and the multiplexer is cleared at this time. The selection signal is a logic low level, allowing the multiplexer to select the input signal I to produce the output signal OUT. In the example shown in FIG. 5, the selection signal (sel[3]) of the fourth unit of the signal transmission synchronizer is logic high when the input signal In transitions from the logic low level to the logic high level at the beginning. At the time, the delay signal In_clk_d is inserted by the signal transmission synchronization unit of the fourth stage. Then, when the input signal In transitions from the logic high level to the logic low level, the selection signal (sel[7]) of the signal transmission synchronization unit of the eighth stage of the signal transmission synchronizer is a logic high level, and the delay is performed. The signal In_clk_d is inserted by the signal transmission synchronization unit of the eighth stage. When the input signal In is again transitioned from the logic low level to the logic high level, the selection signals sel[3] and sel[7] are both logic low levels, and the delay signal In_clk_d can be synchronized by other stages of signal transmission. The unit is inserted. Please refer to FIG. 6. FIG. 6 illustrates an embodiment of a combined logic gate delay circuit 230 in accordance with an embodiment of the present invention. The combinational logic gate delay circuit 230 is formed by a plurality of delay units 610-6M0. Each delay unit includes a buffer and an alternative multiplexer. The delay unit 610 is taken as an example. The delay unit 610 is used. Includes a buffer 611 and an alternative multiplexer 612. The multiplexer 612 outputs the received input signal to its output terminal, or delays the input signal delayed by the buffer 611, and outputs it to the output terminal of the multiplexer 612. The selection action of the output signal of the multiplexer 612 is determined according to the received control signal Ck_nn[0]. Through the setting of the control signals Ck_nn[0]~Ck_nn[6], the input signal CK1 is sequentially delayed by the delay unit 610-6M0 and output to the output terminal of the combined logic gate delay circuit 230 to generate an output signal CK_out. In an embodiment of the present invention, the combined logic gate delay circuit 230 is formed by connecting 64 delay units 610-6M0. Notably, the number of delay units 610-6M0 is not limited thereto, and the technical field of the present invention Those with ordinary knowledge should understand that this length can be adjusted according to different needs.

As shown in FIG. 2, the input signal In is fed back to the output signal CK_out at the output of the combined logic gate delay circuit 230. The principle of the ring oscillator is known to those skilled in the art. Here, the input signal In passes through the clock count delay unit 210, the signal transfer synchronizer 220, and is combined with the original logic gate delay circuit 230. The input signal In reverses the output signal Ck_out.

Please refer to FIG. 7. FIG. 7 is a schematic diagram of a ring oscillator 700 according to another embodiment of the present invention. The ring oscillator 700 includes a synchronous clock count delay 710 and a combined logic gate delay circuit 720. The combined logic gate delay circuit 720 of FIG. 7 is identical to the combinational logic gate delay circuit 230 of FIG. 2, while the synchronous clock count delay 710 is functionally equivalent to the clock count delay 210 and signal transfer synchronization of FIG. 220.

Please refer to FIG. 8 , which illustrates a synchronization clock according to an embodiment of the present invention. An embodiment of counting delay 710. The sync clock count delay 710 includes a edge detector 820, an oscillator 830, and a counter 840. The sync clock count delay 710 delays the input signal In by a delay amount in accordance with the delay control signal CK_delay[19:0] to generate a delay signal In_ck_d. The amount of delay therein is equal to one or more cycles of the clock signal Tune_clk generated by the oscillator 830. In other words, when the sync pulse count delay 710 detects the rising edge or the falling edge of the input signal In through the edge detector 820, the oscillator 830 is immediately activated by the start signal En to generate the clock signal Tune_clk. The counter 840 receives the Tune_clk signal and starts counting the number of Tune_clk, and when the counter 840 counts the result equal to the number set by the corresponding delay control signal CK_delay[19:0], the oscillator 830 is correspondingly turned off. The above-mentioned shutdown operation of the oscillator 830 is performed by the counter 840 transmitting the reset signal CLR to the edge detector 820. The edge detector 820 turns off the enable signal En according to the received reset signal CLR, and thereby turns off the oscillator 830.

As shown in Figure 10. The oscillator 830 is configured to oscillate according to the enable signal En to generate a clock signal Tune_clk. The counter 840 is configured to receive the input signal In, the clock signal Tune_clk, and the delay control signal CK_delay[19:0], and delay the input signal In according to the delay control signal CK_delay[19:0] by the corresponding clock signal Tune_clk. To generate a first delayed signal In_ck_d. And when the number of counting operations performed according to the clock signal Tune_clk reaches a corresponding period, the reset signal CLR is output to turn off the enable signal En of the oscillator 830.

Please refer to FIG. 9. FIG. 9 is a diagram of a wave edge detector 820 according to an embodiment of the invention. Schematic diagram. In the present embodiment, the edge detector 820 includes a delay 922, an anti-mutation or gate 924, and a SR latch 926. The delay 922 is configured to delay the input signal In described above to generate a delayed input signal In_d. The input signal In and the delayed input signal In_d pass through the exclusive reversal OR gate 924 to obtain an output preamble S1. The flip flop 926 can be an SR flip flop, the preamble S1 is coupled to the set terminal S of the SR latch 926, and the reset terminal R of the SR latch 926 receives the reset signal CLR.

The oscillator 830 described above can be a voltage controlled oscillator, a ring oscillator or other type of oscillator.

In summary, the delay line circuit of the present invention adjusts the delay of its input signal based on the clock signal, and sets the delay control signal to decide to delay the input signal by the corresponding clock signal period. Thereby, the delay line circuit can delay the input signal to the required length without using too many delay units, thereby adjusting the oscillation clock to the required frequency.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧ ring oscillator

INV1‧‧‧ reverser

200, 700‧‧‧ ring type oscillation circuit

210‧‧‧clock count retarder

710‧‧‧Synchronous Clock Count Delayer

220‧‧‧Signal Synchronizer

230, 720‧‧‧ combination logic gate delay circuit

In‧‧‧ input signal

Tune_clk‧‧‧ clock signal

CK_delay[19:0]‧‧‧ Delay control signal

In_ck_d‧‧‧delay signal

410~4N0‧‧‧Signal transmission synchronizer unit

I‧‧‧ input signal

OUT, CK_out‧‧‧ output signal

411‧‧‧delay logic gate

413‧‧‧Multiplexer

412‧‧‧ phase comparator

I1, I2‧‧‧ input signal terminal

Sel[0], sel[3], sel[7]‧‧‧ selection signal

610-6M0‧‧‧ delay unit

611‧‧‧buffer

612‧‧‧Multiplexer

Ck_nn[0]~Ck_nn[6]‧‧‧Control signals

820‧‧‧ Wave edge detector

830‧‧‧Oscillator

840‧‧‧ counter

En‧‧‧ start signal

CLR‧‧‧Reset signal

In_d‧‧‧Delayed input signal

922‧‧‧ retarder

924‧‧‧mutual exclusion or gate

926‧‧‧SR latch

S‧‧‧Setting end

R‧‧‧Reset end

A conventional ring oscillator 100 shown in FIG.

2 is a schematic diagram of a ring oscillator circuit 200 in accordance with an embodiment of the present invention; Figure.

3 is an example of a timing chart of an input signal In, a clock signal Tune_clk, and a delay signal In_ck_d according to an embodiment of the present invention.

4 is a schematic diagram of an embodiment of a signal transfer synchronizer 220.

FIG. 5 is another timing diagram for extending the timing diagram described in FIG.

FIG. 6 illustrates an embodiment of a combined logic gate delay circuit 230 in accordance with an embodiment of the present invention.

FIG. 7 is a schematic diagram of a ring oscillator 700 according to another embodiment of the present invention.

FIG. 8 illustrates an embodiment of a synchronous clock count delay 710 in accordance with an embodiment of the present invention.

FIG. 9 is a schematic diagram of a wave edge detector 820 according to an embodiment of the invention.

FIG. 10 is a diagram showing the operation waveforms of the ring oscillator 700 of FIG. 7 of the present invention.

200‧‧‧ring type oscillation circuit

210‧‧‧clock count retarder

220‧‧‧Signal Synchronizer

230‧‧‧Combined logic gate delay circuit

In‧‧‧ input signal

Tune_clk‧‧‧ clock signal

CK_delay[19:0]‧‧‧ Delay control signal

Claims (12)

A ring oscillator circuit includes: a clock count delayer that receives an input signal, a clock signal, and a first delay control signal, and delays the input signal according to the first delay control signal and the clock signal to generate a first delay signal; a signal transmission synchronizer coupled to the clock count delayer, receiving the input signal, and generating a second delay signal according to a transition point of the input signal; and a combined logic gate delay circuit And coupling the signal transmission synchronizer to receive the second delay signal, delaying the second delay signal according to the second delay control signal to generate an output signal, wherein the clock count delay device receives the end of the input signal A point is coupled to the combined logic gate delay circuit to generate an endpoint of the output signal. The ring oscillator circuit of claim 1, wherein the signal transmission synchronizer comprises: a plurality of first delay units, the first delay units are connected in series, and each of the first delay units has a first An input end, a second input end, and an output end, the second input end of the first delay unit of the first stage receives the input signal, and the output end of each of the first delay units is coupled to the first delay unit of the subsequent stage a first input end of the first delay unit and receiving the first delay signal, wherein each of the first delay units compares a signal received by the second input end with a phase of a signal of the output end. To select the first delayed signal And one of the signals received by the second input of each of the first delay units is output to its output. The ring oscillator circuit of claim 2, wherein each of the first delay units comprises: a buffer, the input end of which is coupled to the second input end of each of the first delay units; a phase comparison The second input end of each of the first delay units and the output end thereof are coupled to generate a selection signal according to the signal received by the second input terminal and the phase of the signal at the output end; and a multiplexer coupled An output of the buffer and the phase comparator, the multiplexer selecting one of the first delay signal and the signal received by the second input of each of the first delay units according to the selection signal Output to the output of each of the first delay units. The ring oscillator circuit of claim 1, wherein the combined logic gate delay line comprises a plurality of serially connected second delay units, each of the second delay units including an input end, a control end, and an output. The second delay unit directly outputs the signal received by the input terminal to the output terminal or the input terminal of each of the second delay units according to the second delay control signal received by the control terminal. The signal is transmitted to at least one logic gate for delay, and the delayed signal is output to the output ends of each of the second delay units. The ring oscillator circuit of claim 4, wherein each of the second delay units comprises: a buffer, the input end of which is coupled to the input of each of the second delay units And a multiplexer coupled to the output end of the buffer and the input end, and receiving a bit of the second delay control signal, the multiplexer according to the received one of the second delay control signal The element selects to output a signal on the output or input of the buffer to the output of each of the second delay units. A ring oscillator circuit includes: a synchronous clock count delayer for receiving an input signal and a delay control signal, and delaying the input signal according to the first delay control signal and a clock signal to generate a first a delay signal; and a combination logic gate delay circuit for receiving the first delay signal and delaying the first delay signal to generate an output signal according to a second delay control signal, wherein the synchronous clock count delay An endpoint receiving the input signal is coupled to the combined logic gate delay circuit to generate an endpoint of the output signal. The ring oscillator circuit of claim 6, wherein the synchronous clock counter retarder comprises: a wave edge detector for detecting at least one edge of the input signal, and thereby outputting the same The energy signal, wherein the edge of the input signal is synchronized with at least one transition point of the enable signal; an oscillator coupled to the edge detector, the oscillator is generated according to the enable signal The clock signal; and a counter for receiving the input signal, the clock signal and the delay control signal, and delaying a period of the plurality of clock signals of the input signal according to the delay control signal to generate the delayed signal. The ring oscillator circuit of claim 6, wherein the oscillator is a ring oscillator. The ring oscillator circuit of claim 6, wherein the edge detector comprises: a delay device that receives the input signal and delays the input signal to generate a delayed input signal; a gate having an input receiving the input signal and another input receiving the delayed input signal; and an SR latch having a set end coupled to the output of the mutex or gate, the reset end receiving a weight Set the signal. A ring oscillator circuit includes: a clock count delayer, receiving an input signal, a clock signal, and a delay control signal, and delaying the input signal according to the delay control signal and the clock signal to generate a delay signal; And a combination logic gate delay circuit coupled to the clock count delay device, receiving the delay signal, delaying the delay signal according to the delay control signal to generate an output signal, wherein the clock count delay device receives the input signal The end point is coupled to the combination logic gate delay circuit to generate an endpoint of the output signal. The ring oscillator circuit of claim 10, wherein the combined logic gate delay line comprises a plurality of serially connected delay units, each of the delay units including an input end, a control end, and an output end, each of which The delay unit directly outputs the signal received at the input end thereof to the output terminal according to the delay control signal received by the control terminal thereof or causes each of the delay orders The signal received at the input of the element is passed to at least one logic gate for delay, and the delayed signal is output to the output of each of the delay units. The ring oscillator circuit of claim 11, wherein each of the delay units comprises: a buffer, an input end of which is coupled to an input end of each of the delay units; and a multiplexer coupled An output end of the buffer and an input end, and receiving a bit of the delay control signal, the multiplexer selectively outputting the output or the input end of the buffer according to the received one bit of the delay control signal The signal is sent to the output of each of the delay units.