JP2009267471A - Scan type ad converting method and scan type ad conversion system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a scan type AD converting method and system, which reduces sample jitters. <P>SOLUTION: The scan type AD conversion system AD-converts sequentially analog signals inputted from a plurality of parallelly connected sensors 12 by an AD converter 16 into serial data 32, and outputs the serial data, under the control of a microcomputer 72. Sequence control by a sequencer 18 such that a multiplexer 14 selects the plurality of sensors one after another and the sequentially inputted analog signals are AD-converted, is periodically performed. The sequencer 18 is driven with a clock outputted from a microcomputer 18 as a clock source and the serial data 32 are inputted to a serial interface 76 in the microcomputer 72. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

The present invention relates to AD conversion, and more particularly to AD conversion technology for converting an analog signal from a sensor connected in parallel into a serial digital signal.

The sensor outputs an analog signal. For this reason, when a user using a sensor needs a digital output, an analog / digital (A / D) converter is connected after the sensor, and the analog signal output from the sensor is converted into a digital signal for use. is doing. Furthermore, even in devices that require multiple vibration sensors such as head mounted displays used for posture detection, posture control, virtual reality, etc., trackers that detect head posture angles, 3D game pads, etc. AD conversion is performed on the signal.

Conventionally, when performing AD conversion of a plurality of analog signals, an AD converter called a scan type using a multiplexer having one AD converter has been used (see Patent Document 1). The scan type AD converter connects a plurality of sensors in parallel and can select an analog signal input from one sensor, and is connected to the multiplexer and converts the analog signal selected by the multiplexer into a digital signal. An AD converter and a microcomputer connected to the AD converter and operating the AD converter and the multiplexer to acquire the digital signal are included. Based on the operation from the microcomputer, the multiplexer selects one of the plurality of inputs, inputs the signal to the AD converter, and sequentially selects the input from the vibration sensor to perform AD conversion. With such a configuration, the cost can be reduced because there is only one AD converter, and analog signals from a plurality of sensors can be AD converted on the same scale.
JP 2000-278128 A

However, the conventional AD converter is controlled by operation from a microcomputer connected to the subsequent stage. Therefore, the task of the microcomputer is occupied to some extent by the operation of the AD converter, and the reliability of the entire system is lowered. In addition, AD conversion is a high-priority task that is performed at equally spaced times.
Since interruption of a task related to D conversion is performed by software, timing for AD conversion is shifted, which causes sampling jitter.

Therefore, the present invention pays attention to the above-mentioned problems, and provides a scan type AD conversion system that improves the reliability of the entire system and reduces sampling jitter.

SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following application examples.

[Application Example 1] A scan-type A in which analog signals input from a plurality of sensors connected in parallel are sequentially AD-converted and converted into serial data by microcomputer control.
A D conversion method, wherein the plurality of sensors are sequentially selected, the analog signal that is sequentially input is AD converted, and serial control is performed to periodically output the data.
A scan type AD conversion method characterized by the above.

By the above method, a sequence control for sequentially selecting a sensor in place of a microcomputer and a sequence control for converting an analog signal into an AD signal and converting it into serial data are performed. Therefore, the microcomputer only needs to command the sequence to be driven / stopped, and the proportion of the software resources of the microcomputer that require conventional AD conversion work to the system can be reduced. Furthermore, since AD conversion is performed by a hardware sequence, sampling jitter can be reduced as compared with the case where the microcomputer performs AD conversion through software.

Application Example 2 The scan according to Application Example 1, wherein the sequence control is driven using a clock output from a microcomputer as a clock source, and the serial data is input to a serial interface in the microcomputer. Type AD conversion method.

According to the above method, the sequence control uses a microcomputer that generates a clock by crystal oscillation as a clock source, and can perform sampling without the influence of tasks inside the microcomputer, so that sample jitter can be reduced. The serial data is output in synchronization with the clock of the microcomputer and is parallelized when input to the serial interface. Therefore, a microcomputer that transmits and receives parallel data can easily acquire parallelized data without any processing. Therefore, it is possible to reduce the ratio of software resources for fetching data from the AD converter of the microcomputer to the system. In particular, when the microcomputer uses direct memory access, since the CPU in the microcomputer does not need to perform data acquisition work, the ratio of software resources for taking in data from the AD converter to the system can be minimized.

Application Example 3 A scan-type A in which analog signals input from a plurality of sensors connected in parallel are sequentially AD-converted and converted into serial data by microcomputer control.
A D-conversion system having a plurality of ports for connecting the sensors in parallel, a multiplexer for sequentially selecting the ports using a port select as a trigger, and a multiplexer connected to the multiplexer and sequentially input The analog signal is AD-converted using a chip select as a trigger, and is connected to an AD converter that outputs serial data related to the AD conversion, the multiplexer and the AD converter, and generates the port select and the chip select. And a sequencer for periodically performing sequence control for outputting the port select to the multiplexer and outputting the chip select to the AD converter, and a scan type AD conversion system.

With the above configuration, the sequencer sequentially selects a sensor in place of the microcomputer, and performs sequence control in which an analog signal is AD converted and converted into serial data. Therefore, the microcomputer only needs to command the sequence to be driven / stopped, and an AD conversion system in which the ratio of the software resources of the microcomputer requiring the conventional AD conversion work to the system is reduced. Furthermore, since AD conversion is performed by a hardware sequencer, an AD conversion system in which sampling jitter is reduced compared to a case where a microcomputer performs AD conversion through software.

Application Example 4 The sequencer generates a serial clock based on an external clock input from a microcomputer, the AD converter outputs serial data using the external clock as a trigger, and the serial data is the serial clock The scan type AD conversion system according to claim 3, wherein the scan type AD conversion system is input to a serial interface of the microcomputer in synchronization with the microcomputer.

With the above configuration, the sequencer and the AD converter are driven by using a microcomputer that generates a clock by crystal oscillation as a clock source. Therefore, sampling without the influence of tasks inside the microcomputer can be performed, so that an AD conversion system with reduced sample jitter is obtained. The serial data is output in synchronization with the clock of the microcomputer and is parallelized when input to the serial interface. Therefore, a microcomputer that transmits and receives parallel data can easily acquire parallelized data without any processing. Therefore, an AD conversion system in which the ratio of software resources for taking in data from the AD converter of the microcomputer to the system is reduced is obtained. In particular, when the microcomputer uses direct memory access, the CPU in the microcomputer does not need to perform data acquisition work. Therefore, an AD that minimizes the ratio of software resources for capturing data from the AD converter to the system. It becomes a conversion system.

Hereinafter, the present invention will be described in detail with reference to embodiments shown in the drawings. However, the components, types, combinations, shapes, relative arrangements, and the like described in this embodiment are merely illustrative examples and not intended to limit the scope of the present invention only unless otherwise specified. .

As shown in FIG. 1, an AD conversion system 10 according to the present embodiment includes a plurality of sensors 12 that output analog signals, a multiplexer 14 that selects the sensors 12, an AD converter 16, and an AD
It comprises a sequencer 18 that controls the converter 16 and the multiplexer 14 based on a protocol. As for a signal flowing in the circuit, a high voltage signal is H and a low voltage signal is L.

The sensor 12 outputs each physical quantity in analog form as a current value like an acceleration sensor, a pressure sensor, a temperature sensor, etc., and the sensor 12 is connected to a port of a multiplexer. In the present embodiment, for simplicity of explanation, two or more sensors 12 (first sensor 12a and second sensor 12b) may be used.

The multiplexer 14 electrically or mechanically selects one port from a plurality of ports using a first port select and a second port select (described later) output from the sequencer 18 as a trigger. In the multiplexer 14, a first port 14a for inputting an analog signal from the first sensor 12a and a second sensor 14b for inputting an analog signal from the second sensor 12b are disposed. Also output from the sequencer 18 and the multiplexer 1
4 to select the first port 14a (second port 14b), which will be described later.
First port select input terminal 14c (second port) for inputting (second port select 28 described later).
A port select input terminal 14d) is provided.

On the other hand, the output terminal 14e of the multiplexer 14 connected to the AD converter 16 described later is one. Thereby, one port can be selected from the first port and the second port, and an analog signal related to the one port can be output from the output terminal 14e. In addition, the first port 14
The first sensor 12 is selected by successively selecting a in the order of the second port 14b (or reverse).
The analog signals of a and the second sensor 12b can be successively output from the output terminal.

The AD converter 16 converts an analog signal input via the multiplexer 14 into a digital signal. In addition to the analog signal input terminal 16a described above, the AD converter 16 includes a chip select input terminal 16b for inputting a chip select 30 (to be described later) output from the sequencer 18, and an external clock 22 (a clock obtained by dividing the external clock 22). The external clock input terminal 16c inputs the same, and the serial data output terminal 16d outputs serial data 36 obtained by AD conversion of the analog signal. The serial data output terminal 16d is connected to a serial interface 76 described later.

The AD converter 16 uses the chip select 30 output from the sequencer 18 as a trigger.
The input analog signal is converted into binary digital information. The AD converter 16 only needs to have the necessary number of bits for ensuring the S / N ratio necessary for the analysis of the amplitude direction of the analog signal. In this embodiment, a case where 16 bits are used will be described. The AD converter 16 has a sample-and-hold circuit (not shown) corresponding to the required number of bits (16 bits), and can hold information on each bit after AD conversion. The AD converter 16 is a frequency divider 24.
Is a data sequence in which digital information is multiplied by 16 pulse sequences in order from the upper digit of each bit using a serial clock 32a generated by multiplying a chip select 30 and an external clock 22 described later as a trigger. Can be output as
In other words, the AD conversion is performed in a time sufficiently shorter than the clock interval of the serial clock 32 a and the digital information is held in the sample hold circuit (not shown), but the output of the digital information is the serial clock 32 synchronized with the chip select 30. Are performed in order from the upper digit of each bit.

Further, as described above, the multiplexer 14 sequentially outputs analog signals from the first sensor 12a and the second sensor 12b. At this time, the sample hold circuit (not shown)
The digital information related to the analog signal from the sensor 12b is overwritten on the digital information from the first sensor 12a. Therefore, the protocol 20 of the sequencer 18 described later is designed so that the analog signal from the second sensor 12b is input after all the analog signals from the first sensor 12a are output using the serial clock 32a as a trigger. .

As a result, the pulse train that is output after AD conversion of the analog signal from the first sensor 12a and the pulse train that is output after AD conversion of the analog signal from the second sensor 12b are arranged in a line, 32 Serial data 32 composed of a number of pulse trains is formed.

The sequencer 18 is configured according to the number of states of combinations of operations of the multiplexer 14 and the AD converter 16, and selects each state in turn by the protocol 20 or performs control to maintain each state for a certain time. Hardware. The sequencer 18 has a reset signal input terminal 18a for inputting a reset signal from a microcomputer or the like, an external clock input terminal 18b for inputting an external clock 22 from a microcomputer or the like by crystal oscillation, and a multiplexer 1
A first port select output terminal 18c (second port select output terminal 18d) for outputting a first port select (second port select), which will be described later, which performs the selection control of 4, and an AD conversion command for the AD converter 16 to be described later. A chip select output terminal 18e for outputting a chip select and a serial clock output terminal 18f for outputting a serial clock 32 (described later) generated inside the sequencer are provided. The serial clock output terminal 18f is connected to a serial interface 76 described later.

The sequencer 18 receives an external clock 22 such as a microcomputer from the outside, and if necessary, a frequency divider 24.
The first port select 26, the second port select 28, the chip select 30, and the serial clock 32 whose phases are synchronized with each other are configured based on a protocol 20 to be described later. Is generated. The first port select 26 is a trigger for ON / OFF control of the first port 14a, and the second port select 28 is a trigger for controlling the second port 14a.
This is a trigger for ON / OFF control of b. In order to avoid the simultaneous output of the first port select 26 and the second port select 28, in the protocol 20 described later, the first port select 26 is output and input from the first port 14a by the AD converter 16. The second port select 28 is designed to be output after an analog signal is output as a pulse train of a digital signal. Therefore, strictly speaking, analog signals from a plurality of sensors 12 are not subjected to AD conversion at the same time, but the difference is sufficiently smaller than the sampling frequency of AD conversion. AD signal at the same time
It can be considered that the conversion has been performed.

FIG. 2 shows a protocol 20 (timing chart) of the sequencer 18. In FIG. 2, the first port 14a, the second port 14b, and the AD converter 16 are activated at the negated positions (H → L) of the first port select 26, the second port select 28, and the chip select 30. The timer clock 34 is inverted from the external clock 22 because the input of the signal H to each set S of the ADC control logic described later is performed at the assert position (L → H).
For simplification of description, frequency division by the frequency divider 24 is omitted. And serial clock 32
Are synchronized with the external clock 22 without inversion of H and L. Further, the serial clock 32 maintains the H state when there is no clock. The first negation of the clock portion of the serial clock 32 matches the negation of the chip select, and the chip select 30 is asserted one clock after the last assertion of the clock portion of the serial clock 32. Therefore, in the AD converter 16, the serial clock 32 a generated by multiplying the chip select 30 and the external clock 22 is synchronized with the clock portion of the serial clock 32.

In FIG. 2, the protocol 20 defines nine substates including the 0th substate 20a to the 8th substate 20i in the time axis direction. In the 0th substate 20a, the second port select 28 and the chip select 30 are reset. After eight clocks, the first port select 26 is set as the first substate 20b. After 8 clocks, the chip select 30 and the serial clock 32 are set as the second substate 20c. 15
After the clock, the serial clock 32 is reset as the third substate 20d. After one clock, as the fourth substate 20e, the first port select 26 and the chip select 3
Reset 0. Eight clocks later, the second port select 2 as the fifth substate 20f
Set 8. After 8 clocks, the chip select 30 and the serial clock 32 are set as the sixth substate 20g. After 15 clocks, the serial clock 32 is reset as the seventh substate 20h. After one clock, the substate management RS-FF 40 described later is reset as the eighth substate 20i. Here, the clock time between the first substate 20b and the second substate 20c and between the fifth substate 20f and the sixth substate 20g is stabilized after the multiplexer 14 selects each port. The time until is secured. The eighth sub-state 20i is for resetting a sub-state counter, which will be described later, and starting the sub-state from the 0th sub-state 20a after releasing the reset.

By configuring the protocol in this way, the first port 14a and the second port 14b
Are sequentially input to the AD converter 16 by the first port select 26 and the second port select 28. Then, serial data 36 consisting of 32 pulse trains, which are AD-converted sequentially into 16 pulse train digital signals by the chip select 30, is created.

FIG. 3 shows a circuit configuration diagram of the sequencer 18 for realizing the protocol 20. The sequencer 18 includes a binary counter 38, a substate management RS-FF 40, a substate counter 42, a line decoder 44, an upcount timer 46, a timer preset data table 48, and an ADC control logic 50.

The binary counter 38 receives a clock from the external clock 22 and outputs H to the set 40a (S) of the substate management RS-FF 40 when full count is reached. When the count is further counted from the full count, it returns to zero (initial value) and starts counting up again. Further, when a reset signal (signal H) is obtained from the microcomputer, the count is reset to zero and the count is stopped, thereby stopping AD conversion. This count-up cycle becomes a sampling cycle of the AD converter, and the serial data 32 is periodically output in this cycle. It is assumed that the sampling period has a clock time sufficiently longer than the time during which the sub-state counter 42 goes through all the sub-states.

The substate management RS-FF 40 is a flip-flop that stores the signal from the binary counter 38 and resets the store by the output signal of the eighth substate of the line decoder 44 and the reset signal from the microcomputer side. By inputting the signal H from the binary counter 38 from the set 40a (S), the signal H is stored in the output Q40b, and the sub-state counter 42 and the upcount timer 46 are made countable.
By inputting the signal H to the reset 40c (R) and setting the output 40b (Q) to L, the count values of the state counter and the upcount timer are returned to the initial values. Furthermore, since the inverted output 40d (nQ) obtained by logically inverting the output 40b of the sub-state management RS-FF 40 is connected to the reset side of the ADC control logic 50 that controls the serial clock, the inverted output 40d (output 40b) ) Is reset, the signal H is output to the reset side. The binary counter 38 and the sub-state management RS-FF 40 are elements that realize the main state task 66 in the operation flow 64 described later.

As the sub-state counter 42, a counter such as a Johnson counter that does not cause a static hazard is used. The sub-state counter has a carry input terminal 42a for inputting a carry from the up-count timer 46, and an output terminal 42b for outputting the count value counted up with the carry negation as a trigger to the line decoder in parallel. Therefore, the substate counter 42 counts up when it receives a carry from the upcount timer 46, and stops counting when it reaches the maximum value. The number that can be counted is the number of substates as it is. The substate counter 42 is provided with a negative reset 42c (nR). When the signal at the negative reset 42c becomes L, the count value becomes an initial value, and the reset state is maintained as long as L is maintained. The state counter does not operate. The time until this substate counter counts from the initial value to the maximum value is obtained by successively converting analog signals input from the first port and the second port to AD.
This is the time from conversion to serial data creation. Here, the initial value of the substate counter is 0 and the maximum value is 8, and the 0th substate 20a to the 8th substate 2 respectively.
0i is supported.

The line decoder 44 is assigned to the input terminal 44a for inputting the numerical value indicated by the sub-state counter in parallel and the numerical value of the state count, and the 0th sub-state 20a.
To output terminals (Q0 terminal 44b to Q8 terminal 44j) for realizing the eighth sub-state 20i;
Have The line decoder decodes the numerical value input from the substate counter, compares the substate value obtained by decoding with the substate value incorporated in advance, and outputs the signal H to the output terminal of the substate associated with the matching numerical value. Is output. In this embodiment,
The number of substates is nine, and the output shifts from the Q0 terminal 44b to the Q8 terminal 44i. Each output terminal is connected to an appropriate position in the ADC control logic 50 and the timer preset data table 48 as described later in order to realize each substate.

The up-count timer 46 is a binary counter that receives the external clock 22 from the external clock input terminal 46e and counts up when the external clock 22 is asserted as a trigger, and presets the binary data sent in parallel from the timer preset data table 48. It has a configuration that can be input as data. Therefore, the upcount timer 46 is provided with a timer preset data trigger 46a (nLD) and a preset data port 46b (PD) for inputting timer preset data. Also, the counter has a C0 terminal 46c for outputting a carry when the counter reaches a full count, the carry branches in the middle, one connected to the sub-state counter 42, and the other connected to the timer preset data trigger 46a via the inverter 60. Yes. Here, the timer preset data trigger 46a functions as a trigger when negated, and the preset data port 46b stores preset data triggered by the assertion following the negate. The up-count timer 46 is provided with a negative reset 46d (nR) so that the negative reset 4
When the signal at 6d becomes L, the count value becomes an initial value, and the reset state is maintained as long as L is maintained. At this time, the upcount timer 46 does not operate. In the present embodiment, the up-count timer 46 can count from 0 to 15 (decimal number) with 4 bits, and a carry is generated when 15 is counted.

Note that the negative resets 42c and 46d of the sub-state counter 42 and the up-count timer 46 are connected to the output 40b of the sub-state management RS-FF 40. It is reset when the reset signal from is input.

The timer preset data table 48 receives the output from the line decoder 44 and outputs the timer preset data, which is binary data, to the up-count timer 46 in parallel for each bit. In this embodiment, the timer preset data table has three timer preset data (1 clock, 8 clocks, 15 clocks), and outputs preset data related to the clock time required for the next state to the upcount timer. Yes. Here, one clock time means a time width of one clock. The timer preset data (15) 48a is connected to the Q2 terminal 44d and the Q6 terminal 44h, and outputs the timer preset data (15 clocks) of the next substate to the up-count timer. At this time, the upcount timer 46 generates a carry in one clock time. Timer preset data (1) 48b is connected to Q3 terminal 44e and Q7 terminal 44i,
The timer preset data (1 clock) of the next sub-state is output to the up-count timer 46, respectively. At this time, the upcount timer 46 generates a carry in 15 clock times. The timer preset data (8) 48c is connected to the Q0 terminal 44b, the Q1 terminal 44c, the Q4 terminal 44f, and the Q5 terminal 44g, and outputs the timer preset data (8 clocks) of the next-stage substate to the upcount timer 46, respectively. At this time, the upcount timer 46 generates a carry in 8 clock times. The substate counter 42, the line decoder 44, the upcount timer 46, and the timer preset data table 48 described above are elements that realize the substate task 68 in the operation flow 64 described later.

The ADC control logic 50 includes a first port select 26, a second port select 28, a chip select 30, and a serial clock 3 in accordance with the substate of the sequencer 18.
2 is a group of flip-flops of RS-FFs 52, 54, 56, 58, and the first port select 26, the second port select 28, the chip select 30, and the serial clock according to each substate from the line decoder 44. 32 sets and resets.

The first port select 26 is output from the inverted output 52a (nQ) of the RS-FF 52 and is output from the first port select output terminal 18c. The set 52b (S) has Q1.
A terminal 44c is connected, and a Q4 terminal 44f and a Q8 terminal 44j are connected to the reset 52c (R).

The second port select 28 is output from the inverted output 52a of the RS-FF 54 and output from the second port select output terminal 18d. The set 54b (S) is connected to the Q5 terminal, and the reset 54c (R) is connected to the Q0 terminal 44b.

The chip select 30 is output from the inverted output 56a (nQ) of the RS-FFF 56 and output from the chip select output terminal 18e. The set 56b (S) is connected to the Q2 terminal and the Q6 terminal, and the reset 56c (R) is connected to the Q0 terminal and the Q4 terminal.

The serial clock 32 is output from the output 58a (Q) of the RS-FF 58 and is output from the serial clock output terminal 18f. The Q2 terminal 44d and the Q6 terminal 44h are connected to the set 58b (S), and the Q3 terminal 44e and the Q7 terminal 44 are connected to the reset 58c (R).
The i and Q8 terminals 44j are connected.

Here, since the first port select 26, the second port select 28, and the chip select 30 perform the negation as a trigger, the terminals for storing the set / reset of each signal are connected to the inverted outputs 52b, 54b, 56b. The terminal for storing the set of the serial clock 32 is the output 58b, but the external clock inverted by the inverter 62 (n
CK) and the NAND 58d, the serial clock 32 is the external clock 2
Synchronizes with 2 without inversion. By performing such wiring, each substate of the protocol 20 can be realized. The ADC control logic 50 is an element that realizes the ADC control logic task 70 in an operation flow 64 described later.

A flow of the AD conversion system according to the present embodiment based on the above configuration will be described. FIG.
FIG. 5 shows an operation flow 64 of the AD conversion system 10. FIG. 4 is an overall view of the operation flow.
FIG. 5 shows a partial detailed view of the operation flow. The operation flow 64 of the AD conversion system 10 according to the present embodiment includes a main state task 66 that determines the sampling frequency and ON / OFF control of the entire sequencer, a substate task 68 that determines a substate of the AD conversion system 10, ADC that performs AD conversion of analog signals input from multiple sensors
It is classified as a control logic task 70.

First, in the main state task 66, the reset signal from the microcomputer is set to L to release the reset, and the binary counter is activated to count up until the full count is reached (first step 66a). And when full count is reached, state management RS-FF4
The signal H is stored in the output 40b of 0, the reset of the substate counter 42 is released, and the substate task 68 is started (second step 68a). When a signal indicating a substate from 0 to 7 is input to the line decoder 44 from the substate counter 42, the line decoder 44 decodes the substate (third step 68b), and a timer preset for the next substate. Data is prepared (fourth step 68c), and this state is maintained until the upcount timer 46 outputs a carry (fifth step 68d).

Next, in the third step 68b, the ADC control logic task 70 is started (sixth step
Step 70a), the first port select 26, the second port select 28, the chip select 30, and the serial clock 32 are output according to each substate (the 0th substate 20a to the seventh substate 20h) (seventh step). 70b). When the upcount timer 46 carries in the substate task 68, timer preset data relating to the next substate is loaded into the upcount timer 46 (eighth step 68e), and the substate counter 42 counts up. Thus, the signal indicating the substate is advanced (9th step 68f). When the signal indicating the sub-state advances, the line decoder decodes the sub-state again (third step 68b) on the condition that the sub-state is not full count (tenth step 68g), and then the fourth step 68c, 5 Step 68d is performed. Then, in the ADC control logic task 70, the previous ADC control logic task is terminated (11th step 70c), and the ADC control logic task related to the advanced substate is started (seventh step 70b). And the seventh substate 20h
Is executed, the ADC control logic task ends (11th step 70c).

On the other hand, in the substate task 68, the substate counter 42 is fully counted (
When the value becomes 8), the line decoder 44 decodes the sub-state related to the full count (eighth substate 20i) (12th step 68h), executes the 8th substate 20i (13th step 68i), A reset signal is output to the state management RS-FF 40, and the substate task 68 ends (14th step 68j). When the main state task 66 reaches full count again, the substate task 68 is resumed (second step 68a).

In the above flow, when the reset signal (signal H) is input to the main state task 66 during the execution of the substate task 68 and the ADC control logic task 70, the substate management RS-FF 40 is also reset. Stops immediately. At this time, the substate counter 42 and the upcount timer 46 are also reset, and the substate becomes the 0th substate 20a.

FIG. 6 shows a schematic connection diagram between the AD conversion system 10 and the microcomputer 72 according to this embodiment.
As shown in FIG. 6, the clock of the microcomputer 72 is input to the AD conversion system 10 as the external clock 22. The AD conversion system 10 has a parallel interface 7
4 and the serial interface 76 are connected to the microcomputer 72. Here, the serial interface 76 converts the serial data 36 into parallel data 82 and outputs it, or vice versa.

An interrupt terminal 74 a (not used in this embodiment) and a chip select 74 b (nCS) of the parallel interface 74 are connected to a control bus 78 of the microcomputer 72. The digital input output 74c (Dio) is connected to the data bus 80 of the microcomputer 72 and can input / output parallel data 82. The other end of the digital input output 74 c is connected to the reset input terminal 18 a of the sequencer 18 of the AD conversion system 10. As a result, the reset signal from the microcomputer 72 is sent to the data bus 80.
, And through the parallel interface 74. At this time, if the reset signal is H, the sequencer 18 is reset, and if it is L, the reset is canceled and the sequencer 18 is activated.

Interrupt terminal 76a of serial interface 76 and chip select 76b (nCS
) Is connected to the control bus 78 of the microcomputer 72, and the digital input output 76 c (Dio) is connected to the data bus 80. On the other hand, the clock input 76 d (SCK) of the serial interface 76 is the serial clock output terminal 18 of the sequencer 18.
and the input terminal 76e (RxD) is connected to the serial data output terminal 1 of the AD converter 16.
Connected to 6d. As described above, the serial clock 32 and serial data 36 output from the sequencer 18 of the AD conversion system 10 are generated from the clock of the microcomputer 72, and thus are synchronized with the clock of the microcomputer 72. Therefore, since this connection is not synchronous start (asynchronous), it is not necessary to configure a sequencer (not shown) that adds and processes a start bit and an end bit for measuring the synchronization timing before and after the serial data 36. Each time serial data 36 consisting of 32 pulse trains is stored in a register (not shown) in the serial interface 76, an interrupt can be made from the interrupt terminal of the serial interface 76 to the control bus 78. ing.

On the other hand, a memory (not shown) in the microcomputer 72 is connected to the data bus 80 in parallel. A CPU (not shown) in the microcomputer 72 saves the address of an instruction being executed at that time in a save area of a memory (not shown) each time the interrupt is received, and a chip select 74b of the serial interface 76. Is selected by negation, the parallel data 82 is transferred via software, a memory address is assigned to the parallel data 82 and stored in a memory (not shown) in the microcomputer 72 (polling). Thereby, the microcomputer 72 becomes A
Since only the ON / OFF operation of the D conversion system 10 is performed, and the sequencer 18 performs the output of signals related to each AD conversion task, the microcomputer 72 can be executed concentrated on other tasks, and the reliability of the entire system Will improve.

Further, when the microcomputer 72 has a DMA (Direct Memory Access) controller (not shown), the CPU (not shown) in the microcomputer 72 gives the DMA controller (not shown) the control authority of the control bus 78. I have yielded. Therefore, when the interrupt is input, the DMA controller (not shown) designates a transfer destination address in the memory (not shown) via the control bus 78, and the data bus 80 is opened to the serial interface 76.
It is written in a memory (not shown) in one clock time. Therefore, C in the microcomputer 72
The PU (not shown) does not need to perform a polling operation for data transfer, and can spend more time for processing other tasks.

When a reset signal (signal H) is input during AD conversion, the binary counter 38 of the sequencer 18 is reset to an initial value, and the binary counter 38 is not counted up as long as there is a reset signal. In this case, incomplete data (not shown) that is not completed as serial data 36 may be input to the serial interface 76. Therefore, in the microcomputer 72, if there is unfinished data (not shown) in the serial interface 76 after resetting, it may be configured to discard the data without storing it in the memory (not shown). However, if serial data 36 is being stored in a memory (not shown) at the time of reset, software that does not interrupt the work may be configured. And serial data 3
6 is stored and the serial interface 76 does not have the serial data 36, the task of the microcomputer 82 is stopped as it is, and software for initializing the setting of the microcomputer at the next activation may be configured.

A host PC 86 is connected to the microcomputer 72 via a serial interface 84. The host PC 86 is a terminal having an application for operating the AD converter 16 via the microcomputer 72. The input terminal 84a (RxD) of the serial interface 84 is connected to the serial data output terminal 86a of the host PC 86, and the output terminal 84b (TxD).
Is connected to the serial data input terminal 86 b of the host PC 86. Interrupt terminal 84
c and chip select 84d (nCS) are connected to the control bus 78. The digital input output 84e (Dio) is connected to the data bus 80 and can input / output parallel data 82. The host PC 86 inputs and outputs serial data 88, but is driven by a clock independent of the microcomputer 72. Accordingly, data communication between the host PC 86 and the serial interface 84 is performed in a synchronous step (asynchronous).

The host PC 86 outputs serial data 88 to the microcomputer 72 side, and the microcomputer 72 decodes the contents, so that the microcomputer can turn AD conversion ON / OFF. That is, the host PC 86 performs an AD conversion ON / OFF operation via the microcomputer 72. Therefore, when serial data 88 relating to a command from the host PC 86 to the microcomputer 72 is input to a register (not shown) of the microcomputer interface 84 and an interrupt request is made from the interrupt terminal 84, the microcomputer 72 selects the chip select 84d by negation. Then, the software of the microcomputer 72 that can acquire the parallel data 82 through the digital input output 84e and store it in the memory (not shown) of the microcomputer 72 may be configured.

Further, the host PC 86 can logically correct, for example, AD conversion sensitivity and offset on the application. Similar correction processing can be executed by software of the microcomputer 72 and correction data can be output to the host PC 88. For example, the data acquired from the serial interface 76 is calculated as a correction value such as sensitivity correction or offset, down-sampled into data that can be converted into serial data 88 that can be recognized by the host PC by calculating with an FIR filter, The software of the microcomputer 72 may be configured so that the chip select 84d of the serial interface 84 on the PC 86 side is selected by negation and the data is output.

Therefore, according to the AD conversion method and the AD conversion system according to the present embodiment, the microcomputer 7
The sequence in place of 2 and the sequencer 18 that implements the sequence perform control for successively selecting the sensor 12 and the sequence control for converting the analog signal from analog to digital and outputting it as serial data. Therefore, the microcomputer 72 only needs to command the driving / stopping of the sequencer 18, and the ratio of the software resources of the microcomputer requiring the conventional AD conversion work to the system can be reduced. Furthermore, since the AD conversion is performed by the sequencer 18 which is hardware, sampling jitter can be reduced as compared with the case where the microcomputer 72 performs AD conversion through software.

Further, the sequencer and AD converter 16 are driven with the microcomputer 72 generating a clock by crystal oscillation as a clock source. Therefore, sampling can be performed without the influence of tasks in the microcomputer 72, so that sample jitter can be reduced. The serial data 82 is output in synchronization with the clock of the microcomputer 72, and is parallelized when input to the serial interface 76. Therefore, the microcomputer 72 that transmits and receives parallel data can easily acquire the parallelized data without any processing. Therefore, it is possible to reduce the ratio of software resources for taking in data from the AD converter 16 of the microcomputer 72 to the system. Especially microcomputer 7
When 2 uses direct memory access, since the CPU (not shown) in the microcomputer 72 does not need to perform data acquisition work, the ratio of software resources for taking in data from the AD converter 16 to the system Can be minimized.

It is a schematic diagram of an AD conversion system concerning this embodiment. It is a figure which shows the protocol of the sequencer of the AD conversion system which concerns on this embodiment. It is a circuit block diagram of the sequencer of the AD conversion system which concerns on this embodiment. It is a whole figure of the operation flow of the AD conversion system concerning this embodiment. It is a partial detailed view of the operation flow of the AD conversion system according to the present embodiment. It is a connection outline figure with an AD conversion system concerning this embodiment, and a microcomputer.

Explanation of symbols

10 ... AD conversion system, 12 ... Sensor, 14 ... Multiplexer, 16 ...
... AD converter, 18 ......... sequencer, 20 ......... protocol, 22 ......... external clock, 24 ......... frequency divider, 26 ......... first port select, 28 ......... second port select,
30 ......... Chip Select, 32 ......... Serial Clock, 34 ......... Timer Clock,
36 ......... Serial data, 38 ......... Binary counter, 40 ......... Sub-state management RS-FF, 42 ......... Sub-state counter, 44 ......... Line decoder, 46 .........
Up-count timer, 48 ... Timer preset data table, 50 ... ADC
Control logic 52... RS-FF 54 54 RS-FF 56 RS
-FF, 58RS-FF, 60 ......... Inverter, 62 ......... Inverter, 64 ......... Operation flow, 66 ......... Main state task, 68 ......... Sub-state task, 70 ...
... ADC control logic task, 72 ......... Microcomputer, 74 ......... Parallel interface, 76 ......... Serial interface, 78 ......... Control bus, 80
... Data bus, 82 ... Parallel data, 84 Serial interface,
86 ……… Host PC, 88 ……… Serial data.

Claims (4)

A scan type AD conversion method in which analog signals input from a plurality of sensors connected in parallel are successively AD converted by microcomputer control, and converted into serial data and output.
A scan type AD characterized in that the plurality of sensors are sequentially selected, the analog signal that is sequentially input is AD-converted, and the sequence control is performed periodically as serial data. Conversion method. The sequence control is driven using a clock output from the microcomputer as a clock source,
The scan type AD conversion method according to claim 1, wherein the serial data is input to a serial interface in the microcomputer. A scan type AD conversion system that sequentially converts analog signals input from a plurality of sensors connected in parallel under microcomputer control, and converts the signals into serial data.
A plurality of ports that connect the sensors in parallel, and a multiplexer that sequentially selects the ports using a port select as a trigger;
An analog-to-digital converter connected to the multiplexer and sequentially converting the analog signal to be AD-converted using a chip select as a trigger, and outputting serial data related to the AD conversion;
Connected to the multiplexer and the AD converter, to generate the port select, the chip select,
A scan type AD conversion system comprising: a sequencer that periodically performs sequence control for outputting the port select to the multiplexer and outputting the chip select to the AD converter. The sequencer generates a serial clock based on an external clock input from a microcomputer, and the AD converter outputs serial data using the external clock as a trigger,
4. The scan type AD conversion system according to claim 3, wherein the serial data is input to a serial interface of the microcomputer in synchronization with the serial clock.

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