JP2009267764A - Simultaneous sampling type ad conversion method and simultaneous sampling type ad conversion system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a simultaneous sampling type AD conversion method and AD conversion system that reduces sample jitters. <P>SOLUTION: In the simultaneous sampling type AD conversion method that AD-converts a plurality of analog signals simultaneously by a plurality of AD converters 14 under microcomputer control and outputs serial data, the plurality of digital data 20 obtained through the AD conversion are outputted one after another by a shift register 26, and a sequencer 34 periodically makes sequence control for outputting the plurality of the digital data 20 in the form of the serial data. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

The present invention relates to AD conversion, and more particularly to AD conversion technology for converting an analog signal from a sensor connected in parallel into a serial digital signal.

The sensor outputs an analog signal. For this reason, when a user using a sensor needs a digital output, an analog / digital (A / D) converter is connected after the sensor, and the analog signal output from the sensor is converted into a digital signal for use. is doing. Furthermore, even in devices that require multiple vibration sensors such as head mounted displays used for posture detection, posture control, virtual reality, etc., trackers that detect head posture angles, 3D game pads, etc. AD conversion is performed on the signal.

Conventionally, when performing AD conversion of a plurality of analog signals, an AD converter called a scan type using a multiplexer having one AD converter has been used (see Patent Document 1). The scan type AD converter connects a plurality of sensors in parallel and has a multiplexer having a channel capable of selecting an analog signal input from one sensor, and the analog signal selected by the multiplexer is converted into digital data. And an A / D converter connected to the A / D converter and a microcomputer for operating the multiplexer and acquiring the digital data. Based on the operation from the microcomputer, the multiplexer selects one of the plurality of inputs, inputs the signal to the AD converter, and sequentially selects the input from the vibration sensor to perform AD conversion.

On the other hand, apart from the above-described AD conversion system, there is also a simultaneous sampling AD converter that performs AD conversion simultaneously with a plurality of AD converters connected to a plurality of sensors when AD converting a plurality of analog signals. It has been used (see Patent Document 2). The simultaneous sampling AD converter includes a plurality of sensors, a plurality of AD converters connected to the plurality of sensors, a plurality of buffer memories for storing a plurality of digital data obtained by AD conversion, and the plurality of the plurality of AD converters. The microcomputer is configured by operating an AD converter and the plurality of buffer memories to convert the plurality of digital data into serial data.

Based on the operation from the microcomputer, the AD converter simultaneously AD converts the analog signal, and sequentially outputs the digital data stored in the buffer memory to output serial data. With such a configuration, unlike the scan type AD conversion described above, the crosstalk between the channels of the multiplexer can be reduced, there is no time lag in the sampling time between the channels, and the sampling of the AD converter is also possible. The speed has the advantage that it does not depend on the number of channels.
JP-T-2001-523429 JP 2007-17650 A

However, the conventional AD converter is controlled by operation from a microcomputer connected to the subsequent stage. Therefore, the task of the microcomputer is occupied to some extent by the operation of the AD converter, and the reliability of the entire system is lowered. In addition, AD conversion is a high-priority task that is performed at equally spaced times.
Since interruption of a task related to D conversion is performed by software, timing for AD conversion is shifted, which causes sampling jitter.

Therefore, the present invention pays attention to the above-mentioned problems, and provides a simultaneous sampling AD conversion method and an AD conversion system that improve the reliability of the entire system and reduce sampling jitter.

SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following application examples.

[Application Example 1] A simultaneous sampling AD conversion method in which a plurality of analog signals are simultaneously AD-converted and converted into serial data by microcomputer control, and a plurality of digital data obtained by the AD conversion are sequentially obtained. The simultaneous sampling type AD conversion method is characterized in that sequence control is performed periodically to output the plurality of digital data to serial data and output the serial data.

By the above method, instead of the microcomputer, the sequence AD-converts analog signals simultaneously,
Sequence control is performed in which digital data obtained by AD conversion is converted into serial data and output. Therefore, the microcomputer only needs to command the sequence to be driven / stopped, and the proportion of the software resources of the microcomputer that require conventional AD conversion work to the system can be reduced. Furthermore, since AD conversion is performed by a hardware sequence, sampling jitter can be reduced as compared with the case where the microcomputer performs AD conversion through software.

Application Example 2 The simultaneous control according to claim 1, wherein the sequence control is driven by using a clock output from a microcomputer as a clock source, and the serial data is input to a serial interface in the microcomputer. Sampling type AD conversion method.

According to the above method, the sequence control uses a microcomputer that generates a clock by crystal oscillation as a clock source, and can perform sampling without the influence of tasks inside the microcomputer, so that sample jitter can be reduced. The serial data is output in synchronization with the clock of the microcomputer and is parallelized when input to the serial interface. Therefore, a microcomputer that transmits and receives parallel data can easily acquire parallelized data without any processing. Therefore, it is possible to reduce the ratio of software resources for fetching data from the AD converter of the microcomputer to the system. In particular, when the microcomputer uses direct memory access, since the CPU in the microcomputer does not need to perform data acquisition work, the ratio of software resources for taking in data from the AD converter to the system can be minimized.

Application Example 3 A simultaneous sampling AD conversion system that simultaneously converts a plurality of analog signals by AD and converts the analog signals into serial data, and outputs the input analog signals using a chip select as a trigger. A plurality of AD converters that perform AD conversion and output a plurality of digital data, and are connected to the plurality of AD converters, store the plurality of digital data, and store the plurality of serial data using a plurality of serial clocks as triggers A plurality of shift registers that sequentially output digital data and output serial data, and are connected to the AD converter and the shift register to generate the chip select, and to the plurality of AD converters, the chip A selection is output, and a serial clock is output to each of the plurality of shift registers. Simultaneous sampling AD converter system, characterized in that it comprises a sequencer for performing Nsu control periodically, the.

With the above configuration, instead of the microcomputer, the sequencer AD-converts analog signals simultaneously,
Sequence control is performed in which digital data obtained by AD conversion is converted into serial data and output. Therefore, the microcomputer only needs to command the sequencer to be driven / stopped, and the ratio of the software resources of the microcomputer that require conventional AD conversion work to the system is reduced.
D conversion system. Furthermore, since AD conversion is performed by a hardware sequencer, an AD conversion system in which sampling jitter is reduced compared to a case where a microcomputer performs AD conversion through software.

Application Example 4 The sequencer generates the serial clock based on an external clock input from a microcomputer, and the serial data is input to a serial interface of the microcomputer in synchronization with the serial clock. The simultaneous sampling AD conversion system according to claim 3.

With the above configuration, the sequencer uses a microcomputer that generates a clock by crystal oscillation as a clock source, and can perform sampling that eliminates the influence of tasks in the microcomputer, thus providing an AD conversion system with reduced sample jitter. The serial data is output in synchronization with the clock of the microcomputer and is parallelized when input to the serial interface. Therefore, a microcomputer that transmits and receives parallel data can easily acquire parallelized data without any processing. Therefore, an AD conversion system in which the ratio of software resources for taking in data from the AD converter of the microcomputer to the system is reduced is obtained. Especially when the microcomputer uses direct memory access, it is not necessary for the CPU in the microcomputer to do data acquisition work.
This is an AD conversion system in which the ratio of software resources for taking in data from the AD converter to the system is minimized.

Hereinafter, the present invention will be described in detail with reference to embodiments shown in the drawings. However, the components, types, combinations, shapes, relative arrangements, and the like described in this embodiment are merely illustrative examples and not intended to limit the scope of the present invention only unless otherwise specified. .

As shown in FIG. 1, the AD conversion system 10 according to the present embodiment is connected to a plurality of sensors 12 that output analog signals, a plurality of AD converters 14 that are connected to the sensors 12, and an AD converter 14. The shift register 26 holds digital data obtained by conversion, the AD converter 14, and a sequencer 34 that controls the shift register 26 based on a protocol 48. As for a signal flowing in the circuit, a high voltage signal is H and a low voltage signal is L.

The sensor 12 outputs each physical quantity in analog form as a current value or a voltage value, such as an acceleration sensor, a pressure sensor, a temperature sensor, etc., and the sensor 12 is an AD converter 1 for each sensor.
4 is connected. In the present embodiment, for simplicity of explanation, two or more sensors 12 (first sensor 12a and second sensor 12b) may be used.

The AD converter 14 converts the analog signal input via the sensor 12 into digital data 20.
It is to convert to. Here, the direction connected to the first sensor 12a is referred to as a first AD converter 16, and the direction connected to the second sensor 12b is referred to as a second AD converter 18. Digital data is 1A
The one output from the D converter 16 is the first digital data 20a, and the one output from the second AD converter 18 is the second digital data 20b. The first AD converter 16 (second AD converter 18) has the above-described analog signal input terminal 16a (18a), a chip select input terminal 16b (18b) for inputting a later-described chip select 46 output from the sequencer 34,
And an external clock input terminal 16c (18c) for inputting an external clock 24, and a digital data output terminal 16d (18d) for outputting first digital data 20a (second digital data 20b) obtained by AD converting an analog signal. .

The AD converter 14 uses the chip select 46 output from the sequencer 34 as a trigger.
The input analog signal is converted into binary digital information. The AD converter 14 only needs to have the necessary number of bits for ensuring the S / N ratio necessary for the analysis of the amplitude direction of the analog signal. In this embodiment, a case where 16 bits are used will be described. The AD converter 14 has a sample hold circuit (not shown) corresponding to the required number of bits (16 bits), and can hold information of each bit after AD conversion. The AD converter 14 receives the external clock 24 from the sequencer 34, and triggers the AD conversion output serial clock 22 generated by multiplying the chip select 46, which will be described later, with the external clock 24. It can be output as a data string multiplied by 16 pulse strings in order from the digit. That is, the AD conversion is performed in a time sufficiently shorter than the clock interval of the AD conversion output serial clock 22 and the digital data 20 is held in the sample hold circuit (not shown). The AD conversion output serial clock 22 (see FIG. 2) synchronized with the clock is sequentially performed from the upper digit of each bit.

The shift register 26 stores the digital data 20 by using the digital data 20 input from the AD converter 14 as a trigger by the serial clock 36 (first serial clock 38, second serial clock 40) input from the sequencer 34, and again. Serial clock 3
The digital data 20 is output using 6 as a trigger. In this embodiment, since a 16-bit AD converter is used, the 16 pulse trains in the previous stage of the serial clock 36 are stored in order from the upper digit of the digital data 20, and the digital data is stored in the 16 pulse trains in the subsequent stage. It is configured to output in order from the upper 20 digits. Here, the first shift register 28 is connected to the first AD converter 16, and the second shift register 30 is connected to the second AD converter 18.

The first shift register 28 (second shift register 30) includes a first AD converter 16 (second shift register 30).
The first digital data input terminal 28a (second digital data input terminal 30a) for inputting the first digital data 20a (second digital data 20b) from the AD converter 18) and the first serial clock 38 ( The first serial clock input terminal 28b (second serial clock input terminal 30b) for inputting the second serial clock 40) and the first digital data output for outputting the stored first digital data 20a (second digital data 20b) A terminal 28c (second digital data output terminal 30c) is provided.

The first digital data output terminal 28c and the second digital data output terminal 30c are connected in parallel by the OR circuit 32. Here, the first digital data 20a and the second digital data 20b are respectively converted into the first serial clock 38 and the second serial clock 40.
Thus, the signals are output at intervals that do not overlap in time. As a result, the digital data 20a output by AD conversion of the analog signal from the first sensor 12a, and the second sensor 12b
The digital data 20b obtained by AD-converting the analog signals from are aligned in a line to form serial data 44 composed of 32 pulse strings, which are output from the OR circuit 32.

The sequencer 34 is configured according to the number of states of the combination of operations of the AD converter 16 and the shift register 26, and selects each state in turn by the protocol 48 or performs control for maintaining each state for a certain period of time. It is hardware. The sequencer 34 receives a reset signal input terminal 34a for inputting a reset signal from the microcomputer 88, an external clock input terminal 34b for inputting the external clock 24 from the microcomputer 88 by crystal oscillation, and an AD conversion command for the AD converter 14. A chip select output terminal 34c for outputting a chip select 46 to be described later, a first serial clock output terminal 34d for outputting a first serial clock 38 to be described later generated in the sequencer 34 to the first shift register 28, and a second serial clock 4
A second serial clock output terminal 34e for outputting 0 to the second shift register 30 and a third serial clock output terminal 34f for outputting a third serial clock 42 are provided. The third serial clock output terminal 34f is connected to a serial interface 92 described later.

The sequencer 34 externally inputs the external clock 24 such as the microcomputer 88 to an appropriate frequency by a frequency divider 50 as necessary, configures a logic circuit based on a protocol 48 described later, and synchronizes with each other. A serial clock 36 (first serial clock 38, second serial clock 40, third serial clock 42) and chip select 46 are generated.

The chip select 46 is a trigger for issuing an AD conversion command to the first AD converter 16 and the second AD converter 18. Since the first AD converter 16 and the second AD converter 18 simultaneously perform AD conversion, there is one chip select 46.

The first serial clock 38 is a trigger for outputting the first digital data 20 a stored in the first shift register 28, and the second serial clock 40 is the second digital data 20 b stored in the second shift register 30. It is a trigger. In order to avoid the simultaneous output of the first serial clock 38 and the second serial clock 40, the first digital data stored in the first shift register 28 is output by the first serial clock 38 in the protocol 48 described later. The second serial clock 40 is designed to be output after 20a is output as a pulse train. Therefore, analog signals from the plurality of sensors 12 are AD converted at the same time, but a time difference is provided so as not to overlap with the output of the plurality of digital data 20 after AD conversion, and a line of serial data 44 is generated. Yes.

The third serial clock 42 is synchronized with the first serial clock 38 and the second serial clock 40. That is, it synchronizes with the serial data 44 composed of the first digital data 20a output by the first serial clock 38 and the second digital data 20b output by the second serial clock 40 output thereafter. .

FIG. 2 shows the protocol 48 of the sequencer 34. In FIG. 2, the first AD converter 16 and the second AD converter 18 are activated at the negated position (H → L) of the chip select 46.
The first digital data 2 is triggered by the negation of the preceding stage 38a of the first serial clock 38.
0a is stored in the first shift register 28, and the first digital data 20a stored in the first shift register 28 is triggered by the negation of the subsequent stage 38b of the first serial clock 38.
Is output. The second digital data 20b is stored in the second serial clock 40 using the negation of the previous stage 40a of the second serial clock 40 as a trigger, and stored in the second shift register 30 using the negation of the subsequent stage 40b of the second serial clock 40 as a trigger. The second digital data 20b is output. The digital data 20 output from each shift register becomes serial data 44. The third serial clock 42 is synchronized with the first serial clock 38 and the second serial clock 40. That is, it becomes a trigger for inputting the serial data 44 to the serial interface described later in synchronization with the serial data 44.

In FIG. 2, the protocol 48 is set in the 0th substate 4 in the time axis (clock time) direction.
Ten substates including 6a to 9th substate 46j are defined. Here, one clock time corresponds to one clock of the external clock 24, and the frequency division by the frequency divider 50 is omitted for simplicity of explanation. In the 0th substate 46a, the next first substate 46
The time for b (8 clock times) is secured. As the first substate 46b, the chip select 46, the preceding stage 38a of the first serial clock 38, and the second serial clock 4
The zero front stage 40a is set. After 15 clock times, as the second substate 46c,
The preceding stage 38a of the first serial clock 38 and the preceding stage 40a of the second serial clock 40 are set. After one clock time, as the third substate 46d, the chip select 46
To reset. After eight clock times, the subsequent stage 38b of the first serial clock 38 and the preceding stage 42a of the third serial clock 42 are set as the fourth substate 46e. 1
After 5 clock times, as the fifth substate 46f, the subsequent stage 38b of the first serial clock 38 and the previous stage 42a of the third serial clock 42 are reset. In the sixth substate 46g, a time (8 clock times) for the next seventh substate 46h is secured. As the seventh substate 46h, the subsequent stage 40b of the second serial clock 40 and the subsequent stage 42b of the third serial clock 42 are set. After 15 clock times, as the eighth sub-state 46i, the subsequent stage 40b of the second serial clock 40 and the subsequent stage 42b of the third serial clock 42 are reset. After 1 clock time, in order to return to the 0th substate 46a as the 9th substate 46i, a reset signal for resetting a later-described substate management RS-FF 54 is output.

By configuring the protocol 48 in this way, the first sensor 12a and the second sensor 1
A plurality of analog signals input from 2b are AD-converted by the AD converter 16 using the chip select 46 as a trigger to become digital data 20. Then, the first digital data 20a of 16 pulse trains by the first serial clock 38 and the second serial clock 40,
The second digital data 20b is sequentially output in this order, and serial data 44 including a total of 32 pulse trains is generated.

FIG. 3 shows a circuit configuration diagram of the sequencer 34 for realizing the protocol 48. The sequencer 34 includes a binary counter 52, a substate management RS-FF 54, a substate counter 56, a line decoder 58, an upcount timer 60, a timer preset data table 62, and an ADC control logic 64.

The binary counter 52 has an external clock input terminal 52a for inputting the external clock 24 inputted via the external clock input terminal 34b of the sequencer 34, a reset signal input terminal 52b for inputting a reset signal, and an output for outputting the counter value in parallel. A terminal 52c is provided. The clock is input from the external clock 24, counted up by the negation of the clock, and when full count is reached, the set 54a (S) of the sub-state management RS-FF 54 is set to H.
Is output. And when it counts further from full count, it returns to zero (initial value),
Start counting up again. The period when the counter reaches the initial value from the initial value and returns to the initial value again becomes the sampling period of the AD converter 14, and the serial data 44 is periodically output at this period. It is assumed that the sampling period has a clock time sufficiently longer than the time required for the substate counter 56 to go through all the substates. When the reset signal (signal H) is obtained from the microcomputer 88, the count is reset to zero and the count is stopped.
As a result, AD conversion stops.

The sub-state management RS-FF 54 is a flip-flop that stores the signal from the binary counter 52 and resets the store by the output signal of the ninth sub-state 46j of the line decoder 58 and the reset signal from the microcomputer 88 side. Binary counter 5
2 is input from the set 54a (S), the signal H is stored in the output Q54b, the sub-state counter 56 and the upcount timer 60 are made countable, and the signal H is input to the reset 54c (R). And the output 54b (Q) is set to L to return the count values of the sub-state counter 56 and the up-count timer 60 to the initial values. Further, an inverted output 54d (nQ) obtained by logically inverting the output 54b of the substate management RS-FF 54 is an ADC control logic 64 that controls the serial clock 36.
Therefore, when the inverted output 54d (output 54b) is reset, the signal H is output to the reset side. The binary counter 52 and the substate management RS-FF 54 are elements that realize the main state task 82 in an operation flow 80 described later.

As the sub-state counter 56, a counter such as a Johnson counter that does not cause a static hazard is used. The sub-state counter 56 has a carry input terminal 56a for inputting a carry from the up-count timer 60, and an output terminal 56 for outputting a count value counted up with the carry negation as a trigger to the line decoder 58 in parallel.
b. Therefore, the substate counter 56 counts up when it receives a carry from the upcount timer 60 and stops counting when it reaches the maximum value. The number that can be counted is the number of substates as it is. The substate counter 56 is provided with a negative reset 56c (nCR). When the signal at the negative reset 56c becomes L, the count value becomes an initial value, and the reset state is maintained as long as L is maintained. The state counter 56 does not operate. The time until the substate counter 56 counts from the initial value to the maximum value is the time from when the first AD converter 16 and the second AD converter 18 simultaneously perform AD conversion to the generation of the serial data 44. Here, the initial value of the substate counter 56 is 0 and the maximum value is 9, which correspond to the 0th substate 46a to the 8th substate 46j, respectively.

The line decoder 58 has an input terminal 58a for inputting the numerical value indicated by the sub-state counter 56 in parallel, and an output terminal for realizing the 0th sub-state 46a to the ninth sub-state 46j respectively assigned to the numerical value of the sub-state counter 56 ( Q0 terminals 58b to Q9 terminals 58k). The line decoder 58 decodes the numerical value input from the sub-state counter 56, compares the sub-state value obtained by decoding with the sub-state value incorporated in advance, and outputs the sub-state corresponding to the numerical value to the output terminal of the sub-state. The signal H is output. In the present embodiment, the number of substates is 10, and the Q0 terminal 58b to the Q8 terminal 58 are used.
The output shifts to j. Each output terminal is connected to an appropriate position in the ADC control logic 64 and the timer preset data table 62, as will be described later, in order to realize each substate.

The upcount timer 60 receives the external clock 24 input via the external clock input terminal 34b of the sequencer 34 from the external clock input terminal 60e, and receives the external clock 2
A binary counter that counts up with the assertion of 4 (L → H) as a trigger,
Binary data sent in parallel from the timer preset data table 62 can be input as preset data. For this reason, the up-count timer 6
0 is provided with a timer preset data trigger 60a (nLD) and a preset data port 60b (PD) for inputting timer preset data. Further, the counter has a C0 terminal 60c for outputting a carry when the counter reaches a full count. The carry is branched in the middle, one is connected to the sub-state counter 56, and the other is connected to the timer preset data trigger 60a via the inverter 74. Yes. Here, timer preset data trigger 60a
Functions as a trigger at the negate, and the preset data port 60b stores preset data triggered by an assert following the negate. The up-count timer 60 is provided with a negative reset 60d (nCR). When the signal at the negative reset 60d becomes L, the count value becomes an initial value, and the reset state is maintained as long as L is maintained. The count timer 60 does not operate. In this embodiment,
The up-count timer 60 can count from 0 to 15 (decimal number) with 4 bits, and generates a carry when 15 is counted.

Note that the negative resets 56c and 60d of the sub-state counter 56 and the up-count timer 60 are connected to the output 54b of the sub-state management RS-FF 54. It is reset when a reset signal from 88 is input.

The timer preset data table 62 receives the output from the line decoder 58 and outputs the timer preset data, which is binary data, to the up-count timer 60 in parallel for each bit. In the present embodiment, the timer preset data table 6
2 has three timer preset data (1 clock, 8 clocks, 15 clocks),
Preset data relating to the clock time required for the next state is output to the upcount timer 60. Timer preset data (15) 62a includes Q2 terminals 58d and Q5.
Connected to terminal 58h and Q8 terminal 58j, the timer preset data (15 clocks) of the next substate is output to the upcount timer 60, respectively. At this time, the upcount timer 60 generates a carry in one clock time. The timer preset data (1) 62b is connected to the Q1 terminal 58c, the Q4 terminal 58f, and the Q7 terminal 58i,
The timer preset data (1 clock) of the next substate is output to the upcount timer 60. At this time, the upcount timer 60 generates a carry in 15 clock times. The timer preset data (8) 62c is connected to the Q0 terminal 58b, the Q3 terminal 58e, and the Q6 terminal 58h, and outputs the timer preset data (8 clocks) of the next-stage substate to the upcount timer 60, respectively. At this time, the upcount timer 60 generates a carry in 8 clock times. The substate counter 56, the line decoder 58, the upcount timer 60, and the timer preset data table 62 described above are elements that realize the substate task 84 in the operation flow 80 described later.

The ADC control logic 64 is a flip-flop composed of RS-FFs 66, 68, 70, 72 that generate a chip select 46, a first serial clock 38, a second serial clock 40, and a third serial clock 42 according to the substate of the sequencer 34. The chip select 46, the first serial clock 38, the second serial clock 40, and the third serial clock 42 are set and reset according to each substate from the line decoder 58.

The chip select 46 is output from the inverted output 66a (nQ) of the RS-FF 66, and is output from the chip select output terminal 34c. The set 66b (S) has a Q1 terminal 58.
b is connected, and the Q3 terminal 58e is connected to the reset 66c (R).

The first serial clock 38 is output from the output 68a (Q) of the RS-FF 68, and is output from the first serial clock output terminal 34d. The set 68b (S) is connected to the Q1 terminal 58c and the Q4 terminal 58f, and the reset 54c (R) is connected to the Q2 terminal 58d.
And Q5 terminal 58g.

The second serial clock 40 is output from the output 70a (Q) of the RS-FF 70 and is output from the second serial clock output terminal 34e. The set 70b (S) is connected to the Q1 terminal 58c and the Q7 terminal 58i, and the reset 70c (R) is connected to the Q2 terminal 58e and the Q8 terminal 58j.

The third serial clock 42 is output from the output 72a (Q) of the RS-FF 72 and is output from the third serial clock output terminal 34f. The set 72b (S) is connected to the Q4 terminal 58g and the Q7 terminal 58i, and the reset 72c (R) is connected to the Q5 terminal 58g, Q
Eight terminals 58j are connected. Further, the resets 66c, 68c, 70c, 72c are connected to the inverted output 54d (nQ) of the substate management RS-FF 54.

Here, since the chip select 46 uses the negation as a trigger, the terminal for storing the set / reset is connected to the inverted output 66a. The terminals for storing the set / reset of the first serial clock 38, the second serial clock 40, and the third serial clock 42 are the output 68a, the output 70a, and the output 72a, respectively, but the external clock 24 is inverted by the inverter 76. Since each of the serial clocks is connected to the external clock 24 by the NAND circuit 78, each serial clock is synchronized with the external clock 24 without being inverted. By performing such wiring, each substate of the protocol 48 can be realized. The ADC control logic 64 is an element that realizes the ADC control logic task 86 in an operation flow 80 described later.

A flow of the AD conversion system according to the present embodiment based on the above configuration will be described. FIG.
FIG. 5 shows an operation flow 80 of the AD conversion system 10. FIG. 4 is an overall view of the operation flow 80, and FIG. 5 is a partial detailed view of the operation flow 80. AD conversion system 10 according to the present embodiment
In the operation flow 80, the sampling frequency is determined and the entire sequencer 34 is set to O.
A main state task 82 for N / OFF control, a sub-state task 84 for determining a sub-state of the AD conversion system 10, and an analog signal input from a plurality of sensors at the same time A
It is classified into ADC control logic task 86 for D conversion.

First, in the main state task 82, the reset signal from the microcomputer 88 is set to L to release the reset, and the binary counter 52 is activated to count up until the full count is reached (first step 82a). When full count is reached, the signal H is stored in the output 54b of the substate management RS-FF 54, the reset of the substate counter 56 is released, and the substate task 84 is started (second step 84a). When a signal indicating a substate from 0 to 8 is input to the line decoder 58 from the substate counter 84, the line decoder 58 decodes the substate (third step 84b), and a timer preset related to the next substate. Data is prepared (fourth step 84c), and this state is maintained until the upcount timer 60 outputs a carry (fifth step 84d).

Next, in the third step 84b, the ADC control logic task 86 starts (sixth step).
Step 86a), the chip select 46, the first serial clock 38, the second serial clock 40, and the third serial clock 42 are set / reset according to each substate (the 0th substate 46a to the 8th substate 46i). (Seventh step 86b). When the up-count timer 60 issues a carry in the sub-state task 84, timer preset data relating to the next-stage sub-state is loaded into the up-count timer 60 (the eighth count).
In step 84e), the substate counter 56 counts up to advance the signal indicating the substate (9th step 84f). When the signal indicating the sub-state advances, the line decoder 58 decodes the sub-state again (third step 84b) on condition that the sub-state is not full count (tenth step 84g), and then the fourth step 84c.
The fifth step 84d is performed. Then, in the ADC control logic task 86, the previous ADC control logic task 86 is terminated (11th step 86c), and the ADC control logic task 86 related to the advanced substate is started (seventh step 86b).
). When the eighth substate 46j is executed, the ADC control logic task 86 ends (11th step 86c).

On the other hand, in the substate task 84, the substate counter 56 is set to the full count (
When the numerical value becomes 9), the line decoder 58 decodes the sub-state related to the full count (the ninth sub-state 46j) (the twelfth step 84h), executes the eighth sub-state 46j (the thirteenth step 84i), A reset signal is output to the state management RS-FF 54, and the sub-state task 84 ends (14th step 84j). When the main state task 82 reaches full count again, the substate task 84 is resumed (second step).

In the above flow, when the reset signal (signal H) is input to the main state task 82 during the execution of the substate task 84 and the ADC control logic task 86, the substate management RS-FF 54 is also reset. Stops immediately. At this time, the substate counter 56 and the upcount timer 60 are also reset, and the substate becomes the 0th substate 46a.

FIG. 6 shows a schematic connection diagram between the AD conversion system 10 and the microcomputer 88 according to the present embodiment.
As shown in FIG. 6, the clock of the microcomputer 88 is input to the AD conversion system 10 as the external clock 24. The AD conversion system 10 includes a parallel interface 9
0 and a serial interface 92 are connected to the microcomputer 88. Here, the serial interface 92 converts the serial data 44 into parallel data 94 and outputs it, or vice versa.

The interrupt terminal 90a (not used in this embodiment) and the chip select 90b (nCS) of the parallel interface 90 are connected to the control bus 96 of the microcomputer 88. The digital input output 90c (Dio) is connected to the data bus 98 of the microcomputer 88, and can input / output parallel data 94. The other end of the digital input output 90 c is connected to the reset input terminal 34 a of the sequencer 34 of the AD conversion system 10. As a result, the reset signal from the microcomputer 88 is sent to the data bus 98.
And to the AD conversion system 10 through the parallel interface 90. At this time, if the reset signal is H, the sequencer 34 is reset, and if it is L, the reset is canceled and the sequencer 34 is activated.

Interrupt terminal 92a of serial interface 92 and chip select 92b (nCS
) Is connected to the control bus 96 of the microcomputer 88, and the digital input output 92c (Dio) is connected to the data bus 98. On the other hand, the clock input 92 d (SCK) of the serial interface 92 is connected to the third serial clock output terminal 34 f of the sequencer 34, and the input terminal 92 e (RxD) is connected to the output terminal of the AND circuit 32 in the sequencer 34. As described above, the third serial clock 42 and the serial data 44 output from the sequencer 34 of the AD conversion system 10 are generated from the clock of the microcomputer 88 and are thus synchronized with the clock of the microcomputer 88. Therefore,
Since this connection is not synchronous start (asynchronous), it is not necessary to configure a sequencer (not shown) that adds and processes a start bit and an end bit for measuring the synchronization timing before and after the serial data 44. The serial data 44 consisting of 32 pulse trains is the third data.
Each time the serial clock 42 is triggered and stored in a register (not shown) in the serial interface 92, an interrupt can be made from the interrupt terminal 92 a of the serial interface 92 to the control bus 96. .

On the other hand, a memory (not shown) in the microcomputer 88 is connected to the data bus 98 in parallel. A CPU (not shown) in the microcomputer 88 saves the address of an instruction being executed at that time in a save area of a memory (not shown) each time the interrupt is received, and a chip select 92b of the serial interface 92. Is selected by negation, the parallel data 94 is transferred via software, a memory address is assigned to the parallel data 94 and stored in a memory (not shown) in the microcomputer 88 (polling). Thereby, the microcomputer 88 is A
Since only the ON / OFF operation of the D conversion system 10 is performed, and the sequencer 34 performs the output of signals related to each task of AD conversion, the microcomputer 88 can be executed concentrated on other tasks, and the reliability of the entire system Will improve.

Further, when the microcomputer 88 has a DMA (direct memory access) controller (not shown), a CPU (not shown) in the microcomputer 88 gives the DMA controller (not shown) the control authority of the control bus 96. I have yielded. Therefore, when the interrupt is received, the DMA controller (not shown) designates a transfer destination address in the memory (not shown) via the control bus 96, and the data bus 98 is opened to the serial interface 92.
It is written in a memory (not shown) in one clock time. Therefore, C in the microcomputer 88
The PU (not shown) does not need to perform a polling operation for data transfer, and can spend more time for processing other tasks.

When a reset signal (signal H) is input during AD conversion, the binary counter 52 of the sequencer 34 is reset to the initial value, and the binary counter 52 is not counted up as long as there is a reset signal. In this case, incomplete data (not shown) that is not completed as serial data 44 may be input to the serial interface 92. Therefore, in the microcomputer 88, if there is unfinished data (not shown) in the serial interface 92 after resetting, the software may be configured to discard it without storing it in the memory (not shown). However, if serial data 44 is being stored in a memory (not shown) at the time of reset, software that does not interrupt the work may be configured. And serial data 4
4 is stored and the serial data 44 in the serial interface 92 has not been transferred to the memory (not shown), the task of the microcomputer 88 is stopped as it is, and the software for initializing the settings of the microcomputer 88 at the next startup is configured. do it.

A host PC 102 is connected to the microcomputer 88 via the second serial interface 100. The host PC 102 is a terminal having an application for operating the AD conversion system 10 via the microcomputer 88. The input terminal 100a (RxD) of the second serial interface 100 is connected to the serial data output terminal 102a of the host PC 102, and the output terminal 100b (TxD) is the serial data input terminal 102b of the host PC 102.
It is connected to the. The interrupt terminal 100c and the chip select 100d (nCS) are connected to the control bus 96. Digital input output 100e (Dio
) Is connected to the data bus 98 and can input / output parallel data 94. The host PC 102 inputs / outputs serial data 104 but is driven by a clock independent of the microcomputer 88. Therefore, data communication between the host PC 102 and the second serial interface 100 is performed in a synchronous step (asynchronous).

The host PC 102 outputs the serial data 104 to the microcomputer 88 side, and the microcomputer 88 decodes the contents so that the microcomputer 88 can turn AD conversion ON / OFF. In order to do this, when the serial data 104 related to the instruction from the host PC 102 to the microcomputer 88 is stored in a register (not shown) of the second serial interface 100 and an interrupt request is made from the interrupt terminal 100c, the microcomputer 88 is connected to the chip. Select 100d
Is selected by negating, and the software of the microcomputer 88 can be configured to acquire the parallel data 94 through the digital input output 100e and store it in the memory (not shown) of the microcomputer 88.

Further, the host PC 102 can logically correct, for example, AD conversion sensitivity and offset on the application. Similar correction processing can be executed by the software of the microcomputer 88 to output correction data to the host PC 102. For example, the correction value such as sensitivity correction or offset is calculated for the data acquired via the serial interface 92, the FIR filter is used to downsample the data that can be recognized as the serial data 104 on the host PC 102 side, and the host PC 102 The software of the microcomputer 88 may be configured to select the chip select 100d of the second serial interface 100 on the side with the negate and output the data.

Therefore, according to the AD conversion method and the AD conversion system 10 according to the present embodiment, the sequencer 34 embodying this instead of the microcomputer 88 simultaneously AD-converts analog signals and obtains the digital data 20 obtained by AD conversion. Is converted to serial data 44 and output. Therefore, the microcomputer 88 only needs to command the sequencer 34 to be driven / stopped, and the AD conversion method and the AD conversion system 10 reduce the ratio of the software resources of the microcomputer 88 that require conventional AD conversion work to the system. AD
Since the conversion is performed by the sequencer 34 which is hardware, the AD conversion method in which the sampling jitter is reduced and the AD is reduced compared to the case where the microcomputer 88 performs AD conversion through software.
The conversion system 10 is obtained.

Further, since the sequencer 34 uses the microcomputer 88 that generates a clock by crystal oscillation as a clock source and can perform sampling without the influence of the task in the microcomputer 88, sample jitter can be reduced. The serial data 44 is stored in the microcomputer 8
8 is output in synchronization with the clock of 8 and parallelized when input to the serial interface 92. Therefore, the microcomputer 88 that transmits and receives parallel data can easily acquire the parallelized data without any processing. Therefore, it is possible to reduce the ratio of software resources for taking in data from the AD converter 14 of the microcomputer 88 to the system. In particular, when the microcomputer 88 uses direct memory access, a CPU (not shown) in the microcomputer 88 does not need to perform data acquisition work, so software resources for fetching data from the AD converter 14 are included in the system. Minimize the share.

It is a schematic diagram of an AD conversion system concerning this embodiment. It is a figure which shows the protocol of the sequencer of the AD conversion system which concerns on this embodiment. It is a circuit block diagram of the sequencer of the AD conversion system which concerns on this embodiment. It is a whole figure of the operation flow of the AD conversion system concerning this embodiment. It is a partial detailed view of the operation flow of the AD conversion system according to the present embodiment. It is a connection outline figure with an AD conversion system concerning this embodiment, and a microcomputer.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... AD conversion system, 12 ... Sensor, 14 ... AD converter, 16 ... First AD converter, 18 ... Second AD converter, 20 ... Digital data, 22 ... ... AD
Serial clock for conversion, 24 ... External clock, 26 ... Shift register, 28 ...
... first shift register, 30 ... second shift register, 32 ... OR circuit, 34 ...
... Sequencer, 36 ... Serial clock, 38 ... First serial clock, 40
......... Second serial clock, 42 ......... Third serial clock, 44 ......... Serial data, 46 ......... Chip select, 48 ......... Protocol, 50 ......... Divider, 52 ...
... Binary counter, 54 ... Sub-state management RS-FF, 56 ......... Sub-state counter, 58 ...... Line decoder, 60 ... Up-count timer, 62 ...... Timer preset data table, 64 ... ... ADC control logic, 66 ......... R
S-FF, 68 .... RS-FF, 70 ... RS-FF, 72 ... RS-FF, 74
......... Inverter, 76 ...... Inverter, 78 ......... NAND circuit, 80 ......... Operation flow, 82 ......... Main state task, 84 ......... Sub-state task, 86 ...... Control logic task, 88 ......... Microcomputer, 90 ......... Parallel interface, 92 ......... Serial interface, 94 ......... Parallel data, 96 ......... Control bus, 98 ......... Data bus, 100 ......... Second serial interface, 10
2 ... Host PC, 104 ... Serial data.

Claims (4)

A simultaneous sampling type AD conversion method in which a plurality of analog signals are simultaneously AD-converted by microcomputer control, converted into serial data, and output.
A simultaneous sampling AD conversion method characterized in that a plurality of digital data obtained by the AD conversion are sequentially output, and a sequence control for periodically outputting the plurality of digital data as serial data is periodically performed. . The sequence control is driven using a clock output from the microcomputer as a clock source,
The simultaneous sampling AD conversion method according to claim 1, wherein the serial data is input to a serial interface in the microcomputer. A simultaneous sampling type AD conversion system that simultaneously converts a plurality of analog signals by AD and converts them into serial data under microcomputer control.
A plurality of AD converters that AD convert a plurality of input analog signals using a chip select as a trigger and output a plurality of digital data;
A plurality of digital data connected to the plurality of AD converters, storing the plurality of digital data, and using the plurality of serial clocks as triggers, sequentially outputting the plurality of stored digital data to output serial data A shift register;
Connected to the AD converter and the shift register to generate the chip select;
A simultaneous sampling AD conversion comprising: a sequencer that periodically performs sequence control that outputs the chip select to the plurality of AD converters and outputs a serial clock to each of the plurality of shift registers. system. 4. The sequencer generates the serial clock based on an external clock input from a microcomputer, and the serial data is input to a serial interface of the microcomputer in synchronization with the serial clock. A simultaneous sampling AD conversion system described in 1.

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