JPS59167151A - Data transmission system - Google Patents

Abstract

PURPOSE:To enhance the transmission speed by performing the A/D converting operation of a terminal processing device LCU periodically independently of the calling timing due to a central controller CCU to write digital data in a register and reading out this data at the calling timing. CONSTITUTION:In each of terminal processing devices 30-32, a received signal RXD inputted from a transmission line 20 is supplied to a synchronizing circuit 102 and is synchronized with clocks from a clock generator 107, and a clock which is synchronized in the start-stop system with clock components of the received signal RXD is given to a control circuit 101, and then, the control circuit 101 generates a control signal to read a data part of the received signal into a shift register 104 serially. Meanwhile, the address assigned to a pertinent terminal processing device is preliminarily given to an address comparing circuit 103, and this address and data read into a prescribed bit position of the shift register 104 are compared with each other by an address comparing circuit 103; and if they coincide with each other, data in the shift register 104 is transferred to an I/O buffer 105 and is given to an external device.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an analog data transmission system, and more particularly to an analog data transmission system suitable for an integrated wiring system using multiplex transmission in an automobile or the like.

[Prior art]

For example, automobiles have electrical components such as various lamps and motors,
In addition, a large number of electrical devices such as various sensor actuators for automobile control are arranged, and the number of these devices is increasing as automobiles become more electronic.

For this reason, if each of these many electrical devices was wired independently as in the past, the wiring would be extremely complex and large-scale, resulting in increased cost, weight, and space. This causes serious problems such as an increase in the amount of energy used or mutual interference.

Therefore, as one method to solve these problems, it has been proposed to simplify the wiring by using a multiplex transmission system that can transmit a large number of signals with a small number of wiring lines.

FIG. 1 shows an example of an in-vehicle integrated wiring system using such a multiplex transmission method.

The system shown in Figure 1 uses an optical fiber cable OF as a signal transmission path, and uses a central control unit [CCU (hereinafter simply referred to as CCU)
It's called CU. In addition, @CentralCont
rol Unit) and multiple terminal processing units [LCU(
Hereafter, I will refer to it as LCU(・U).This is also engineering local.
(abbreviation for Control Unit) and a common optical signal channel.
An optical branch connector OC is provided at the branch point F.

The CCU is installed at a suitable location, such as near the dashboard of an automobile, and is designed to control the entire system.

LCUs are distributed in a predetermined number and placed near electrical devices installed in large numbers inside the car, such as various operation switches 8W, indicators such as meters M, pipes L, sensors S, etc. .

A photoelectric conversion module A10/E that bidirectionally converts optical signals and electrical signals is provided in the CCU and each LCU car optical fiber (the part that connects with the cable OF).

The CCU is equipped with a microcomputer and has a data communication function using serial data, and each LCU
is a communication processing circuit CIM (hereinafter simply referred to as CIM).
ace Adaptor) is provided, and the CCU is L
By sequentially selecting one of the CUs and exchanging data with that LCU, and repeating this process, multiplex transmission via a single channel/channel optical fiber cable OF is possible. Complex and large-scale in-vehicle wiring can be simplified.

By the way, some electrical devices installed in automobiles operate using analog data. For example, there are various sensors necessary for engine control.

Therefore, in LCUs that are equipped with electrical devices as external loads that operate using analog data, an analog-to-digital converter (hereinafter simply referred to as A/D) is installed to convert the analog data from the external load into digital data. It is necessary to import it into CIM.

At this time, in general, the A/D conversion operation requires the A/D conversion operation.
/D, there necessarily exists a specific time delay, and this time delay varies within limits that depend on the operating conditions and is not necessarily constant (1°. As a result, the above-mentioned conventional In the system, CCU
If the LCU that attempts to transmit its own data to the CCU in response to a call from the CCU contains an external load of analog data.

During the above-mentioned A/D' time delay, data cannot be transmitted to the CCU side, and the start of data transmission is delayed by the time required for A/I) conversion operation, resulting in a data transmission speed There was a drawback that the value decreased.

[Purpose of the invention]

The object of the present invention is to eliminate the above-mentioned drawbacks of the prior art, and to
It is an object of the present invention to provide a data transmission system that can maintain a sufficiently high data transmission rate regardless of the conversion time required for D.

[Summary of the invention]

In order to achieve this object, the present invention periodically performs a conversion operation by the A/D of the LCU at a predetermined timing, regardless of the timing of the call by the CCLI, and stores the digital data obtained by this in a register. The timing is defined as the point at which the digital data kL'f written in this register is output and transmitted.

[Embodiments of the invention]

Embodiments of the data transmission system according to the present invention will be described below with reference to the drawings.

FIG. 2 is an overall block configuration diagram showing one embodiment of the present invention, where 10 is a central processing unit (corresponding to the CCU in FIG. 1), and signal transmission line (corresponding to the optical fiber cable OF in FIG. 1) is shown in FIG.
, 30 to 32 are terminal processing units (corresponding to the LCU in Figure 1)
, 40 is an A/D, and 51 to 58 are external loads. In addition,
In this embodiment, a case is shown in which an electrical signal transmission path is used as the signal transmission path. Therefore, a photoelectric conversion module is not required for the central processing unit 10 and the terminal processing devices 30 to 32. The contents of the processing devices 30 to 32 are essentially only CLM.

A central processing unit 10 including a computer (microcomputer) is connected to each terminal processing unit 32 through a transmission line, and transmits data to external loads 51 to 58 made up of electrical devices such as various sensors, lamps, actuators, and motors. The transmission of data and the acquisition of data from these are performed using a multiplex transmission method.

At this time, external loads 57, 58 such as sensors that output analog data are coupled to the terminal processing unit [32] via the A/D 40, so that a digital data transmission operation can be performed.

Any signal transmission path can be used as long as it is bidirectional, and not only electrical signal transmission paths but also optical signal transmission systems using optical fibers can be used, and the communication method using this is the so-called half-duplex method. In response to a call from the central processing unit 10 to one of the plurality of terminal processing units 30 to 32, data is exchanged between one of the terminal processing units and the central processing unit 10 via the transmission path. It is designed to be performed alternately.

Because of this half-duplex multiplex transmission, data sent from the central processing unit 10 is given an address indicating its destination, and the address given to the lost data is attached to the data sent from the central processing unit 10. Only one of the terminal processing devices that recognizes that the address is its own responds.

In this way, depending on the data sent from the central processing unit 10 with an address attached, only one of the terminal processing units that understands the address and determines that it is its own responds. By sending its own data to the central processing unit [10], the above-mentioned half-duplex data transmission operation can be obtained.

In addition, in this embodiment, the functions of each terminal processing device [30 to 32] are consolidated into a specific one, and the functions of each terminal processing device [30 to 32] are
This makes it easy to integrate 2 into LSI (large scale integrated circuit).

The specific functions at this time include the above-mentioned data transmission function, that is, the function necessary for multiplex transmission using the half-duplex method, and the A/D 4 attached to each terminal processing device.
There are two types of functions that control external devices such as Q.

As a result, it becomes possible to dedicate the data transmission function. For example, when applied to an integrated wiring system in a car, the above-mentioned half-duplex method is used, and the required transmission speed and number of address bits are adjusted. You can do things like decide accordingly.

Furthermore, in this multiplex transmission system, as mentioned above, the LSI
It is possible to utilize the functions of the terminal processing device that has been developed as it is and to apply it to the central processing unit 10. As a result, it is possible to use a general-purpose computer (such as a microcomputer) that does not have a data transmission function as the central processing unit 1o. The central processing unit 10 can be constructed by simply combining this with the above-mentioned LSI terminal processing 33, and the load on the software web required for the computer of the central processing unit 1o can be completely reduced. The versatility of the terminal processing device can be increased. In this case, some of the functions of the terminal processing device M33 combined with the central processing unit remain inactive, but this is unavoidable.

Next, FIG. 3 shows a rough block configuration of an embodiment of each terminal processing device 30 to 32, in which the received signal RXD input from the transmission path is supplied to the synchronization circuit 102,
The clock from the clock generator 107 is synchronized, and the control circuit 101 is given a clock that is start-stop synchronized with the clock component of the received signal RXD.
1 generates a control signal and inputs the data portion of the received signal into the shift register 104 serially.

On the other hand, the address comparison circuit 103 is given an address previously assigned to the terminal processing device, and the address comparison circuit 103 compares this address with the data read into a predetermined bit position of the shift register 104. , shift register 10 only when both match.
The data in 4 is transferred to I10 buffer 105 and given to external equipment.

Further, the control circuit 101 includes a counter that is incremented by a clock, generates a sequential control signal, and generates a received signal R.
,
Data to be transmitted from an external device to the central processing unit 10 is prepared in the shift register 104 as serial data. Then, it is read out serially from this booter shift register 104 and sent to the transmission line side as a transmission signal TXD.

At this time, since the address attached to the received signal RXi) is attached to the transmitted signal TXD and sent out, the central processing unit 10 takes in this transmitted signal TXLI because it matches the address sent by itself. This completes the transmission and reception of one cycle's worth of data using the half-duplex method.

In this way, the central processing unit @io sends data to the next terminal processing device, and by repeating this, data is periodically exchanged with each of the plurality of terminal processing devices 30 to 32, and multiplex transmission is performed. becomes possible.

The A/D control circuit 106 is the terminal processing device 3 in FIG.
This is to provide the necessary A/D 4Q control function when used as A/D 4Q.
Digitize by D4Q and shift register 10
4. It functions to provide the control functions necessary to incorporate Note that the details will be described later.

Next, FIG. 4 is a block diagram showing one embodiment from the terminal processing device side, in which the same or equivalent parts as in FIG. 3 are given the same reference numerals. A synchronous circuit for generating a clock asynchronously synchronized with the signal RXD, 302 a counter for generating two-phase clocks φ and φY, 303 a counter for sequential control, 3
04 is a sequence decoder that generates various control signals from the output of the counter 303; 305 is an abnormality detector; 306
307 is a 4-bit comparator v-p for address comparison, 308 is an error detection circuit, and 31o is a composite gate consisting of two AND gates and one NOR gate. ,3
11 is an exclusive or gate for error detection; 3
12 is for data transmission), 313.31
4 is a tri-state buffer, 32o is an 8-bit shift register, 321 is a 32-bit register, 322 is a 32-channel gate, 323 is a counter for A/D control, 324 is a signal generation circuit for A/D control, 325 is A
/D channel selection counter. Note that the shift register 104 has 5 bits (24 bits + 1 bit).
The I10 buffer 105 is of 14 baud (14 bits).

These terminal processing devices 30 to 33 (hereinafter referred to as CIM) are designed to operate by selecting one of a plurality of operation modes, and when used as CIMs 30 to 31 in FIG. 2, the DIO mode is selected. Also, CIM in Figure 2
When used as CIM 32, AD mode is selected, and when used as CIM 33 in FIG. 2, MPU mode is selected. Note that this mode selection will be described later.

First, when the DIO mode is selected, the A/D control circuit 106 does not operate, and the shift register 10 at this time
The data contents of A4 are as shown in FIG. 5, and 6 bits from 40 to M5 are not used, and 14 bits from A6 to 419 are allocated to data DIO of I10 buffer 105. Then, 4 bits from 420 to A23 are assigned to address data ADDR, and A24
is assigned to the start bit. Note that the number of bits allocated to DIO data is 14 because the I10 buffer 105 is of 14 bits.

Moreover, for this reason, in the CIM according to this embodiment, I10
The maximum number of external loads that can be connected to the buffer 105 is 14.

The data transmission method according to this embodiment includes a start-stop interval,
This is called a bidirectional, reverse double-feed force type.
It is now transmitted using the o zero ) method,
The transmission waveform is as shown in FIG. In other words, CCU side f) CI Mcal) L CU@NOCI
If the frame that transmits MK Qi fi is the receive frame, and conversely, the frame that is transmitted from the LCU side to the CCU side is the transmit frame, both the receive frame and the transmit frame are 74.
Therefore, one frame is 148 bits. Both the received frame and the transmitted frame have the same frame structure. 1 There are 6 pits of 0" at the beginning, followed by a start bit consisting of 1 bit of 1" for start-stop synchronization, and Subsequently, 24-pit reception data (Xi) or transmission data TXD is transmitted in the NRZ signal format, and the reason why these data are inverted data is to check for transmission errors.

As already explained, in this embodiment, multiplex transmission is performed using the half-duplex method, so the data k of the received frame
1. The first 4 bits of XD contain the address data Al) of the LCU to which the CCU is calling at that time.
DB is attached as shown in FIG. 5, and in response to this, the same address data ADDR is attached to the first 4 bits of the data TXD of the transmission frame sent out from the LCIJ and transmitted. Note that transmission frames from the LCU side are only transmitted by calls from the CCU side or by CUK, so even if an address is not added to the transmission data TXD, the data can be sent to any LCU in CCU 01lJ.
You can immediately determine whether it is from

Therefore, it is not necessary to attach an address to the data TXD of the transmission frame, and the leading four bits of the data TXi) may be data such as (oooo) that does not match any address of the LCU.

Now, returning to FIG. 4, the CIM address will be explained.

As already explained, in this embodiment, l, C on the CU side
Different 4-bit addresses are assigned to each IM, and data is multiplexed in a half-duplex system based on these addresses.

An input 4 which serves to assign this address to each CIM is connected to a comparator 307.
The inputs of the book are 2° to 2a, and the data ADDR'1i-ADD'R3 to be given to these inputs allows the CIM to be
address is specified. For example, in order to specify the address of the CIM as '10'', address data Al
)D RO=O1ADD■ also 1=1, ADDR2=0,
It is sufficient to set ADDR3=1 and input (1010) to inputs 2° to 23. In addition, in this example,
Data IIO” is ground potential, data @1” is power supply voltage V
Since it is represented by cc, for the address "10", the input 2° 2m is grounded and the inputs 21.28 are connected to the power supply.

Incidentally, in this embodiment, address inputs 2° to 23 are also input to the address decoder 306, and the directionality of the I10 buffer 105 is controlled by its output. As a result, when an address is specified, it is determined which of the 14 terminals of the I10 buffer 105 will serve as the data output port. In this embodiment, the address directly corresponds to the number of output votes.

Therefore, if the address is set to 1o'', 1o out of the 14 terminals of the I10 buffer will be controlled as output ports, and the remaining 4 will be controlled as input ports.

Although not shown in FIG. 4, the output of the address decoder 306 is also given to the sequence decoder 304 of the control circuit 101, so that as shown in FIG.
The operating mode of this CIM can be switched. That is, in this embodiment, the CIM whose address is set to ``θ'' is in MPU mode, the CIM whose address is set between 1'' and N D N is in DIO mode, and the CIM whose address is set to ``θ'' is in DIO mode. The CIMs set to any of the above are respectively operated in the AD mode.

Next, the functions of the control circuit 101 and the synchronization circuit 102 will be explained.

In this embodiment, as already explained in connection with FIG. 6, the start-stop synchronization method is adopted, and therefore, when data is transmitted in both the reception frame and the transmission frame, the δ bit is always set to 0'' before the start of data transmission. is inserted, and then "1" data is inserted as a 1-bit start bit (FIG. 6).

Therefore, the synchronization circuit 301 detects the rising edge of the start bit after the '0' of the δ bit that exists at the beginning of the received frame, and synchronizes the bits of the internal clock. The operation is performed by an internal clock that is bit synchronized with the timing of .

The counter 302 generates two-phase clocks φ- and φM from internal clocks synchronized by the synchronization circuit 302. As a result, the clocks φ and φ become phase-synchronized with the reception data RXD that will be input thereafter.

The sequence counter 303 receives a signal representing the rising edge detection timing of the start bit from the synchronization circuit 302,
It is set to the state of a specific count value, e.g. count 0, and then the clock φ1 or φ.

is counted by. Therefore, the control procedure for the entire CIM can be determined based on the count output, and by looking at the count value, the CI at any timing can be determined.
It is possible to know which step M is in.

Therefore, the count output of this counter 303 is supplied to the 7-cence decoder 304, which is necessary for the operation of this CIM.
- a control signal, e.g. l-LXMODO1'rXMODE
, READ, 5HIFT, and other internally required control signals are generated by the sequence decoder 304. In other words, this embodiment uses a sequence control system using two clocks φ1φ, and therefore, by decoding the output of the counter 303, all necessary controls can be performed.

Next, a description will be given of an operation for determining whether or not the transmitted data RXD is data for the CIM, that is, whether or not the call by transmitting the 7 received frames from the CCU is for itself.

As already explained, one input of the comparator 307 is given the address data from the inputs 2° to 28, and the other input is given the address data from the Q of the shift register 104.

Data from bit to Qts bit is given. Then, this comparator 307 outputs a match signal MYAD only when both input data match.
Outputs D. Therefore, the received data RXD is input to the shift register 104, and its Q. Bit to Q2.
The output signal MYA D D of the comparator 307 is output at the timing when the address data (see Fig. 5) attached to the beginning of the data (data up to the bit) is stored.
)I, and at that time this signal MYADI)R is "
1”, it means that the data 14XD is for you and that the call from the CCU is for you.

Therefore, the control signal COMPM is sent to the error detection circuit 308.
OL)E, and at the above-mentioned predetermined timing, the signal M
It takes in Y A D D R, and when it is 0'', it generates an output INITIAL, which causes the sequence counter 303 to count o.
The operation of the entire CIM is restored to prepare for the next data transmission to be input. On the other hand, when the signal MYADDR is 1'', the error detection circuit 308
Since no IAL occurs, the operation of the CIM continues according to the current count value of the sequence counter 303.

Next, the transmission error detection operation will be explained.

In this embodiment, as already explained with reference to FIG. 6, data transmission by the inversion two-pass method is adopted, and transmission errors can be detected using this method. And for this reason, the first Q of shift register 104. Data is applied from the bit and the last Qtt bit to an exclusive OR gate 311, and the output of this gate 311 is applied as a signal ERROR to an error detection circuit 308.

The sequence decoder 304 outputs a control signal RXMODE to open the lower gate of the composite gate 310 during the transmission period of the received signals LXD and RXD (FIG. 6) following the start bit, thereby decoding the data from the transmission path. is input to the shift register 104 as a serial signal 8I. At this time, since the composite gate 310 includes a NOR gate, the data supplied from the transmission line side is inverted and input to the shift register 104.

Therefore, when the data for <24 pits following the start bit of the received frame (FIG. 6) is input to the shift register 104, the Q of this shift register 104 is input. Bit to Q2. Inverted data RXD of received signal RXD is written in the portion up to the bit. Next, as is clear from FIG. 6, after the U-bit reception signal RXD is transmitted, the inverted signal ratio
When D is transmitted, it is inverted by composite gate 310 to become data RX D, which begins to be input to shift register 104 as serial signal SI. As a result, the Q of the shift register 104. At the timing when the first bit of the inverted signal RXD is inverted and input, the previously written inverted data of the first bit of the received signal XD is transferred to the Qta bit of the shift register 104 and the second bit of the inverted signal RXD is The data of the th bit is Q. At the timing written in , the data of the second bit of the received signal RXD is transferred to the Q and 4 bits, and as a result, the inverted signal RXD is serially written into the shift register 104 one bit at a time. At each bit timing of Q! of the shift register 104, 4 bits and Q. Data of the same bit of the received signal RXD and the inverted signal RXD are always written in corresponding bits.

By the way, as described above, the data of the Q0 bit and the Q14 pit of the shift register 104 are input to the two inputs of the exclusive OR gate 311. Therefore, if no error occurs during the transmission of the received signal RXD and the inverted signal RXD, the output of the exclusive OR gate 311 is always 1'' during the transmission of the inverted signal RXD.
It should be.

This is because the corresponding bits of the received signal 1 (XD and its inverted signal RXD) should always have inverted ``1'' and 0'', and as a result, the input to the gate 311 will always show a mismatch. This is because it only occurs when there is an error in transmission.

Therefore, the error detection circuit 308 monitors the signal F3RROR during the valid bit period when the inverted signal RXD is being transmitted, and when it reaches the 0'' level, the signal INITIA
If L is generated, an error detection operation can be obtained. Note that, as a method for handling transmission errors in such a data transmission system, there is a known method in which when a transmission error is detected, it is repaired to obtain correct data. However, in this embodiment, the transmission error is Once detected, the data reception operation for that frame is canceled at that point and preparations are made for data reception for the next frame, thereby simplifying the configuration.

Next, the overall operation of data transmission in the DIO mode of the embodiment shown in FIG. 4 will be explained with reference to the timing chart shown in FIG.

φ and φ are two-phase clocks output from the counter 302, which are generated based on an internal clock by a clock oscillator included in the synchronous circuit 301.

On the other hand, RESET is a signal supplied to this CIM from the outside, and is the same as the reset signal of the microcombi controller, etc., and is supplied to every CIM in Figure 2, and is supplied to each CIM when the power is turned on. When necessary, it is supplied from an external reset circuit and initializes the entire transmission system.

When the initialization is completed, the count value of the sequence counter 303 is set to 0, and from there it is incremented by the clock φ. No operation is performed until the count value reaches 5. When the count value reaches 5, the IDLE signal and RXENA signal are generated, the CIM enters the idle state, and sequential control based on the count value of the sequence counter 3030 is stopped. , the tri-state buffer 313 opens and becomes ready for signal reception. At this time, the reason why the signal reception is not enabled after initialization until the count value of the sequence counter 303 reaches 5 is because the synchronization circuit 301 synchronizes the pace and the received signal RXD is clear. This is because since it is a bit, it is necessary to provide an 'O' period of at least δ bits.

When the idle state is entered in this way, the sequence counter 30
2 is a clock φ8. The sequence decoder 304 continues to advance by counting φ輔, but the sequence decoder 304
It remains in the state where NITIAL is generated and is simply waiting for the reception signal to be input. For this purpose, 5 bits O'' are added to the beginning of each received frame and transmitted frame, as shown in FIG.

In this way, the idle state is entered, and now, at time 1.
-1- Assume that a received signal RXD is input. Then, a 1-bit start bit is attached to the beginning of this signal box XD. Therefore, the synchronization circuit 301 detects this start bit and establishes bit synchronization of the internal clock.

Therefore, from now on, data 1-LXD, RXD, clock φ, and φ1 until the transmission operation for one frame is completed.
Synchronization with the internal clock is maintained by the stability of the internal clock, providing an asynchronous function.

When the start bit is detected, the sequence counter 30
3 is set to count output 0 (hereinafter, the output data of this counter 303 will be denoted by S, for example, in this case, it will be expressed as SO), and as a result, the sequence decoder 304 stops the control signal I DLR and outputs the control signal RXMODE. occurs. Further, in parallel with this, a shift pulse SHIFT is supplied to the shift register 104 in synchronization with the clock φ.

As a result, the received signal XD of the missing bit following the start bit and the inverted signal 1 (XD (Fig. 6) are transferred from the transmission line side to the composite gate) 310 and are sequentially shifted one bit at a time to the shift register 104 as serial data. It is being written. At this time, the first spit received signal RXD
is data 1 (XD
are sequentially written into the shift register 104 in serial, so during the valid bit period following the start bit, that is, when the sequence counter 303 reaches 824 from 81, the shift register 105 changes from Qo bit to Q8.
Data RX in which the received signal RXD is inverted to bits up to
D will be written. At this point, the control signal COMPMODB is output at the next rising edge of the 825 clock φyo, and the error detection circuit 308 functions. Then, in this state, the inverted signal RXD starts to be input, and as a result, data XD, which is the inverted version of the inverted signal RXD, is serially written from the Q bit of the shift register 105. Shift register 104 from 81 to 824 from K
The data RXD written to Q3. of the shift register 104 starts from the first bit. The bit positions are overflowed one bit at a time until the sequence counter 303 reaches from 825 to 848. On the other hand, in parallel with this, data XD based on the inverted signal RXD is serially written through the Q0 bit position of the shift register 104 from the first bit, and during this time, the exclusive OR gate 311 and the error detection circuit Detection of transmission errors at 308 proceeds as described above.

Therefore, when the sequence counter 303 reaches 848, the same data RXD as the received signal RXD is written as is from the Q0 bit to the Q□ bit of the shift register 104. Therefore, at this timing of 848, the output signal MYADDR of the comparator 307
The above-mentioned address is confirmed by checking whether the data RXD just received is addressed to the user, that is, whether the call from the CCU at this time is addressed to the user. A judgment will be made. If a transmission error or address mismatch is detected while the sequence counter 303 is between 825 and 848, the error detection circuit 308 generates the control signal INITIAL when the value reaches 848. At this point, the sequence counter 303 is set to SO and returns to the pre-idle 6-bit state, canceling all reception operations for this received frame and preparing for input of the next signal.

Now, when no transmission error was detected while the sequence counter 303 was between 825 and 848, and no address mismatch was detected, that is, when the count reached 848, the error detection circuit 308 did not generate the INITIAL signal. Sometimes, the sequence decoder 304 generates the control signal WRITESTH at this point of 848. As a result, at the time of 848, I N I'
Either the f' I A L signal or the WRITE8TB (@ sign) is generated, and when neither a transmission error nor an address mismatch occurs, the former occurs, and when either a transmission error or an address mismatch occurs, the latter occurs. Each will be output.

Now, when the control signal WRITE:8TB is output at time 848, the data in the shift register 104 at that time is written in parallel to the buffer 105, and as a result, the data brought from the CCU by the received data RXD is The data is supplied from the output port of I10 buffer 105 to any of external loads 51-56. Note that at this time, it is operating in DIO mode, so
As explained in FIG. 5, a maximum of 14 pits from the Q6 pit to the Q, · bit can be transmitted as data RXD, and how many bits of these can be
As already explained, whether a port is an output port or not is determined by the address.

When the process reaches 848, all the processing of the received frame is completed, and the processing of the transmitted frame starts from the next step 849 (FIG. 6).

First, no processing is performed from 849 to 872.

This is for start-stop synchronization of the CIM on the CCU side, and has the same purpose as the operation in the period set before IDLE in the processing of the 7 received frames described above.

873, the control signal Pa is output from the getance decoder 304, which causes the shift register 104 to perform a parallel data reading operation, and the I10 buffer 10
Data given from any of the external loads 51 to 56 is input in parallel to the input ports 5. The number of bits of data read at this time is the remaining number of bits of the 14-bit I10 buffer 105 after subtracting the bits used as output ports in processing the received frame. For example, as mentioned above, set the address of this CIM to 10.
When set to , the number of output ports is 10, so the input port is 4 bits at this time.

Writing parallel data to the shift register 104 requires one bit of the shift clock 5HIFT along with the signal PS, so after raising the signal SP with the clock φ of 873, a shift pulse synchronized with the clock φ of 874 is generated. 5HIFT is supplied before the rise of the control signal TXMODE.

Also, at this time, as is clear from FIG. 6, a start bit must be added before the transmission data TXD, and an address must be added to the first four bits of the data TXD. For this reason, although it is omitted in FIG. 4, the signal P
Q of the shift register 104 only during the period when S is occurring.
When t<Bit 2, the signal representing data “1” is set and Q
! Input 2° to 21 from o bit to Qta bit
Address data is supplied from each.

In this way, after the DUMMY state from 848 to 873 sets the data "'0" transmission period for δ pits necessary for start-stop synchronization, when entering 874, the control signal TXMOD
E rises, thereby entering the TX (transmission) state. The generation of this signal TXMODE activates the upper AND gate of composite gate 310, and furthermore, AND gate 31
2 is activated. As a result, the data of the Qz+ bit of the shift register 104, that is, the data @1'' serving as the start bit, is sent to the transmission channel hole through the AND gate 312. Then, it is generated in synchronization with the clock φ from S75 onward. The contents of the shift register 104 are shifted one bit at a time to the next stage by the shift clock 5HIl'T, and are sent from the Q!4 bit through the AND gate 312 to the transmission channel hole.
The transmission of the transmission signal TXD including the start pitch (FIG. 6) is performed.

On the other hand, in parallel with such DSO reading from the shift register 104, the data read from the QCs bit cell is inverted through the composite gate 310 and supplied to the serial input of the shift register 104. As a result, Q of the shift register 104 starts from S75. Transmission data T written from bit to Qzs bit
XD is sent out bit by bit to the transmission line side by the shift clock 5HIFT, and is inverted and sequentially written from the Q0 bit of the shift register 104 as serial data SI.

Therefore, when all the transmission data TXD written in the cells of bits Q0 to Ql of the shift register 104 during the period in which the control signal PS is being generated has been read out, this Q. The cell from bit to Ql and bit receives inverted data TXD instead of the previous transmission data TXD.
will be stored.

Therefore, after the reading of the transmission data TXD is completed, the shift register 104
Reading of the inverted data TXD starts from then, and the inverted data TXD is sent out to the transmission line side following the transmission data TXD as shown in FIG.

When 5122 is reached in this way, the Q of the shift register 104 is
Since all the inverted data from bit 1 to bit Q0 has been read out, the control signal TXMODE falls, the supply of the shift clock SHIFT is also stopped, and the transmission state ends. Then, the control signal INITIAL is generated by the next clock φ following 5122, the sequence counter 303 is set to SO, and the CIM is set to idle A/(■D
LE) Return to the previous signal reception ready state.

Therefore, according to this embodiment, half-duplex multiplex communication using start-stop synchronization, bidirectional, and inverted two-way transmission is performed between CCU and LC.
This can be done reliably with U, and the transmission lines can be consolidated.

Next, the operation of the CIM according to this embodiment in the AD mode will be explained.

As mentioned above, the electrical devices that should exchange data with the CCU via the CIM include various sensors and external loads 57 and 58 (Fig. 2) that output analog signals. In the example, it includes an A/I) control circuit 106 and also has a function of controlling an external A/D 40. The operating mode of the CIM at this time is the AD mode.

Now, as already explained, in this embodiment, the operation mode is set by the address data to be applied to the inputs 2° to 2s, and the address data corresponding to the AD mode is the 7th As shown in the figure′
E" and 'F".

Next, when this CIM is set to operate in the AD mode, the contents of the data stored in the shift register 104 are as shown in FIG.
Up to 8 bits can be connected to external load 5 via A/D 4Q.
For storing AD data imported from A8.7.58, etc.
2 bits of 49 are for storing AD channel data,
As a result, for DIO data, from 1610 to 19
10 bits. Note that the rest is the same as in the L)IO mode. In addition, the AD channel data at this time is data for specifying a channel when a multi-channel A/D is used, and in this example, a 4-channel one is used as the A/D 40, so 2 It allocates bits.

The shift register 320 is an 8-bit one, and an external A
It stores the digital data (A/D converted from analog data given from an external load 57, 58, etc.) serially taken in from the A/D 4Q and enables parallel reading, as well as the A/D 40 channels. A counter 325 for specifying the channel selection data also receives the provided 2-bit channel selection data in parallel, serially outputs it, and supplies it to the A/D 40.

The register 321 has 32 pits, and the A/D 40 has 8
Since it is a bit and has 4 channels, 8
Used as a bit 4 channel register, A'/
Data taken in from D40 in 8 bits is accommodated for each channel.

The gate 322 also has 32 bits (corresponding to the register 321).
It is controlled by the AD channel data (Fig. 5) read from the Q, pitted Q, and bit cells of the shift register 104 for data transmission, and one of the channels in the register 321 is selected. Then, the 8-bit data is transferred to shift register Q. It serves to write AD data (FIG. 5) into the Q7 bit cell.

The counter 323 is incremented by the count of the clock φ, and functions to sequentially and cyclically control the operation of the entire A/D control circuit 106.

The A/D control code generation circuit 324 includes a decoder for decoding the output of the counter 323 and a logic circuit, and functions to generate various control signals necessary for the operation of the entire A/D control circuit 106.

Next, the overall operation of this A/D control circuit 106 will be explained.

In this embodiment, the control proceeds sequentially in response to each count output of the callan p323, and the number of steps is G, from count output O (this is called SO) to count output 26 (this is called S). One cycle of control is completed, and data for one channel of A/l) 40 is taken into the register 321.

First, when one cycle of control starts, the channel selection counter 325 is incremented by the signal INC, and the output data of the counter 325 is sequentially (0, 0) → (0, 1) → ( 1,0)
→ (1, 1) → (o, o).

The output data of this counter 325 is transferred to the shift register 32.
It is written in parallel to the first two bit positions of 0, and then output as serial data AD8I (A/L).
40.

In parallel, the output data of the counter 325 is also supplied to the register 321 via a decoder (not shown), and 8 bits of the corresponding channel of the register 321 are selected.

Next, the A/D 40 selects a corresponding analog signal according to the channel selection data inputted as serial data AD8I, converts the analog data into digital data, and then outputs it to the shift register as 8-bit serial data AD80. 320 and stored in this shift register 320.

Thereafter, the 8-bit digitally converted data AD stored in this shift register 320 is read out in parallel at a predetermined timing, and the 8-bit data AD of a predetermined channel of the register 321 selected in advance by the output data of the counter 325 is read out in parallel at a predetermined timing. , and one cycle of control operation is completed.

In this way, for example, the output data of the counter 325 is (0,
0), the analog data on channel 0 of the A/D 40 is digitized and stored in the 8 bits of channel O of the register 321, and then the counter 323 is reset to SO, and the counter 323 is reset to SO in the next cycle. Proceeding to operation, counter 325 is incremented to its output data &'! (0, 1), and this time the analog data of channel 1 is digitized and stored in the register 32.
It is accommodated in 8 bits of 10 channels.

Therefore, according to this embodiment, the A/D control circuit 106
The data acquisition operation from the Kyoru A/D 40 is performed timing-wise independently of the data transmission processing by the sequence counter 303 and the sequence counter 304, and the data of each channel of the register j1321 is stored in 4 cycles of A.
It is refreshed once per D control operation, and the analog data input to the four channels of A/D 4Q is always prepared in the register 321 as 8-bit digital data for each channel. become.

Therefore, now the received signal RXD is input from the transmission path,
Assume that the address data attached to it is for this CIM. Note that the address data at this time is 0E" or F", as already explained.

Then, since the format of the data written to the shift register 104 at the time when the input of the received frame is finished (848 in FIG. 8) is the AI) mode in FIG.

A 2-bit signal for channel selection is stored in the Q0 bit and the Q0 bit. This person D channel data is then output at 848 when signal WRITEESTB is generated, thereby selecting one of the four channels of gate 322.

As a result, when the signals P8 and 5HIFT are generated at 573 (FIG. 8), Q, ', Q of the shift register 104 among the four channels of the register 321 are generated.

Only the AD data of the channel selected by the two bits is read out and written into the 8-bit portion from bit Q to bit Q of shift register 104.

And this is the transmission state after 874 and the transmission signal TXI
) and will be transmitted to the CCU.

Incidentally, in this embodiment, as described above, AD data is always prepared in the register 321, regardless of the reception process of the received signal (LXD) and the subsequent transmission process of the transmission signal TXD.

Therefore, in this embodiment, no matter what timing the received signal RX D addressed to itself appears, the transmission signal 'I' X D using AI) data can be immediately transmitted. The transmission process is affected by the operation of t#
There is no risk that the transmission speed will decrease due to the time required for the A/D conversion operation.

In this embodiment, the A/D 4Q is externally attached when converting the CIM into I and SI, thereby reducing costs when making the CIM more general-purpose.

In summary, as explained in FIG. 2, in this embodiment, depending on the mode setting, one type of CIM can be used as LCU30-31, LCU32, or CCUlo CI
It can also be used as an M33.

However, in this case, if the A/D is built in, the CI
When used as M2O, 31, 33, it becomes wasteful, and moreover, when it is generally applied to an automobile integrated wiring system, the number used as CIM32 is more likely to be used as other CI M2O, 31, 33. Since the number of A/Ds is smaller than the number of CIMs, there is not much merit in having A/Ds built into all CIMs. Therefore, the A/D is externally attached.

However, as it is clear from Figure 4, because the A/D is externally connected, four connection terminals are required for the external A/D 40, and when it is converted into an LSI, the terminal pins are There is a risk that the number will increase.

Therefore, in one embodiment of the present invention, when the CIM is set to AD mode, four of the fourteen ports of the I10 buffer 105 are switched as connection terminals for the A/D 40. That is, in the embodiment of the present invention, the I10 buffer 105 has 14 ports, and as is clear from FIG.
When set to IO mode, all ports may be used as input/output ports, but when in AD mode, only 10 ports are used at most, and 4 ports are used as DIO ports.
It is left unused for data input/output. Therefore, these remaining 4 boats were switched to Ai) mode, and A/
If used as a terminal pin for D 4Q, A/L
) is externally attached, there is no increase in the number of terminal pins, and when integrated into an LSI, versatility increases and costs can be reduced.

Next, an embodiment in which the present invention is embodied using a well-known IC is shown in FIGS. 9 and 10.

First, in FIG. 9, according to this embodiment, a shift register 104 and a 320t-HD 14035,! :, L”1
It is composed of a known IC, and the register 321 is HI)14.
It is composed of an IC known as 175. Also,
The gate 322 is composed of an IC called MD245, and
/D40 is #PD7001 C,! - It consists of an IC called Note that a part of the wiring for the shift register 104 and a cell for storing a start bit are omitted.

The 2-bit counter 325 for AD channel selection is 2
It consists of flip-flops (hereinafter referred to as FF) and one exclusive-or gate.

Further, 90 is a 2-bit register consisting of two FFs, which functions to read and hold the data Qa, Q=bibit, of the shift register 104.

Further, 91 and 92 are both decoders using an IC known as K1-ID14556, and the decoder 91 selects one of the gate 3220 channels according to the data in the register 90,
The decoder 92 functions to select the channel of the register 321 according to the channel of the AD data read from the shift register 320.

The functions of the Nant gate 93 and the negative logic AND gates 94 to 97 will be described later.

Next, Figure 10 shows an IC known as HD14163.
A counter 323 configured with a decoder and a plurality of FFs.
This figure shows an A/D control signal generation circuit 324 composed of gates. Note that the control signal 5HIFT in FIGS. 9 and 10 is applied to the sequence decoder 304 (
4), and is a signal shown as A D S HIF T in FIG. 4. Also, regarding other signals, A
The signals to which D is added are shown in FIGS. 9 and 10, with AD removed.

FIG. 11 is a timing chart in the AD mode of the embodiment shown in FIGS. 9 and 10.
The operation will be explained using the timing chart shown in the figure.

As already explained, in this embodiment, the A/D control circuit 1
The control operation by 06 is performed sequentially based on the count data of the counter 323, and one cycle ends when the output data of the counter 323 changes from 0 to 2, and this is cyclically repeated. Therefore,
Hereinafter, the count data of this counter 323 is assumed to be 826 from SO.

Now, this @Figure 11 is the first reset (signal in Figure 8)
LESHT) is completed, and begins when the output state of the counter 323 becomes SO due to the first clock φ operation after reset.

When this SO occurs, a signal INC is generated, whereby the AD channel selection counter 325 is incremented (stepped by 1). Meanwhile, in parallel with this, a chip select signal C8 is generated. This Iki No. C8 is determined by the specifications of A/D 40, and A/D
In the A/D in this embodiment, A/D conversion is performed when No. 4i C8 is at No. 40 level, and A/D conversion is performed when No. 4i C8 is at Low level. The operation is stopped and a state is reached in which it is possible to read the A/D transformation results and to specify the channel. However, S
The signal that is at high level at O is A/D.
40, and has no particular relation to the above operation. In the period following this SO, no control operation is performed until the time reaches 87, so that the time necessary for initializing the A/D 40 is provided.

After the initialization of the A/D 40 is completed, the control signal A/DCHLOAD is generated at S7, and the output data of the counter 323, that is, the data specifying the analog input channel, is first transferred to the shift register 320. Inputs are input in parallel to ,D,. Next, at 88.89, the shift clock 5) LIFT is outputted to the first @ order, which causes the shift register 320
The data written to Del, D, of serial data SI
as the Q8 bit and feeds it into the A/D 40. On the other hand, at this time, the shift clock C8K is supplied to the A/D 40, so that the A/D 4
Serial data 8I is written to the shift register in Q. Note that this is the μP used in this example.
This is based on the specifications of A/D 40 called D7001C.

When S9 ends in this way, the analog input channel is designated for A/l)4Q, and the analog data of that channel can be A/D converted.

Therefore, when entering S10, the signal C8 is raised to a high level, thereby causing the A/D 40 to start the A/D conversion operation. When the A/D conversion operation starts in this way, A/D 4
The signal EOC/So from 0 rises to high level.

By the way, the period required for the conversion operation by this A/D 40 shows considerable variation depending on the conversion conditions.
As already explained, it is not necessarily constant, and although the standard value of the conversion time in the A/D 40 of this embodiment is 140 μs, the upper and lower limits have a certain range and are undefined. ing.

Therefore, during this period, the signal WAIT is generated and the counter 3
The decoding operation of the output data of No. 25 is stopped for a while. Therefore, during this period, as is clear from Fig. 11, the signals C8 and WAIT are only at level 7 and level 11C, and the sequential control is temporarily stopped up to this point.
The counter 323 simply continues counting.

In this way, a predetermined time determined by the A/D 40 and the A/D conversion conditions has elapsed, and when the conversion operation by the A/D 40 is completed, the signal EOC/80 falls to a low level.

Therefore, the A/D control circuit 324 generates internal signals EOCI and EOC2 in response to the fall of the signal EOC/80.
The signal WAIT falls to start the decoding operation, and the signal BEGINE is generated to input the data D0. of the counter 324. Load the high level of the signal goc2 into D, , D3, and set the count output of this counter 323 to 8.
Return to 11. In other words, as is clear from Figure 11, 8
When the conversion operation of the A/D 40 starts at step 10, the decoding operation of the output data of the counter 323 is stopped by the signal WAIT, the sequential control of the A/D 40 becomes a standby state, and the control proceeds to the next step. As a result, in preparation for the completion of the A/D 4Q conversion time, which is an undefined time, the output data of the counter 323 is reset to 811 at that point when the conversion operation is completed, and the control for the next step is started. I am trying to move forward.

After the analog data to digital data conversion operation by the A/D 40 is completed and the output data of the counter 323 becomes 811, the digital data reading operation for the A/D 40 does not begin until the output data of the counter 323 reaches 818. . This is due to the specifications of the A/D 40; the A/D of this embodiment requires a certain amount of time after the signal Hoe/SO falls;
The periods up to 8 correspond to this.

After 818, the shift clock SCK and 5HIF are output in synchronization with the clocks φ and φ, and 71st-order eight shift clocks SCK and 5HIF are output. First, the data converted into digital data from the shift register in the A/D 40 is sequentially converted into one bit using the shift clock SCK. Then, this signal is written into the 8-bit shift register 320 while being shifted one bit at a time by the shift clock 5HIFT. Therefore, when S26 is reached, A/D
At step 40, all digital data converted from the analog input is completely written into the shift register 320.

When the clock reaches 826, the signal W l'(, I T E 8 T B rises in synchronization with the clock φ1, and the signal E is input from the Nantes gate 93 to the decoder 92. As a result, the decoder 92 outputs its outputs 1t8o to R8 ，
generates a signal to only one of the four outputs of
. The 8-bit data 'fc' to Q is written to the input D0 to one of the channels of the register 321 of the four channels. That is, the decoder 92 is given channel selection data from the 2-bit counter 325,
This determines whether the signal E is applied or generated. On the other hand, the data of this counter 325 is sent to the A/D 40 via the shift register 320, thereby selecting an analog input channel. Therefore, the four channels controlled by the decoder 92 to enable data writing via any of the AND gates 94 to 97.
Each channel of the 8-bit register 321 is always controlled to be writable only when the corresponding digital data of the 4 channels of analog input is written to the shift register 320.

As a result, each time counter 323 increments from SO to 826, one of the analog inputs of A/D 40
One signal is converted to digital data, which is written into the 8-bit portion of the corresponding channel of register 321. After S26, the counter 323 returns to SO again, the 2-bit counter 325 is incremented by the generation of the signal INC, and the data conversion operation for the next channel is started.

In this way, when the operations from SO to 826 of the counter 323 are repeated four times, all the analog inputs of the four channels of A/D 4Q are converted into digital data and written to each of the registers /l/ of the register 321. Furthermore, by repeating this, an operation is obtained in which four channels of data, which are refreshed every four cycles of the counter 323, always exist in the register 321.

Next, the operation of reading data from the register 321 by the shift register 104 will be described.

When the processing of the received frame (FIG. 6) is completed, the data of the Q, , Q, bits of the shift register 104 is given to the register 90 and held there. The data in this register 90 is given to a decoder 91, which outputs kLS when the human power E is supplied. to R8, it is determined which of the signals is generated. Therefore, the control signal RE A D E
When NA is supplied to the E input of the decoder 91 via an inverter, which channel of the 4-channel gate 322 is opened is the reception signal RXD from the CCU side.
It is controlled by the data to be inserted into the bits Q, ,Q, of .

On the other hand, since the 'l gate 22 controls which channel of the data in the register 321 is stored as AD data in the shift register 104, the
The CU can designate the channel of the AD data to be stored and fetched into Qo to Q of the shift register 322 using data inserted into bits Q, , Q, of the received signal RXD.

In this embodiment, due to the sequential operation of the counter 323, the register 321 always has an AD value.
Since the data is prepared, the transmission following the reception of the reception signal RXD (AI at the timing of sending the i signal 'I'XD)
There is no risk of any delay in data capture.

By the way, in this embodiment, the operation of taking in AD data from the register 321 to the shift register 104 upon reception of the reception signal 1 (, Since these operations are performed independently, there are cases where these operation timings coincide, and in this case, the data in the register 321 is disturbed and incorrect data is stored in the shift register 104 as AD data. There is a risk that the data will be transmitted to the CCU.

Therefore, in the embodiment shown in FIG. 9, a Nant gate 93 is provided to inhibit the signal W'I'I'EENA and prevent the signal E from being input to the decoder 92 at the timing when the signal READENA is generated. At the timing when AD data is taken into the shift register 104 from the register 321, refreshing of AD data by the shift register 320 is prohibited.

Therefore, according to this embodiment, it is possible to reduce the possibility of an error occurring when AD data is taken into the shift register 104, and to enable more reliable transmission of AD data.

[Effects of the Invention] 1. As explained above, according to the present invention, A/D converted data can be transmitted immediately, regardless of the time delay required for the A/D conversion operation from analog data to digital data. Therefore, without the drawbacks of the conventional technology, A/D
It is possible to easily provide a data transmission method that can always provide a sufficient transmission speed without reducing the data transmission speed due to the conversion operation.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram showing an example of an in-vehicle integrated wiring system, Fig. 2 is a block diagram showing an embodiment of the data transmission system according to the present invention, and Fig. 3 is an illustration of an embodiment of each terminal processing device. 4 is a more detailed block diagram of FIG. 3, FIG. 5 is an explanatory diagram showing an example of data contents, and FIG. 6 is an explanatory diagram showing an example of transmission waveforms. FIG. 7 is an explanatory diagram showing an example of seventh-word selection, and FIG. 8 is a DIO
FIGS. 9 and 10 are timing charts for explaining the operation of an embodiment of the present invention in mode, and FIGS.
The figure is a timing chart for explaining the operation. 10...Central processing unit, addition...signal transmission line, addition~32...terminal processing unit,...
...Communication control system, 40...A/D (analog-digital converter), 51-58...External load, 101...Control circuit, 102... ...
・Synchronization circuit, 103...Address comparison circuit, 1
04・Song・Shift register, 105・・・・・・Engineer 10
Buffer, 106...A/D control circuit, 107
... Clock generator, 301 ... Synchronous circuit, 302 ... Counter, 303 ...
・Sequence counter, 304... Sequence decoder, 305... Abnormality detector, 306...
... Address decoder, 307 ... Comparator, 308 ... Error detection circuit, 310.
...Compound gate, 311...Exclusive or gate, 312...And gate,
320...Shift register, 321...
・Register, 322... Gate, 323...
... Counter, 324 ... A/D control signal generation circuit, 325 ... Counter. 1st eye lips 2[1 5th eye Qin 6 Condolence 7Ili0

Claims (1)

[Claims] 1. In a data transmission system that includes an analog-to-digital converter and transmits analog information converted into digital information in response to intermittent data transmission requests, the above-mentioned analog-to-digital conversion A control means for periodically performing the conversion operation of the converter at predetermined timings, and a register for accumulating the digital output of the analog-to-digital converter are provided. A data transmission system characterized in that the data transmission method is configured such that the transmission of computerized analog information can be performed immediately in response to the data transmission request. 2. In claim 1, means is provided for controlling the commitment of the digital output of the analog-to-digital converter to the register, and data replacement to the register at the timing of occurrence of the transmission request is prohibited. A data transmission method characterized by being configured to