JPH059840B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to an analog data transmission system,
In particular, the present invention relates to an analog data transmission method suitable for an integrated wiring system for mass transmission in automobiles and the like.

[Background of the invention]

For example, automobiles are equipped with a large number of electrical components such as various lamps and motors, as well as electrical devices such as various sensors and actuators for controlling the automobile, and the number of these devices continues to increase as automobiles become more electronic. It's on.

For this reason, if each of these many electrical devices was wired independently as in the past, the wiring would be extremely complex and large-scale, resulting in increased costs, weight, and space. This causes serious problems such as an increase in the amount of energy used or mutual interference.

Therefore, one way to solve these problems is to simplify the wiring by using a multiplex transmission method that allows the transmission of a large number of signals with a small number of wiring lines. JP-A-58-136149
(No.) and others.

FIG. 1 shows an example of an in-vehicle integrated wiring system using such a multiplex transmission method.

The system shown in Figure 1 uses an optical fiber cable OF as a signal transmission path, and the central control unit CCU
(Hereafter, simply referred to as CCU. Note that this is Central
Control Unit) and multiple terminal processing units LCU
(Hereafter, simply referred to as LCU. Note that this is Local
(abbreviation for Control Unit) is commonly connected by an optical signal channel, and is an optical fiber cable.
An optical branch connector OC is provided at the branch point of OF.

The CCU is installed in a suitable location, such as near the car's dash board, and controls the entire system.

A predetermined number of LCUs are distributed in the vicinity of a large number of electrical devices installed in the automobile, such as various operation switches SW, indicators such as meters M, lamps L, and sensors S.

A photoelectric conversion module O/E that bidirectionally converts optical signals and electrical signals is provided at the portion where the CCU and each LCU are connected to the optical fiber cable OF.

The CCU is equipped with a microcomputer and has a data communication function using serial data.
It's called CIM. Note that this is a Communication
Interface Adapter) is provided, and the CCU is
By sequentially selecting one of the LCUs and transmitting and receiving data to and from that LCU, multiplex transmission via one channel of optical fiber cable OF is possible, which is complicated and requires large amounts of data. It is possible to simplify the large-scale wiring inside a car.

By the way, some electrical devices installed in automobiles operate using analog data. For example, various sensors necessary for controlling the engine are used.

Therefore, in an LCU equipped with an electrical device that operates using analog data as an external load, an analog-to-digital converter (hereinafter simply referred to as an A/D converter) is used.
D) is installed to convert analog data from an external load into digital data and import it into CIM.
It has to be transmitted to the CCU, so
In such an LCU, the CIM used therein requires a control function for A/D.

By the way, various types of A/D are known, and the typical types used in such cases include the sequential comparison type and the integral type. In an A/D type A/D, the conversion result changes depending on the reference voltage and offset voltage applied at that time within the A/D, so these are included in the control functions for the A/D described above. It is necessary to provide an arithmetic processing function to obtain unknown analog input from the reference voltage and offset voltage.

Therefore, in the conventional analog data transmission system, when an integral type A/D is used, the functions required for the CIM increase, and the cost increases when the CIM becomes general-purpose.

[Purpose of the invention]

An object of the present invention is to provide an analog data transmission method that eliminates the drawbacks of the prior art described above and minimizes the increase in processing functions required on the LCU side even if an integral A/D is used. It is in.

[Summary of the invention]

In order to achieve this objective, the present invention is characterized in that all the data necessary for processing analog input data, such as the reference voltage and offset voltage provided by the integral A/D, are encoded and transmitted to the CCU side. shall be.

[Embodiments of the invention]

Hereinafter, the analog data transmission system according to the present invention will be explained in detail with reference to illustrated embodiments.

FIG. 2 is an overall block configuration diagram showing one embodiment of the present invention, and 10 is a central processing unit (CCU in FIG. 1).
20 is a signal transmission line (corresponds to the optical fiber cable OF in Figure 1), 30 to 32 is a terminal processing unit (corresponds to LCU in Figure 1), 40 is an integral type A/
D, 51 to 58 are external loads. Note that this embodiment shows a case where an electrical signal transmission line is used as the signal transmission line 20, and therefore, a photoelectric conversion module is not required for the central processing unit 10 and the terminal processing units 30 to 32. , the contents of the terminal processing devices 30 to 32 are essentially only CIM.

A central processing unit 10 including a computer (microcomputer) is connected to each terminal processing unit 30 to 32 via a transmission path 20, and data is transmitted to external loads 51 to 58 consisting of various sensors, lamps, actuators, motors, and other electrical devices. The transmission of data and the acquisition of data from these are performed using a multiplex transmission method. At this time, external loads 57 and 58 such as sensors that output analog data are
It is coupled to the terminal processing device 32 via the terminal 40, so that a digital data transmission operation can be performed.

The signal transmission line 20 may be of any type as long as it is bidirectional, and any type of signal transmission path such as not only an electrical signal transmission system but also an optical signal transmission system using an optical fiber may be used.
Duplex), in response to a call from the central processing unit 10 to one of the plurality of terminal processing units 30 to 32, data is exchanged between one of the terminal processing units and the central processing unit 10 via the transmission path 20. It is designed to be carried out alternately through

Because of this half-duplex multiplex transmission,
The data sent from the central processing unit 10 is attached with an address indicating its destination, and among the terminal processing units that recognize that the address attached to the data received from the transmission path 20 is its own address. only one of them is responding.
In other words, in response to the data sent from the central processing unit 10 with an address attached, only one of the terminal processing units that understands the address and determines that it is its own responds to it. By sending its own data to the central processing unit 10, the half-duplex data transmission operation described above can be achieved.

Next, FIG. 3 shows an embodiment of each terminal processing device 30 to 32 in a rough block configuration.
The received signal RXD inputted from the transmission path 20 is supplied to the synchronization circuit 102, which synchronizes the clock from the clock generator 107, and provides the control circuit 101 with a clock asynchronously synchronized with the clock component of the received signal RXD. As a result, the control circuit 101 generates a control signal and serially reads the data portion of the received signal into the shift register 104.

On the other hand, the address comparison circuit 103 is given an address previously assigned to the terminal processing device, and this address and the shift register 104
The address comparison circuit 103 compares the data read into a predetermined bit position of the shift register 104, and only when the two match, the data in the shift register 104 is transferred to the I/O buffer 105 and provided to an external device.

Further, the control circuit 101 includes a counter that is incremented by a clock, generates a sequential control signal, and after giving the data according to the received signal RXD to the I/O buffer 105, the control circuit 101 subsequently outputs the data to the I/O buffer 105. to shift register 104
The data to be transmitted from the external device to the central processing unit 10 is prepared in the shift register 104 as serial data. Then, this data is transferred to the shift register 104.
The signal is serially read out from TXD and sent to the transmission line 20 as a transmission signal TXD. At this time, the received signal
Since the address attached to RXD is attached to the transmission signal TXD as it is and sent out, the central processing unit 10 takes in this transmission signal TXD because it matches the address sent by itself, and thereby half One cycle of data exchange using the duplex method is completed.

In this way, the central processing unit 10 sends data to the next terminal processing device, and by repeating this, data is periodically exchanged with each of the plurality of terminal processing devices 30 to 32, and multiplex transmission is performed. It becomes possible. This transmission operation is described in Japanese Patent Application Laid-Open No. 167151/1983 (Patent Publication No. 03-1989) by the present applicant.
It is explained in detail in the application (No. 15866).

The A/D control circuit 106 provides a control function for the integral type A/D 40, which is necessary when used as the terminal processing device 32 in FIG. The analog data from the external loads 57 and 58 is taken in via the integral A/D 40, and the reference voltage and offset voltage during the conversion operation of the A/D 40 are converted into digital codes along with the necessary analog input data, and then sent to the central processing unit. 10.

By the way, in this embodiment, the terminal processing device 30
~33 (hereinafter referred to as CIM) are designed to operate by selecting one of a plurality of operation modes, and when used as CIM30~31 in Figure 2, the DIO mode is selected, and the second
When used as CIM32 in the figure, AD mode is selected, and when used as CIM33 in figure 2,
Each MPU mode is selected. Regarding this mode selection and the transmission operation in each mode, please refer to the above-mentioned Japanese Patent Application Laid-Open No. 58-167151 and Japanese Patent Application Laid-Open No. 60-551 (Japanese Patent Application Publication No. 60-551) also filed by the present applicant.
It is explained in detail in the application (No. 03-12746).

FIG. 4 shows a specific example of the A/D control circuit 106 in the embodiment of FIG. 3, including a part of the shift register 104.
04 is constructed using six 4-bit shift registers called, for example, HD14035, and hereinafter these are simply referred to as SR1 to SR6. On the other hand, the A/D control circuit 106 includes an 8-byte register RG1 (hereinafter simply referred to as RG1), a 3-bit register RG2 (also referred to as RG2), and a 4-bit counter C.
1 to C4 (also C1 to C4) and 4-bit decoders DC1 to DC4 (also DC1 to DC4), and as an integral type A/D 40, for example,
A 6-channel device called MC14447 is used.

Note that RG1 may be configured using, for example, 16 4-bit registers called HD14175, or it may be configured using a register with an appropriate storage capacity.
It may also be configured with RAM or the like. Furthermore, for RG2, an IC called HD14175 may be used, for example.

On the other hand, DC1, which acts as an 8-bit output decoder that specifies the data write position for RG1,
Acts as an 8-bit output decoder that specifies the position of data to be read from DC2 and RG1.
DC3 and DC4 use ICs called HD14556, for example, and provide decode input to DC1 and DC2, as well as C1, which functions as a counter to specify the channel of D/A 40, and an 8-bit counter that counts the integral output of A/D 40. work as
DC2 and DC3 are ICs called HD14163, for example.
You can use

Next, the operation of this embodiment will be explained with reference to the time chart shown in FIG.

C1 operates as a 3-bit counter, and the states of outputs _Q0 to _Q2 cyclically change from 0 to 7 each time a pulse signal INC supplied at a predetermined period is input.

On the other hand, the A/D 40 has 3-bit channel select inputs _A0 to _A2 , and in channel 7 generates an integral output representing the internal reference voltage V _REF .
Channel 0 generates an integral output representing the offset voltage V _OS associated with the integral operation. In the six channels from channel 1 to channel 6, external loads 57, 58 such as various sensors etc.
It is designed to generate integral outputs representing the analog signals inputted to the inputs 1CH to 6CH of the A/D 40, respectively.

Based on the above premise, first, the integration operation by the integration type A/D 40, the digitization of the resulting integration output, and the storage operation for RG1 will be described.

In FIG. 5, it is assumed that channel 7 is selected at time T ₀ when a certain INC pulse is generated. That is, assume that at this point, the outputs Q ₀ , Q ₁ , and Q ₂ of C1 all become "H", and the channel select inputs A ₀ , A ₁ , and A ₂ of A/D 40 all become "H".

On the other hand, slightly prior to the occurrence of signal INC, the signal
LOAD is generated, and C2 and C3 are reset by this.

When the channel selection changes, the A/D 40 first lowers the output RS signal RAMPSTART for a predetermined fixed period _tc , and charges the integrating capacitor with the unknown voltage Vx to be converted during this period _tc . Note that since channel 7 is currently selected, the voltage to be converted at this time is the reference voltage, and therefore Vx=V _REF .

Also, the A/D 40 checks the terminal voltage Vc of the integrating capacitor (also called lamp capacitor),
Outputs the signal COMPOUT that becomes “H” only when it exceeds 0, that is, when Vc>0.
This is becoming more common.

On the other hand, these signals RAMPSTART and
COMPOUT is input to a control signal generation circuit (not shown), and this control signal generation circuit generates a clock pulse signal COUNT only when an AND condition of these signals is satisfied.

Note that the signal INC described above and the signal WRITEENA, which will be described later, are also supplied from this control signal generation circuit (not shown).

Thus, the period t _c elapses and the signal RAMPSTART
When t rises, the integrating capacitor starts discharging, and its terminal voltage Vc becomes at the end of period _tc .
After reaching Vc = Vx = V _REF , it decreases from there. And the terminal voltage Vc of this integrating capacitor
When becomes 0, the signal
COMPOUT returns to “L”. Note that the discharge of the integral capacitor at this time is a constant current discharge. Therefore, the time from when the integrating capacitor starts discharging until its terminal voltage Vc becomes 0 is:
The terminal voltage when it starts discharging, that is, the period during which the signal RAMPSTART is “L” t _c
unknown voltage Vx given at (in this case, Vx
Since the signal COUNT is supplied only during a value t _x proportional to V _REF ), the number of clock pulses contained in this signal ends up being data representing the _{time t} C1, C2 output
When the signal COMPOUT returns to "L", the data of Q ₀ to Q ₇ will indicate a count value representing this time t _x =t _REF .

Next, RG1 is 8 bytes as mentioned above, and the control input ₀ for specifying the write position
~ When a pulse is input to any one of ₇ , it takes in 1 byte of data that was given to data inputs D ₀ to D ₇ at that time and writes it to the memory location specified by the input. In addition to storing it in
When a pulse is input to any one of the control inputs ₀ to ₇ for specifying the read position, 1 byte of data stored in the memory position corresponding to this input is read out, and it is output as data output Q ₀ ~ Works to take out to _Q7 .

Therefore, first, to explain the writing of data to RG1, the signals for inputs ₀ to ₇ that specify the writing position of data to RG1 are given by the decoded outputs of DC1 and DC2, and , these DC
1. The decode input of DC2 is the count output of C1, which is the same as the channel selection signal for A/D 40. Therefore, the designated write position for each byte of this RG1 is determined by the channel of A/D 40. In this embodiment, the channel number of A/D 40 and the control input number of RG1 are matched.

Also, decode output ₀ to DC1 and DC2
The generation timing of RS ₇ is given by the signal WRITEENA, but this signal
As shown in FIG. 5, WRITEENA is generated near the end of each channel selection period, that is, at a time point slightly before each signal INC and earlier than the signal INC.

As a result, the signal INT is generated, channel 7 is selected, and the pulse count data corresponding to the time t _REF appears on the count outputs Q ₀ to Q ₇ of C2 and C3, after which the signal WRITEENA is generated. Then, count data representing this time t _REF will be written to the storage location specified by the control input ₇ of RG1.

After that, when the signal INC shown by is generated, C1
The outputs Q ₀ to Q ₂ of the RG1 all become "0", channel 0 is selected, and during this period, the count data representing the time t _x = t _ps corresponding to the offset voltage Vos of the A/D 40 is input to the control input ₀ of the RG1. is written to the storage location specified by .

Furthermore, when the signal INC expressed by is generated, the count data representing the analog data (voltage) of CH1 of the six channels of analog input of the A/D 40 is written to the storage location specified by the control input ₁ of RG1. rare, less, sequential, signal
Every time INC appears, count data representing the analog voltages of CH2 to CH6 will be written to the corresponding storage location of RG1.

Therefore, according to this embodiment, each time the signal INC appears, count data representing each of the A/D reference voltage, offset voltage, and analog voltages of CH1 to CH6 are written to the corresponding memory locations of RG1. This means that each count value is updated once every eight times the signal INC appears.

Next, reading data from RG1 will be explained.

As explained in FIG.
4 stores the 24-bit data Q ₀ to Q ₂₃ transmitted from the CCU 10 when the LCU including this shift register, for example LCU 32 in FIG. 2, operates in data reception mode. The data format in the shift register 104 is as shown in FIG. 6a, and the Q ₈
The 3 bits from bit to _Q10 contain data for channel selection specified on the CCU side.

On the other hand, as shown in Fig. 4, the output Q ₈ of SR3 ~
_Q10 is connected to the 3-bit RG2 inputs _D0 to _D2 .

Therefore, when the signal WRITESTB is supplied to RG2 at a predetermined time after the reception of one batch of data from the CCU 10 is completed and the 24-bit received data is stored in the shift register 104, the CCU 1
The 3-bit data for specifying the channel transmitted from RG2 is latched to RG2, and its output Q ₀ ~
Appears in Q ₂ .

Then, the output Q ₀ ~ _{Q 2} of this RG2 and the signal
READENA causes DC3 and DC4 to perform a decoding operation, and a channel select signal with the same timing as the signal READENA is generated at one of their eight outputs RS ₀ to RS ₇ , and the read position designation input of RG1 is generated.
Supply a signal to one of _G0 to _G7 .

Therefore, the outputs Q ₀ to Q ₇ of RG1 have signals
At the timing when READENA occurs, it is stored in bits _Q8 to _Q10 of the shift register 104 and
The count data of the channel corresponding to the channel select data transmitted from SR1 to SR6 is read out, and this is read out from SR1 to SR6, which are put into parallel read operation state by the signal READENA.
It is input to the parallel inputs D ₀ to D ₇ of the shift register 104, and is stored in the Q ₀ bit to Q ₇ bit of the shift register 104.
When the LCU32 including 04 enters the transmission mode,
The sixth
It will be transmitted to the CCU 10 in the format shown in Figure b, and as a result, the CCU 10 will
This means that the eight channels of data stored in RG1 of the LCU 32 can be arbitrarily selected and independently captured at any timing.

Therefore, CCU10 is an integral type A/D of LCU32.
By sequentially reading the count data taken in from 40 and stored in RG1 in an updated state, and performing processing according to the following equation, all six channels of analog data can be read.

Vx=V _REF・t _x −t _ps /t _REF −t _ps Here, V _REF is the reference voltage of the integrating A/D 40, so it must be given as a constant in advance. It is something that can be done.

Therefore, if the CCU 10 selects the necessary channel and sets t _x = t _ch1 , the input CH of the A/D 40
1 analog data and t _x =t _ch2 , the analog data of input CH2 can be taken in arbitrarily, and the analog data of channels 1 to 6 can be taken in.

According to this embodiment, part of the processing for obtaining data from the conversion result of the integral type A/D is
It can be provided on the CCU side, and therefore, even when an integral type A/D is used, there is no need to increase the functions required on the LCU side, and the cost increase of the system can be reduced.

By the way, if we look at the reference voltage V _REF and offset voltage Vos of the integral type A/D, these are
does not change that much during operation, and in particular, the reference voltage V _REF often hardly changes. Therefore, the data t _REF and t _ps that represent these data are imported into the CCU when the transmission system is started up, that is, when the engine start switch is turned on when applied to a car, and then stored. After that, the data representing the analog data of each channel may be captured at a frequency lower than that of data t _ch1 to t _ch6 , and the stored data may be updated. It may be possible to import the data into the CCU only when necessary, such as when operating conditions change such as when the temperature changes.

〔Effect of the invention〕

As explained above, according to the present invention, all the data necessary for the conversion operation of the integral type A/D can be transmitted to the CCU side, so that digital data can be obtained from the integral output of the integral type A/D. Some of the necessary processing functions can be placed on the CCU side,
Except for the drawbacks of the prior art, even when an integral type A/D is used, the cost increase of CIM is small, and an analog data transmission system that is useful for lowering system costs can be easily provided.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an example of an in-vehicle integrated wiring system, Fig. 2 is an overall block diagram showing an embodiment of a transmission system to which the analog data transmission method according to the present invention is applied, and Fig. 3 is a terminal processing device. FIG. 4 is a block diagram showing a more specific embodiment of the terminal processing device, FIG. 5 is a time chart for explaining the operation, and FIG.
Figures a and b are explanatory diagrams showing an example of a data format. 40... Integral type A/D, 104... Shift register, 106... A/D control circuit, RS1 to RS6
...4-bit shift register, RG1...8-byte register, RG2...3-bit register, C1-C3...3-bit counter, DC1
~DC4...4-bit decoder.

Claims (1)

[Scope of Claims] 1. In a transmission system that includes an analog-to-digital converter and digitizes the transmission of analog data from the terminal side to the central side, the above-mentioned analog-to-digital conversion is performed at least at the time of starting up the transmission system. The reference voltage and offset voltage of the converter are transmitted as digital data to the central side and stored therein.Then, the integral output of the analog-to-digital converter is transmitted as-is as digital data to the central side, and the central side stores the reference voltage and offset voltage as digital data. An analog data transmission method characterized by a configuration in which data processing is performed using voltage. 2. Claim 1 provides that the reference voltage and offset voltage of the analog-to-digital converter are transmitted to the center side even when a predetermined operating condition is changed. An analog data transmission method characterized by: