JP4805746B2 - ΔΣ A / D converter - Google Patents

Description

  The present invention relates to an A / D converter that converts an analog signal into a digital signal, and more particularly to a multi-input ΔΣ A / D converter that converts a plurality of analog input signals into digital signals.

Conventionally, a ΔΣ A / D converter has been proposed as a high-resolution A / D converter that can reduce aliasing noise and quantization noise by oversampling and noise shaping (for example, Patent Document 1 and Patent Document 2). reference).
FIG. 11 shows the configuration of a conventional ΔΣ A / D converter. The ΔΣ A / D converter includes a ΔΣ modulator 1 that converts an analog input signal into a 1-bit digital signal, and a signal frequency band of the output signal of the ΔΣ modulator 1 that passes through the ΔΣ modulator 1. And a digital filter (LPF) 2 that outputs a 1-bit digital output signal. The ΔΣ modulator 1 is composed of an analog circuit, and the digital filter 2 is composed of a digital circuit.

  The conventional ΔΣ A / D converter shown in FIG. 11 has a problem that digital noise generated in the digital circuit after the digital filter 2 is mixed into the analog input signal. For example, in the case of a controller such as a temperature controller, the sensor output signal is converted into a digital signal by an A / D converter and input to the microprocessor, and the control output is calculated by the microprocessor. When it is away, noise is likely to be mixed into the output signal of the sensor.

  When the conventional ΔΣ A / D converter shown in FIG. 11 is integrated, the digital filter 2 occupies more than half of the chip area. Digital circuits can be easily miniaturized by design rules and the circuit area can be reduced, but analog circuits have a problem that miniaturization is difficult in consideration of noise resistance. Therefore, when the ΔΣ modulator 1 and the digital filter 2 are formed on the same chip as in the conventional ΔΣ A / D converter, it is difficult to optimally design each of the ΔΣ modulator 1 and the digital filter 2. In addition, it is difficult to insulate the ΔΣ modulator 1 from the digital filter 2.

  In order to solve the problems of the conventional ΔΣ A / D converter shown in FIG. 11, the ΔΣ A / D converter is divided into a ΔΣ modulator and a digital filter and formed on different integrated circuits. (For example, refer nonpatent literature 1). According to such an integrated circuit configuration, electrical ground separation can be performed between the ground of the analog module including the ΔΣ modulator and the ground of the digital module including the digital filter. The noise resistance of the converter can be improved.

JP 2000-101523 A JP 2000-244324 A “ADS1204 Data Sheet”, Texas Instruments, [searched July 24, 2006], Internet <http://focus.ti.com/docs/prod/folders/print/ads1204.html>

  According to the integrated circuit disclosed in Non-Patent Document 1, as described above, the ground of the analog module and the ground of the digital module can be separated. However, in the integrated circuit disclosed in Non-Patent Document 1, when a large number of analog input signals are converted into digital signals, it is necessary to provide a number of ΔΣ modulators corresponding to the number of input channels and corresponding output terminals. There is a problem that not only the chip area increases but also the power consumption of the chip increases.

  In the integrated circuit disclosed in Non-Patent Document 1, when a large number of analog input signals are converted into digital signals, the number of signal lines between the ΔΣ modulator and the subsequent digital filter increases. Therefore, when an insulating element is inserted between the delta-sigma modulator and the digital filter and the ground separation is performed by the insulating element, the number of insulating elements is increased and the board mounting area is increased. There was a problem that the disadvantages increased.

  The present invention has been made to solve the above-described problems, and provides a multi-input ΔΣ A / D converter that has excellent noise resistance and can reduce circuit area, power consumption, and cost. With the goal.

  A ΔΣ A / D converter according to the present invention includes a ΔΣ modulator that converts an analog input signal into a 1-bit digital signal, a digital filter that passes only a signal frequency band in the output of the ΔΣ modulator, and a plurality of A switching circuit that selects any one of the input channels, inputs an analog input signal of the selected input channel to the ΔΣ modulator, and generates an identification signal indicating the selected input channel, and the ΔΣ modulation A first insulating element that is provided between the digital filter and the digital filter, converts the output signal of the ΔΣ modulator into a non-electric signal, converts the output signal back into an electric signal, and inputs the signal to the digital filter; A second insulating element that converts the electric signal into an electric signal and inputs the digital signal to the digital module including the digital filter, and the switching circuit and the ΔΣ The analog module ground including the modulator and the digital module ground including the digital filter are separated from each other.

In addition, according to one configuration example of the ΔΣ type A / D converter of the present invention, a clock signal generated by the digital module is converted into a non-electric signal, and then converted back to an electric signal and input to the analog module. The switching circuit sequentially selects any one of the plurality of input channels in synchronization with the clock signal.
In the configuration example of the ΔΣ A / D converter of the present invention, the analog module further includes a rectifier circuit that rectifies the clock signal to generate a power supply voltage of the analog module.
In one configuration example of the ΔΣ A / D converter of the present invention, the first, second, and third insulating elements are photocouplers or transformers.

  According to the present invention, by separating the ΔΣ modulator and the digital filter into different modules, for example, instead of routing the signal line of the analog input signal input from the sensor to the ΔΣ modulator, the digital output of the ΔΣ modulator Since the signal line can be extended, it is possible to suppress noise from being mixed into the analog input signal. Further, in the present invention, by mixing the ground of the analog module including the ΔΣ modulator and the ground of the digital module including the digital filter, it is possible to suppress noise from the digital module to the analog input signal. Further, according to the present invention, transmission / reception of a signal between the ΔΣ modulator and the digital filter is performed via the first insulating element, thereby further suppressing noise from the digital module to the analog input signal. Furthermore, in the present invention, the ΔΣ modulator and the digital filter are separated into different modules, so that an optimum design can be performed for each of the analog module and the digital module. In the present invention, the identification signal is transmitted and received between the digital module and the analog module via the second insulating element, so that the multi-channel ΔΣ A / D converter converts the digital module to the analog input signal. Noise can be suppressed. In the present invention, since the input channel is switched using the switching circuit, it is not necessary to provide a ΔΣ modulator and a digital filter for each input channel, and the input channels can be shared. In the present invention, the number of first insulating elements provided between the ΔΣ modulator and the digital filter can be reduced by this sharing. Therefore, according to the present invention, the circuit area, power consumption, and cost can be reduced as compared with the conventional ΔΣ A / D converter in which a ΔΣ modulator needs to be provided for each input channel. Further, in the present invention, since the identification signal is transmitted from the analog module to the digital module, the processing means such as a CPU that performs predetermined processing based on the digital output signal of the digital filter has a plurality of digital output signals. It is possible to identify from which input channel the input signal is.

  In the present invention, the clock signal is transmitted and received between the digital module and the analog module via the third insulating element, so that the multi-channel ΔΣ A / D converter converts the digital module to the analog input signal. Noise can be suppressed.

  In the present invention, the analog module power circuit can be simplified by providing the analog module with a rectifier circuit that rectifies the clock signal to generate the power voltage of the analog module. Cost can be reduced.

[First Embodiment]
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a ΔΣ A / D converter according to a first embodiment of the present invention.
The ΔΣ A / D converter according to the present embodiment sequentially selects any one of a plurality of input channels CH1, CH2, CH3, and CH4, and outputs an analog input signal of the selected input channel. A multiplexer (MUX) 10 serving as a switching circuit for generating an identification signal SYNC indicating the selected input channel and selection timing, a programmable gain amplifier (PGA) 11 for amplifying an analog input signal output from the multiplexer 10, and a programmable gain A ΔΣ modulator 12 that converts an analog input signal output from the amplifier 11 into a 1-bit digital signal, a setting circuit 13 that sets an input channel selected by the multiplexer 10, and a setting circuit that sets the gain of the programmable gain amplifier 11 14, multiplexer 10 and program Among the output signals of the ΔΣ modulator 12, the multiphase clock circuit 15 that generates the multiphase clock signals φ 1, φ 2, bar φ 1, bar φ 2... Required by the mable gain amplifier 11 and the ΔΣ modulator 12. A digital filter (LPF) 20 that removes quantization noise of the ΔΣ modulator 12 by passing only the signal frequency band and outputs a 1-bit digital output signal, and a synchronization that generates a CH synchronization signal from the identification signal SYNC The signal generation circuit 21, the synchronization clock generation circuit 22 that generates a synchronization clock from the identification signal SYNC, the ΔΣ modulator 12 and the digital filter 20 are electrically insulated from each other, and the output signal of the ΔΣ modulator 12 is not An insulating element 30 that converts the signal into an electric signal and then converts it back into an electric signal and inputs it to the digital filter 20, the multiplexer 10, and the synchronization signal generation circuit 21 and the synchronous clock generation circuit 22 are electrically insulated from each other, and the identification signal SYNC is converted into a non-electric signal and then converted back into an electric signal and input to the synchronous signal generation circuit 21 and the synchronous clock generation circuit 22. And an insulating element 31.

  FIG. 2 is a block diagram showing one configuration example of the ΔΣ modulator 12. The ΔΣ modulator 12 includes an arithmetic unit 200 that subtracts an output signal of a D / A converter described later from an analog input signal input from the programmable gain amplifier 11, an integrator 201 that integrates an output signal of the arithmetic unit 200, A quantizer 202 that quantizes the output signal of the integrator 201 with one bit, a delay circuit 203 that delays the output signal of the quantizer 202 by a predetermined timing, and a D / D that converts the output signal of the delay circuit 203 into an analog signal A converter 204 is provided.

The multiplexer 10, the programmable gain amplifier 11, the ΔΣ modulator 12, the setting circuits 13 and 14, and the multiphase clock circuit 15 are configured by analog circuits and are mounted on the analog module 100.
The digital filter 20, the synchronization signal generation circuit 21, and the synchronization clock generation circuit 22 are configured by digital circuits and are mounted on the digital module 101.

Examples of the insulating elements 30 and 31 include a photocoupler and a pulse transformer.
A photocoupler is an insulating element that converts electricity → light → electricity by converting an input signal into light by a light emitting element such as a light emitting diode and converting the light into an electric signal by a light receiving element such as a phototransistor.
The pulse transformer is an insulating element that converts an electric signal into a magnetic change on the primary side and converts the magnetic change into an electric signal on the secondary side, and performs conversion of electricity → magnetic change → electricity.

Next, the operation of the ΔΣ A / D converter of this embodiment will be described. FIG. 3 is a timing chart for explaining operations of the multiplexer 10, the synchronous clock generation circuit 22, and the digital filter 20.
The plurality of input channels CH1 to CH4 are sequentially switched by the multiplexer 10. The setting circuit 13 sets which of the input channels CH1 to CH4 is used.

  The analog input signal output from the multiplexer 10 is amplified by the programmable gain amplifier 11. The gain of the programmable gain amplifier 11 is set by the setting circuit 14. Control such as sequential switching of the ΔΣ modulator 12, the multiplexer 10, and the programmable gain amplifier 11 is performed by a multiphase clock circuit 15. The output signal DO of the ΔΣ modulator 12 shown in FIG. 3A is passed to the digital filter 20 in the digital module 101 via the first insulating element 30.

  The identification signal SYNC indicating the switching timing of the multiplexer 10 in the analog module 100 is output at the rising edge when the multiplexer 10 selects the input channel CH1 as shown in FIGS. 3 (A) and 3 (B). The identification signal SYNC is passed to the synchronization signal generation circuit 21 and the synchronization clock generation circuit 22 in the digital module 101 via the second insulating element 31.

  Since the number of channels used in the analog module 100 is known to the digital module 101, the synchronization clock generation circuit 22 and the synchronization signal generation circuit 21 of the digital module 101 are used by using the identification signal SYNC transmitted from the analog module 100. Thus, it is easy to generate a reproduction clock and a CH synchronization signal. For example, when four channels CH1 to CH4 are used, the synchronous clock generation circuit 22 generates a reproduction clock at a frequency four times the identification signal SYNC (FIG. 3C). On the other hand, the synchronization signal generation circuit 21 generates a CH synchronization signal indicating which input channel is selected from CH1 to CH4 according to the identification signal SYNC.

  The digital filter 20 identifies from which channel of the input channels CH1, CH2, CH3, and CH4 each bit of the output signal DO of the ΔΣ modulator 12 is based on the reproduction clock and the CH synchronization signal. In this way, by using the identification signal SYNC from the analog module 100, the output signal of each input channel is output from the ΔΣ modulator 12 in a time division manner, and which output bit is from which input channel. Can be determined. As long as the timing corresponding to the input channel CH1 among the signals to the digital filter 20 is known, the output signals of the respective input channels are sequentially sent in order, so that the input signal DO from the output signal DO of the ΔΣ modulator 12 is input. The output signal for each channel can be separated.

The output of the delta-sigma modulator 12 for each of these input channels is shown for each of the channels CH1, CH2, CH3, and CH4 as shown in FIGS. 3D, 3E, 3F, and 3G, respectively. And is averaged by the digital filter 20. The averaged value for each channel is obtained as a multi-bit digital conversion result.
In FIG. 1, all the input channels CH1 to CH4 are used. However, for example, only the input channels CH1 and CH2 may be used depending on the setting of the setting circuit 13 of the multiplexer 10.

  In the above-described ΔΣ-type A / D converter, in the present embodiment, the ΔΣ modulator 12 and the digital filter 20 are separated into different modules, so that the analog module 100 including the ΔΣ modulator 12 is, for example, a sensor. The digital module 101 including the digital filter 20 can be instrumented, for example, close to the controller. That is, in this embodiment, instead of routing the analog input signal line from the sensor or the like and connecting it to the analog module 100, the digital output signal line of the ΔΣ modulator 12 can be stretched. Mixing of noise into the signal can be suppressed.

  In this embodiment, since the input channel is switched using the multiplexer 10, it is not necessary to provide a ΔΣ modulator and a digital filter for each input channel, and the input channels can be shared. In this embodiment, since the ΔΣ modulator and the digital filter can be shared by each input channel, when an insulating element for ground separation is provided between the ΔΣ modulator and the digital filter, the number of insulating elements Can be reduced. Since the insulating element has a large area and high cost, if the insulating element can be omitted, the size and cost of the A / D converter can be reduced. Therefore, according to the present embodiment, the circuit area, power consumption, and cost can be reduced as compared with the integrated circuit of Non-Patent Document 1 in which a ΔΣ modulator needs to be provided for each input channel.

  Although the ground is omitted in FIG. 1 for ease of description, in this embodiment, the ground of the analog module 100 including the ΔΣ modulator 12 and the ground of the digital module 101 including the digital filter 20 are used. It is separated. Here, the ground separation means that the ground points of the analog module 100 and the digital module 101 are separated as much as possible so that the mutual interference between the analog module 100 and the digital module 101 can be ignored. .

  In the present embodiment, by separating the ΔΣ modulator 12 and the digital filter 20 into different modules, the ground of the ΔΣ modulator 12 and the ground of the digital filter 20 can be easily separated. By separating the ground of the analog module 100 including the digital signal from the ground of the digital module 101 including the digital filter 20, noise mixing from the digital module 101 to the analog input signal of the analog module 100 can be suppressed.

  In the present embodiment, digital signals are transmitted and received between the ΔΣ modulator 12 and the digital filter 20 via the insulating element 30, and identification between the multiplexer 10 and the synchronization signal generation circuit 21 of the digital module 101 is performed. The signal SYNC is transmitted and received through the insulating element 31. Thereby, in this Embodiment, the noise mixture from the digital module 101 to an analog input signal can further be suppressed.

  Further, in the present embodiment, the ΔΣ modulator 12 and the digital filter 20 are separated into different modules (IC chips), so that an optimum design according to the requirements of each module can be performed. That is, for the analog module 100, it is possible to design a chip that emphasizes not only the circuit area during integration but also for noise resistance. For the digital module 101, reduction of the circuit area is emphasized during integration. Chip design can be done.

  FIG. 4 is a block diagram showing the configuration of a temperature controller, which is an example of a device in which the ΔΣ A / D converter according to this embodiment is mounted. The same components as those in FIG. It is. In FIG. 4, the multiplexer 10, the programmable gain amplifier 11, the setting circuits 13 and 14, the multiphase clock circuit 15, the insulating element 31, the synchronization signal generation circuit 21, and the synchronization clock generation circuit 22 are omitted for simplicity of explanation. It is.

  A ΔΣ A / D converter including the ΔΣ modulator 12, the insulating element 30, and the digital filter 20 converts an analog input signal from the temperature sensor 102 into a digital signal. After converting the digital output signal of the digital filter 20 into a temperature, the CPU 4 of the digital module 101 calculates an operation amount by, for example, a PID control algorithm so that the temperature (control amount) matches a predetermined set value. The operation amount is output as a digital signal. The D / A converter 5 converts the output signal of the CPU 4 into an analog signal. An analog output signal (operation amount) output from the D / A converter 5 is given to the heater 103. In this way, the temperature controller controls the temperature at the measurement point to be a predetermined set value.

If the ΔΣ A / D converter according to the present embodiment is applied to such a temperature controller, the analog module 100 is disposed near the temperature sensor 102 as described above, and a signal line for digital output from the analog module 100 is provided. Can be extended to the digital module 101, and noise can be suppressed from being mixed into the analog input signal.
Further, although the single temperature sensor 102 is shown in FIG. 4, according to the present embodiment, analog input signals from the plurality of temperature sensors 102 can be switched by the multiplexer 10 (not shown in FIG. 4). It is possible to control the temperature at a plurality of measurement points so as to become a predetermined set value.

  FIG. 5 is a block diagram showing a configuration of a pressure gauge, which is another example of a device in which the ΔΣ A / D converter according to the present embodiment is mounted. The same reference numerals are given to the same configurations as those in FIG. It is. In FIG. 5, the multiplexer 10, the programmable gain amplifier 11, the setting circuits 13, 14, the multiphase clock circuit 15, the insulating element 31, the synchronization signal generation circuit 21, and the synchronization clock generation circuit 22 are omitted for the sake of simplicity. It is.

  A ΔΣ A / D converter including the ΔΣ modulator 12, the insulating element 30, and the digital filter 20 converts an analog input signal from the pressure sensor 104 into a digital signal. The CPU 6 of the digital module 101 converts the digital output signal of the digital filter 20 into pressure, and outputs the converted pressure value as a digital signal. The D / A converter 7 converts the output signal of the CPU 6 into an analog signal. The analog output signal output from the D / A converter 7 is input to a controller (not shown) in the form of a 4-20 mA current signal that transmits the pressure value as a 4-20 mA current.

In such a pressure gauge, the analog circuit and the digital circuit are arranged close to each other. However, if the ΔΣ A / D converter of the present embodiment is applied, the analog module 100 including the ΔΣ modulator 12 is applied. And the ground of the digital module 101 including the digital filter 20 can be separated, and noise mixing into the analog input signal can be suppressed.
Further, although the single pressure sensor 104 is shown in FIG. 5, according to the present embodiment, the analog input signals from the plurality of pressure sensors 104 can be switched by the multiplexer 10 (not shown in FIG. 5). Pressure values at a plurality of measurement points can be transmitted to the controller.

[Second Embodiment]
Next, a second embodiment of the present invention will be described. FIG. 6 is a block diagram showing a configuration of a ΔΣ A / D converter according to the second embodiment of the present invention. The same reference numerals are given to the same configurations as those in FIG.
In the first embodiment, the analog module 100 and the digital module 101 generate clock signals separately. In the present embodiment, the digital module 106 generates a clock signal used in the analog module 105. Then, it is sent to the analog module 105.

  The analog module 105 includes a multiplexer 10 serving as a switching circuit, a programmable gain amplifier 11 that amplifies an analog input signal output from the multiplexer 10, a ΔΣ modulator 12, setting circuits 13 and 14, a multiplexer 10, and a programmable gain amplifier. 11 and a delta-sigma modulator 12 are provided with a multi-phase clock circuit 15a for generating multi-phase clock signals φ1, φ2, bar φ1, bar φ2,... Based on the clock signal SCLK from the digital module 106. Yes.

  The digital module 106 includes a digital filter 20, a synchronization signal generation circuit 21 that generates a CH synchronization signal from the identification signal SYNC of the multiplexer 10, and a clock generation circuit that generates the clock signal SCLK and supplies it to the digital module 106 and the analog module 105. 23.

  The third insulating element 32 electrically insulates between the clock generation circuit 23 and the multiphase clock circuit 15a, converts the clock signal SCLK into a non-electric signal, and then converts it back into an electric signal to convert it into a multiphase clock. Input to the circuit 15a. The insulating element 32 is formed of a photocoupler or a pulse transformer, similarly to the insulating elements 30 and 31.

  FIG. 7 is a timing chart for explaining the operation of the clock generation circuit 23 and the multiplexer 10. First, the clock generation circuit 23 generates a clock signal SCLK as shown in FIG. 7A and inputs it to the digital filter 20 and the insulating element 32.

The multi-phase clock circuit 15a that has received the clock signal SCLK from the clock generation circuit 23 via the insulating element 32 is configured to sequentially select the four input channels CH1, CH2, CH3, and CH4 in synchronization with the clock signal SCLK. Clock signals φ1, φ2, bar φ1, bar φ2,... Are generated.
As shown in FIG. 7B, the multiplexer 10 sequentially selects four input channels CH1, CH2, CH3, CH4 according to the multiphase clock signals φ1, φ2, bar φ1, bar φ2,. An analog input signal from the channel is input to the ΔΣ modulator 12.

The operations of the ΔΣ modulator 12, the insulating element 30, the synchronization signal generation circuit 21, and the digital filter 20 are the same as described in the first embodiment.
Then, as shown in FIG. 7C, the multiplexer 10 outputs an identification signal SYNC that becomes a significant level when the input channel CH1 is selected to the digital module 106 via the insulating element 31.

  When the ΔΣ A / D converter of the present embodiment is applied to, for example, the temperature controller shown in FIG. 4, the digital filter 20 and the CPU 4 of the digital module receive the digital output signal input from the ΔΣ modulator 12. Which channel of the channels CH1, CH2, CH3, and CH4 can be identified based on the CH synchronization signal and the clock signal SCLK.

  Although the ground is omitted in FIG. 6 for ease of description, the ground of the analog module 105 including the ΔΣ modulator 12 and the digital filter 20 are also provided in the present embodiment, as in the first embodiment. The ground of the digital module 106 including it is separated. In the present embodiment, the digital signal is transmitted and received between the ΔΣ modulator 12 and the digital filter 20 via the insulating element 30, and the clock signal SCLK between the clock generation circuit 23 and the multiphase clock circuit 15a is transmitted. Are transmitted and received via the insulating element 32, and the identification signal SYNC is transmitted and received between the multiplexer 10 and the synchronization signal generating circuit 21 via the insulating element 31.

In the present embodiment, as in the first embodiment, the input channel is switched using the multiplexer 10, whereby the ΔΣ modulator 12 and the digital filter 20 are shared by the input channels.
Thus, also in this embodiment, the same effect as that of the first embodiment can be obtained.

  Since the clock signal can be generated separately for the analog module and the digital module, the third insulating element 32 that sends the clock signal SCLK from the digital module to the analog module is not an essential component of the present invention.

[Third Embodiment]
Next, a third embodiment of the present invention will be described. FIG. 8 is a block diagram showing the configuration of the ΔΣ A / D converter according to the third embodiment of the present invention. The same components as those in FIGS. 1 and 6 are denoted by the same reference numerals.
This embodiment shows an application example of the second embodiment, in which the power supply voltage of the analog module 107 is generated using the clock signal from the digital module 106.

The analog module 107 rectifies the clock signal SCLK from the multiplexer 10, the programmable gain amplifier 11, the ΔΣ modulator 12, the setting circuits 13 and 14, the multiphase clock circuit 15 a, and the digital module 106, and the analog module 107. And a rectifier circuit 16 for generating a DC power supply voltage.
FIG. 9 is a circuit diagram showing a configuration of the rectifier circuit 16. The rectifier circuit 16 includes a diode D1 and a capacitor C1.

  The clock signal SCLK from the digital module 106 is sent to the multiphase clock circuit 15 a of the analog module 107 via the insulating element 32 and is input to the rectifier circuit 16. The rectifier circuit 16 rectifies the clock signal SCLK internally to generate a DC power supply voltage used in the analog module 107. Similarly to the second embodiment, since the digital module 106 and the analog module 107 are grounded, the rectifier circuit 16 serves as a power source that is grounded from the digital module 106. By operating the analog module 107 using the power supply voltage output from the rectifier circuit 16, it is possible to use a power supply separated from the digital module 106 and the ground.

According to the present embodiment, since the power supply circuit that supplies the power supply voltage to the analog module side can be simplified, the circuit size and cost of the analog module 107 can be reduced.
The ground-separated power source can be generated separately without using the clock signal from the digital module side. Therefore, the third insulating element 32 for sending the clock signal from the digital module to the analog module, and the power source Is not an essential component of the present invention.

[Fourth Embodiment]
Next, a fourth embodiment of the present invention will be described. FIG. 10 is a block diagram showing a configuration of a ΔΣ A / D converter according to the fourth embodiment of the present invention. The same reference numerals are given to the same configurations as those in FIGS. It is.
This embodiment shows another example of the second embodiment, in which input channel setting and gain setting are performed from the digital module side by serial communication.

  The analog module 108 includes a multiplexer 10, a programmable gain amplifier 11, a ΔΣ modulator 12, a multiphase clock circuit 15 a, and a selection operation of the multiplexer 10 according to the data signal DI sent from the digital module 109 and the programmable gain amplifier 11. And a register circuit 17 for controlling the gain. The multiplexer 10 and the register circuit 17 constitute a switching circuit.

The digital module 109 includes a digital filter 20, a synchronization signal generation circuit 21, a clock generation circuit 23, an SPI (Serial Peripheral Interface) 24 that is a control communication circuit for the analog module 108, and a CPU 25.
A clock signal SCLK and a data signal DI are output from the SPI 24 of the digital module 109. It is assumed that the chip select signal CS as the SPI is connected to the active side, and the SPI data output from the analog module 108 is omitted in FIG.

Setting of the multiplexer 10 and the programmable gain amplifier 11 included in the analog module 108 necessary for the ΔΣ A / D converter of the present embodiment is performed by the data signal DI from the SPI 24 of the digital module 109.
The CPU 25 performs desired input channel setting and gain setting, causes the SPI 24 to generate a data signal DI based on the setting, and controls the multiplexer 10 and the programmable gain amplifier 11 of the analog module 108.

  The data signal DI is input to the analog module 108 via the fourth insulating element 33. The insulating element 33 is formed of a photocoupler or a pulse transformer, like the insulating elements 30, 31, and 32.

  The register circuit 17 of the analog module 108 controls the multiplexer 10 according to the data signal DI to select a desired input channel. The register circuit 17 sets the gain of the programmable gain amplifier 11 according to the data signal DI. Then, the multiplexer 10 generates an identification signal SYNC indicating the selected input channel and selection timing, and inputs the identification signal SYNC to the digital module 109 via the insulating element 31.

The operations of the multiphase clock circuit 15a, the ΔΣ modulator 12, the isolation elements 30, 31, 32, the digital filter 20, the synchronization signal generation circuit 21, and the clock generation circuit 23 have been described in the first and second embodiments. It is as follows.
Thus, according to the present embodiment, the input channel setting and gain setting are performed by serial communication from the digital module 109 side, although the board area and cost are increased compared to the second embodiment. Therefore, the degree of freedom in design can be improved.

  In FIG. 7, the ground is omitted for ease of description, but in this embodiment as well, the ground and digital filter of the analog module 108 including the ΔΣ modulator 12 are the same as in the first embodiment. The ground of the digital module 109 including 20 is separated. As a result, the same effects as those of the first embodiment can be obtained in the ΔΣ A / D converter.

Since the clock signal can be generated separately for the analog module and the digital module, the third insulating element 32 that sends the clock signal SCLK from the digital module to the analog module is not an essential component of the present invention.
In the first to fourth embodiments, the mounting location of the insulating elements 30, 31, 32, and 33 is not specified, but the insulating elements 30, 31, 32, and 33 may be mounted on an analog module. However, it may be mounted on a digital module or may be mounted on another module.

  The present invention can be applied to a multi-input ΔΣ A / D converter that receives a plurality of analog input signals.

1 is a block diagram illustrating a configuration of a ΔΣ A / D converter according to a first embodiment of the present invention. FIG. 2 is a block diagram illustrating a configuration example of a ΔΣ modulator of the ΔΣ A / D converter in FIG. 1. 2 is a timing chart for explaining operations of a multiplexer, a synchronous clock generation circuit, and a digital filter in the ΔΣ A / D converter of FIG. 1. It is a block diagram which shows the structure of the temperature controller which is an example of the apparatus which mounts the delta-sigma A / D converter of FIG. It is a block diagram which shows the structure of the pressure gauge which is another example of the apparatus which mounts the delta-sigma type A / D converter of FIG. It is a block diagram which shows the structure of the delta-sigma type A / D converter which concerns on the 2nd Embodiment of this invention. 7 is a timing chart for explaining operations of a clock generation circuit and a multiplexer in the ΔΣ A / D converter of FIG. 6. It is a block diagram which shows the structure of the delta-sigma type A / D converter which concerns on the 3rd Embodiment of this invention. It is a circuit diagram which shows one structural example of the rectifier circuit in the delta-sigma type A / D converter of FIG. It is a block diagram which shows the structure of the delta-sigma A / D converter which concerns on the 4th Embodiment of this invention. It is a block diagram which shows the structure of the conventional delta-sigma A / D converter.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Multiplexer, 11 ... Programmable gain amplifier, 12 ... Delta-sigma modulator, 13, 14 ... Setting circuit, 15, 15a ... Multiphase clock circuit, 16 ... Rectifier circuit, 17 ... Register circuit, 20 ... Digital filter, 21 ... Synchronization Signal generation circuit, 22 ... Synchronous clock generation circuit, 23 ... Clock generation circuit, 24 ... SPI, 25 ... CPU, 30, 31, 32, 33 ... Insulating element.

Claims (4)

A ΔΣ modulator that converts an analog input signal into a 1-bit digital signal;
A digital filter that passes only the signal frequency band of the output of the ΔΣ modulator;
A switching circuit that selects any one of a plurality of input channels, inputs an analog input signal of the selected input channel to the ΔΣ modulator, and generates an identification signal indicating the selected input channel;
A first insulating element that is provided between the ΔΣ modulator and the digital filter, converts the output signal of the ΔΣ modulator into a non-electric signal, and then converts the output signal back into an electric signal and inputs the digital filter;
A second insulating element that converts the identification signal into a non-electric signal and then converts it back to an electrical signal and inputs it to the digital module including the digital filter;
A ΔΣ A / D converter characterized in that a ground of an analog module including the switching circuit and the ΔΣ modulator is separated from a ground of a digital module including the digital filter. In the delta-sigma type A / D converter according to claim 1,
And a third insulating element that converts the clock signal generated by the digital module into a non-electric signal and then converts the clock signal back to the electric signal and inputs the analog signal to the analog module.
The switching circuit sequentially selects any one of a plurality of input channels in synchronization with the clock signal. The ΔΣ A / D converter according to claim 1, wherein: The ΔΣ A / D converter according to claim 2,
The analog module further includes a rectifier circuit that rectifies the clock signal to generate a power supply voltage of the analog module. The ΔΣ type A / D converter according to claim 1 or 2,
The ΔΣ A / D converter characterized in that the first, second and third insulating elements are photocouplers or transformers.

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