JP2013201487A - D/a converter and jitter frequency control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a D/A converter that reduces effects of noise on electronic components.SOLUTION: The D/A converter includes: a sampling circuit 160 having a sample-and-hold section 150b for sampling an input signal based on a digital signal input by a digital section 150c and holding and transferring the sampled signal, and a continuous section 150a for outputting the signal transferred by the sample-and-hold section as an analog signal; a clock signal generation section 143 for generating a clock signal φ1' supplied to the sample-and-hold section 150b and a clock signal φ2 supplied to the continuous section 150a; a jitter generation section 141 for generating jitter added to at least the clock signal φ1'; and a jitter frequency control circuit 171 for controlling the frequency of the jitter generated by the jitter generation section 141.

Description

  The present invention relates to a D / A converter and a jitter frequency control circuit provided in the D / A converter.

  Currently, the demand for downsizing of electronic devices is increasing, electronic parts mounted on electronic devices are downsized, and electronic parts are arranged closer to each other. When electronic components are arranged close to each other, noise generated in the electronic components may be transmitted to other electronic components directly or via a mounting substrate or wiring, and may interfere with normal operation of the other electronic components. For this reason, recent electronic devices are required to be reduced in size and to suppress the influence of noise (hereinafter also referred to as noise countermeasures).

In order to prevent the noise generated by electronic components from affecting other electronic components, it is generally necessary to place electronic components apart so that the effect of noise is reduced, or when manufacturing electronic components. In the process, it is conceivable to devise arrangement and separation of elements. It is also conceivable to provide input / output terminals separately for each electronic component.
However, it is not preferable to dispose the electronic components apart from each other because it prevents the electronic device from being downsized. Further, in order to prevent noise from affecting the outside due to the process of the electronic component, an advanced process technique is required, which is not preferable because the manufacturing cost increases. Furthermore, separating input terminals and output terminals of electronic components is disadvantageous in reducing the size of electronic equipment due to the increase in the number of pins of electronic equipment.

Incidentally, there is a D / A converter as an electronic component mounted on an electronic device. The D / A converter is an electronic component that is often used for an audio function of an electronic device, and particularly an electronic component that requires countermeasures against noise.
As a conventional technique for countermeasures against noise in a D / A converter, for example, there is an invention described in Patent Document 1. In the invention described in Patent Document 1, jitter is added to the synchronization signal (control clock signal) of the input signal of the D / A converter. According to the invention described in Patent Document 1, it is possible to diffuse beat noise radiation caused by a synchronization signal (conversion clock signal) for outputting an output signal and a control clock signal.

  Such prior art is based on the idea of reducing radiation noise generated by a D / A converter and reducing the influence of noise on other devices.

JP 62-6536 A

However, as in the prior art, even if the radiation noise generated by the D / A converter is reduced, the influence of noise generated from outside the D / A converter on the D / A converter is sufficiently reduced. Can not.
Further, since the prior art adds jitter only to the digital part, it is not possible to diffuse periodic noise caused by the inrush current of the analog part. For this reason, the diffusion effect of the prior art is limited.

  In order to reduce the influence of radiation noise generated by individual electronic components directly or indirectly on the D / A converter using the conventional technology, a plurality of other components mounted in the electronic device are used. A circuit for inputting jitter must be provided for these components. In such a configuration, it is necessary to provide a large number of circuits for inputting jitter, and it is considered that miniaturization of electronic devices is hindered.

  The present invention has been made in view of the above-described points, and does not hinder downsizing of electronic components and avoids the advancement of process technology, while reducing the noise received by electronic components mounted on electronic devices. An object of the present invention is to provide a D / A converter and a jitter frequency control circuit capable of reducing the influence.

  In order to solve the above problems, a D / A converter (D / A converter illustrated in FIG. 12) of one embodiment of the present invention is a digital signal input by a digital unit (for example, the digital unit 150c illustrated in FIG. 13). A sample and hold unit (for example, the sample and hold unit 150b shown in FIG. 13) that samples the input signal based on the signal, holds and transfers the sampled signal, and the signal transferred by the sample and hold unit A sampling circuit (for example, the sampling circuit 160 illustrated in FIGS. 12 and 13) including a continuous unit (for example, the continuous unit 150a illustrated in FIG. 13) that outputs as a signal, and a first clock supplied to the sample and hold unit The signal (for example, the clock signal φ1 ′ shown in FIGS. 12 and 13) and the second signal supplied to the continuous unit A clock signal generation unit (for example, the clock signal generation unit 143 illustrated in FIG. 13) that generates a lock signal (for example, the clock signal φ2 illustrated in FIGS. 12 and 13), and jitter added to at least the first clock signal. A jitter generator (for example, jitter generator 141 shown in FIG. 13) and a jitter frequency controller for controlling the frequency of the jitter generated by the jitter generator (eg, jitter frequency control circuit 171 shown in FIG. 13). It is characterized by including these.

  In the D / A converter according to one aspect of the present invention, in the D / A converter according to the above aspect, the jitter frequency control unit is mixed in the input signal from the frequency characteristic of the input signal supplied to the sample and hold unit. A detector (for example, the detector 170 shown in FIG. 13) that detects a peak frequency at which the noise has a peak, and a frequency converter (for example, FIG. 13) that converts the peak frequency of the noise detected by the detector into an arbitrary frequency. And the jitter generator 141) shown in FIG.

  In the D / A converter of one embodiment of the present invention, in the D / A converter of the above embodiment, the sample and hold unit includes a capacitor element (for example, the capacitor 152 shown in FIG. A switching element (for example, the switches 151 and 153 shown in FIG. 12) that transfers the electric charge accumulated in the capacitive element to the continuous part, and the switching element is turned on according to the clock signal to which jitter is added, It is desirable to perform an off operation.

  A jitter frequency control circuit according to one embodiment of the present invention (for example, the frequency control circuit 171 illustrated in FIG. 13) samples an input signal based on a digital signal input by a digital unit, and holds and transfers the sampled signal. A sampling circuit including a hold unit and a continuous unit that outputs a signal transferred by the sample and hold unit as an analog signal, a first clock signal supplied to the sample and hold unit, and a continuous unit A jitter frequency control circuit used in a D / A converter including a second clock signal to be supplied, a clock signal generation unit that generates a jitter, and a jitter generation unit that generates at least a jitter added to the first clock signal The input signal is determined from the frequency characteristics of the input signal supplied to the sample and hold unit. A detector for detecting a peak frequency having a peak noise to be mixed in, the peak frequency of the noise detected by the detector, characterized in that it comprises a frequency converter for converting to an arbitrary frequency.

  According to the present invention described above, it is possible to provide a sampling circuit capable of reducing the influence of noise received by an electronic component mounted on an electronic device, and a D / A converter including this circuit. Such an effect is obtained by operating the continuous unit based on the first clock signal to which no jitter is added and operating the sample and hold unit based on the second clock signal to which jitter is added. Therefore, downsizing of electronic parts is not hindered. Moreover, it is not necessary to upgrade process technology.

Furthermore, since the radiation noise caused by the inrush current of the analog part can be diffused, the radiation noise can be effectively suppressed.
Furthermore, by changing the peak of the noise frequency detected by the detector to an arbitrary frequency by FM modulation, optimum characteristics can be obtained in a desired frequency band (for example, in-band band).

It is a figure for demonstrating the sampling circuit in the D / A converter of one Embodiment of this invention. FIG. 2 is a diagram for explaining the operation of the D / A converter shown in FIG. 1 when there is no periodic noise in the reference signal Vref. It is a figure for demonstrating the signal regarding the capacitor shown in FIG. FIG. 2 is a diagram for explaining the operation of the D / A converter when the reference signal Vref has periodic noise in the sampling circuit shown in FIG. 1. It is a figure for demonstrating the periodic noise shown in FIG.4 (c), (d). FIG. 2 is a diagram for explaining periodic noise when jitter is added to a clock signal for operating a digital unit in the D / A converter shown in FIG. 1. FIG. 7 is a diagram for further explaining FIG. 2 is a diagram for explaining periodic noise when jitter is added to the clock signal of the digital unit and the clock signal of the sample and hold unit in the D / A converter shown in FIG. 1. FIG. It is a figure for demonstrating the signal output from a capacitor at the time of supplying the clock signal which has a jitter of a fixed frequency to the capacitor shown in FIG. It is a figure for demonstrating the signal output from a capacitor at the time of supplying the clock signal with which the jitter which has two different frequencies was added to the capacitor shown in FIG. It is a figure for demonstrating the signal output from a capacitor at the time of supplying the clock signal with which the jitter which has a random frequency was added to the capacitor shown in FIG. It is a figure for demonstrating the D / A converter of one Embodiment of this invention. It is a functional block diagram of the D / A converter shown in FIG. It is a figure for demonstrating the jitter frequency control circuit of one Embodiment of this invention. It is a figure for demonstrating the signal containing the control signal which controls the D / A converter shown in FIG.

(Overview)
Prior to the description of the embodiments of the present invention, the concept of the sampling circuit of the present invention will be described below. In this description, a D / A converter to which the sampling circuit of this embodiment is applied is taken as an example.
Hereinafter, the digital unit is composed of a general digital circuit, and is characterized by transmitting a quantized and sampled signal. The sample and hold unit is composed of a general switched capacitor circuit (SC circuit), and is characterized by transmitting a sampled signal without being quantized. The continuous part is composed of a general continuous signal circuit (Continuous circuit), and is characterized by transmitting a signal that is not quantized and not sampled.

FIG. 1 is a diagram for explaining a sampling circuit in the D / A converter of this embodiment.
The sampling circuit shown in FIG. 1 has a sample and hold unit that samples and holds a signal and a continuous unit that processes an analog signal, and includes capacitors 111, 112, and 113, and an operational amplifier 121. In FIG. 1, a digital unit that handles digital signals is not shown.

  A reference signal Vref (sampled reference signal Vref is referred to as an input signal Vin) sampled by the switches 101 and 102 is added to the capacitor 111, and charges are accumulated. The electric charge accumulated in the capacitor 111 is input to the inverting input terminal of the operational amplifier 121 according to the switching of the switches 101 and 102. The operational amplifier 121 receives the reference signal Vcom1 from the non-inverting input terminal and outputs an analog output signal Vout.

  Here, in the circuit configuration shown in FIG. 1, when noise is superimposed on the reference signal Vref and the reference signal Vcom1, it appears in the output waveform with a gain of 0 dB, so the sensitivity to noise is the highest. In the present embodiment, a case where noise is superimposed on the reference signal Vref will be described, but the same consideration can be applied even when noise is superimposed on other than the reference signal Vref. An example is the reference signal Vcom1.

(I) When there is no periodic noise FIGS. 2A to 2D are diagrams for explaining the operation of the D / A converter shown in FIG. 1 when there is no periodic noise in the reference signal Vref. .
FIG. 2A shows the sampling timing of the reference signal Vref. 2B shows the timing at which the capacitor 111 holds and releases the charge accumulated by the input signal Vin, FIG. 2C shows the reference signal Vref which is a DC voltage, and FIG. 2D shows the operational amplifier. An output signal VAout, which is an analog signal, is output from 121. In FIG. 2D, the signal indicated by the solid line is the input signal Vin generated by the charge transferred from the capacitor 111, and the output signal VAout indicated by the broken line is generated by feedback via the capacitor 112.

  The graph shown in FIG. 3A is a diagram for explaining a signal output from the capacitor 111 shown in FIG. 1, and shows a spectrum obtained by converting the input signal Vin into the frequency axis by Fourier transform. The graph shown in FIG. 3B is a spectrum obtained by converting a sampling clock (hereinafter referred to as a clock signal) that regulates the timing at which the capacitor 111 holds and discharges the charge accumulated by the input signal Vin into the frequency axis by Fourier transform. The graph shown in FIG. 3C shows a spectrum obtained by converting the output signal VAout to the frequency axis by Fourier transform. In any of the graphs shown in FIGS. 3A, 3B, and 3C, the vertical axis indicates the intensity of the signal spectrum, and the horizontal axis indicates the frequency. The position of the vertical axis indicated by the arrow line in the graphs of FIGS. 3A, 3B, and 3C indicates the frequency reference (“0”).

  As shown in FIG. 3, the signal output from the capacitor 111 (indicated by spectrum p in the figure) has a constant frequency. The spectrum q shows the noise shaped floor noise in the input signal Vin. When the spectra p and q are sampled, held and emitted by the switches 101 and 102, the output signal VAout shown in FIG. 3C is generated by convolution. In the output signal VAout, the spectra p and q are mirrored symmetrically.

(Ii) When there is periodic noise Next, a case where there is periodic noise in the reference signal Vref will be described.
4A to 4D are diagrams for explaining the operation of the D / A converter in the sampling circuit shown in FIG. 1 when the reference signal Vref has periodic noise.
FIG. 4A shows the sampling timing of the reference signal Vref. 4B shows the timing at which the capacitor 111 holds and releases the charge accumulated by the reference signal Vref, FIG. 4C shows the reference signal Vref which is a DC voltage, and FIG. 4D shows the operational amplifier. An output signal VAout, which is an analog signal, is output from 121. When the periodic noise N1 shown in FIG. 4C is generated in the reference signal Vref, the D / A converter generates the periodic noise N2 corresponding to the periodic noise N1 in the output signal VAout.

The periodic noise shown in FIGS. 4C and 4D will be described with reference to FIGS. 5A, 5B, and 5C.
The graph shown in FIG. 5A is a diagram for explaining a signal output from the capacitor 111 shown in FIG. 1, and shows a spectrum obtained by converting the input signal Vin into the frequency axis by Fourier transform. The graph shown in FIG. 5B shows a spectrum obtained by converting the clock signal that regulates the timing at which the capacitor 111 holds and releases the charge accumulated by the input signal Vin into the frequency axis by Fourier transform, and FIG. 5C shows the spectrum. The graph shown shows a spectrum obtained by converting the output signal VAout to the frequency axis by Fourier transform. In any of the graphs shown in FIGS. 5A, 5 </ b> B, and 5 </ b> C, the vertical axis indicates the signal spectrum intensity, and the horizontal axis indicates the frequency. The position of the vertical axis indicated by the arrow line in the graphs of FIGS. 5A, 5B, and 5C indicates the frequency reference (“0”).

  When the spectrum shown in FIG. 5A is sampled, held, and emitted by the switches 101 and 102 shown in FIG. 1, the periodic noise N2 is turned back and the periodic noise N2 'appears in the vicinity of DC. Then, as shown in the graph of FIG. 5C, the periodic noise N2 'is mirrored symmetrically by convolution to generate the output signal VAout. When the D / A converter is used in an audio device, for example, the periodic noise N2 'appears in a frequency region (hereinafter also referred to as in-band) used for output sound.

In the present embodiment, jitter is added to a clock signal for operating a device such as a sampling circuit, so that periodic noise appearing in the in-band is diffused by a signal output from another device, and the signal quality of an output signal such as sound is transmitted. This is based on the technical idea of preventing the damage.
(Iii) In the case where jitter is added to the digital part Next, in order to clarify the difference between the present invention and the prior art, the prior art will be described.

The D / A converter processes a digital part that processes a digital signal that is a non-continuous signal, a sample-and-hold part (S / H part) that samples and holds a signal, and processes an analog signal that is a continuous signal. A sampling circuit including a continuous unit is included.
6A, 6B, and 6C are diagrams for explaining periodic noise when jitter is added to a clock signal for operating the digital unit in the D / A converter shown in FIG. It is.

  The graph shown in FIG. 6A is a diagram for explaining a signal output from the capacitor 111 shown in FIG. 1, and shows a spectrum obtained by converting the input signal Vin into the frequency axis by Fourier transform. The graph shown in FIG. 6B shows a spectrum obtained by converting the clock signal that regulates the timing at which the capacitor 111 holds and releases the charge accumulated by the input signal Vin into the frequency axis by Fourier transform, and FIG. 6C shows the spectrum. The graph shown shows a spectrum obtained by converting the output signal VAout to the frequency axis by Fourier transform. In any of the graphs shown in FIGS. 6A, 6 </ b> B, and 6 </ b> C, the vertical axis indicates the signal spectrum intensity, and the horizontal axis indicates the frequency. The position of the vertical axis indicated by an arrow in the graphs of FIGS. 6A, 6 </ b> B, and 6 </ b> C indicates the frequency reference (“0”).

  In the prior art, jitter is added to the clock signal of the digital part of the D / A converter. According to such a conventional technique, as shown in FIG. 6A, the energy of the periodic noise N3 is dispersed in a wider frequency region than before adding jitter. For this reason, the peak of the spectrum of the periodic noise N3 is lower than the peak of the spectrum of the periodic noise N2 shown in FIG. Further, the peak of the spectrum of the periodic noise N3 'generated in the in-band is also low as with the periodic noise N3. According to such a configuration, the noise generated by the D / A converter itself can be reduced, and the influence of noise on other devices can be reduced.

  The graphs shown in FIGS. 7A, 7 </ b> B, and 7 </ b> C are diagrams for explaining FIG. 6A. The graph shown in FIG. 7A is a frequency characteristic of the reference signal Vref shown in FIG. 4C, and shows a spectrum obtained by converting the reference signal Vref superimposed with periodic noise into the frequency axis by Fourier transform. The frequency indicated by the broken line in FIG. 7A represents the Nyquist frequency, which is half the sampling operation frequency. The graph shown in FIG. 7B shows a spectrum in which the capacitor 111 stores the input signal Vin, and the clock signal that regulates the sampling timing is converted to the frequency axis by Fourier transform. A frequency indicated by a broken line in FIG. 7B is a sampling operation frequency. The graph shown in FIG. 7C shows a spectrum obtained by converting the output signal VAout to the frequency axis by Fourier transform. In any of the graphs shown in FIGS. 7A, 7 </ b> B, and 7 </ b> C, the vertical axis indicates the intensity of the signal spectrum, and the horizontal axis indicates the frequency. The position of the vertical axis indicated by an arrow line in the graphs of FIGS. 7A, 7B, and 7C indicates the frequency reference (“0”).

As shown in FIG. 7, since modulation does not occur in the sampling operation to the capacitor 111 in FIG. 1, the spectrum of the periodic noise N3 is folded as it is to become the periodic noise N3 ′.
(Iv) Concept of this Embodiment However, in this embodiment, the spectrum peak of the periodic noise N3 ′ shown in FIG. 6 can be further dispersed, and the influence of noise generated by other devices can be canceled by itself. The object is to provide a sampling circuit and the like.

In this embodiment, jitter is added to the clock signal of the sample and hold unit of the D / A converter in order to realize the above-described object.
FIGS. 8A, 8B, and 8C show periods when jitter is added to the clock signal of the digital unit and the clock signal of the sample and hold unit in the D / A converter shown in FIG. It is a figure for demonstrating noise.

  The graph shown in FIG. 8A is a diagram for explaining a signal output from the capacitor 111 shown in FIG. 1, and shows a spectrum obtained by converting the input signal Vin into the frequency axis by Fourier transform. The graph shown in FIG. 8B shows a spectrum obtained by converting the clock signal that regulates the timing at which the capacitor 111 holds and discharges the charge accumulated by the input signal Vin into the frequency axis by Fourier transform. The graph shows a spectrum obtained by converting the output signal VAout to the frequency axis by Fourier transform. In each of the graphs shown in FIGS. 8A, 8B, and 8C, the vertical axis indicates the signal spectrum intensity, and the horizontal axis indicates the frequency. The position of the vertical axis indicated by an arrow in the graphs of FIGS. 8A, 8B, and 8C indicates the frequency reference (“0”).

  As shown in FIG. 8A, when a clock signal with jitter is added to the digital and sample and hold portions as well, periodic noise caused by the inrush current of the analog portion can be diffused. The peak can be made smaller than the peak of the spectrum of the periodic noise N3 shown in FIG. Further, since jitter is added to the operation clock, modulation is applied at the time of folding, and the spectrum peak of the periodic noise N4 'is further smaller than the spectrum peak of the periodic noise N4. From this, it is clear that this embodiment can reduce the periodic noise generated in the in-band as compared with the prior art.

The graphs shown in FIGS. 9A, 9B, and 9C are obtained from the capacitor 111 when the clock signal added with jitter having a constant frequency fjit1 is supplied to the capacitor 111 shown in FIG. It is a figure for demonstrating the return | turnback of the periodic noise N4 in the signal output.
The graph shown in FIG. 9A is a frequency characteristic of FIG. 4C and shows a spectrum obtained by converting the reference signal Vref superimposed with periodic noise into the frequency axis by Fourier transform. The frequency indicated by the broken line in FIG. 9A represents the Nyquist frequency, which is half the sampling operation frequency. The graph shown in FIG. 9B shows a spectrum in which the capacitor 111 stores the input signal Vin and the clock signal that regulates the sampling timing is converted to the frequency axis by Fourier transform. A frequency indicated by a broken line in FIG. 9B is a sampling operation frequency. The graph shown in FIG. 9C shows a spectrum obtained by converting the output signal VAout to the frequency axis by Fourier transform. In any of the graphs shown in FIGS. 9A, 9B, and 9C, the vertical axis indicates the intensity of the signal spectrum, and the horizontal axis indicates the frequency. The position of the vertical axis indicated by an arrow in the graphs of FIGS. 9A, 9 </ b> B, and 9 </ b> C indicates the frequency reference (“0”).

  As shown in FIG. 9, since FM (Frequency Modulation) modulation is applied to the sampling operation frequency in the sampling operation to the capacitor 111 in FIG. 1, the spectrum of the periodic noise N4 is folded back into a wide range to become the periodic noise N4 ″. For example, when fjit1 = 96 kHz, noise diffused by FM modulation is skipped to the 96 kHz band, so that it can be removed from the in-band, and the noise characteristics in the in-band can be effectively improved. .

  The graphs shown in FIGS. 10A, 10 </ b> B, and 10 </ b> C are obtained when a clock signal with jitters having two different frequencies fjit <b> 1 and fjit <b> 2 is supplied to the capacitor 111 shown in FIG. 1. It is a figure for demonstrating the return | turnback of the periodic noise N4 in the signal output from the capacitor 111. FIG. Note that “jitter having two frequencies fjit1 and fjit2” means, for example, jitter such that a signal of frequency fjit1 appears for a natural number n1 periods, and then a signal of frequency fjit2 appears for a natural number n2 periods. In this case, the natural number n1 and the natural number n2 may be the same or different.

The graph shown in FIG. 10A is a frequency characteristic of the reference signal Vref shown in FIG. 4C, and shows a spectrum obtained by converting the reference signal Vref superimposed with periodic noise into the frequency axis by Fourier transform. The frequency indicated by the broken line in FIG. 10A represents the Nyquist frequency, which is half the sampling operation frequency.
The graph shown in FIG. 10B shows a spectrum in which the capacitor 111 stores the input signal Vin and the clock signal that regulates the sampling timing is converted to the frequency axis by Fourier transform. A frequency indicated by a broken line in FIG. 10B is a sampling operation frequency. The graph shown in FIG. 10C shows a spectrum obtained by converting the output signal VAout to the frequency axis by Fourier transform. In any of the graphs shown in FIGS. 10A, 10 </ b> B, and 10 </ b> C, the vertical axis indicates the signal spectrum intensity, and the horizontal axis indicates the frequency. The position of the vertical axis indicated by an arrow in the graphs of FIGS. 10A, 10B, and 10C indicates the frequency reference (“0”).

  As shown in FIG. 10, in the sampling operation to the capacitor 111 in FIG. 1, FM (Frequency Modulation) modulation is applied to the sampling operation frequency, so that the spectrum of the periodic noise N4 is dispersed and folded over a wide range, and the periodic noise. For example, when fjit1 = 96 kHz and fjit2 = 250 kHz, the noise diffused by FM modulation appears dispersed in the 96 kHz band and the 250 kHz band. The noise N4 ″ ′ can be removed from the in-band, and the noise characteristics in the in-band can be effectively improved.

  Further, in the present embodiment, since the periodic noise N4 ″ ″ is dispersed even in the frequency band where the periodic noise N4 ″ ″ appears, the noise peak can be suppressed. The present embodiment is not limited to a jig having two different frequencies, and the same effect can be obtained even when jitter having two or more different frequencies is added to a clock signal. can get.

  The graphs shown in FIGS. 11A, 11B, and 11C are obtained when a clock signal added with jitter having a random frequency is supplied to the capacitor 111 of the D / A converter shown in FIG. It is a figure for demonstrating the return | turnback of the periodic noise N4 in the signal output from the capacitor 111. FIG. The “jitter having a random frequency” means, for example, a jitter in which a signal having a certain frequency appears for a natural number n1 periods, and subsequently a signal having another frequency appears for a natural number n2 periods. In this case, the natural number n1 and the natural number n2 may be the same or different.

  The graph shown in FIG. 11A is a frequency characteristic of the reference signal Vref shown in FIG. 4C, and shows a spectrum obtained by converting the reference signal Vref superimposed with periodic noise into the frequency axis by Fourier transform. The frequency indicated by the broken line in FIG. 11A represents the Nyquist frequency, which is half the sampling operation frequency. The graph shown in FIG. 11B shows a spectrum in which the capacitor 111 stores the input signal Vin and the clock signal that regulates the sampling timing is converted to the frequency axis by Fourier transform. A frequency indicated by a broken line in FIG. 11B is a sampling operation frequency. The graph shown in FIG. 11C shows a spectrum obtained by converting the output signal VAout to the frequency axis by Fourier transform. In any of the graphs shown in FIGS. 11A, 11B, and 11C, the vertical axis indicates the signal spectrum intensity, and the horizontal axis indicates the frequency. The position of the vertical axis indicated by an arrow in the graphs of FIGS. 11A, 11B, and 11C indicates the frequency reference (“0”).

  As shown in FIG. 11, since FM (Frequency Modulation) modulation is applied to the sampling operation frequency in the sampling operation to the capacitor 111 of FIG. 1, the spectrum of the periodic noise N4 is dispersed and folded over a wide range, and the periodic noise N4 " " The frequency width at which the noise spectrum spreads is proportional to the jitter amplitude, in other words, the modulation factor. Since the noise spectrum is equally distributed within the jitter frequency width, the peak of the noise spectrum after FM modulation can be effectively suppressed.

  According to the present embodiment as described above, since the frequency spreading effect is obtained in the modulation from the periodic noise N4 to the periodic noise N4 ′ shown in FIG. 8, the periodic noise generated in the in-band in the D / A converter. Can be reduced. This periodic noise is not limited to only the periodic noise generated by the D / A converter, and an example thereof is periodic noise from an A / D converter mounted on the same substrate. For this reason, the present embodiment can be applied to an electronic component in which periodic noise affects the operation, and the periodic noise of the electronic component can be reduced. Such an embodiment is advantageous in reducing the size and configuration of the electronic device.

Next, an embodiment of the present invention based on the concept described above will be described.
(Embodiment)
FIG. 12 is a diagram for explaining a D / A converter according to an embodiment of the present invention. The illustrated D / A converter includes a sampling circuit 160, a control circuit 159, and a detector 170.

  The sampling circuit 160 intermittently samples an input signal (reference signal Vref, the sampled reference signal Vref is referred to as an input signal Vin) based on the input digital signal Din, and holds and transfers the sampled signal. A hold unit 150b and a continuous unit 150a that outputs the signal transferred by the sample and hold unit 150b as an analog signal Aout are included.

The control circuit 159 generates and outputs clock signals φ1 and φ2 that do not include jitter, and clock signals φ1 ′ and φ2 ′ to which jitter is added. The clock signal φ2 to which jitter is not added is input to the continuous unit 150a, and the clock signal φ1 ′ to which jitter is added is input to the sample and hold unit 150b.
The detector 170 detects the frequency characteristic of the noise peak of the reference signal Vref that is a noise mixing path, and is added by the control circuit 159 so that the noise peak is modulated to a frequency other than a desired frequency band (for example, in-band band). Change the jitter frequency. In the present embodiment, the configuration shown in FIG. 12 is configured as a semiconductor integrated circuit, but the detector 170 may be provided outside the semiconductor integrated circuit. When the detector 170 is provided outside the semiconductor generation circuit, the detector 170 is realized by, for example, a spectrum analyzer.

The sample-and-hold unit 150 b includes a capacitor 152 that accumulates charges generated by the input signal Vin, a switch 151 that accumulates in the capacitor 152, and a switch 153. The switch 151 and the switch 153 perform a switching operation according to the clock signal φ1 ′.
The continuous unit 150a includes an operational amplifier 155, a feedback path 158 that inputs the analog output signal Aout of the operational amplifier 155 to the inverting input terminal, a capacitor 154 that accumulates charges generated by the analog output signal Aout on the feedback path 158, and a capacitor A switch 156 for transferring the charge accumulated in 152 to the analog output signal Aout and a switch 157 are included. A clock signal φ2 having no jitter is output to the switches 156 and 157 of the continuous unit 150a, and the continuous unit 150a is operated by the clock signal φ2.

The continuous part 150 a further includes a capacitor 154. This capacitor 154 forms an LPF, and the cutoff frequency of the LPF is determined by the capacitance ratio of the capacitors 154 and 152 and the switching frequency. Note that the capacitor 154 shown in FIG. 12 is not an essential component of this embodiment. FIG. 13 is a functional block diagram of a D / A converter (denoted as DAC in the drawing) including the sampling circuit 160 and the control circuit 159 shown in FIG. In FIG. 13, the same components as those shown in FIG. 15 are denoted by the same reference numerals, and the description thereof is partially omitted.

The control circuit 159 supplies the clock signal φ2 without adding jitter to the continuous unit 150a, and supplies the clock signal φ1 ′ with added jitter to the digital unit 150c, and supplies it to the sample and hold unit 150b. On the other hand, a clock signal φ1 ′ with jitter added is supplied.
That is, the control circuit 159 includes a clock signal generation unit 143 that generates clock signals φ1 and φ2 without adding jitter, and a jitter generation unit that generates clock signals φ1 ′ and φ2 ′ with addition of jitter (jitter_Gen. 141) and clock signals φ1, φ2, φ1 ′, φ2 ′ are input, the clock signal φ1 ′ generated by the jitter generator 141 is selected and output to the sample and hold unit 150b, and the clock signal φ1 ′ And a jitter selector (denoted as jitter_Sel. In FIG. 13) 162 that operates to select and output the clock signal φ2 to the digital unit 150c and output it to the continuous unit 150a.

  In addition, this embodiment is not limited to the structure provided with the jitter selection part 162, It can be set as the structure which does not provide the jitter selection part 162. FIG. In the case where the jitter selection unit 162 is not provided, in the present embodiment, the clock signal φ1 ′ is directly output from the jitter generation unit 141 to the sample and hold unit 150b and the digital unit 150c. Then, the clock signal generation unit 143 outputs the clock signal φ2 directly to the continuous unit 150a.

  The detector 170 detects the frequency characteristic of the noise peak of the reference signal Vref that is a noise mixing path. The jitter generation unit 141 generates a clock signal to which jitter whose frequency changes is added based on the control signal output from the detector 170. The frequency is changed so that the noise peak of the reference signal Vref is modulated to a frequency other than a desired frequency band (for example, in-band band). In the present embodiment, the detector 170 and the jitter generator 141 function as the jitter control circuit 171 of the present embodiment.

  FIG. 14 is a diagram for explaining the circuit configuration of the jitter frequency control circuit 171 shown in FIG. 13, and specifically shows the configuration of the jitter generation unit 141. The jitter generator 141 includes delay elements 144_1, 144_2, 144_3, 144_4, switch groups 145_1, 145_2, 145_3, 145_4, a control circuit 146, and a jitter clock generator 148. The delay elements 144_1 to 144_4 are connected in series. The switch groups 145_1 to 145_4 are connected between delay elements connected in series, and the switch groups 145_1 to 145_4 are connected to the control circuit 146.

  The clock signal output from the clock signal generation unit 143 illustrated in FIG. 13 is input to the delay element 144_1. The output terminal of the delay element 144_1 is connected to the input terminal of the delay element 144_2 and the input terminal (denoted as “I” in the drawing) of the switch group 145_1. The output terminal of the delay element 144_2 is connected to the input terminal of the delay element 144_3 and the input terminal of the switch group 145_2 (denoted as “I” in the drawing), and the output terminal of the delay element 144_3 is connected to the input terminal of the delay element 144_4. It is connected to an input terminal (denoted as “I” in the drawing) of the switch group 145_3. The output terminal of the delay element 144_4 is connected to the input terminal of the switch group 145_4. The output terminals of the switch groups 144_1, 144_2, 144_3, and 144_4 are short-circuited, and a signal output from the shorted output terminal is output from the jitter generation unit 141 as a clock signal.

The reference signal Vref is input to the detector 170, and the detector 170 detects the frequency characteristic of the noise peak of the reference signal Vref. A control signal 173 is output from the detector 170 based on the detected frequency characteristic. The control signal 173 is input to the jitter clock generator 148.
The jitter clock generator 148 is configured to output a signal that oscillates at a constant frequency, and includes a VCO (voltage controlled oscillator) that changes the oscillation frequency based on a control signal 173. The frequency change in the jitter clock generator 148 is performed as follows.

  The jitter clock generator 148 outputs a signal having a frequency obtained by multiplying the frequency of 48 kHz by the value of the control signal and “8”. For example, when the control signal 173 is 1V, the jitter clock generator 148 outputs a signal 149 having an oscillation frequency of 384 kHz (48 kHz × 8 = 384 kHz). When the control signal 173 is 2V, the jitter clock generator 148 outputs a signal 149 having an oscillation frequency of 768 kHz (48 kHz × 2 × 8 = 384 kHz).

  When the control signal 173 is 3V, the jitter clock generator 148 outputs a signal 149 having an oscillation frequency of 1152 kHz (48 kHz × 3 × 8 = 1152 kHz). Further, when the control signal 173 is 4V, the jitter clock generator 148 outputs a signal 149 having an oscillation frequency of 1536 kHz (48 kHz × 4 × 8 = 1536 kHz).

  The jitter clock generator 148 generates control signals 147_1, 147_2, 147_3, and 147_4 based on the detected frequency characteristic of the noise peak. As will be described later, in the control signals 147_1, 147_2, 147_3, and 147_4, only one signal is always High (hereinafter referred to as “H”), and the remaining three signals are referred to as Low (hereinafter referred to as “L”). )

  The control signal 147_1 is input to a control signal input terminal (denoted as “S” in the drawing) of the switch group 145_1. The control signal 147_2 is input to a control signal input terminal (denoted as “S” in the drawing) of the switch group 145_2. The control signal 147_3 is input to a control signal input terminal (denoted as “S” in the drawing) of the switch group 145_3. The control signal 147_4 is input to a control signal input terminal (denoted as “S” in the drawing) of the switch group 145_4.

  The delay elements 144_1, 144_2, 144_3, and 144_4 add an arbitrary delay amount (for example, 1 ns) to the input clock signal and output the added signal. The switch groups 145_1, 145_2, 145_3, and 145_4 are input terminals (denoted as “I” in the figure) and output terminals (in the figure) when the control signals 147_1, 147_2, 147_3, and 147_4 inputted from the input terminals are H. When the control signal is L, the input terminal and the output terminal are released.

  FIGS. 15A to 15E are timing charts for explaining the control signals 147_1, 147_2, 147_3, 147_4 and the signal 149 output from the jitter clock generator 148. FIG. FIG. 15A shows the signal 149. FIG. 15B shows the control signal 147_1, FIG. 15C shows the control signal 147_2, and FIG. 15D shows the control signal 147_3. FIG. 15E shows the control signal 147_4. In each of FIGS. 15A to 15E, the vertical axis indicates H and L of the signal, and the horizontal axis indicates time.

  The control circuit 146 shown in FIG. 14 sets the control signals 147_1, 147_2, 147_3, and 147_4 to H in the order of the control signals 147_1, 147_2, 147_3, and 147_4 in synchronization with the signal 149. At this time, the control signals 147_1, 147_2, 147_3, and 147_4 are switched so that none of them becomes H at the same time.

  As can be seen from FIG. 15, the control circuit 146 switches the control signal so that the jitter period makes one round with the period obtained by dividing the signal 149 by eight. When the control signal 173 output from the detector 170 is 1V, the jitter generator 141 outputs a clock signal to which jitter having a frequency of 48 kHz is added. When the control signal 173 output from the detector 170 is 2V, the jitter generator 141 outputs a clock signal to which jitter having a frequency of 96 kHz is added. Further, when the control signal 173 output from the detector 170 is 3V, the jitter generator 141 outputs a clock signal to which jitter having a frequency of 144 kHz is added. When the control signal 173 output from the detector 170 is 4V, the jitter generator 141 outputs a clock signal to which jitter having a frequency of 192 kHz is added.

  According to the present embodiment, the sample and hold unit 150b transmits the discretized signal, and the signal component is a DC component. For this reason, in this embodiment, the signal component is not modulated by the jitter added to the operation clock signal. However, since periodic noise mixed from the D / A converter itself or other electronic devices is an AC component, the noise component is modulated by jitter applied to the operation clock signal, and a noise diffusion effect is obtained. . In other words, the present embodiment does not change to STF (Signal Transfer Function), but can modulate only NTF (Noise Transfer Function) by jitter, and efficiently separates mixed periodic noise from signal components. can do. For this reason, this embodiment can disperse only the noise in the in-band without adding noise to the signal to be transmitted, and reduce the peak of the spectrum.

  Further, according to the present embodiment, for example, when the D / A converter performs a sampling operation at 6.000 MHz and noise having a peak at 6.010 MHz is superimposed on the reference signal Vref, the detector 170 causes the jitter generating unit to The frequency of jitter added at 141 is set to 96 kHz, for example. According to such a setting, in the conventional case, a noise peak appears at 6.010 MHz−6.0000 MHz = 10 kHz by folding, but in this embodiment, the frequency band is 96 kHz × N + 10 kHz (N is a natural number) by FM modulation. The peak can be moved. In particular, the highest noise peak can be moved to 96 kHz + 10 kHz = 106 kHz. Therefore, this embodiment can efficiently suppress noise in the in-band.

In this embodiment, the noise generated from the devices around the D / A converter is not reduced, but the resistance of the D / A converter itself to noise can be enhanced. For this reason, the influence of noise on the D / A converter can be reduced by changing only the D / A converter without changing the configuration of other devices around the D / A converter.
Further, the embodiment can be realized only by adding a circuit for adding jitter to the clock signal. This eliminates the need for advanced semiconductor process technology and the increase in the number of pins on the chip, thereby preventing an increase in cost of the D / A converter. Furthermore, according to the embodiment, since the D / A converter can be arranged close to other devices without considering the influence of noise, it is effective in reducing the size of the device including the D / A converter. Play.

  Further, in the embodiment, it is possible to reduce the noise suppression requirement for a decoupling capacitor that is generally provided for the purpose of reducing noise generated from devices around the D / A converter. In addition, according to the embodiment, since the noise suppression requirement for the decoupling capacitor can be reduced, it may be considered that the decoupling capacitor itself is unnecessary.

The noise component moved out of the band by FM modulation can be removed by, for example, an LPF (Low Path Filter).
Further, the present embodiment is not limited to the configuration described above. That is, in the present embodiment, the case where the resolution of the jitter applied by the jitter generator 141 is 4 has been described. However, the resolution of the jitter applied by the jitter generator 141 is not determined to be 4, and an arbitrary resolution N This embodiment can obtain the same effect even in the case where N is a natural number of 2 or more.

Further, the present embodiment is not limited to the one that inputs the clock signal φ1 ′ with jitter added to the digital unit 150c. Even if the clock signal φ1 that does not add jitter is input to the digital unit 150c, the effect of enhancing the resistance to noise of the D / A converter itself is not impaired at all.
Furthermore, also in the embodiment, the clock signal generation unit 143 may be provided outside the D / A converter. Further, when the sampling circuit of the D / A converter shown in FIGS. 12 and 13 is configured as another device, the control circuit 159 may be provided outside the device.

  In addition, the scope of the present invention is not limited to the exemplary embodiments shown and described above, but includes all embodiments that bring about effects equivalent to those intended by the present invention. Further, the scope of the invention is not limited to the combinations of features of the invention defined by the claims, but is defined by any desired combination of particular features among all the disclosed features. sell.

(effect)
Next, consider a CODEC in which the D / A converter of this embodiment and an existing A / D converter are mounted together.
The D / A converter of the present embodiment has the same configuration as that of the A / D converter and the D / A converter even when the sampling frequencies of the A / D converter and the D / A converter are the same (operating frequency difference 0 on the horizontal axis). Even when the sampling frequency with the / A converter has a difference of about ± 25 Hz, the distortion of the output signal is small. In this embodiment, the output signal is distorted both in an asynchronous operation in which the A / D converter and the D / A converter operate with different clock signals, and in a synchronous operation in which the same clock signal operates. Can be reduced.

  In the present embodiment, the frequency of jitter applied to the operation clock is 48 kHz to 384 kHz. In any of jitter frequencies of 48 kHz to 384 kHz, this embodiment can reduce distortion of the output signal.

  The present invention can be used for all electronic devices having a D / A conversion function in addition to a D / A converter.

101, 151, 153, 156, 157 switches 111, 112, 152, 154 capacitors 121, 155 operational amplifiers 141 jitter generators 143 clock signal generators 144_1 to 141_4 delay elements 145_1 to 145_4 switches 146, 159 control circuits 147_1 to 147_4 , 173 Control signal 148 Jitter clock generator 149 Signal 150a Continuous unit 150b Sample and hold unit 150c Digital unit 158 Feedback path 160 Sampling circuit 162 Jitter selection unit 170 Detector 171 Jitter frequency control circuit

Claims (4)

A sample-and-hold unit that samples an input signal based on a digital signal input by the digital unit, holds and transfers the sampled signal, and a continuous signal that outputs the signal transferred by the sample-and-hold unit as an analog signal A sampling circuit comprising:
A clock signal generation unit that generates a first clock signal supplied to the sample and hold unit and a second clock signal supplied to the continuous unit;
A jitter generator for generating jitter added to at least the first clock signal;
A jitter frequency control unit for controlling the frequency of the jitter generated by the jitter generation unit;
D / A converter characterized by including. The jitter frequency controller is
From a frequency characteristic of the input signal supplied to the sample-and-hold unit, a detector that detects a peak frequency at which noise mixed in the input signal has a peak;
A frequency converter that converts a peak frequency of noise detected by the detector into an arbitrary frequency;
The D / A converter according to claim 1, comprising: The sample and hold unit is
A capacitive element that accumulates charges generated by the input signal, and a switching element that transfers the charges accumulated in the capacitive element to the continuous unit,
The D / A converter according to claim 1, wherein the switching element performs an on / off operation in accordance with the clock signal to which jitter has been added. A sample-and-hold unit that samples an input signal based on a digital signal input by the digital unit, holds and transfers the sampled signal, and a continuous signal that outputs the signal transferred by the sample-and-hold unit as an analog signal A sampling circuit comprising:
A clock signal generation unit that generates a first clock signal supplied to the sample and hold unit and a second clock signal supplied to the continuous unit;
A jitter frequency control circuit used in a D / A converter including at least a jitter generation unit that generates jitter added to the first clock signal,
From a frequency characteristic of the input signal supplied to the sample-and-hold unit, a detector that detects a peak frequency at which noise mixed in the input signal has a peak;
A frequency converter that converts a peak frequency of noise detected by the detector into an arbitrary frequency;
A jitter frequency control circuit comprising:

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