JP2007184695A - Wireless communication apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wireless communication apparatus capable of carrying out frequency conversion while suppressing the degration of a gain and sampling a wireless frequency signal. <P>SOLUTION: A sampling clock generating circuit 9 generates a sampling clock Cs whose pulse width Ton is set so that an integral value of a current held in a sample and holed circuit 4 is not canceled and outputs the sampling clock Cs to the sample and hold circuit 4, and the sample and hold circuit 4 samples the wireless frequency signal amplified by a low noise amplifier 3 while integrating the wireless frequency signal according to the sampling clock Cs and down-converts the wireless frequency signal to convert the wireless frequency signal into a baseband signal. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a wireless communication apparatus, and is particularly suitable for application to a method for performing frequency conversion while sampling a radio frequency signal.

  It is known that when a radio frequency signal is sampled, the radio frequency signal is turned back by aliasing, so that frequency conversion is possible. Here, if the sampling frequency is fs, the spectrum is folded every fs / 2. If this principle is used, the sampling frequency can be reduced to 1 / N, and the power consumption can be reduced while relaxing the circuit requirement for generating the clock (Patent Document 1).

In the frequency conversion by sampling, the sampling frequency fs, the radio frequency (RF frequency) _frf , and the intermediate frequency (IF frequency) _fif have the following relationship.
f _if = f _rf ± N * fs (1)
Here, N is a sub-sampling ratio.

  For example, when a signal having an RF frequency of 5.1 GHz is converted to an IF frequency of 100 MHz, the analog mixer requires a local signal of 5 GHz. On the other hand, when the frequency is converted by a sampling mixer, the sampling frequency may be 2.5 GHz (N = 2), 1.25 GHz (N = 4), etc. in addition to 5 GHz.

On the other hand, when the RF frequency increases, the impedance of the capacitor used for sample / hold decreases. For this reason, in order to ensure an effective sample voltage, it is necessary to reduce the hold capacitance so that the impedance is sufficiently higher than the output impedance.
JP 2002-26758 A

However, for example, as can be seen from the fact that the impedance of the capacitance of 5 GHz and 0.1 pF drops to about 300Ω, in the normal CMOS process, the output impedance of the previous stage (about several hundred to several kΩ) and the ON resistance of the MOS switch (several hundred There is a problem that it is difficult to create a capacitor having a sufficiently high impedance compared to (Ω).
On the other hand, there is a method of sampling current after performing voltage-current conversion in order to enable sampling even at a high frequency without causing a decrease in capacitance impedance, but when sampling is performed by this method, There was a problem that the gain decreased.

  Accordingly, an object of the present invention is to provide a wireless communication apparatus capable of performing frequency conversion while sampling a radio frequency signal while suppressing a decrease in gain.

  In order to solve the above-described problem, according to a wireless communication apparatus according to an aspect of the present invention, a sampling clock generation circuit that generates a sampling clock and a sample that performs frequency conversion while sampling a radio frequency signal according to the sampling clock And the sampling clock generation circuit sets the pulse width of the sampling clock so that the integrated value of the current held by the sample and hold circuit is not canceled.

  Thereby, it is possible to hold by the sample and hold circuit while integrating so that the current flowing by the radio frequency signal is not canceled. For this reason, even when it is difficult to create a capacitor with a sufficiently high impedance compared to the output impedance of the previous stage in the sample and hold circuit, frequency conversion is performed while sampling the radio frequency signal while suppressing a decrease in gain. This makes it possible to receive radio frequency signals without using an analog mixer.

In the wireless communication apparatus according to one aspect of the present invention, the pulse width is (1/2 + P (P is an integer of 0 or more)) times the period of the radio frequency signal.
As a result, the sampling clock can be generated so as to correspond to the positive or negative region of the radio frequency signal, and can be held while integrating so that the current flowing through the radio frequency signal is not canceled.

In the wireless communication device according to one aspect of the present invention, the sampling clock generation circuit includes a delay element that generates a delay clock obtained by delaying a reference clock, and an exclusive logic of the reference clock and the delay clock. And an exclusive OR circuit that takes a sum.
Thus, by using a simple circuit configuration, the pulse width of the sampling clock can be adjusted so that the integrated value of the current held by the sample and hold circuit is not canceled.

  According to the wireless communication device of one aspect of the present invention, a multiphase sampling clock generation circuit that generates a non-overlapping multiphase sampling clock, and a frequency while subsampling a radio frequency signal according to the multiphase sampling clock A sample-and-hold circuit that performs conversion, and the multi-phase sampling clock generation circuit sets a pulse width of the multi-phase sampling clock so that an integral value of a current held by the sample-and-hold circuit is not canceled. Features.

  As a result, the current flowing by the radio frequency signal can be held by the sample and hold circuit while being integrated so that the current flowing by the radio frequency signal is not canceled, and the current flowing by the subsampled radio frequency signal can be superimposed. For this reason, even when it is difficult to create a capacitor with a sufficiently high impedance compared to the output impedance of the previous stage in the sample-and-hold circuit, it is possible to increase the gain while subsampling the radio frequency signal. Conversion can be performed, the sampling frequency can be reduced to 1 / N, and power consumption can be reduced while relaxing circuit requirements for clock generation.

In the wireless communication apparatus according to one aspect of the present invention, the pulse width is substantially ½ times the period of the radio frequency signal.
As a result, while integrating the current flowing by the radio frequency signal so as not to be canceled, the current flowing by the sub-sampled radio frequency signal can be superimposed, and gain can be gained while the sampling frequency is reduced to 1 / N. Can be reduced.

  Further, according to the wireless communication device of one aspect of the present invention, the multiphase sampling clock generation circuit includes a multiphase clock generation circuit that generates a multiphase clock having a phase difference of equal intervals while referring to a reference clock. And a delay element that generates a delay clock obtained by delaying the multiphase clock, and an exclusive OR circuit that obtains an exclusive OR of the multiphase clock and the delay clock.

  Thus, by using a simple circuit configuration, the pulse width of the multiphase sampling clock can be adjusted so that the integrated value of the current held by the sample hold circuit is not canceled.

Hereinafter, a wireless communication apparatus according to an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing a schematic configuration of the wireless communication apparatus according to the first embodiment of the present invention, and FIG. 2 is a timing chart showing signal waveforms of the wireless communication apparatus of FIG.
In FIG. 1, a radio communication apparatus includes an antenna 1 that receives radio waves, a bandpass filter 2 that attenuates unnecessary frequency components from radio frequency signals received by the antenna 1, and radio frequencies received by the antenna 1. (RF: Radio Frequency) A low noise amplifier 3 that amplifies a signal, a sample hold circuit 4 that performs frequency conversion while sampling a radio frequency signal according to a sampling clock, and an unnecessary radio frequency signal that is down-converted by the sample hold circuit 4 A low-pass filter 5 for attenuating high-frequency components, an amplifier 6 for amplifying the radio frequency signal output from the low-pass filter 5, an A / D converter 7 for converting the radio frequency signal output from the amplifier 6 into a digital signal, sampling Reference clock Cref of frequency fs And a sampling clock generation circuit 9 that generates a sampling clock using a reference clock. Here, the sampling clock generation circuit 9 can set the pulse width of the sampling clock so that the integrated value of the current held by the sample hold circuit 4 is not canceled. The radio frequency signal means a signal having a frequency that can be propagated wirelessly, for example, a signal having a frequency of about several hundred MHz to several tens GHz.

  The radio frequency signal received via the antenna 1 is sent to the low noise amplifier 3 after an unnecessary frequency component is attenuated by the band pass filter 2. On the other hand, the frequency synthesizer 8 generates a reference clock Cref having a sampling frequency fs (FIG. 2A) and outputs the reference clock Cref to the sampling clock generation circuit 9. The sampling clock generation circuit 9 generates a sampling clock Cs in which the pulse width Ton is set so that the integrated value of the current held by the sample hold circuit 4 is not canceled (FIG. 2B), and the sample hold circuit 4 is output. Note that the pulse width Ton of the sampling clock Cs is (1/2 + P (P is 0 or more)) with a period 1 / frf of the radio frequency signal when the frequency of the radio frequency signal (RF signal) is frf (FIG. 2C). It is preferable that the integer)) times.

  When the radio frequency signal is sent through the band pass filter 2, the low noise amplifier 3 amplifies the radio frequency signal and sends it to the sample hold circuit 4. When the sampling clock Cs is sent from the sampling clock generation circuit 9, the sample hold circuit 4 samples the radio frequency signal amplified by the low noise amplifier 3 while integrating it according to the sampling clock Cs, and down-converts the radio frequency signal. Is converted into a baseband signal. The baseband signal generated by the sample and hold circuit 4 is sent to the A / D converter 7 via the amplifier 6 after an unnecessary frequency component is attenuated by the low-pass filter 5. Then, after the baseband signal is digitized by the A / D converter 7, baseband signal processing is performed.

  As a result, the sample and hold circuit 4 can hold the signal while integrating so that the current flowing by the radio frequency signal is not canceled. For this reason, even when it is difficult to create a capacitor having a sufficiently high impedance in comparison with the output impedance of the low noise amplifier 3 in the sample and hold circuit 4, it is possible to sample the radio frequency signal while suppressing a decrease in gain. Frequency conversion can be performed, and radio frequency signals can be received without using an analog mixer.

FIG. 3 is a diagram illustrating a sampling pulse width setting method of the wireless communication apparatus of FIG.
In FIG. 3A, it is assumed that an RF signal having a period of 1 / frf is input to the sample hold circuit 4. As shown in FIG. 3B, if the pulse width Ton of the sampling clock Cs is set to ½ times the period 1 / frf of the RF signal, the sampling clock Cs is turned on when the sampling clock Cs is turned on. A current flows into the capacitance of the hold circuit 4. Therefore, the capacitor of the sample hold circuit 4 is charged while the sampling clock Cs is on, and an integrated value corresponding to the area S1 of the RF signal is obtained as shown in FIG.

  On the other hand, as shown in FIG. 3C, the pulse width Ton of the sampling clock Cs is set to be equal to the period 1 / frf of the RF signal. When the sampling clock Cs is turned on, current flows into the capacity of the sample and hold circuit 4 between the times t1 and t2, and current flows out of the capacity of the sample and hold circuit 4 between the times t2 and t3. As shown in e), the integral value corresponding to the area S1 of the RF signal is canceled by the integral value corresponding to the area S2 of the RF signal.

FIG. 4 is a diagram showing the relationship between the sampling pulse width and the IF voltage of the wireless communication apparatus of FIG. In the example of FIG. 4, the IF voltage is normalized to 1.
In FIG. 4, when the pulse width Ton of the sampling clock Cs is changed,
When the pulse width Ton is 1/2 frf, 3/2 frf,..., The amount of cancellation of the integrated value of the RF signal is small, and it can be seen that the IF voltage output from the sample hold circuit 4 takes a maximum value. Therefore, the maximum gain can be obtained by setting the pulse width Ton of the sampling clock Cs to be 1/2, 3/2,... Of the RF band. That is, the pulse width Ton of the sampling clock Cs is preferably ½ times the RF band, but there is no problem even if the pulse width Ton of the sampling clock Cs is slightly deviated from ½ times the RF band. The pulse width Ton of the sampling clock Cs may be shifted from about 1/2 times the RF band to about 20%, and more preferably, the pulse width Ton of the sampling clock Cs is shifted from about 1/2 time to about 10% of the RF band. It is better to keep within the range.

FIG. 5 is a diagram showing a configuration example of the sampling clock generation circuit 9 of FIG.
In FIG. 5, the sampling clock generation circuit 9 is provided with an exclusive OR circuit 11 and a delay element 12. One input terminal of the exclusive OR circuit 11 has a reference clock Cref generated by the frequency synthesizer 8. , And the reference clock Cref is input to the other input terminal of the exclusive OR circuit 11 via the delay element 12. A sampling clock Cs is output from the exclusive OR circuit 11 to the sample hold circuit 4. Then, by adjusting the delay time of the delay element 12, the pulse width Ton of the sampling clock Cs can be adjusted. Thus, by using a simple circuit configuration, the pulse width Ton of the sampling clock Cs can be adjusted so that the integrated value of the current held by the sample hold circuit 4 is not canceled.

  When the sampling operation of the radio frequency signal is sub-sampling (N ≧ 2 in equation (1)), if the pulse width Ton of the sampling clock Cs is set to ½ frf, a clock with a duty ratio of 50% is used. Compared to the case, the radio frequency signal sampling pause time becomes longer. Therefore, it is possible to further increase the gain by generating a non-overlapping multiphase sampling clock and superimposing currents at the time of sampling. For example, in the case of N = 4, the time for charging the capacity of the sample and hold circuit 4 is quadrupled, so the charge to be charged is quadrupled and the output voltage from the sample and hold circuit 4 is also quadrupled. Can be.

FIG. 6 is a diagram illustrating a configuration of a multiphase sampling circuit of a wireless communication apparatus according to the second embodiment of the present invention, and FIG. 7 is a timing chart illustrating waveforms of a multiphase sampling clock according to an embodiment of the present invention. is there.
6, in the multiphase sampling circuit, field effect transistors M1 to M4 are connected in parallel, and a capacitor C1 is connected to the signal output side of the commonly connected field effect transistors M1 to M4. Then, non-overlapping four-phase sampling clocks Cs1 to Cs4 are generated using the reference clock Cref, and the four-phase sampling clocks Cs1 to Cs4 are input to the gates of the field effect transistors M1 to M4, respectively. When the four-phase sampling clocks Cs1 to Cs4 are respectively input to the gates of the field effect transistors M1 to M4, the field effect transistors M1 to M4 are sequentially turned on / off, and the field effect transistors M1 to M4 Each sampled RF signal current is stored in the capacitor C1 and output as an IF signal.

  As a result, it is possible to hold the multiphase sampling circuit while integrating so that the current flowing through the RF signal is not canceled, and to superimpose the current flowing through the subsampled RF signal. For this reason, even when it is difficult to create a capacitor C1 having a sufficiently high impedance compared to the output impedance of the previous stage, frequency conversion is performed while subsampling the radio frequency signal while allowing gain to be gained. In addition, the sampling frequency can be reduced to 1 / N, and the power consumption can be reduced while relaxing the circuit requirement for generating the clock.

In the examples of FIGS. 6 and 7, the method of performing four-phase sampling by setting N = 4 in equation (1) has been described. However, the present invention is applicable to a sampling method of two-phase sampling, three-phase sampling, or five or more phases. May be.
FIG. 8 is a diagram showing a schematic configuration of a multiphase sampling clock generation circuit according to an embodiment of the present invention.

In FIG. 8, the multiphase sampling clock generation circuit is provided with a phase synchronization circuit 20 and a multiphase sampling clock generation circuit 27. Here, the phase synchronization circuit 20 is provided with a phase comparator 21, a charge pump circuit 22, variable delay elements 23 to 26, and a capacitor C2.
Further, as the multiphase sampling clock generation circuit 27, a configuration in which the configuration of FIG. 5 is arranged in parallel by the number of the variable delay elements 23 to 26 can be used.

  When performing multiphase sampling, the sample hold circuit 4 having the configuration shown in FIG. 1 is replaced with the multiphase sampling circuit shown in FIG. 6, and the sampling clock generating circuit 9 having the configuration shown in FIG. 1 is replaced with the multiphase sampling clock generating circuit shown in FIG. Thus, it is possible to configure a wireless communication apparatus that performs frequency conversion while subsampling a wireless frequency signal according to a multiphase sampling clock.

  The reference clock Cref from the frequency synthesizer 8 in FIG. 1 is input to the phase comparator 21 and also to the variable delay element 23. The reference clock Cref input to the variable delay element 23 is sequentially delayed by the variable delay elements 23 to 26 and then input to the phase comparator 21. Then, the phase comparator 21 compares the phase of the signal output from the variable delay element 26 with the phase of the reference clock Cref, and determines the difference between the phase of the signal output from the variable delay element 26 and the phase of the reference clock Cref. Correspondingly, an Up signal or a Down signal is output to the charge pump circuit 22.

  In the charge pump circuit 22, when the Up signal is output, the capacitor C2 is charged, and when the Down signal is output, the charge accumulated in the capacitor C2 is decharged. Then, the charge pump circuit 22 outputs a voltage defined by the electric charge stored in the capacitor C2 to the variable delay elements 23 to 26 as a control voltage. The variable delay elements 23 to 26 change the delay time according to the control voltage, and control the delay time so that the phase of the signal output from the variable delay element 26 matches the phase of the reference clock Cref. A four-phase clock is generated and output to the multiphase sampling clock generation circuit 27.

When the four-phase clock is output to the multi-phase sampling clock generation circuit 27, the multi-phase sampling clock generation circuit 27 performs the same operation as that of the configuration of FIG. Sampling clocks Cs1 to Cs4 are generated.
Thereby, by using a simple circuit configuration, the pulse widths of the four-phase sampling clocks Cs1 to Cs4 can be adjusted so that the integrated value of the current held in the multiphase sampling circuit of FIG. 6 is not canceled, The sampling frequency can be reduced to 1 / N while making it possible to gain.

1 is a block diagram showing a schematic configuration of a wireless communication apparatus according to a first embodiment of the present invention. 2 is a timing chart showing signal waveforms of the wireless communication device of FIG. 1. The figure which shows the setting method of the sampling pulse width of the radio | wireless communication apparatus of FIG. The figure which shows the relationship between the sampling pulse width and IF voltage of the radio | wireless communication apparatus of FIG. FIG. 3 is a diagram illustrating a configuration example of a sampling clock generation circuit 9 in FIG. 1. The figure which shows the structure of the multiphase sampling circuit of the radio | wireless communication apparatus which concerns on 2nd Embodiment of this invention. The timing chart which shows the waveform of the multiphase sampling clock which concerns on one Embodiment of this invention. The figure which shows schematic structure of the multiphase sampling clock generation circuit which concerns on one Embodiment of this invention.

Explanation of symbols

  1 antenna, 2 band pass filter, 3 low noise amplifier, 4 sample hold circuit, 5 low pass filter, 6 amplifier, 7 A / D converter, 8 frequency synthesizer, 9 sampling clock generation circuit, 11 exclusive OR circuit, 12, 23-26 delay element, M1-M4 field effect transistor, C1, C2 capacitor, 20 phase synchronization circuit, 21 phase comparator, 22 charge pump circuit, 27 multiphase sampling clock generation circuit

Claims (6)

A sampling clock generation circuit for generating a sampling clock;
A sample hold circuit that performs frequency conversion while sampling a radio frequency signal according to the sampling clock,
The wireless communication apparatus, wherein the sampling clock generation circuit sets a pulse width of the sampling clock so that an integrated value of a current held by the sample and hold circuit is not canceled.   2. The wireless communication apparatus according to claim 1, wherein the pulse width is (1/2 + P (P is an integer of 0 or more)) times the period of the radio frequency signal. The sampling clock generation circuit includes:
A delay element that generates a delayed clock obtained by delaying the reference clock;
The wireless communication apparatus according to claim 1, further comprising an exclusive OR circuit that takes an exclusive OR of the reference clock and the delay clock. A multiphase sampling clock generation circuit for generating a non-overlapping multiphase sampling clock;
A sample-and-hold circuit that performs frequency conversion while sub-sampling a radio frequency signal according to the multiphase sampling clock,
The wireless communication apparatus, wherein the multiphase sampling clock generation circuit sets a pulse width of the multiphase sampling clock so that an integrated value of a current held by the sample and hold circuit is not canceled.   5. The wireless communication apparatus according to claim 4, wherein the pulse width is substantially ½ times the period of the radio frequency signal. The multiphase sampling clock generation circuit includes:
A multiphase clock generation circuit that generates a multiphase clock having a phase difference of equal intervals while referring to a reference clock;
A delay element that generates a delayed clock obtained by delaying the multiphase clock;
6. The wireless communication apparatus according to claim 4, further comprising: an exclusive OR circuit that takes an exclusive OR of the multiphase clock and the delayed clock.

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