JP2017121035A - Equalizer circuit and reception device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an equalizer circuit and a reception device that are high in degree of freedom of adjustment of an in-band frequency characteristic and simple in configuration.SOLUTION: An equalizer circuit includes an interphase connection portion including first, second, third and fourth interphase switches whose end terminals are connected to first, second, third, and fourth connection paths to be supplied with first, second, third and fourth conversion signals whose phases are sequentially different by 90 degrees, and interphase capacitors connected to the other terminals of the first, second, third, and fourth interphase switches, first, second, third and fourth output buffers which are respectively connected to the first, second, third and fourth connection paths and output output signals, and a control signal generation circuit which outputs a control signal for controlling connection or disconnection of the first, second, third, and fourth interphase switches. The first, second, third, and fourth interphase switches are repeatedly connected in ascending order or descending order from the N-th interphase switch (N is any one of integers 1 to 4) at an interval of 1/4 cycle based on the control signal.SELECTED DRAWING: Figure 4A

Description

  The present disclosure relates to an equalizer circuit and a radio apparatus such as a receiving apparatus using the equalizer circuit, and relates to signal processing including equalization processing, filtering processing, or frequency conversion by, for example, periodic time-varying continuous time (Periodically Time Varying) processing.

  A discrete-time analog circuit configuration is known as a highly variable circuit suitable for designing in a fine CMOS (Complementary Metal Oxide Semiconductor) process.

  For example, Patent Document 1 discloses a discrete-time analog circuit that performs frequency conversion and complex filtering on an input analog signal.

  The discrete-time analog circuit disclosed in Patent Document 1 performs frequency conversion and complex filtering on an input analog signal by discrete-time analog signal processing. Specifically, the discrete time analog circuit of Patent Document 1 converts an input voltage into a current by a voltage-current conversion circuit, and generates input charges by sampling the converted current. The discrete-time analog circuit of Patent Document 1 performs IIR (Infinite Impulse Response) filter characteristics in which a denominator is a linear expression having a complex coefficient by moving input charges between a plurality of capacitors included in the circuit. Is realized.

US Patent Application Publication No. 2005/0233725

  FIG. 1A is a diagram illustrating an example of frequency characteristics of an RF (Radio Frequency) amplifier of a broadband wireless system. As shown in FIG. 1A, the frequency characteristics of the RF amplifier of the broadband wireless system are not flat in each channel (CH1 to CH4 and the like in FIG. 1A), and there is a deviation (in-band deviation) in the band. For this reason, it is difficult to flatten the frequency characteristics of each channel to be used in a broadband wireless system, and correction (that is, equalization) of the frequency characteristics is required in the baseband.

  FIG. 1B is a diagram illustrating an example of frequency characteristics of a propagation path in a broadband wireless system. In wireless communication, as shown in FIG. 1B, the frequency characteristic of the propagation path is not flat and there is an in-band deviation, so correction of the frequency characteristic is required in the baseband.

  Further, in a broadband wireless system using millimeter waves as RF, when a broadband pass characteristic exceeding several GHz is to be realized, the influence of the switch increases from the viewpoint of clock load and parasitic capacitance. Therefore, the discrete-time analog circuit requires a simple configuration in order to reduce parasitic capacitance and clock load.

  However, the conventional discrete-time analog circuit such as Patent Document 1 can only realize a simple filter characteristic of shifting the center frequency. Therefore, when there is an in-band deviation in the frequency characteristics of the propagation path and the RF circuit as in the broadband wireless system, it is difficult for the conventional discrete time analog circuit to function as an equalizer for correcting the in-band deviation. Further, the conventional discrete-time analog circuit has a complicated structure because it has a large number of capacitors and a large number of switches in order to perform sampling and holding.

  The present disclosure has been made in view of the above point, and an object of the present disclosure is to provide an equalizer circuit having a high degree of freedom of adjustment of in-band frequency characteristics and a simple configuration, and a receiving apparatus using the equalizer circuit.

  The equalizer circuit of the present disclosure is generated by converting an input signal, and the first, second, third, and fourth converted signals that are sequentially different in phase by 90 degrees are input to the first, second, and fourth converted signals, respectively. The first, second, third, and fourth interphase switches, one of which is connected to the second, third, and fourth connection paths, respectively, and the first, second, third, And one or more interphase connections having an interphase capacitance connected to the other terminal of the fourth interphase switch, and by converting a reference signal of a predetermined frequency, the phases are sequentially different by 90 degrees, Generating a four-phase control signal that controls connection or release of the first, second, third, and fourth interphase switches, and the four-phase control signal is transmitted to the first, second, Control signal generation circuit for outputting to the third and fourth interphase switches And first, second, third, and fourth output buffers that are connected to the first, second, third, and fourth connection paths, respectively, and that output four-phase output signals; The first, the second, the third, and the fourth interphase switches are repeatedly connected in a predetermined order by a quarter period based on the control signal of the four phases, and the predetermined Is in ascending order or descending order from the N-th phase switch (N is an integer from 1 to 4).

  A receiving device according to the present disclosure includes an equalizer circuit, an analog-digital conversion unit that converts a signal output from the equalizer circuit into a digital signal, and a digital reception processing unit that performs reception processing of the digital signal and outputs reception data The equalizer circuit is generated by converting the input signal, and the first, second, third, and fourth converted signals are different in phase by 90 degrees in order, respectively. First, second, third, and fourth interphase switches, each of which is connected to the first, second, third, and fourth connection paths that are input, and the first, One or more interphase connections having an interphase capacitance connected to the other terminal of the second, third, and fourth interphase switches, and by converting a reference signal of a predetermined frequency, 9 in order The four-phase control signal is generated to control connection or release of the first, second, third, and fourth interphase switches, and the four-phase control signal is changed to the first , Connected to the control signal generation circuit that outputs to the second, third, and fourth interphase switches, and the first, second, third, and fourth connection paths, respectively. First, second, third, and fourth output buffers that output phase output signals, and the first, second, third, and fourth interphase switches are the four Based on the phase control signal, it is repeatedly connected in a predetermined order by 1/4 period, and the predetermined order is ascending order or descending order from the N-th phase switch (N is an integer from 1 to 4). It is.

  According to the present disclosure, it is possible to provide an equalizer circuit with a high degree of freedom in adjusting the in-band frequency characteristics and a simple configuration, and a receiving apparatus using the equalizer circuit.

The figure which shows an example of the frequency characteristic of RF amplifier of a broadband system Diagram showing an example of frequency characteristics of propagation path in broadband system The figure which shows the structure of the receiver which concerns on Embodiment 1-5 of this indication Diagram showing the difference between continuous-time, discrete-time, and periodic time-varying continuous-time systems FIG. 3 is a diagram showing an example of a configuration of an equalizer circuit according to the first embodiment The figure which shows an example of a structure of IQ mixer which concerns on Embodiment 1. FIG. The figure which shows an example of a structure of the phase-connection part which concerns on Embodiment 1. Timing chart showing an example of control signal The figure which shows the result of the circuit simulation of the frequency characteristic of the equalizer circuit which concerns on Embodiment 1. The figure which shows the result of the circuit simulation of the frequency characteristic of the equalizer circuit which concerns on Embodiment 1. FIG. 10 is a diagram illustrating an example of a configuration of an equalizer circuit according to the second embodiment. The figure which shows the result of the circuit simulation of the frequency characteristic of the equalizer circuit which concerns on Embodiment 2. FIG. 5 is a diagram showing an example of a configuration of an equalizer circuit according to a third embodiment FIG. 10 is a diagram showing an example of a configuration of an equalizer circuit according to a fourth embodiment FIG. 10 is a diagram showing an example of a configuration of an equalizer circuit according to a fourth embodiment FIG. 10 is a diagram showing an example of a configuration of an equalizer circuit according to a fourth embodiment The figure which shows the result of the circuit simulation of the frequency characteristic of the equalizer circuit which concerns on Embodiment 4. FIG. 10 is a diagram showing an example of a configuration of an equalizer circuit according to a fifth embodiment The figure which shows the result of the circuit simulation of the frequency characteristic of the equalizer circuit which concerns on Embodiment 5. FIG. 10 is a diagram illustrating an example of an equalizer circuit according to a sixth embodiment. FIG. 10 is a diagram illustrating an example of a configuration of an equalizer circuit according to a seventh embodiment. Timing chart showing an example of a control signal according to the seventh embodiment The figure which shows the result of the circuit simulation of the frequency characteristic of the equalizer circuit which concerns on Embodiment 7. FIG. 10 is a diagram illustrating an example of a configuration of an equalizer circuit according to an eighth embodiment. FIG. 18 shows an example of a structure of a TA in the eighth embodiment. The figure which shows the result of the circuit simulation of the frequency characteristic of the equalizer circuit which concerns on Embodiment 8. FIG. 10 is a diagram illustrating an example of a configuration of an equalizer circuit according to a ninth embodiment.

  Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. Each embodiment described below is an example, and the present disclosure is not limited by these embodiments.

(Embodiment 1)
[Receiver configuration]
FIG. 2 is a diagram illustrating a configuration of the receiving device 10 according to the first embodiment of the present disclosure.

  2 includes an antenna 11, a low noise amplifier (LNA) 12, a reference frequency oscillating unit 13, an equalizer circuit 14, and an A / D (Analog to Digital) conversion processing unit 15. And a digital reception processing unit 16.

  The antenna 11 receives an RF frequency analog reception signal from a transmission station (not shown), and outputs the RF frequency analog reception signal to the low noise amplifier 12.

  The low noise amplifier 12 amplifies the RF reception analog signal and outputs the amplified RF reception signal to the equalizer circuit 14.

A reference frequency oscillator 13 generates a reference frequency signal f _REF used for periodic time-varying continuous time processing, and outputs a reference frequency signal f _REF to the equalizer circuit 14.

Based on the reference frequency signal f _REF , the equalizer circuit 14 performs frequency conversion and equalization (filtering) on the RF frequency analog reception signal by cyclic time-varying continuous time processing. The equalizer circuit 14 outputs the baseband analog reception signal after equalization (filtering) to the A / D conversion processing unit 15. The configuration and operation of the equalizer circuit 14 will be described later.

  The A / D conversion processing unit 15 converts the baseband analog reception signal into a baseband digital reception signal, and outputs the baseband digital signal to the digital reception processing unit 16.

  The digital reception processing unit 16 generates reception data for a baseband digital signal by predetermined digital reception processing (for example, demodulation processing, decoding processing, etc.), and outputs the generated reception data.

  2 has been described as a configuration in which the equalizer circuit 14 directly outputs a baseband analog reception signal from an analog reception signal having an RF frequency, that is, a direct conversion configuration. However, the receiving apparatus 10 according to the present embodiment may have a configuration in which one or more mixers are added to the subsequent stage of the low-noise amplifier 12 and the like, and an intermediate frequency (IF) is used.

  The equalizer circuit 14 according to the present embodiment is a cyclic time varying continuous time system circuit that performs cyclic time varying continuous time processing. Next, a periodic time-varying continuous time system circuit will be described in comparison with a continuous time system circuit and a discrete time system circuit.

  FIG. 3 is a diagram showing the difference between a continuous time system, a discrete time system, and a periodic time varying system. FIG. 3 conceptually shows signal processing in a continuous-time system, a discrete-time system, and a periodic time-varying continuous-time circuit. The continuous time system, discrete time system, and periodic time-varying continuous time system circuit shown in FIG. 3 perform signal processing on the input continuous time (CT) signal and output a continuous time signal. To do.

  The continuous time system circuit (continuous time circuit) shown in FIG. 3 performs signal processing on the input continuous time signal in continuous time and outputs a continuous time signal. Passive continuous-time circuits use elements that are large in size and poor in flexibility, such as inductors. Therefore, the passive type continuous time circuit is not only suitable for mounting on a fine CMOS, but also has low mounting variability. In addition, since an active continuous time circuit is difficult to design with a low power supply voltage, it is not suitable for mounting in a fine CMOS process, and also consumes a large amount of power.

  The discrete time system circuit (discrete time circuit) shown in FIG. 3 samples an input continuous time signal (CT) by CT / DT conversion and converts it into a discrete time (DT) signal. The discrete-time circuit performs signal processing in discrete time, holds the discrete-time signal after signal processing by DT / CT conversion, and converts it into a continuous-time signal. Then, the discrete time circuit outputs the converted continuous time signal. A discrete-time circuit can be composed of only a switch, a capacitor, and a clock. Since the characteristics of the discrete-time circuit are determined by the capacitance ratio of the capacitor and the clock frequency, the discrete-time circuit is suitable for mounting in a fine CMOS process and has high mounting variability. However, since the discrete-time circuit requires a sample and a hold when converting between a continuous-time signal and a discrete-time signal (CT / DT conversion), a switch is required to realize processing of a complete discrete-time system. The number of will increase.

  3 is a hybrid circuit using a discrete-time circuit as part of the continuous-time circuit. The periodic time-varying continuous-time circuit does not require conversion between a continuous-time signal and a discrete-time signal, and can be designed taking advantage of the discrete-time system with a small number of switches. The periodic time-varying continuous time circuit is suitable for mounting in a fine CMOS process and can simply realize a circuit with high mounting variability.

[Configuration of Equalizer Circuit 100]
Next, the configuration of the equalizer circuit 100 according to the present embodiment will be described with reference to FIGS. 4A to 4C.

  FIG. 4A is a diagram showing an exemplary configuration of the equalizer circuit 100 according to the first embodiment. An equalizer circuit 100 illustrated in FIG. 4A corresponds to the equalizer circuit 14 included in the reception device 10 illustrated in FIG. 2, and performs frequency conversion and filtering processing.

  The equalizer circuit 100 illustrated in FIG. 4A includes an IQ mixer (conversion unit) 101, an interphase connection unit 102, a clock generation circuit (control signal generation circuit) 103, and an output buffer 104 (104-1 to 104-4).

  FIG. 4B is a diagram illustrating an example of a configuration of the IQ mixer 101 according to Embodiment 1. The IQ mixer 101 includes a TA (Transconductance Amplifier: voltage-current converter circuit) 1011, a switch 1012 (1012-1 to 1012-4), and a sample capacitor 1013 (1013-1 to 1013-4). Have.

The TA 1011 converts an input voltage signal V _IN that is an input analog signal into a current (g _m × V _IN ). Note that g _m is a value of transconductance (mutual conductance) of TA1011.

The switches 1012-1 to 1012-4 have one terminal connected to the output terminal of the TA 1011 and the other terminal connected to the input terminals of the output buffers 104-1 to 104-4, respectively. The switches 1012-1 to 1012-4 are on / off controlled based on control signals input from the terminals a to d, respectively. For Figure 4B, the switch 1012-1 is control signals _{S 1} inputted from the terminal a during the high, it turned on. Similarly, switches 1012-2, the control signal _{S 2} input from the terminal b during the high, turned on. Switch 1012-3 is, the control signal _{S 3} which is inputted from the terminal c during the high, turned on. Switch 1012-4, the control signal _{S 4} that is input from the terminal d is the duration of the high, it turned on.

  Sample capacitors 1013-1 to 1013-4 have one terminal grounded and the other terminal connected to terminals T1 to T4, respectively. The sample capacitors 1013-1 to 1013-4 accumulate input charges while the switches 1012-1 to 1012-4 are on, respectively. The detailed operation of the equalizer circuit 100 will be described later.

  With the configuration shown in FIG. 4B, the IQ mixer 101 converts the input signal into a positive phase component (In-phase, hereinafter referred to as “I phase”), a quadrature component (Quadrature, hereinafter “Q Phase)), a negative phase component for the normal phase component (hereinafter referred to as “IB phase”), and a negative phase component for the quadrature component (hereinafter referred to as “QB phase”). 4 conversion signals), and outputs the four-phase signals to different paths. Hereinafter, a path through which an I-phase signal (first conversion signal) is output from the IQ mixer 101, a path through which a Q-phase signal (second conversion signal) is output, and an IB-phase signal (third conversion signal) ) And QB phase signal (fourth conversion signal) are output as I phase path (first connection path), Q phase path (second connection path), and IB phase, respectively. This is called a route (third connection route) and a QB phase route (fourth connection route).

  FIG. 4C is a diagram illustrating an example of a configuration of the interphase connection unit 102 according to Embodiment 1. The interphase connection unit 102 includes a switch (interphase switch) 1021 (1021-1 to 1021-4) and an interphase capacitor (interphase capacitance) 1022.

Each of the switches 1021-1 to 1021-4 is connected to a terminal T1 on the I-phase path, a terminal T2 on the Q-phase path, a terminal T3 on the IB-phase path, and a terminal T4 on the QB path, The other terminal is connected to the interphase capacitor 1022. The switches 1021-1 to 1021-4 are on / off controlled based on control signals input from the terminals e to h, respectively. In FIG. 4C, switch 1021-1 is, the control signal _{S 3} which is inputted from the terminal e for the duration of the high, turned on. Similarly, switch 1021-2 is the control signal _{S 4} that is input from the terminal f is the duration of the high, it turned on. Switch 1021-3 is control signals _{S 1} inputted from the terminal g is the duration of the high, it turned on. Switch 1021-4, the control signal _{S 2} to be input from the terminal h is the duration of the high, it turned on.

  The interphase capacitor 1022 has one terminal connected to the terminals of the switches 1021-1 to 1021-4 and the other terminal grounded.

  Interphase capacitor 1022 is connected to the I-phase path while switch 1021-1 is on. The interphase capacitor 1022 performs charge sharing with the sample capacitor 1013-1. Similarly, the interphase capacitor 1022 is connected to the Q phase path while the switch 1021-2 is on. The interphase capacitor 1022 performs charge sharing with the sample capacitor 1013-2. Interphase capacitor 1022 is connected to the IB phase path while switch 1021-3 is on. The interphase capacitor 1022 shares charge with the sample capacitor 1013-3. Interphase capacitor 1022 is connected to the QB phase path while switch 1021-4 is on. The interphase capacitor 1022 performs charge sharing with the sample capacitor 1013-4.

  With this configuration, the interphase capacitor 1022 performs charge holding and charge sharing between different paths. The detailed operation of the equalizer circuit 100 will be described later.

The clock generation circuit (control signal generation circuit) 103 generates a control signal based on the reference frequency signal (f _REF ) output from the reference frequency oscillating unit 13 (see FIG. 2), and outputs the control signal to the IQ mixer 101 and Supplied to the interphase connection unit 102.

The output buffers 104-1 to 104-4 have a continuous voltage change due to the accumulation of input charges in each of the four phases I phase, Q phase, IB phase, and QB phase, and between the sample capacitor 1013 and the interphase capacitor 1022. And an instantaneous voltage change due to charge sharing are input, and these voltage changes are directly or multiplied by a constant to output output voltage signals V _OUT (V _{OUT_I} , V _{OUT_Q} , V _{OUT_IB} , V _{OUT_QB} ) of each phase. .

[Control signal generated by clock generation circuit 103]
A control signal generated in the clock generation circuit 103 will be described. FIG. 5 is a timing chart of the control signal. The control signals S1 to S4 are composed of a pulse width Ts and a control signal cycle _TCK . Although FIG. 5 shows a rectangular clock, the equalizer circuit 100 operates with a clock with a rounded waveform.

As shown in FIG. 5, the clock generation circuit 103 has a DUTY ratio (= pulse width Ts / control signal cycle T _CK ) of 0.25, and the four-phase control signals S1 to S1 are shifted in phase by 90 degrees. S4 is supplied to the equalizer circuit 100.

In the case of direct conversion, the clock frequency f _CK (f _CK = 1 / T _CK ) of the control signal is determined by the frequency of the signal input to the equalizer circuit. For example, when the frequency of the input signal is 60 GHz, the clock frequency f _CK is 60 GHz.

[Operation of Equalizer Circuit 100]
Next, the operation in the equalizer circuit 100 will be described.

The equalizer circuit 100 performs charge sharing and charge accumulation for each cycle _TCK . The equalizer circuit 100 shares the following three types of charges.
(1-a) TA 1011 converts the input voltage signal _VIN into a current (hereinafter referred to as input charge).
(1-b) Charge held by the interphase capacitor 1022 (1-c) Charge held by the sample capacitor 1013

Equalizer circuit 100, based on the control signal _S 1 to S ₄ shown in FIG. 5, the control switch 1012-1～1012-4 and switch 1021-1～1021-4 (on / off), the following four The operation is performed within one cycle (1T _CK ), and these operations are repeated every cycle T _CK .

The first operation: During period control signal _{S 1} is high, the sample capacitor 1013-1 are connected to TA1011, the input charge is accumulated in the sample capacitor 1013-1. Immediately before this charge accumulation, the sample capacitor 1013-1 holds the charge one cycle before. Simultaneously with the accumulation of the input charge in the sample capacitor 1013-1, the interphase capacitor 1022 is connected to the sample capacitor 1013-3 to perform charge sharing.

Second operation: During period control signal _{S 2} is high, the sample capacitor 1013-2 are connected to TA1011, the input charge is accumulated in the sample capacitor 1013-2. Immediately before this charge accumulation, the sample capacitor 1013-2 holds the charge one cycle before. Simultaneously with the accumulation of the input charge in the sample capacitor 1013-2, the interphase capacitor 1022 is connected to the sample capacitor 1013-4 to perform charge sharing.

Third operation: During period control signal _{S 3} is high, the sample capacitor 1013-3 are connected to TA1011, the input charge is accumulated in the sample capacitor 1013-3. Immediately before this charge accumulation, the sample capacitor 1013-3 holds the charge one cycle before. Simultaneously with the accumulation of the input charge in the sample capacitor 1013-3, the interphase capacitor 1022 is connected to the sample capacitor 1013-1 to perform charge sharing.

Fourth operation: During period control signal _{S 4} is high, the sample capacitor 1013-4 are connected to TA1011, the input charge is accumulated in the sample capacitor 1013-4. Immediately before this charge accumulation, the sample capacitor 1013-4 holds the charge one cycle before. Simultaneously with the accumulation of the input charge in the sample capacitor 1013-4, the interphase capacitor 1022 is connected to the sample capacitor 1013-2 to perform charge sharing.

The equalizer circuit 100 sequentially repeats the first operation, the second operation, the third operation, and the fourth operation every cycle _TCK . By repeating the first operation to the fourth operation in order, the input charge is repeatedly accumulated in the order of the sample capacitors 1013-1, 1013-3, 1013-3, and 1013-4. The interphase capacitor 1022 is repeatedly connected in the order of the IB phase path, the QB phase path, the I phase path, and the Q phase path. The interphase capacitor 1022 sequentially performs charge sharing with the sample capacitors 1013-3, 1013-4, 1013-1, and 1013-2.

That is, in this case, the first switch (first interphase switch) 1021-1, the second switch (second interphase switch) 1021-2, the third switch (third interphase switch) 1021-3, The connection order of the switches of the fourth switch (fourth interphase switch) 1021-4 is ascending order from the Nth switch (N is an integer from 1 to 4). Then, after the fourth switch 1021-4, the first switch 1021-1 is connected to the four-phase connection path. When the switch 1021 is repeatedly connected to the four-phase connection path, the interphase capacitor 1022 is repeatedly connected to the four-phase connection path in the same order as the phase rotation order of I phase, Q phase, IB phase, and QB phase. Charge phase capacitor 1022, a sample capacitor 1013-3,1013-4,1013-1,1013-2, by performing the charge sharing in the _order, which is held in the sample capacitor 1013 input charge at _{T CK} intervals is accumulated The charge held in the interphase capacitor 1022 that repeats charge sharing at intervals of T _CK / 4 performs charge sharing.

  In this case, the timing of input charge accumulation in the sample capacitor 1013 and the charge sharing timing between the sample capacitor 1013 and the interphase capacitor 1022 are different in each sample capacitor 1013, but the order of accumulation of input charges and charge sharing are different. The order of is the same.

  Next, the first to fourth operations will be described mathematically with respect to the discrete system that is the core of the frequency characteristics.

式（１）において、左辺第１項は入力電荷に相当し、左辺第２項は相間キャパシタ１０２２に保持された電荷、つまり、１／４周期前の電荷共有により保持された電荷に相当する。虚数単位ｊは、相間キャパシタ１０２２が１／４周期ずれた電荷共有を行うことに起因する。左辺第３項はサンプル容量１０１１に保持された１周期前の電荷である。ｚ変換することにより、ｎ番目の入力電荷をＱ_ＩＮ（ｎ）＝（Ｃ_Ｓ＋Ｃ_ＩＭ）ＡＶ_ＩＮ（ｎ）とすると（Ａは入力の電荷蓄積によって決まる係数）、イコライザ回路１００の離散系のコアとなる伝達関数Ｈ_Ｄは、概略、式（２）によって表わされる。

ここで、ω_ｉｎは入力電圧信号の角周波数である。伝達関数Ｈ_Ｄに虚数単位ｊを実現することによって、中心に対して左右非対称な周波数特性を実現できる。 The capacitance value of the interphase capacitor 1022 is C _IM , the capacitance value of the sample capacitor 1013 is C _S , the nth (n: integer) input charge is q _in (n), and the nth and n−1th output voltages are v _{Assuming OUT} (n) and v _OUT (n−1), the outline of the nth (n: integer) charge sharing in the equalizer circuit 100 can be described by the difference equation of Expression (1).

In Equation (1), the first term on the left side corresponds to the input charge, and the second term on the left side corresponds to the charge held in the interphase capacitor 1022, that is, the charge held by charge sharing before a quarter cycle. The imaginary unit j is due to the fact that the interphase capacitor 1022 performs charge sharing with a ¼ period shift. The third term on the left side is the charge one cycle before held in the sample capacitor 1011. When the n-th input charge is set to Q _IN (n) = (C _S + C _IM ) AV _IN (n) by performing z conversion (A is a coefficient determined by charge accumulation of the input), the discrete system of the equalizer circuit 100 the transfer function _{H D} core is a schematic, represented by formula (2).

Here, ω _in is the angular frequency of the input voltage signal. By implementing the imaginary unit j in the transfer function H _D, it can be realized asymmetric frequency characteristic with respect to the center.

The frequency characteristics of the equalizer circuit 100 will be described. FIG. 6A is a diagram illustrating a circuit simulation result of the frequency characteristics of the equalizer circuit 100 according to the first embodiment. The horizontal axis in FIG. 6A indicates the output frequency, and the vertical axis indicates Gain. The output frequency is indicated by an input frequency −f _CK . FIG. 6A shows frequency characteristics of the equalizer circuit 100 when C _S is 50 fF, f _CK is 60 GHz, g _m is 10 mS, and C _IM is changed as a parameter in the range of 10 fF to 40 fF. Incidentally, the equalizer circuit 100 _fixes the _{C IM,} may be a parameter _{C S.}

As shown in FIG. 6A, the equalizer circuit 100 displays a gain peak with respect to the center when the control signals S ₃ , S ₄ , S ₁ , and S ₂ are respectively input to the terminals e to h of the interphase connection unit 102. A frequency characteristic shifted to the minus side can be realized.

Note that the equalizer circuit 100 according to the present embodiment has the control signals S ₃ , S ₂ , S at the terminals e to h of the interphase connecting section 102 as shown in the control signals in parentheses in FIGS. 4A and 4C. _1, when the S ₄ is input, having a different frequency characteristic.

When the control signals S ₃ , S ₂ , S ₁ , S ₄ are respectively input to the terminals e to h of the interphase connection section 102, the first switch (first interphase switch) 1021-1, the second switch ( (Second interphase switch) 1021-2, third switch (third interphase switch) 1021-3, and fourth switch (fourth interphase switch) 1021-4 are Mth (M is 1). To the switch in descending order. Then, after the first switch 1021-1, the fourth switch 1021-4 is connected to the four-phase connection path. When the switch 1021 is repeatedly connected to the four-phase connection path, the interphase capacitor 1022 is repeatedly connected in the order of the IB phase path, the Q phase path, the I phase path, and the QB phase path. In other words, the interphase capacitor 1022 is connected to the four-phase connection path in reverse order with respect to the order of phase rotation of the I phase, Q phase, IB phase, and QB phase.

  In this case, the order of charge sharing between the interphase capacitor 1022 and the sample capacitor 1013 is opposite to the order of accumulation of input charges in the sample capacitor 1013. Specifically, accumulation of input charge is repeatedly performed in the order of sample capacitors 1013-1, 1013-3, 1013-3, and 1013-4, while charge sharing is performed by the interphase capacitor 1022 and the sample capacitor 1013-3. 1013-2, 1013-1, and 1013-4 are repeatedly connected in this order.

Since the interphase capacitor 1022 is connected to the four-phase connection path in reverse order with respect to the phase rotation order of the I phase, Q phase, IB phase, and QB phase, the phase is shifted by 3/4 period (that is, -1/4 period). Charge sharing. As a result, the transfer function H _D of the equalizer circuit 100, the sign is inverted according to the imaginary unit j. By code according to imaginary unit j of the transfer function H _D is inverted, the equalizer circuit 100, a frequency characteristic obtained by shifting the Gain peak on the plus side can be realized with respect to the center. When the interphase capacitor 1022 is connected to the four-phase connection path in the positive order with respect to the phase rotation order, the imaginary unit is negative, and when the interphase capacitor 1022 is connected to the four-phase connection path in the reverse order with respect to the phase rotation order, The imaginary unit is positive.

FIG. 6B shows frequency characteristics when the control signals S ₃ , S ₂ , S ₁ , and S ₄ are respectively input to the terminals e to h of the interphase connection unit 102. The vertical axis, horizontal axis, and parameters of each element in FIG. 6B are the same as those in FIG. 6A. When the interphase capacitor 1022 is connected to a four-phase connection path in reverse order to the phase rotation order of I phase, Q phase, IB phase, and QB phase, as shown in FIG. A frequency characteristic in which the Gain peak is shifted to the plus side can be realized.

[effect]
As described above, according to the present embodiment, the interphase capacitor 1022 is sequentially connected to the four-phase connection path to perform charge sharing that is shifted by ¼ period (or −1/4 period). the imaginary unit j can be implemented in the function _{H D.} By implementing the imaginary unit j in the transfer function H _D, equalizer circuit 100 of the present embodiment, as shown in FIG. 6A, FIG. 6B, having asymmetrical frequency response with respect to the center. Therefore, the equalizer circuit of the present embodiment can realize a filter that can adjust the in-band deviation. That is, the equalizer circuit according to the present embodiment can perform an equalization process for reducing the in-band deviation caused by the frequency characteristic of the RF circuit as shown in FIG. 1A, for example.

  In this embodiment, since the conversion from the continuous time signal to the discrete time signal is not performed, the number of switches can be reduced as compared with the conventional discrete time analog circuit. Therefore, in this embodiment, even when a wide band pass characteristic exceeding several GHz is realized, the influence of the clock load and the parasitic capacitance can be suppressed. That is, the equalizer circuit 100 of the present embodiment is a circuit suitable for wideband operation.

  The equalizer circuit 100 can easily change the characteristics by making the sample capacitor 1013 and the interphase capacitor 1022 variable. As a result, for example, it is possible to adaptively change the characteristics with respect to changes in the communication environment such as changes in ambient temperature or power supply voltage, or the influence of variations in circuit elements.

  Examples of the configuration of the variable capacitor include a method of controlling the number of capacitors connected by a switch, and a method of changing a capacitance value by controlling a voltage value applied to a varactor capacitor by a voltage. The same applies to the following embodiments.

  Further, the switches 1012 and 1021 may be configured by transistors. In the case of manufacturing a transistor by a fine CMOS process, as a general transistor configuration, a configuration using an NMOS transistor, a configuration using a PMOS transistor, and a configuration of a complementary switch using NMOS and PMOS are known.

In the above description, in FIGS. 4A to 4C, the case where the charge accumulation in the sample capacitor 1013 and the charge sharing between the sample capacitor 1013 and the interphase capacitor 1022 are performed at different timings is shown. Is not limited to this. Charge accumulation and charge sharing may be performed at the same timing. When charge accumulation and charge sharing are performed at the same timing, control signals S ₁ , S ₂ , S ₃ , and S ₄ are input to the terminals e to h, respectively. That is, when shifting to the low frequency side, the terminals e to h may be S ₁ , S ₂ , S ₃ , S ₄ , or S ₂ , S ₃ , S ₄ , S ₁ , respectively. S ₃ , S ₄ , S ₁ , S ₂ , or S ₄ , S ₁ , S ₂ , S ₃ may be used.

Also, depending on the frequency characteristic to be realized may be output a voltage of a phase capacitor with a buffer interphase capacitor C _IM.

(Embodiment 2)
Next, a second embodiment of the present disclosure will be described. This embodiment is a circuit configuration in which a plurality of configurations of the equalizer circuit 100 of the first embodiment are connected.

[Configuration and Operation of Equalizer Circuit 200]
FIG. 7 is a diagram showing an example of the configuration of the equalizer circuit 200 according to the second embodiment. The equalizer circuit 200 shown in FIG. 7 includes IQ mixers 201-1 and 201-2, interphase connection sections 202-1 and 202-2, a clock generation circuit (control signal generation circuit) 203, and output buffers 204-1 to 204-1. 204-4. The clock generation circuit 203 is the same as the clock generation circuit 103 illustrated in FIG. 4A.

  The configurations of the IQ mixers 201-1 and 201-2 are the same as the configuration of the IQ mixer 101 shown in FIG. 4B. The configuration of the interphase connection sections 202-1 and 202-2 is the same as the configuration of the interphase connection section 102 shown in FIG. 4C. However, the control signal input to the interphase connecting section 202-1 and the control signal input to the 202-2 are different from each other.

Specifically, control signals S ₃ , S ₄ , S ₁ , and S ₂ are input to terminals e to h of the interphase connection section 202-1, respectively. In this case, the interphase capacitor 1022 of the interphase connection section 202-1 is repeatedly connected in the order of the IB phase path, the QB phase path, the I phase path, and the Q phase path. Then, the interphase capacitor 1022 of the interphase connection section 202-1 performs charge sharing in order with the sample capacitors 1013-3, 1013-4, 1013-1, and 1013-2 of the IQ mixer 201-1. That is, the first switch (first interphase switch) 1021-1, the second switch (second interphase switch) 1021-2, the third switch (third interphase switch) 1021-3, the fourth switch The connection order of the switches (fourth interphase switch) 1021-4 is ascending order from the Nth switch (N is an integer from 1 to 4). Then, after the fourth switch 1021-4, the first switch 1021-1 is connected to the four-phase connection path. When the switch 1021 is repeatedly connected to the four-phase connection path, the interphase capacitor 1022 of the interphase connection section 202-1 is connected in four phases in the same order as the phase rotation order of I phase, Q phase, IB phase, and QB phase. Connect to the route. In the circuit composed of the IQ mixer 201-1 and the interphase connection section 202-1, the order of accumulation of input charges and the order of charge sharing are the same.

On the other hand, control signals S ₃ , S ₂ , S ₁ , and S ₄ are input to the terminals e to h of the interphase connection section 202-2, respectively. In this case, the interphase capacitor 1022 of the interphase connection section 202-2 is repeatedly connected in the order of the IB phase path, the Q phase path, the I phase path, and the QB phase path. Then, the interphase capacitor 1022 of the interphase connection unit 202-1 sequentially performs charge sharing with the sample capacitors 1013-3, 1013-3, 1013-1, and 1013-4 of the IQ mixer 201-2. That is, the first switch (first interphase switch) 1021-1, the second switch (second interphase switch) 1021-2, the third switch (third interphase switch) 1021-3, the fourth switch Each switch of the switch (fourth interphase switch) 1021-4 is connected in descending order from the Mth switch (M is an integer from 1 to 4). Then, after the first switch 1021-1, the fourth switch 1021-4 is connected to the four-phase connection path. When the switch 1021 is repeatedly connected, the interphase capacitor 1022 of the interphase connection section 202-1 is connected to the four-phase connection path in reverse order with respect to the phase rotation order of I phase, Q phase, IB phase, and QB phase. . In the circuit configured by the IQ mixer 201-2 and the interphase connection section 202-2, the charge sharing order is opposite to the input charge accumulation order.

  In the equalizer circuit 200, the connection order of the switches 1021 in the interphase connection section 202-1 connected to the IQ mixer 201-1 and the interphase connection section 202-2 connected to the IQ mixer 201-2 is different from each other.

  Since the specific operation of the equalizer circuit 200 is the same as the operation of the equalizer circuit 100 described in the first embodiment, the description thereof is omitted.

  In the circuit composed of the IQ mixer 201-1 and the interphase connection section 202-1, the interphase capacitor 1022 is connected to the four-phase connection path in the same order as the phase rotation order of I phase, Q phase, IB phase, and QB phase. As a result of the connection, as described in the first embodiment, it is possible to realize frequency characteristics in which the gain peak is shifted to the minus side with respect to the center. Further, in the circuit configured by the IQ mixer 201-2 and the interphase connection section 202-2, the interphase capacitor 1022 has four phases in reverse order with respect to the phase rotation order of I phase, Q phase, IB phase, and QB phase. Therefore, as described in the first embodiment, it is possible to realize a frequency characteristic in which the gain peak is shifted to the plus side with respect to the center.

  In FIG. 7, in each of the output buffers 204-1 to 204-4, the phase of the signal output from the IQ mixer 201-1 is opposite to the phase of the signal output from the IQ mixer 201-2. Connect to the route. The output buffers 204-1 to 204-4 are configured to output a difference between two input signals. For example, the output buffer 204-1 is connected to an I-phase path from which an I-phase signal is output from the IQ mixer 201-1 and an IB-phase path from which an IB-phase signal is output from the IQ mixer 201-2. The difference between the I-phase signal and the IB-phase signal is output. That is, each of the output buffers 204-1 to 204-4 is configured to output a difference between the reverse phase signals.

  That is, the output buffers 204-1 to 204-4 output the difference between the negative phase signals of the circuit that shifts the frequency characteristic to the minus side and the circuit that shifts the frequency characteristic to the plus side in the first embodiment.

  Here, the configuration of the output buffer that outputs the difference between the anti-phase signals is shown, but the output buffer is configured so that the difference between the in-phase signals, the sum of the in-phase signals, and the sum of the anti-phase signals are output. Also good.

  For example, each of the output buffers that output the sum of the in-phase signals has a path in which the phase of the signal output from the IQ mixer 201-1 and the phase of the signal output from the IQ mixer 201-2 are in phase. You may connect. The output buffer outputs the sum of the two input signals. For example, the output buffer 204-1 is connected to an I-phase path from which an I-phase signal is output from the IQ mixer 201-1 and an I-phase path from which an I-phase signal is output from the IQ mixer 201-2. You may output the sum of the I-phase signal which each IQ mixer output.

Next, the frequency characteristics of the equalizer circuit 200 will be specifically described. FIG. 8 is a diagram illustrating a circuit simulation result of the frequency characteristics of the equalizer circuit 200 according to the second embodiment. The horizontal axis in FIG. 8 indicates the output frequency, and the vertical axis indicates Gain. The output frequency is indicated by an input frequency −f _CK . Further, FIG. 8 shows C _S = 50 fF, f _CK = 60 GHz, g _m = 10 mS, and C _IM1 = 30 fF and C _IM2 = 40 fF (solid line (A) in FIG. 8) from C _IM1 = 30 fF and C _IM2 = 40 fF. _This is a frequency characteristic of the equalizer circuit 200 when _IM1 = 40 fF and C _IM2 = 30 fF (broken line (B) in FIG. 8). Here, the capacitance value of the interphase capacitor 1022 in the interphase connection section 202-1 is C _IM1 , and the capacitance value of the interphase capacitor 1022 in the interphase connection section 202-1 is C _IM2 .

  As shown in FIG. 8, the equalizer circuit 200 can realize a frequency characteristic having a gain peak shifted to the minus side with respect to the center and a gain peak shifted to the plus side. That is, the equalizer circuit 200 can realize a left-right asymmetric frequency characteristic having a ripple in the passband.

The equalizer circuit 200 may fix C _IM1 and C _IM2 and use C _S1 and C _S2 as parameters. C _S1 is a capacity value of the IQ mixer 201-1. C _S2 is the capacity value of the IQ mixer 201-2. 7 illustrates the equalizer circuit 200 in which the two equalizer circuits 100 illustrated in FIG. 4A are connected as an example, but the equalizer circuit 200 may be connected to three or more equalizer circuits 100.

  In FIG. 7, the order of the control signals input to the interphase connection section 202-1 and the order of the control signals input to the interphase connection section 202-2 are reversed. However, depending on the frequency characteristics to be realized, the order of the control signals input to the interphase connection section 202-1 and the order of the control signals input to the interphase connection section 202-2 may be the same order.

  Depending on the frequency characteristics to be corrected, the TA inside the IQ mixer (TA1011 in FIG. 4B) may be shared.

[effect]
As described above, according to the present embodiment, it is possible to realize a left-right asymmetric frequency characteristic having a ripple in the passband by connecting a plurality of configurations of the first embodiment. Thereby, the equalizer circuit 200 according to the present embodiment can reduce the in-band deviation with respect to the frequency characteristics of the multi-stage RF amplifiers having different gain peaks and the frequency characteristics of the propagation path having ripples in the band. .

(Embodiment 3)
Next, a third embodiment of the present disclosure will be described. The equalizer circuit according to the present embodiment is configured to more easily realize the same characteristics as those of the equalizer circuit 100 according to the first embodiment.

[Configuration and Operation of Equalizer Circuit 300]
FIG. 9 is a diagram showing an example of the configuration of the equalizer circuit 300 according to the third embodiment. An equalizer circuit 300 illustrated in FIG. 9 includes an IQ mixer 301 including an interphase capacitor 302, a clock generation circuit 303, and output buffers 304-1 to 304-4. The configuration of the equalizer circuit 300 is the same as that of the equalizer circuit 100 except that the interphase capacitor 302 is connected to the output side of the TA 3011 in the IQ mixer 301 in place of the interphase connection section 102 in the equalizer circuit 100 shown in FIGS. 4A to 4C. Since it is the same structure as, detailed explanation is omitted. The clock generation circuit 303 is the same as the clock generation circuit 103 illustrated in FIG. 4A.

  This embodiment is different from the first embodiment in that the interphase capacitor 302 is connected to the output side of the TA 3011 in the IQ mixer 301. Since the interphase capacitor 302 is included in the IQ mixer 301, the interphase connection unit described in the first embodiment is not included in the equalizer circuit 300 in the present embodiment.

  The interphase capacitor 302 holds the charge of a quarter cycle before as an initial state before the operation of the equalizer circuit 300 is started.

[Operation of Equalizer Circuit 300]
Next, the operation in the equalizer circuit 300 will be described.

Similarly to the equalizer circuit 100 of the first embodiment, the equalizer circuit 300 performs charge sharing and charge accumulation for each cycle _TCK . The equalizer circuit 300 shares the following three types of charges.
(2-a) Charge obtained by the TA 3011 converting the input voltage signal _VIN into a current (hereinafter referred to as input charge)
(2-b) Charge held by the interphase capacitor 302 (2-c) Charge held by the sample capacitor 3013

The equalizer circuit 300 performs the following four operations within one cycle (1T _CK ) by controlling the switches 3012-1 to 3012-4 based on the control signals S _{1 to} S ₄ shown in FIG. And repeat these operations every cycle _TCK .

The first operation: During period control signals _{S 1} is high, the input charge is accumulated in the phase capacitor 302 and the sample capacitor 3013-1. Immediately before this charge accumulation, the interphase capacitor 302 holds a charge of ¼ period before, and the sample capacitor 3013-1 stores the charge of one period before. Simultaneously with the accumulation of the input charge, the interphase capacitor 302 and the sample capacitor 3013-1 share the charge.

Second operation: During period control signal _{S 2} is high, the input charge is accumulated in the phase capacitor 302 and the sample capacitor 3013-2. Immediately before this charge accumulation, the interphase capacitor 302 holds the charge one quarter cycle before, and the sample capacitor 3013-2 stores the charge one cycle ago. Simultaneously with the accumulation of the input charge, the interphase capacitor 302 and the sample capacitor 3013-2 share the charge.

Third operation: During period control signal _{S 3} is high, the input charge is accumulated in the phase capacitor 302 and the sample capacitor 3013-3. Immediately before this charge accumulation, the interphase capacitor 302 holds the charge one quarter cycle before, and the sample capacitor 3013-3 stores the charge one cycle ago. Simultaneously with the accumulation of the input charge, the interphase capacitor 302 and the sample capacitor 3013-3 share the charge.

Third operation: During period control signal _{S 4} is high, the input charge is accumulated in the phase capacitor 302 and the sample capacitor 3013-4. Immediately before this charge accumulation, the interphase capacitor 302 holds the charge one quarter cycle before, and the sample capacitor 3013-4 stores the charge one cycle ago. Simultaneously with the accumulation of the input charge, the interphase capacitor 302 and the sample capacitor 3013-4 share the charge.

  The output buffers 304-1 to 304-4 have a continuous voltage change in the accumulation of input charges in each of the four phases I phase, Q phase, IB phase, and QB phase, and instantaneous due to charge sharing between the sample capacitor and the interphase capacitor. The voltage change is inputted, and the voltage change is output as it is or multiplied by a constant to output an output voltage signal.

The equalizer circuit 300 repeats the first operation, the second operation, the third operation, and the fourth operation every cycle _TCK . By repeating the first operation to the fourth operation, the input charge is repeatedly accumulated in the order of the sample capacitors 3013-1, 3013-2, 3013-3, and 3013-4. Then, the interphase capacitor 302 performs charge sharing in order with the sample capacitors 3013-1, 3013-2, 3013-3, and 3013-4. In this case, the input charge accumulation order and the charge sharing order are the same, and the input charge accumulation timing and the charge sharing timing are also the same.

For the first to fourth operations, mathematical expressions relating to the discrete system that is the core of the frequency characteristics are the same as those in the first embodiment. Thus as in the first embodiment, the complex coefficient j can be realized in the transfer function H _D. Therefore, the equalizer circuit 300 can realize the same frequency characteristics as in FIG. 6A.

[effect]
As described above, according to the present embodiment, it is possible to realize the filter shown in FIG. 6A that has a frequency characteristic asymmetric with respect to the center and that can adjust the in-band deviation. That is, according to the present embodiment, for example, the in-band deviation caused by the frequency characteristics of the RF circuit as shown in FIG. 1A can be reduced. Further, by connecting the interphase capacitor 302 to the output of the TA 3011, the same characteristics as those of the first embodiment can be realized with a simpler configuration than that of the first embodiment.

(Embodiment 4)
Next, a fourth embodiment of the present disclosure will be described. The present embodiment has a circuit configuration in which a plurality of interphase connection portions 102 of the equalizer circuit 100 of the first embodiment are connected.

[Configuration of Equalizer Circuit 400]
FIG. 10 is a diagram illustrating an example of the configuration of the equalizer circuit 400 according to the fourth embodiment. An equalizer circuit 400 illustrated in FIG. 10 includes an IQ mixer 401, interphase connection units 402-1 and 402-2, a clock generation circuit 403, and output buffers 404-1 to 404-4. The configuration of the IQ mixer 401 is the same as that of the IQ mixer 101 shown in FIG. 4B. The configuration of the interphase connection units 402-1 and 402-2 is the same as the configuration of the interphase connection unit 102 illustrated in FIG. 4C. The clock generation circuit 403 is similar to the clock generation circuit 103 illustrated in FIG. 4A. The output buffers 404-1 to 404-4 are the same as the output buffers 104-1 to 104-4 shown in FIG. 4A, respectively.

  That is, the configuration of the equalizer circuit 400 is a configuration in which one interphase connecting portion is added to the equalizer circuit 100 described in the first embodiment.

[Configuration of Equalizer Circuit 500]
FIG. 11 is a diagram showing an example of the configuration of the equalizer circuit 500 according to the fourth embodiment. An equalizer circuit 500 illustrated in FIG. 11 includes an IQ mixer 501, interphase connection units 502-1, 502-2, and 502-3, a clock generation circuit 503, and output buffers 504-1 to 504-4. The configuration of the IQ mixer 501 is the same as the configuration of the IQ mixer 101 shown in FIG. 4B. The configuration of the interphase connection sections 502-1, 502-2, and 502-3 is the same as that of the interphase connection section 102 shown in FIG. 4C. The configuration of the clock generation circuit 503 is the same as that of the clock generation circuit 103 illustrated in FIG. 4A. The output buffers 504-1 to 504-4 have the same configuration as the output buffers 104-1 to 104-4 shown in FIG. 4A, respectively.

  That is, the configuration of the equalizer circuit 500 is a configuration in which two interphase connecting portions are added to the equalizer circuit 100 described in the first embodiment.

[Configuration of Equalizer Circuit 600]
FIG. 12 is a diagram showing an example of the configuration of the equalizer circuit 600 according to the fourth embodiment. An equalizer circuit 600 illustrated in FIG. 12 includes an IQ mixer 601, interphase connection units 602-1, 602-2, 602-3, and 602-4, a clock generation circuit 603, output buffers 604-1 to 604-4, Have The configuration of the IQ mixer 601 is the same as the configuration of the IQ mixer 101 shown in FIG. 4B. The configuration of the interphase connection portions 602-1 to 602-4 is the same as the configuration of the interphase connection portion 102 illustrated in FIG. 4C. The clock generation circuit 603 is similar to the clock generation circuit 103 illustrated in FIG. 4A. The output buffers 604-1 to 604-4 are the same as the output buffers 104-1 to 104-4 shown in FIG. 4A, respectively.

  That is, the configuration of the equalizer circuit 600 is a configuration in which three interphase connecting portions are added to the equalizer circuit 100 shown in the first embodiment.

  Control signals input to a plurality of interphase connection portions in the equalizer circuits 400, 500, and 600 are different in each interphase connection portion. Therefore, the connection timing of the switches 1021-1 to 1021-4 of the interphase connection units included in the equalizer circuits 400, 500, and 600 differs among the interphase connection units. For example, in the equalizer circuit 400, since the control signal S1 is input to the terminal e of the interphase connection unit 402-1, the switch 1021-1 of the interphase connection unit 402-1 is in a period during which the control signal S1 is high. Connected. On the other hand, since the control signal S2 is input to the terminal e of the interphase connection section 402-2, the switch 1021-1 of the interphase connection section 402-2 is connected during a period in which the control signal S2 is high. That is, in the equalizer circuit 400, the switches 1021-1 included in each of the interphase connection units 402-1 and 402-2 are connected at different timings. The same applies to the switches 1021-2, 1021-3, and 1021-4 included in the interphase connection units 402-1 and 402-2. The same applies to the equalizer circuits 500 and 600.

  While the connection timings of the switches 1021-1 to 1021-4 of the interphase connection units included in the equalizer circuits 400, 500, and 600 are different among the interphase connection units, the switches 1021-1 to 1021-4 of the interphase connection units are The connection order of repeated connection is the same. As a result, the connection order of the interphase capacitors is the same order as the phase rotation order of I phase, Q phase, IB phase, and QB phase. The order of charge sharing between the interphase capacitor and the sample capacitor is the same as the order of accumulation of input charges in the sample capacitor.

  For example, in the case of the equalizer circuit 600, the input charge is repeatedly accumulated in the order of the sample capacitors 1013-1, 1013-3, 1013-3, and 1013-4.

  The interphase capacitor 1022 of the interphase connection unit 602-1 is repeatedly connected in the order of the sample capacitors 1013-1, 1013-3, 1013-3, and 1013-4 of the IQ mixer 601 to perform charge sharing. The interphase capacitor 1022 of the interphase connection unit 602-2 is repeatedly connected in the order of the sample capacitors 1013-2, 1013-3, 1013-4, and 1013-1 of the IQ mixer 601 to perform charge sharing. The interphase capacitor 1022 of the interphase connection unit 602-3 is repeatedly connected in the order of the sample capacitors 1013-3, 1013-4, 1013-1, and 1013-2 of the IQ mixer 601 to perform charge sharing. The interphase capacitor 1022 of the interphase connection unit 602-4 is repeatedly connected in the order of the sample capacitors 1013-4, 1013-1, 1013-3, and 1013-3 of the IQ mixer 601 to perform charge sharing.

  In the equalizer circuits 400, 500, and 600, the connection order of the interphase capacitors is the same as the order of phase rotation of the I phase, the Q phase, the IB phase, and the QB phase. As described in the first embodiment, it is possible to realize a frequency characteristic in which the gain peak is shifted to the minus side with respect to the center. And when the number of connection of an interphase connection part is increased, the amount of shifts can be increased.

  In addition, when the control signal that connects the interphase capacitor in the reverse order to the phase rotation order of I phase, Q phase, IB phase, and QB phase is input to the interphase connection section, the frequency characteristics of the equalizer circuit are It is possible to shift the gain peak to the plus side.

Specifically, the frequency characteristics of the equalizer circuits 400, 500, and 600 will be described. FIG. 13 is a diagram illustrating a result of circuit simulation of the frequency characteristics of the equalizer circuits 400, 500, and 600 according to the fourth embodiment. The horizontal axis in FIG. 13 indicates the output frequency, and the vertical axis indicates the gain normalized by the maximum gain. The output frequency is indicated by an input frequency −f _CK . FIG. 13 also shows the frequency characteristics of the equalizer circuit 100 shown in the first embodiment as a comparative example. FIG. 13 shows the frequency characteristics of the equalizer circuits 100, 400, 500, and 600 under the same conditions. The conditions are C _S = 50 fF, f _CK = 60 GHz, g _m = 10 mS, and the capacitance value C _IM = 40 fF of the interphase capacitor.

  As shown in FIG. 13, the greater the number of inter-phase connection portions of the equalizer circuit, the greater the number of inter-phase capacitor connections in the I-phase, Q-phase, IB-phase, and QB-phase systems. , The shift amount of the Gain peak with respect to the center increases.

[effect]
As described above, according to the present embodiment, the gain peak is shifted in the frequency direction even with the same circuit element value (capacitance value of the sample capacitor and the interphase capacitor) by connecting a plurality of interphase connection portions to the equalizer circuit. The amount can be increased.

(Embodiment 5)
Next, a fifth embodiment of the present disclosure will be described. This embodiment has a circuit configuration in which a plurality of equalizer circuits of the second and fourth embodiments are connected.

[Configuration and Operation of Equalizer Circuit 700]
FIG. 14 is a diagram showing an example of the configuration of an equalizer circuit 700 according to the fifth embodiment. An equalizer circuit 700 illustrated in FIG. 14 includes IQ mixers 701-1, 701-2, and 701-3, interphase connection units 702-1 to 702-6, a clock generation circuit 703, and output buffers 704-1 to 704-. 8 and. The clock generation circuit 703 is similar to the clock generation circuit 103 illustrated in FIG. 4A.

  The configuration of the IQ mixer (first converter) 701-1, IQ mixer (second converter) 701-2, and IQ mixer (third converter) 701-3 is the IQ mixer 101 shown in FIG. 4B. It is the same as that of the structure. The configuration of the interphase connection portions 702-1 to 702-6 is the same as the configuration of the interphase connection portion 102 shown in FIG. 4C. However, the interphase connection section (first interphase connection section) 702-1, the interphase connection section (second interphase connection section) 702-2, the interphase connection section 702-3, the interphase connection section 702-4, Control signals input to the interphase connection section 702-5 and the interphase connection section 702-6 are different from each other.

  The output buffers 704-1 to 704-8 are configured to output a difference between two input signals. In the case of FIG. 14, the output buffers 704-1 to 704-8 are configured to output the difference between the reverse phase signals.

  In the equalizer circuit 700, the configuration including the IQ mixers 701-1 and 701-2, the interphase connection units 702-1 and 702-2, and the output buffers 704-1 to 704-4 is the equalizer circuit according to the second embodiment. 200.

  Further, in the equalizer circuit 700, the configuration including the IQ mixer 701-3 and the interphase connecting sections 702-3 to 702-6 is the same as that of the equalizer circuit 600 of the fourth embodiment except for the output buffer.

  That is, the equalizer circuit 700 according to the present embodiment has a configuration in which the equalizer circuit 200 according to the second embodiment and the equalizer circuit 600 according to the fourth embodiment are connected in parallel. The equalizer circuit 200 according to the second embodiment has a configuration in which two equalizer circuits 100 according to the first embodiment are connected. That is, the equalizer circuit 700 according to the present embodiment has a configuration in which three equalizer circuits are connected. Note that the operation of the equalizer circuit 700 is the same as that described in the first embodiment and the like, and thus detailed description thereof is omitted.

  The equalizer circuit 700 according to the present embodiment has a configuration in which the difference between the negative phase signal of the equalizer circuit 200 of the second embodiment and the negative phase signal of the equalizer circuit 400 of the fourth embodiment is output.

  Here, the output buffer configuration for outputting the difference between the anti-phase signals is shown, but the output buffer may be configured so that the difference between the in-phase signals, the sum of the in-phase signals, and the sum of the anti-phase signals are output. .

  Further, depending on the frequency characteristics to be corrected, the TA inside the IQ mixer may be shared.

Specifically, the frequency characteristics of the equalizer circuit 700 will be described. FIG. 15 is a diagram illustrating a result of circuit simulation of frequency characteristics of the equalizer circuit 700 according to the fifth embodiment. The horizontal axis in FIG. 15 indicates the output frequency, and the vertical axis indicates Gain. The output frequency is indicated by an input frequency −f _CK . Also, the transconductance values of TA in the IQ mixers 701-1 to 701-3 are assumed to be g _m1 , g _m2 , and g _m3 , respectively. The capacitance value of the phase capacitors in interphase connecting portion 702-1～702-3, and _{C IM1, C IM2, C IM3,} respectively. The capacitance value of the phase capacitors in interphase connecting portion 702-4～702-6, like the interphase connecting portion _702-3, a _{C IM3.} The circuit simulation of FIG. 15 is performed when C _S = 50 fF, f _CK = 60 GHz, C _IM1 = 30 fF, C _IM2 = 40 fF, C _IM3 = 20 fF, and when g _m1 , g _m2 , and g _m3 are changed in multiple ways. The frequency characteristics are shown. The solid line (A) in FIG. 15 shows frequency characteristics when g _m1 = 10 mS, g _m2 = 5 mS, and g _m3 = 30 mS. The broken line (B) in FIG. 15 shows the frequency characteristics when g _m1 = g _m2 = g _m3 = 10 mS. The broken line (C) in FIG. 15 shows the frequency characteristics when g _m1 = 5 mS, g _m2 = 10 mS, and g _m3 = 30 mS. As shown in FIG. 15, it can be seen that a plurality of ripples are obtained in the frequency characteristics by connecting three equalizer circuits.

[effect]
As described above, according to the present embodiment, by connecting a plurality of equalizer circuits that perform periodic time-varying continuous time processing, it is possible to realize a left-right asymmetric frequency characteristic having a ripple in the passband. . As a result, the in-band deviation can be reduced by the present embodiment even when ripples appear in the band due to the frequency characteristics of multi-stage RF amplifiers having different gain peaks or propagation channels.

  As an example of the present embodiment, a configuration in which the equalizer circuit 200 of the second embodiment (a configuration in which two equalizer circuits 100 of the first embodiment are connected) and the equalizer circuit 600 of the fourth embodiment are connected in parallel. However, the number of equalizer circuits 100 of the first embodiment and the number of equalizer circuits 600 of the fourth embodiment are not limited to this. The left shift (minus shift), right shift (plus shift), and the number of interphase connections may be arbitrarily changed. That is, a plurality of equalizer circuits having an arbitrary number of interphase connection portions may be prepared in parallel and the outputs may be combined. Depending on the environment, the frequency characteristics may be changed by changing the number of equalizer circuits to be used, the number of interphase connections, the left shift / right shift.

(Embodiment 6)
Embodiment 6 of the present disclosure will be described. In the present embodiment, the equalizer circuit of each embodiment has a differential configuration including two systems of a normal phase and a reverse phase. When the equalizer circuit has a differential configuration, by connecting the equalizer circuit shown in each embodiment to each of the positive phase and the negative phase, the same effect as the effect of each embodiment described above can be obtained. Can do.

  Further, when the equalizer circuit has a differential configuration, the connection position of the interphase capacitor is changed with respect to the four-phase connection paths of the I-phase path, the Q-phase path, the IB-phase path, and the QB-phase path of each of the positive phase and the reverse phase. . Accordingly, the correlation capacitor performs charge sharing that is shifted by 3/4 period (that is, -1/4 period) while being connected in the same order as the phase rotation order of I phase, Q phase, IB phase, and QB phase. Can do. As a result, in the transfer function of the equalizer circuit, the sign relating to the imaginary unit is inverted, so that an equalizer circuit having a frequency characteristic in which the Gain peak is shifted to the plus side with respect to the center can be realized. Hereinafter, referring to FIG. 16, equalizer circuit 100 shown in the first embodiment has a differential configuration, and the correlation capacitors are connected in the same order as the phase rotation order of I phase, Q phase, IB phase, and QB phase. However, an example in which charge sharing that is shifted by 3/4 period (that is, -1/4 period) is performed will be described.

  FIG. 16 is a diagram showing an example of an equalizer circuit 800 according to the sixth embodiment. The equalizer circuit 800 has a differential configuration of the equalizer circuit 100 according to the first embodiment. In addition, the line which shows the connection in terminal T1-T4 of FIG. 16, and terminal T1B-T4B is abbreviate | omitted for convenience of explanation.

The TA 8011 converts the input voltage signal _VIN , which is an analog signal, into two currents of positive phase (plus (+) side in FIG. 16) and opposite phase (minus (−) side in FIG. 16). ,Output. Hereinafter, the configuration provided on the side where the normal phase current is output is referred to as a normal phase system, and the configuration provided on the side where the negative phase current is output is referred to as a reverse phase system.

  In the positive phase system, the switches 8012-1 to 8012-4, the sample capacitors 8013-1 to 8013-4, and the output buffers 804-1 to 804-4 are the switches 1012-1 to 101-2 shown in FIGS. 4A and 4B, respectively. 1012-4, sample capacitors 1013-1 to 1013-4, and output buffers 104-1 to 104-4. As in the first embodiment, a path through which an I-phase signal is output, a path through which a Q-phase signal is output, a path through which an IB-phase signal is output, and a QB-phase signal are output in the positive-phase system. The paths are referred to as the I-phase path, Q-phase path, IB-phase path, and QB-phase path of the positive-phase system, respectively.

  In the reverse phase system, the switches 8012-5 to 8012-8, the sample capacitors 8013-5 to 8013-8, and the output buffers 804-5 to 804-8 are respectively connected to the switches 1012-1 to 1012-1 shown in FIGS. 4A and 4B. 1012-4, sample capacitors 1013-1 to 1013-4, and output buffers 104-1 to 104-4. As in the first embodiment, a path for outputting an I-phase signal, a path for outputting a Q-phase signal, a path for outputting an IB-phase signal, and a QB-phase signal are output in a reverse phase system. The paths are referred to as an I-phase path, a Q-phase path, an IB-phase path, and a QB-phase path of the reverse phase system, respectively.

  The clock generation circuit 803 is the same as the clock generation circuit 103 shown in FIG. 4A and supplies the four-phase control signals S1, S2, S3, and S4 shown in FIG.

  The configuration of the interphase connection units 802-1 and 802-2 is the same as the configuration of the interphase connection unit 102 illustrated in FIG. 4C. However, the connection positions of the terminals T1 to T4 and T1B to T4B of the interphase connection sections 802-1 and 802-2 are different from the connection positions of the terminals T1 to T4 in the interphase connection section 102. Next, the operation of the equalizer circuit 800 based on the difference in the connection positions of the terminals of the interphase connection section will be described.

The equalizer circuit 800 performs the following four operations by controlling the switches 8012-1 to 8012-8 and the switches 8021-1 to 8021-8 based on the control signals S _{1 to} S ₄ shown in FIG. Are performed within one period (1T _CK ), and these operations are repeated every period T _CK .

The first operation: During period control signal _{S 1} is high, the sample capacitor 8013-1 is connected to the positive phase output side of the TA8011, the input charge is accumulated in the sample capacitor 8013-1. In addition, the sample capacitor 8013-5 is connected to the reverse phase output side of TA8011, and the input charge is accumulated in the sample capacitor 8013-5. Immediately before this charge accumulation, each of the sample capacitors 8013-1 and 8013-5 holds the charge of one cycle before. Simultaneously with the accumulation of input charges into the sample capacitors 8013-1 and 8013-5, the interphase capacitor 802-1 is connected to the sample capacitor 801-3, and the interphase capacitor 802-2 is connected to the sample capacitor 801-3, respectively. Charge sharing.

Second operation: During period control signal _{S 2} is high, the sample capacitor 8013-2 is connected to the positive phase output side of the TA8011, the input charge is accumulated in the sample capacitor 8013-2. Further, the sample capacitor 8013-6 is connected to the reverse phase output side of TA8011, and the input charge is accumulated in the sample capacitor 8013-6. Immediately before this charge accumulation, each of the sample capacitors 8013-2 and 8013-6 holds the charge of one cycle before. Simultaneously with the accumulation of input charges in the sample capacitors 8013-2 and 8013-6, the interphase capacitor 8022-1 is connected to the sample capacitor 8013-8, the interphase capacitor 8022-2 is connected to the sample capacitor 8013-4, respectively. Charge sharing.

Third operation: During period control signal _{S 3} is high, the sample capacitor 8013-3 is connected to the positive phase output side of the TA8011, the input charge is accumulated in the sample capacitor 8013-3. In addition, the sample capacitor 8013-7 is connected to the reverse phase output side of TA8011, and the input charge is accumulated in the sample capacitor 8013-7. Immediately before this charge accumulation, the sample capacitors 8013-3 and 8013-7 hold the charge of one cycle before. Simultaneously with the accumulation of input charges into the sample capacitors 8013-3 and 8013-7, the interphase capacitor 8022-1 is connected to the sample capacitor 8013-1, and the interphase capacitor 8022-2 is connected to the sample capacitor 8013-5, respectively. Charge sharing.

Fourth operation: During period control signal _{S 4} is high, the sample capacitor 8013-4 is connected to the positive phase output side of the TA8011, the input charge is accumulated in the sample capacitor 8013-4. Further, the sample capacitor 8013-8 is connected to the reverse phase output side of the TA 8011, and the input charge is accumulated in the sample capacitor 8013-8. Immediately before this charge accumulation, the sample capacitors 8013-4 and 8013-8 hold the charge of one cycle before. Simultaneously with the accumulation of input charges in the sample capacitors 8013-4 and 8013-8, the interphase capacitor 8022-1 is connected to the sample capacitor 8013-6, and the interphase capacitor 8022-2 is connected to the sample capacitor 8013-2, respectively. Charge sharing.

The equalizer circuit 800 sequentially repeats the first operation, the second operation, the third operation, and the fourth operation every cycle _TCK . By repeating the first operation to the fourth operation in order, the input charge accumulation in the positive phase system is repeated in the order of the sample capacitors 8013-1, 8013-2, 8013-3, and 8013-4. The interphase capacitor 8022-1 is connected to the four-phase connection path repeatedly in the order of the IB phase path of the normal phase system, the QB phase path of the reverse phase system, the I phase path of the positive phase system, and the Q phase path of the reverse phase system. To do. The interphase capacitor 8022-1 performs charge sharing in order with the sample capacitors 8013-3, 8013-8, 8013-1, and 8013-6. The interphase capacitor 8022-2 is connected to the four-phase connection path repeatedly in the order of the IB phase path of the negative phase system, the QB phase path of the positive phase system, the I phase path of the negative phase system, and the Q phase path of the positive phase system. To do. The interphase capacitor 8022-2 performs charge sharing with the sample capacitors 8013-7, 8013-4, 8013-5, and 8013-2 in this order.

  In the normal phase system and the reverse phase system, the phases differ from each other by 180 ° in each path. For example, the phase of the signal in the QB phase path of the negative phase system is equivalent to the phase of the Q phase signal in the positive phase system. The phase of the signal in the QB phase path of the normal phase system is equivalent to the phase of the signal in the Q phase path of the negative phase system. That is, the connection order in which the interphase capacitor 8022-1 is repeatedly connected in the order of the IB phase path of the normal phase system, the QB phase path of the reverse phase system, the I phase path of the positive phase system, and the Q phase path of the reverse phase system is This is equivalent to the connection order in which the capacitor 8022-1 is connected in the order of the IB phase path of the positive phase system, the Q phase path of the positive phase system, the I phase path of the positive phase system, and the QB phase path of the positive phase system. The same applies to the interphase capacitor 8022-2. Therefore, the interphase capacitor can perform charge sharing that is shifted by 3/4 period (that is, -1/4 period) while being connected in the same order as the phase rotation order of I phase, Q phase, IB phase, and QB phase. it can. As a result, in the transfer function of the equalizer circuit 800 according to the sixth embodiment, the frequency characteristic in which the Gain peak is shifted to the plus side with respect to the center can be realized by inverting the sign relating to the imaginary unit.

(Embodiment 7)
A seventh embodiment of the present disclosure will be described. In the present embodiment, a clock (control signal) different from that of the first embodiment is input to the IQ mixer 101 and the interphase connecting section 102 of the equalizer circuit 100 of the first embodiment.

[Configuration and Operation of Equalizer Circuit 900]
FIG. 17A is a diagram showing an exemplary configuration of the equalizer circuit 900 according to the seventh embodiment. The IQ mixer 101, the interphase connection unit 102, and the output buffer 104 of the equalizer circuit 900 have the same configuration as that of the equalizer circuit 100 of FIG. 4A. The equalizer circuit 900 of FIG. 17A is different from the equalizer circuit 100 of FIG. 4A in that the equalizer circuit 900 includes two clock generation circuits (clock generation circuit 903-1 and clock generation circuit 903-2).

  Control signals L 1 to L 4 output from the clock generation circuit 903-1 are input to the IQ mixer 101. Control signals S <b> 1 to S <b> 4 output from the clock generation circuit 903-2 are input to the interphase connection unit 102.

FIG. 17B shows an example of waveforms of the control signals L1 to L4. An example of the waveforms of the control signals S1 to S4 is the same as the waveform shown in FIG. _TL is the pulse width of the control signals L1 to L4. Period _{T LO} is the period of the control signal L1 to L4. The cycle T _LO of the control signals L1 to L4 is T _LO = T _CK / M. _{Here, T CK} is the period of the control signal S1 to S4, M is an arbitrary positive number.

The control signals L1 to L4 and the control signals S1 to S4 have different frequencies. M is such that the clock frequency f _LO (f _LO = 1 / T _LO ) of the control signals L1 to L4 matches the carrier frequency of the RF signal for the IQ mixer 101 to convert the RF signal into a baseband signal. Determined. In addition, the clock frequency f _CK (f _CK = 1 / T _CK ) of the control signals S1 to S4 is determined to be about several times the band of the baseband signal. Although the clock generation circuit 903-1 for frequency conversion operates at a high frequency, the clock generation circuit 903-2 operates at a low frequency, so that the design of the clock generation circuit 903-2 is relatively easy.

  However, the clock generation circuit 903-1 and the clock generation circuit 903-2 may generate the control signals L1 to L4 and the control signals S1 to S4 as one clock generation circuit. The clock generation circuits 903-1 and 903-2 may output a control signal having a rounded waveform, or may output a sine wave control signal to adjust the bias. Thereby, the clock generation circuits 903-1 and 903-2 can realize the on-time of the switch corresponding to the clock input whose DUTY ratio is 25%.

  The IQ mixer 101 performs on / off control of the switches 1012 (1012-1 to 1012-4) (see FIG. 4B) based on the control signals L1 to L4, thereby converting the frequency of the input signal and connecting the frequency-converted signal to the terminal. Output to T1 to T4.

  The interphase connecting section 102 performs on / off control of the switches 1021-1 to 1021-4 (see FIG. 4C) connected to the terminals T1 to T4 based on the control signals S1 to S4. As a result, the four-phase signals whose phases are shifted at the terminals T <b> 1 to T <b> 4 are connected via the inter-phase capacitor 1022. Since the interphase connection unit 102 weights and synthesizes signals whose phases are shifted by 90 degrees, complex filter characteristics are realized. The output buffers 104-1 to 104-4 multiply the potentials at the terminals T1 to T4 by a constant and output the result.

  In addition, although the number of the phase connection parts 102 is one in FIG. 17A, it is not restricted to this. The number of interphase connection units 102 may be two to four, and when the number of clock phases is increased, five or more may be connected.

FIG. 18 shows a simulation result of frequency characteristics of the equalizer circuit 900 according to the seventh embodiment. The horizontal axis of FIG. 18 shows the output frequency, and the vertical axis shows Gain. The conditions are f _LO = 60 GHz, f _CK = 6 GHz, g _m = 10 mS, C _S = 50 fF, and C _IM = 40 fF. As can be seen from FIG. 18, the equalizer circuit 900 can realize frequency characteristics (complex filter characteristics) in which the gain peak is shifted to the negative side with respect to the center.

  Further, although the clock conversion circuit 903-1 for frequency conversion operates at a high frequency, the clock generation circuit 903-2 operates at a low frequency, so that the design of the clock generation circuit 903-2 is relatively easy.

  In the equalizer circuit of each embodiment described above, a single balance or double balance mixer may be used as the frequency conversion switch.

  Moreover, although the equalizer circuit in each embodiment described above has been described as performing frequency conversion and equalizer, if there is a four-phase input signal, the equalizer circuit may be used alone or the frequency characteristics may be changed. Then, it may be used as a filter or an image removal mixer.

(Embodiment 8)
Embodiment 8 of the present disclosure will be described. Unlike the first to seventh embodiments, this embodiment has a configuration in which an input signal is not frequency-converted. In the present embodiment, a CT (Continuous Time) / DT (Discrete Time) hybrid type complex filter is applied to an input signal without frequency conversion. That is, the equalizer circuit according to the present embodiment corrects the frequency characteristics of the input four-phase baseband signal and outputs the corrected four-phase baseband signal.

  FIG. 19A is a diagram showing an exemplary configuration of the equalizer circuit 1000 according to the eighth embodiment. In the equalizer circuit 1000 shown in FIG. 19A, the same components as those of the equalizer circuit 600 shown in FIG. 12 (Embodiment 4) are denoted by the same reference numerals, and detailed description thereof is omitted. A difference between the equalizer circuit 1000 shown in FIG. 19A and the equalizer circuit 600 shown in FIG. 12 (Embodiment 4) is that the equalizer circuit 1000 uses a voltage-current conversion circuit (TA) 1001 instead of the IQ mixer 601. 1 to 1001-4 and sample capacitors 1002-1 to 1002-4.

  For example, TAs 1001-1 to 1001-4 each have an ideal TA configuration shown in FIG. 19B. Note that the voltage-current conversion circuits (TA) 1001-1 to 1001-4 may be configured by a single or a plurality of transistors when mounted.

Here, the operation of the equalizer circuit 1000 will be described. Four-phase input signals (voltage signals V _{IN_I} , V _{IN_Q} , V _{IN_IB} , V _{IN_QB} ) _whose phases are shifted by 90 degrees are input to TAs 1001-1 to 1001-4, and the voltage signals are converted into current signals. The electric charge of the current signal is accumulated in the sample capacitors 1002-1 to 1002-4. The interphase connecting sections 602-1 to 602-4 are connected in order to the terminals T1 to T4 so that the connection paths (terminals T1 to T4) to be connected do not overlap based on the control signals S1 to S4. As a result, signals having different phases by 90 degrees are weighted and synthesized, so that the equalizer circuit 1000 can realize complex filter characteristics. The voltage at the terminals T1 to T4 changes discontinuously when the interphase capacitor 1022 (see FIG. 4C) in the interphase connection section 602 is connected to the terminals T1 to T4, and continuously changes at other times. . The output buffers 604-1 to 604-4 multiply the voltages at the terminals T1 to T4 by a constant, and output them.

  In addition, although the number of the phase connection parts 602 is four in FIG. 19A, it is not restricted to this. The number of interphase connection portions 602 may be only 1 to 3, or five or more may be connected when increasing the number of clock phases.

FIG. 20 shows an example of the simulation result of the frequency characteristics of the equalizer circuit 1000 according to the eighth embodiment. In the simulation, the phase differences between V _{IN — I} and the four-phase input signal were V _{IN — I} : 0 °, V _{IN — Q} : −90 °, V _{IN — IB} : −180 °, and V _{IN — QB} : −270 °, respectively. The horizontal axis in FIG. 20 indicates the output frequency, and the vertical axis indicates Gain. As can be seen from FIG. 20, the equalizer circuit 1000 can realize frequency characteristics (complex filter characteristics) in which the gain peak is shifted to the plus side with respect to the center. Thus, the equalizer circuit 1000 can realize complex filter characteristics without frequency conversion of the input signal.

  Similar to the embodiments described so far, the gain peak can be shifted to the plus side by inverting the clock input order.

(Embodiment 9)
In the eighth embodiment, as shown in FIG. 19A, the equalizer circuit having a configuration that does not frequency-convert the input signal has been described. The configuration that does not frequency-convert the input signal described in the eighth embodiment can be applied to other embodiments. In the ninth embodiment of the present disclosure, an example in which a configuration in which an input signal is not frequency converted is applied to the equalizer circuit 700 illustrated in FIG. 14 will be described.

  FIG. 21 is a diagram showing an example of the configuration of the equalizer circuit 1100 according to the ninth embodiment. In the equalizer circuit 1100 shown in FIG. 21, the same components as those of the equalizer circuit 700 shown in FIG. 14 are denoted by the same reference numerals, and detailed description thereof is omitted. A difference from the equalizer circuit 700 shown in FIG. 14 is that an equalizer circuit 1100 includes TAs 1101-1 to TA1101-12 and sample capacitors 1102-1 to 1102-12 instead of the IQ mixer 701.

  Note that operations for input signals in TA 1101 and sample capacitor 1102 are the same as those in TA 1001 and sample capacitor 1002 described in Embodiment 8, and thus detailed description thereof is omitted.

  The configuration of the equalizer circuit 1100 of FIG. 21 is a configuration in which a plurality of equalizer circuits 1000 shown in FIG. 19A are connected. Therefore, the equalizer circuit 1100 does not perform frequency conversion. In addition, the configuration of the equalizer circuit 1100 of FIG. 21 can realize the frequency characteristics as shown in FIG. 15 as in the equalizer circuit 700 shown in FIG. 14 (however, since frequency conversion is not performed, The input and output frequencies are the same).

  The number of interphase connection sections and the order of clocks input to the interphase connection sections are not limited to those shown in FIG. 21 and may be arbitrarily changed.

  In addition, the equalizer circuit in each of the embodiments described above changes temporally the element value of the circuit, the number of interphase connection portions, and the clock input order if the frequency characteristic to be corrected changes with time. You may let them.

<Summary of this disclosure>
The equalizer circuit according to the first aspect of the present disclosure is:
First, second, third, and fourth converted signals that are generated by converting the input signal and that are different in phase by 90 degrees in order are input to the first, second, third, and fourth converted signals, respectively. First, second, third, and fourth interphase switches, and the first, second, third, and fourth interphase switches, each having one terminal connected to each of four connection paths. One or more interphase connections having an interphase capacitance connected to the other terminal of
By converting a reference signal of a predetermined frequency, the phase is different by 90 degrees in order, and the connection of the first, the second, the third, and the fourth interphase switch is controlled or opened. A control signal generating circuit that generates a control signal and outputs the four-phase control signal to the first, second, third, and fourth inter-phase switches;
First, second, third, and fourth output buffers connected to the first, second, third, and fourth connection paths, respectively, for outputting a four-phase output signal;
With
The first, the second, the third, and the fourth interphase switches are repeatedly connected in a predetermined order by a quarter period based on the control signal of the four phases,
The predetermined order is ascending order or descending order from the N-th phase switch (N is an integer from 1 to 4).

An equalizer circuit according to a second aspect of the present disclosure is the equalizer circuit according to the first aspect.
One or more conversion units for generating the first, second, third, and fourth conversion signals from the input signal;
The one or more conversion units are:
A voltage-current conversion circuit for converting the input signal into a current signal;
The first, second, third, and second ones connected to the output side of the voltage-to-current converter circuit and the other connected to the first, second, third, and fourth connection paths, respectively. 4 sample switches,
First, second, third, and fourth sample capacitors, one connected to the first, second, third, and fourth connection paths, respectively, and the other connected to ground;
Have
The first, second, third, and fourth sample switches are based on the four-phase control signal, and the first, second, third, and The connection is repeated in the order of the fourth sample switch.

The equalizer circuit according to the third aspect of the present disclosure is the equalizer circuit according to the first or second aspect.
The one or more interphase connection portions are connected in parallel to the first, second, third, and fourth connection paths;
The predetermined order in each of the one or more interphase connecting portions is the same as each other,
The first inter-phase switches included in each of the one or more inter-phase connection units are connected at different timings.

An equalizer circuit according to a fourth aspect of the present disclosure is the equalizer circuit according to the second aspect,
The one or more conversion units are provided in parallel with each other,
The one or more interphase connecting portions connect to each of the one or more converting portions;
The predetermined order in each of the one or more interphase connection units connected to the one or more conversion units is different from each other.
In the output buffer, the phase of the signal output from each of the one or more conversion units in the first, second, third, and fourth connection paths is in an opposite phase relationship. It connects to one or more connection paths, and outputs a difference between signals output from each of the one or more conversion units.

An equalizer circuit according to a fifth aspect of the present disclosure is the equalizer circuit according to the second aspect,
The one or more conversion units are provided in parallel with each other,
The one or more interphase connecting portions connect to each of the one or more converting portions;
The predetermined order in each of the one or more interphase connection units connected to the one or more conversion units is different from each other.
In the output buffer, the phase of the signal output from each of the one or more conversion units in the first, second, third, and fourth connection paths is in phase 1 Connect to one or more connection paths and output the sum of the signals output from each of the one or more conversion units.

  In the equalizer circuit according to the sixth aspect of the present disclosure, the equalizer circuit according to the fourth or fifth aspect and the equalizer circuit according to the third aspect are provided in parallel.

The receiving device according to the seventh aspect of the present disclosure is:
An equalizer circuit;
An analog-to-digital converter that converts a signal output from the equalizer circuit into a digital signal;
A digital reception processing unit for performing reception processing of the digital signal and outputting reception data;
Have
The equalizer circuit is
First, second, third, and fourth converted signals that are generated by converting the input signal and that are different in phase by 90 degrees in order are input to the first, second, third, and fourth converted signals, respectively. First, second, third, and fourth interphase switches, and the first, second, third, and fourth interphase switches, each having one terminal connected to each of four connection paths. One or more interphase connections having an interphase capacitance connected to the other terminal of
By converting a reference signal of a predetermined frequency, the phase is different by 90 degrees in order, and the connection of the first, the second, the third, and the fourth interphase switch is controlled or opened. A control signal generating circuit that generates a control signal and outputs the four-phase control signal to the first, second, third, and fourth inter-phase switches;
First, second, third, and fourth output buffers connected to the first, second, third, and fourth connection paths, respectively, for outputting a four-phase output signal;
With
The first, the second, the third, and the fourth interphase switches are repeatedly connected in a predetermined order by a quarter period based on the control signal of the four phases,
The predetermined order is ascending order or descending order from the N-th phase switch (N is an integer from 1 to 4).

  The present disclosure is useful for a high-frequency signal and baseband signal processing circuit in a wireless communication device, and is useful for filter processing, equalizer processing, or frequency conversion processing.

DESCRIPTION OF SYMBOLS 10 Reception apparatus 11 Antenna 12 Low noise amplifier 13 Reference frequency oscillation part 14, 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100 Equalizer circuit 15 A / D conversion process part 16 Digital reception process Unit 101, 201, 301, 401, 501, 601, 701 IQ mixer 102, 202, 402, 502, 602, 702, 802 Interphase connection unit 103, 203, 303, 403, 503, 603, 703, 803, 903 1, 903-2 Clock generation circuit 104, 204, 304, 404, 504, 604, 704, 804 Output buffer 302, 1022, 8022 Interphase capacitor 1001, 1101, 1011, 3011, 8011 TA
1012, 1021, 3012, 8012, 8021 Switch 1002, 1013, 1102, 3013, 8013 Sample capacitor

Claims (7)

First, second, third, and fourth converted signals that are generated by converting the input signal and that are different in phase by 90 degrees in order are input to the first, second, third, and fourth converted signals, respectively. First, second, third, and fourth interphase switches, and the first, second, third, and fourth interphase switches, each having one terminal connected to each of four connection paths. One or more interphase connections having an interphase capacitance connected to the other terminal of
By converting a reference signal of a predetermined frequency, the phase is different by 90 degrees in order, and the connection of the first, the second, the third, and the fourth interphase switch is controlled or opened. A control signal generating circuit that generates a control signal and outputs the four-phase control signal to the first, second, third, and fourth inter-phase switches;
First, second, third, and fourth output buffers connected to the first, second, third, and fourth connection paths, respectively, for outputting a four-phase output signal;
With
The first, the second, the third, and the fourth interphase switches are repeatedly connected in a predetermined order by a quarter period based on the control signal of the four phases,
The predetermined order is ascending order or descending order from the N-th phase switch (N is an integer from 1 to 4).
Equalizer circuit. One or more conversion units for generating the first, second, third, and fourth conversion signals from the input signal;
The one or more conversion units are:
A voltage-current conversion circuit for converting the input signal into a current signal;
The first, second, third, and second ones connected to the output side of the voltage-to-current converter circuit and the other connected to the first, second, third, and fourth connection paths, respectively. 4 sample switches,
First, second, third, and fourth sample capacitors, one connected to the first, second, third, and fourth connection paths, respectively, and the other connected to ground;
Have
The first, second, third, and fourth sample switches are based on the four-phase control signal, and the first, second, third, and It is repeatedly connected in the order of the fourth sample switch.
The equalizer circuit according to claim 1. The one or more interphase connection portions are connected in parallel to the first, second, third, and fourth connection paths;
The predetermined order in each of the one or more interphase connecting portions is the same as each other,
The first interphase switch included in each of the one or more interphase connections is connected at different timings.
The equalizer circuit according to claim 1 or 2. The one or more conversion units are provided in parallel with each other,
The one or more interphase connecting portions connect to each of the one or more converting portions;
The predetermined order in each of the one or more interphase connection units connected to the one or more conversion units is different from each other.
In the output buffer, the phase of the signal output from each of the one or more conversion units in the first, second, third, and fourth connection paths is in an opposite phase relationship. Connecting to one or more connection paths, and outputting a difference between signals output from each of the one or more conversion units;
The equalizer circuit according to claim 2. The one or more conversion units are provided in parallel with each other,
The one or more interphase connecting portions connect to each of the one or more converting portions;
The predetermined order in each of the one or more interphase connection units connected to the one or more conversion units is different from each other.
In the output buffer, the phase of the signal output from each of the one or more conversion units in the first, second, third, and fourth connection paths is in phase 1 Connected to one or more connection paths, and outputs a sum of signals output from each of the one or more conversion units;
The equalizer circuit according to claim 2.   An equalizer circuit, wherein the equalizer circuit according to claim 4 and the equalizer circuit according to claim 3 are provided in parallel. An equalizer circuit;
An analog-to-digital converter that converts a signal output from the equalizer circuit into a digital signal;
A digital reception processing unit for performing reception processing of the digital signal and outputting reception data;
A receiving device comprising:
The equalizer circuit is
First, second, third, and fourth converted signals that are generated by converting the input signal and that are different in phase by 90 degrees in order are input to the first, second, third, and fourth converted signals, respectively. First, second, third, and fourth interphase switches, and the first, second, third, and fourth interphase switches, each having one terminal connected to each of four connection paths. One or more interphase connections having an interphase capacitance connected to the other terminal of
By converting a reference signal of a predetermined frequency, the phase is different by 90 degrees in order, and the connection of the first, the second, the third, and the fourth interphase switch is controlled or opened. A control signal generating circuit that generates a control signal and outputs the four-phase control signal to the first, second, third, and fourth inter-phase switches;
First, second, third, and fourth output buffers connected to the first, second, third, and fourth connection paths, respectively, for outputting a four-phase output signal;
With
The first, the second, the third, and the fourth interphase switches are repeatedly connected in a predetermined order by a quarter period based on the control signal of the four phases,
The predetermined order is ascending order or descending order from the N-th phase switch (N is an integer from 1 to 4).
Receiver device.

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