CN107026616A - Equalizer and use its reception device - Google Patents

Equalizer and use its reception device Download PDF

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Publication number
CN107026616A
CN107026616A CN201610892396.4A CN201610892396A CN107026616A CN 107026616 A CN107026616 A CN 107026616A CN 201610892396 A CN201610892396 A CN 201610892396A CN 107026616 A CN107026616 A CN 107026616A
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China
Prior art keywords
alternate
switch
signal
access path
equalizer
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CN201610892396.4A
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Chinese (zh)
Inventor
森下阳平
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Publication of CN107026616A publication Critical patent/CN107026616A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/18—Modifications of frequency-changers for eliminating image frequencies
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
    • H04B1/12—Neutralising, balancing, or compensation arrangements
    • H04B1/123—Neutralising, balancing, or compensation arrangements using adaptive balancing or compensation means

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Filters That Use Time-Delay Elements (AREA)
  • Analogue/Digital Conversion (AREA)
  • Networks Using Active Elements (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

Equalizer includes：Alternate connection unit；1st output buffer, the 2nd output buffer, the 3rd output buffer and the 4th output buffer；And control signal generative circuit.Alternate connection unit has the 1st alternate switch, the 2nd alternate switch, the 3rd alternate switch and the 4th alternate switch and capacitive coupling.1st output buffer, the 2nd output buffer, the 3rd output buffer and the 4th output buffer are connected respectively to the 1st access path, the 2nd access path, the 3rd access path and the 4th access path, and output signal is exported.Control signal generative circuit exports connection or the control signal of open circuit for controlling the 1st alternate switch, the 2nd alternate switch, the 3rd alternate switch and the 4th alternate switch.1st alternate switch, the 2nd alternate switch, the 3rd alternate switch and the 4th alternate switch, based on control signal, every 1/4 cycle is connected repeatedly from the alternate switches of N with ascending order or descending order, and N is one of integer from 1 to 4.

Description

Equalizer and use its reception device
Technical field
The present invention relates to equalizer and using the wireless device of its reception device etc., for example, being related to Periodic time-varying At continuous time (Periodically Time Varying) processing, equilibrium treatment, filtering process or signal comprising frequency conversion Reason.
Background technology
Setting in known suitable fine CMOS (Complementary Metal Oxide Semiconductor) technique Meter, is used as the circuit structure of the discrete-time analogues type of the circuit with higher changeability.
For example, Patent Document 1 discloses for the analog signal of input, carrying out the discrete time of frequency conversion and complex filter Analog circuit.
Discrete-time analogues circuit disclosed in patent document 1 carries out discrete-time analogues for the analog signal of input The frequency conversion of signal transacting and complex filter.Specifically, the discrete-time analogues circuit of patent document 1 by input voltage in voltage Electric current is converted in current converter circuit, input charge is generated by the electric current after sample conversion.Moreover, patent document 1 Discrete-time analogues circuit realizes denominator by making input charge carry out electric charge movement between multiple capacitors that the circuit is included IIR (the Infinite Impulse Response of 1 formula with complex coefficient；Infinite-duration impulse response) filter characteristic.
Prior art literature
Patent document
Patent document 1：No. 2005/0233725 specification of U.S. Patent Application Publication No.
The content of the invention
Figure 1A is RF (the Radio Frequency for representing broadband wireless system；Radio frequency) amplifier frequency characteristic one The figure of example.As shown in Figure 1A, the frequency characteristic of the RF amplifiers of broadband wireless system is in each channel (CH1~CH4 in Figure 1A Deng) in be not flat, there is deviation (deviation in frequency band) in frequency band.Therefore, in broadband wireless system, it is difficult to will use The frequency characteristic of each channel become flat, it is necessary to the correction (that is, balanced (balanced device)) of frequency characteristic in base band.
Figure 1B is the figure of one of the frequency characteristic for representing the propagation path in broadband wireless system.In wireless communications, As shown in Figure 1B, the frequency characteristic of propagation path is not flat, there is deviation in frequency band, so needing baseband intermediate frequency rate characteristic Correction.
In addition, in broadband wireless system of the millimeter wave as RF is used, to achieve over passing through for several GHz broadband In the case of characteristic, with the load of clock, parasitic capacitance it is such from the viewpoint of, the influence of switch becomes big.Therefore, discrete time Analog circuit needs simple structure to reduce the load of parasitic capacitance and clock.
But, conventional discrete-time analogues circuit can only be realized carrier deviation so as patent document 1 Simple filter characteristic.Therefore, as broadband wireless system, there is frequency in the frequency characteristic of propagation path and RF circuits In the case of with interior deviation, conventional discrete-time analogues circuit is difficult to have as by the balanced device of offset correction in frequency band Function.In addition, conventional discrete-time analogues circuit is had many electric capacity and many switches in order to be sampled, be kept, so It is complicated.
The present invention in view of such situation and complete, it is therefore intended that the adjustment free degree that provides frequency characteristic in frequency band is high, The equalizer of simple structure and use its reception device.
The equalizer of the present invention includes：More than one alternate connection unit, by input respectively by changing input Signal generation, different the 1st conversion signal of the every 90 degree of orders of phase, the 2nd conversion signal, the 3rd conversion signal and the 4th conversion letter Number, have：1st alternate switch, the 2nd alternate switch, the 3rd alternate switch and the 4th alternate switch, a terminal are connected respectively to the 1 access path, the 2nd access path, the 3rd access path and the 4th access path；And capacitive coupling, it is connected to the described 1st alternate Switch, it is described 2nd it is alternate switch, it is described 3rd it is alternate switch and the 4th alternate switch another terminal；Control signal is given birth to Into circuit, by the reference signal of frequency as defined in conversion, phase sequence every 90 degree it is different, control the described 1st it is alternate switch, Connection or the open circuit of the 2nd alternate switch, the 3rd alternate switch and the 4th alternate switch, the control letter of 4 phases of generation Number, by the control signal of 4 phase be output to the described 1st it is alternate switch, it is described 2nd it is alternate switch, it is described 3rd it is alternate switch and The 4th alternate switch；And the 1st output buffer, the 2nd output buffer, the 3rd output buffer and the 4th output buffer, The 1st access path, the 2nd access path, the 3rd access path and the 4th access path are connected respectively to, it is defeated Go out the output signal of 4 phases, the 1st alternate switch, the 2nd alternate switch, the 3rd alternate switch and described 4th alternate Switch, based on the control signal of 4 phase, every 1/4 cycle is connected repeatedly with defined order, it is described as defined in order be from Ascending order or descending N (N is one of integer from 1 to 4) alternate switch.
In accordance with the invention it is possible to which the adjustment free degree for providing frequency characteristic in frequency band is high, the equalizer of simple structure And use its reception device.
The further advantages effects in the mode of the present invention are will be clear that from specification and drawings.These advantages and/ Or effect can respectively be provided by the feature described in several embodiments and specification and accompanying drawing, it is not necessary in order to obtain one Or more than one feature and whole features are provided.
Brief description of the drawings
Figure 1A represents one of the frequency characteristic of the RF amplifiers of broadband system.
Figure 1B represents one of the frequency characteristic of the propagation path in broadband system.
Fig. 2 represents the structure of the reception device of embodiments of the present invention 1~5.
Fig. 3 represents the difference of continuous time system, discrete-time system and Periodic time-varying continuous time system.
Fig. 4 A represent one of the structure of the equalizer of embodiment 1.
Fig. 4 B represent one of the structure of the IQ frequency mixers of embodiment 1.
Fig. 4 C represent one of the structure of the alternate connection unit of embodiment 1.
Fig. 5 represents the timing diagram of one of control signal.
Fig. 6 A represent the result of the circuit simulation of the frequency characteristic of the equalizer of embodiment 1.
Fig. 6 B represent the result of the circuit simulation of the frequency characteristic of the equalizer of embodiment 1.
Fig. 7 represents one of the structure of the equalizer of embodiment 2.
Fig. 8 represents the result of the circuit simulation of the frequency characteristic of the equalizer of embodiment 2.
Fig. 9 represents one of the structure of the equalizer of embodiment 3.
Figure 10 represents one of the structure of the equalizer of embodiment 4.
Figure 11 represents one of the structure of the equalizer of embodiment 4.
Figure 12 represents one of the structure of the equalizer of embodiment 4.
Figure 13 represents the result of the circuit simulation of the frequency characteristic of the equalizer of embodiment 4.
Figure 14 represents one of the structure of the equalizer of embodiment 5.
Figure 15 represents the result of the circuit simulation of the frequency characteristic of the equalizer of embodiment 5.
Figure 16 represents one of the equalizer of embodiment 6.
Figure 17 A represent one of the structure of the equalizer of embodiment 7.
Figure 17 B represent the timing diagram of one of the control signal of embodiment 7.
Figure 18 represents the result of the circuit simulation of the frequency characteristic of the equalizer of embodiment 7.
Figure 19 A represent one of the structure of the equalizer of embodiment 8.
Figure 19 B represent one of the structure of the TA in embodiment 8.
Figure 20 represents the result of the circuit simulation of the frequency characteristic of the equalizer of embodiment 8.
Figure 21 represents one of the structure of the equalizer of embodiment 9.
Embodiment
Hereinafter, embodiments of the present invention are described in detail with reference to accompanying drawings.Further, each embodiment in following explanation is One, the present invention is not limited by these embodiments.
(embodiment 1)
[structure of reception device]
Fig. 2 is the figure of the structure for the reception device 10 for representing embodiments of the present invention 1.
Reception device 10 shown in Fig. 2 has antenna 11, low-noise amplifier (LNA：Low Noise Amplifier) 12nd, reference frequency oscillating unit 13, equalizer 14, A/D (Analog to Digital) conversion processing units 15 and Digital received processing unit 16.
Antenna 11 receives the analog receiving signal of RF frequency from dispatching station (not shown), by the analog receiving signal of RF frequency It is output to low-noise amplifier 12.
Low-noise amplifier 12 amplifies the analog receiving signal of RF frequency, and the simulation of the RF frequency after amplification is received and believed Number it is output to equalizer 14.
Reference frequency oscillating unit 13 generates the reference frequency signal f handled for Periodic time-varying continuous timeREF, will join Examine frequency signal fREFIt is output to equalizer 14.
Equalizer 14 is based on reference frequency signal fREF, Periodic time-varying is carried out for the analog receiving signal of RF frequency The frequency conversion and equilibrium (filtering) of continuous time processing.Equalizer 14 is defeated by the baseband analog received signal after balanced (filtering) Go out to A/D conversion processing units 15.Further, structure and action about equalizer 14, will be aftermentioned.
Baseband analog received signal is converted to base-band digital and receives signal by A/D conversion processing units 15, by base-band digital Signal output is to digital received processing unit 16.
Digital received processing unit 16 is handled (for example, solution is mediated for baseband digital signal by defined digital received Reason, decoding process etc.) generation reception data, export the reception data of generation.
Further, the reception device 10 shown in Fig. 2 is directly defeated from the analog receiving signal of RF frequency as equalizer 14 Go out the structure of the analog receiving signal of base band, i.e., the structure directly changed illustrates.But, the reception device 10 of present embodiment It can also be that frequency mixer is added more than one in rear class of low-noise amplifier 12 etc., use intermediate frequency (IF： Intermediate Frequency) structure.
The equalizer 14 of present embodiment is the Periodic time-varying continuous time for carrying out Periodic time-varying continuous time processing The circuit of system.Then, for the circuit of Periodic time-varying continuous time system, circuit, discrete time with continuous time system The circuit of system contrastively illustrates.
Fig. 3 is to represent continuous time system, discrete-time system, Periodic time-varying continuous time (Periodically Time Varying) the different figures of system.Fig. 3 conceptually represents that continuous time system, discrete-time system and Periodic time-varying connect Signal transacting in the circuit of continuous time system.Continuous time system, discrete-time system and Periodic time-varying shown in Fig. 3 connect Continuous time (CT of the circuit of continuous time system respectively for input：Continuous Time) signal progress signal transacting, it is defeated Go out continuous time signal.
The circuit (continuous time circuit) of continuous time system shown in Fig. 3 is for the continuous time signal of input, with even The continuous time carries out signal transacting, exports continuous time signal.The continuous time circuit of passive using size as inductance compared with Greatly, the element of flexibility is lacked.Therefore, the continuous time circuit of passive is not only unsuitable for the installation in fine CMOS, and Changeability is installed also low.In addition, the continuous time circuit of active type, it is difficult to carry out the design under relatively low supply voltage, so Not only it is unsuitable for the installation in fine CMOS technology, and consumption power is also larger.
The circuit (discrete-time circuits) of discrete-time system shown in Fig. 3 passes through the continuous time signal (CT) of input CT/DT is changed and sampled, and is transformed to discrete time (DT：Discrete Time) signal.Then, discrete-time circuits are with discrete Time carries out signal transacting, and the discrete-time signal after signal transacting is changed by DT/CT and kept, continuous time is converted to Signal.Then, discrete-time circuits export the continuous time signal after conversion.Discrete-time circuits are only by switch, capacitor Constituted with clock.Moreover, the characteristic of discrete-time circuits is determined by the capacity ratio and clock frequency of capacitor, so discrete time Circuit is suitable to the installation in fine CMOS technology, installs changeability also high.But, discrete-time circuits in continuous time signal and , it is necessary to sample and keep, so in order to realize complete discrete time system during conversion (CT/DT conversion) between discrete-time signal The processing of system and the number that switchs increase.
The circuit (Periodic time-varying continuous time circuit) of Periodic time-varying continuous time system shown in Fig. 3 is in continuous time The hybrid circuit of discrete-time circuits is used in a part for circuit.Periodic time-varying continuous time circuit need not be believed continuous time Conversion number between discrete-time signal, with the number of less switch, can carry out the advantage effectively using discrete-time system Design.In addition, Periodic time-varying continuous time circuit is suitable to the installation in fine CMOS technology, it can simply realize that installation can The higher circuit of denaturation.
[structure of equalizer 100]
Then, reference picture 4A~Fig. 4 C illustrate the structure of the equalizer 100 of present embodiment.
Fig. 4 A are the figures of one of the structure for the equalizer 100 for representing embodiment 1.Balanced device electricity shown in Fig. 4 A Road 100 carries out the processing of frequency conversion and filtering equivalent to the equalizer 14 that the reception device 10 shown in Fig. 2 has.
Equalizer 100 shown in Fig. 4 A has IQ frequency mixers (converting unit) 101, alternate connection unit 102, clock Generative circuit (control signal generative circuit) 103 and output buffer 104 (104-1~104-4).
Fig. 4 B are the figures of one of the structure for the IQ frequency mixers 101 for representing embodiment 1.IQ frequency mixers 101 have TA (Transconductance Amplifier：Trsanscondutance amplifier：Voltage-current converter circuit) 1011, switch 1012 (1012-1 ~1012-4) and sampling capacitor 1013 (1013-1~1013-4).
The analog signal of input is input voltage signal V by TA1011INBe converted to electric current (gm×VIN).Further, gmIt is The value of TA1011 mutual conductance (mutual conductance).
Switch in 1012-1~1012-4, a terminal is connected to TA1011 lead-out terminal, and another terminal each connects It is connected to output buffer 104-1~104-4 input terminal.Switch 1012-1~1012-4 is based respectively on from terminal a~d inputs Control signal, be switched on/cut-off control.In the case of Fig. 4 B, switch 1012-1 is in the control signal S inputted from terminal a1For Turned in during " height ".Similarly, switch 1012-2 is in the control signal S inputted from terminal b2Led in during for " height " It is logical.1012-3 is switched in the control signal S inputted from terminal c3Turned in during for " height ".1012-4 is switched from terminal d The control signal S of input4Turned in during for " height ".
In sampling capacitor 1013-1~1013-4, a terminal is grounded, and another terminal is connected respectively to terminal T1 ~T4.Moreover, sampling capacitor 1013-1~1013-4 respectively switch 1012-1~1012-4 conducting during, accumulation input Electric charge.Further, about the action of detailed equalizer 100, will be aftermentioned.
By the structure shown in Fig. 4 B, it is different just that input signal is converted to the every 90 degree of orders of phase by IQ frequency mixers 101 (Quadrature (90 degree of phase shifts) below, remembers for phase component (In-phase (same to phase), below, be recited as " I phases "), quadrature component Carry as " Q phases "), the out-of-phase component of relatively positive phase component (following, to be recited as " IB phases "), the out-of-phase component of relative orthogonal component The signal (the 1st conversion signal~the 4th conversion signal) of 4 phases of (following, be recited as " QB phases "), the signal of 4 phases is exported respectively To different paths.Hereinafter, the path of the signal (the 1st conversion signal) of I phases will be exported from IQ frequency mixers 101, the letter of Q phases is exported The path of number (the 2nd conversion signal), export IB phases signal (the 3rd conversion signal) path, export (the 4th turn of the signals of QB phases Change signal) path be referred to as I phase paths (the 1st access path), Q phase paths (the 2nd access path), IB phase paths (the 3rd connect Connect path), QB phase paths (the 4th access path).
Fig. 4 C are the figures of one of the structure for the alternate connection unit 102 for representing embodiment 1.Alternate connection unit 102 With switch (alternate switch) 1021 (1021-1~1021-4) and capacitive coupling device (capacitive coupling) 1022.
Switch in 1021-1~1021-4, a terminal is connected respectively in terminal T1, Q phase path in I phase paths The terminal T4 on terminal T3, QB paths in terminal T2, IB phase path, another terminal is connected to capacitive coupling device 1022.Open Close 1021-1~1021-4 and be based respectively on the control signal inputted from terminal e~h, be switched on/cut-off control.Fig. 4 C situation Under, switch 1021-1 is in the control signal S inputted from terminal e3Turned in during for " height ".Similarly, switch 1021-2 exists The control signal S inputted from terminal f4Turned in during for " height ".1021-3 is switched in the control signal S inputted from terminal g1 Turned in during for " height ".1021-4 is switched in the control signal S inputted from terminal h2Turned in during for " height ".
In capacitive coupling device 1022, a terminal is connected to switch 1021-1~1021-4 terminal, another terminal quilt Ground connection.
Capacitive coupling device 1022 is connected to I phase paths during switch 1021-1 conductings.Moreover, capacitive coupling device 1022 Electric charge is carried out with sampling capacitor 1013-1 to share.Similarly, capacitive coupling device 1022 connects during switch 1021-2 conductings It is connected to Q phase paths.Shared moreover, capacitive coupling device 1022 and sampling capacitor 1013-2 carries out electric charge.Capacitive coupling device 1022 IB phase paths are connected to during switch 1021-3 conductings.Moreover, capacitive coupling device 1022 enters with sampling capacitor 1013-3 Row electric charge is shared.Capacitive coupling device 1022 is connected to QB phase paths during switch 1021-4 conductings.Moreover, capacitive coupling device 1022 carry out electric charge with sampling capacitor 1013-4 shares.
By the structure, capacitive coupling device 1022 carry out between different paths in electric charge keep, electric charge is shared.Further, , will be aftermentioned about the action of detailed equalizer 100.
Clock forming circuit (control signal generative circuit) 103 is based on defeated from reference frequency oscillating unit 13 (reference picture 2) Reference frequency signal (the f gone outREF), control signal is generated, control signal is supplied to IQ frequency mixers 101 and alternate connection unit 102。
Output buffer 104-1~104-4 in I phases, Q phases, IB phases, 4 phases of QB phases, is transfused to because of input charge respectively The accumulation continuous voltage change, sampling capacitor 1013 and the capacitive coupling device 1022 that cause between electric charge shared cause Instantaneous voltage change, their voltage change is directly exported, or is multiplied by the output voltage signal that fixed multiple exports each phase VOUT(VOUT-I、VOUT-Q、VOUT-IB、VOUT-QB)。
[control signal generated by clock forming circuit 103]
Illustrate the control signal generated in clock forming circuit 103.Fig. 5 is the timing diagram of control signal.Control signal S1~S4 is by pulse width Ts, the cycle T of control signalCKConstitute.Further, Fig. 5 illustrates rectangle clock, but equalizer 100 also act even if for the blunt clock of waveform.
As shown in figure 5, clock forming circuit 103 by duty (DUTY) than (cycle of=pulse width Ts/ control signals TCK) it is supplied to equalizer 100 for 0.25, every 90 degree of phase offsets, 4 phases control signal S1~S4.
In the case where directly changing, the clock frequency f of control signalCK(fCK=1/TCK) by being input into balanced device electricity The frequency of the signal on road is determined.For example, in the case where the frequency of input signal is 60GHz, clock frequency fCKIt is 60GHz.
[action of equalizer 100]
Then, the action in equalizer 100 is illustrated.
The each cycle T of 100 pairs of equalizerCKElectric charge is carried out to share and charge accumulation.Equalizer 100 will be following 3 kinds of electric charges carry out electric charge and shared.
(1-a) TA1011 is by input voltage signal VtNBe converted to the electric charge (following, to be recited as input charge) of electric current
The electric charge that (1-b) capacitive coupling device 1022 is kept
The electric charge that (1-c) sampling capacitor 1013 is kept
Equalizer 100 is based on control signal S1~S4 shown in Fig. 5, by switching 1012-1~1012-4 and switch 1021-1~1021-4 control (conduction and cut-off), in 1 cycle (1TCK) 4 following actions of interior progress, to each cycle TCK These actions are repeated.
1st action：In control signal S1During for " height ", sampling capacitor 1013-1 is connected to TA1011, defeated Enter electric charge to be accumulated in sampling capacitor 1013-1.Before the immediately charge accumulation 1 is remain in sampling capacitor 1013-1 Electric charge before cycle.While the accumulation of the input charge to sampling capacitor 1013-1, capacitive coupling device 1022 is connected To sampling capacitor 1013-3, carry out electric charge and share.
2nd action：In control signal S2During for " height ", sampling capacitor 1013-2 is connected to TA1011, defeated Enter electric charge to be accumulated in sampling capacitor 1013-2.Before the immediately charge accumulation 1 is remain in sampling capacitor 1013-2 Electric charge before cycle.While the accumulation of the input charge to sampling capacitor 1013-2, capacitive coupling device 1022 is connected To sampling capacitor 1013-4, carry out electric charge and share.
3rd action：In control signal S3During for " height ", sampling capacitor 1013-3 is connected to TA1011, defeated Enter electric charge to be accumulated in sampling capacitor 1013-3.Before the immediately charge accumulation 1 is remain in sampling capacitor 1013-3 Electric charge before cycle.While the accumulation of the input charge to sampling capacitor 1013-3, capacitive coupling device 1022 is connected To sampling capacitor 1013-1, carry out electric charge and share.
4th action：In control signal S4During for " height ", sampling capacitor 1013-4 is connected to TA1011, defeated Enter electric charge to be accumulated in sampling capacitor 1013-4.Before the immediately charge accumulation 1 is remain in sampling capacitor 1013-4 Electric charge before cycle.While the accumulation of the input charge to sampling capacitor 1013-4, capacitive coupling device 1022 is connected To sampling capacitor 1013-2, carry out electric charge and share.
The each cycle T of 100 pairs of equalizerCKSequentially be repeated the 1st action, the 2nd action, the 3rd action, the 4th move Make.By the way that the 1st action is sequentially repeated to the 4th action, the accumulation of input charge is with sampling capacitor 1013-1,1013- 2nd, 1013-3,1013-4 reiteration are carried out.In addition, capacitive coupling device 1022 with IB phase paths, QB phase paths, I phase paths, The reiteration connection of Q phase paths.Moreover, capacitive coupling device 1022 and sampling capacitor 1013-3,1013-4,1013-1, 1013-2 sequentially carries out electric charge and shared.
I.e., in this case, the 1st switch (the 1st alternate switch) 1021-1, the 2nd switch (the 2nd alternate switch) 1021-2, 3rd switch (the 3rd alternate switch) 1021-3, the order of connection of the 4th each switch for switching (the 4th alternate switch) 1021-4 are from the Ascending order N (N is one of integer from 1 to 4) switch.Moreover, continue the 4th switch 1021-4, the 1st switch 1021-1 connections To the access path of 4 phases.The access paths that 4 phases are connected to by switch 1021 repeatedly, capacitive coupling device 1022 with I phases, Q Phase, IB phases, the same order of phase place as QB phases are connected to the access path of 4 phases repeatedly.Capacitive coupling device 1022 are shared by sequentially carrying out electric charge with sampling capacitor 1013-3,1013-4,1013-1,1013-2, with TCKInterval is tired The electric charge that keeps and with T in the sampling capacitor 1013 of product input chargeCKThe shared capacitive coupling of electric charge is repeated in/4 intervals The electric charge kept in device 1022 carries out electric charge and shared.
In addition, in this case, timing, sampling capacitor 1013 to the accumulation of the input charge of sampling capacitor 1013 The shared timing with the electric charge of capacitive coupling device 1022, it is different in each sampling capacitor 1013, but the accumulation of input charge Order is identical with the order that electric charge is shared.
Then, for from the 1st action to the 4th action, about the discrete system of the core as frequency characteristic, mathematically saying It is bright.
The capacitance of capacitive coupling device 1022 is set to CIM, the capacitance of sampling capacitor 1013 is set to CS, by n-th (n：Integer) input charge is set to qin(n) the n-th output voltage and the (n-1)th output voltage, are set to vOUTAnd v (n)OUT(n- 1) when, the n-th (n in equalizer 100：Integer) the shared outline of electric charge can be remembered by the difierence equation of formula (1) State.
qin(n)+jCIMvout(n)+CSvout(n-1)=(CS+CIM)vout(n) (1)
In formula (1), the 1st, the left side is equivalent to input charge, and the 2nd, the left side is kept equivalent in capacitive coupling device 1022 Electric charge, i.e. pass through shared the kept electric charge of electric charge before 1/4 cycle.Imaginary unit j enters due to capacitive coupling device 1022 The electric charge in 1/4 cycle of line displacement is shared.The 3rd, the left side is the electric charge before 1 cycle kept in sampling capacitance 1011.Pass through z Conversion, Q is set to by the n-th input chargeIN(n)=(CS+CIM)AVIN(n) (A is when Number), it is used as the transfer function H of the core of the discrete system of equalizer 100DRoughly represented by formula (2).
Wherein, ωinIt is the angular frequency of input voltage signal.By in transfer function HDIn realize imaginary unit j, Neng Goushi Now with respect to the asymmetrical frequency characteristic in center or so.
Illustrate the frequency characteristic of equalizer 100.Fig. 6 A are the frequencies for the equalizer 100 for representing embodiment 1 The figure of the result of the circuit simulation of characteristic.Fig. 6 A transverse axis represents output frequency, and the longitudinal axis represents gain.Further, output frequency with Incoming frequency-fCKRepresent.Fig. 6 A represent CSFor 50fF, fCKFor 60GHz, gmFor 10mS, CIMAs parameter from 10fF to 40fF Scope in change in the case of equalizer 100 frequency characteristic.Further, equalizer 100 can also be by CIMGu It is fixed, by CSIt is used as parameter.
As shown in Figure 6A, in control signal S3、S4、S1、S2It is separately input to terminal e~h's of alternate connection unit 102 In the case of, equalizer 100 can realize frequency characteristic of the peak value with respect to off-centring to minus side of gain.
Further, as shown in the control signal in Fig. 4 A, Fig. 4 C parantheses, in terminal e respectively to alternate connection unit 102 ~h have input control signal S3、S2、S1, in the case of S4, the equalizer 100 of present embodiment has different frequencies special Property.
In control signal S3、S2、S1、S4In the case of the terminal e~h for being separately input to alternate connection unit 102, the 1st opens Close (the 1st alternate switch) 1021-1, the 2nd switch (the 2nd alternate switch) 1021-2, the 3rd switch (the 3rd alternate switch) 1021-3, 4th switch (the 4th alternate switch) 1021-4 each switch is from M (M is one of integer from 1 to 4) switch with descending Connection.Moreover, the 1st the switch 1021-1, the 4th switch 1021-4 that continue is connected to the access path of 4 phases.By switch 1021 repeatedly The access path of 4 phases is connected to, capacitive coupling device 1022 is anti-with the order of IB phase paths, Q phase paths, I phase paths, QB phase paths It is multiply-connected to connect.That is, for the order of phase place as I phases, Q phases, IB phases, QB phases, the reverse order of capacitive coupling device 1022 It is connected to the access path of 4 phases.
Then, in this case, between capacitive coupling device 1022 and sampling capacitor 1013 in the shared order of electric charge It is opposite with the order of the accumulation of the input charge in sampling capacitor 1013.Specifically, the accumulation of input charge is with electricity of sampling Container 1013-1,1013-2,1013-3,1013-4 reiteration are carried out, on the other hand, and electric charge is shared to pass through capacitive coupling device 1022 connect to carry out with sampling capacitor 1013-3,1013-2,1013-1,1013-4 reiteration.
Capacitive coupling device 1022 connects reverse order for the order of phase place as I phases, Q phases, IB phases, QB phases The access path of 4 phases is connected to, the electric charge in every 3/4 cycle (that is, -1/4 cycle) is shared so progress has been staggered.As a result, equal The transfer function H of weighing apparatus circuit 100DIn, it is added in the sign-inverted on imaginary unit j.By being added in transfer function HDImaginary number list Sign-inverted on the j of position, equalizer 100 can realize frequency characteristic of the gain peak relative to off-centring to positive side. In the case where capacitive coupling device 1022 is connected to the access path of 4 phases with forward sequence for the order of phase place, imaginary number Unit is negative, is connected to the feelings of the access path of 4 phases with reverse order for the order of phase place in capacitive coupling device 1022 Under condition, imaginary unit is just.
Fig. 6 B represent control signal S3、S2、S1、S4In the case of the terminal e~h for being separately input to alternate connection unit 102 Frequency characteristic.The parameter and Fig. 6 A of the longitudinal axis, transverse axis and each element in Fig. 6 B are same.In capacitive coupling device 1022 When the order of phase place as I phases, Q phases, IB phases, QB phases is connected to the access path of 4 phases with reverse order Under, as shown in Figure 6B, equalizer 100 can realize frequency characteristic of the gain peak relative to off-centring to positive side.
[effect]
As more than, according to present embodiment, the access path of 4 phases is sequentially connected to by capacitive coupling device 1022, is entered The capable electric charge for staggering for 1/4 cycle (or -1/4 cycle) is shared, to transfer function HDImaginary unit j can be realized.By right Transfer function HDImaginary unit j is realized, as shown in Fig. 6 A, Fig. 6 B, the equalizer 100 of present embodiment has relative in The asymmetrical frequency characteristic of heart or so.Therefore, the equalizer of present embodiment can realize deviation in adjustable frequency band Wave filter.That is, for example, the equalizer of present embodiment can be reduced because of the frequency characteristic of the RF circuits shown in Figure 1A The equilibrium treatment of deviation in caused frequency band.
In addition, in the present embodiment, without the conversion from continuous time signal to discrete-time signal, so comparing Conventional discrete-time analogues circuit, can reduce the number of switch.Therefore, in the present embodiment, exceed even in realizing Number GHz as broadband by characteristic in the case of, can also suppress load, the influence of parasitic capacitance of clock.That is, this reality The equalizer 100 for applying mode is adapted for the circuit of broadband action.
Further, equalizer 100 by sampling capacitor 1013 and capacitive coupling device 1022 by being set to variable capacitance, The change of characteristic is easier.Thus, for example, change or the electricity of the communication environment of change for environment temperature or supply voltage etc. The influence of the deviation of circuit component, can adaptively feature change.
As the structure of variable capacitance, it can enumerate by the method for the connected electric capacity number of switch control and by voltage Control to make the method for capacitance variation to the magnitude of voltage that varactor capacitance applies.It is also same in this embodiment afterwards Sample.
In addition, switch 1012,1021 can also be made up of transistor.The feelings of transistor are being manufactured by fine CMOS technology Under condition, the structure of common transistor is used as, it is known that employ the structure of nmos pass transistor, employ the knot of PMOS transistor Structure, employ NMOS and PMOS complementary switch structure.
In addition, in the above description, in Fig. 4 A~Fig. 4 C, illustrating the charge accumulation to sampling capacitor 1013, adopting Electric charge between sample capacitor 1013 and capacitive coupling device 1022 shares situation about being carried out with different timings, but the present invention is not limited In this.Charge accumulation and electric charge, which are shared, to be carried out with identical timing.It is shared fixed with identical in charge accumulation and electric charge In the case of Shi Jinhang, terminal e~h is upper by input control signal S respectively1、S2、S3、S4.That is, it is being displaced to the situation of lower frequency side Under, on terminal e~h, S can be inputted respectively1、S2、S3、S4, S can be inputted respectively2、S3、S4、S1, can be by defeated respectively Enter S3、S4、S1、S2, S can also be inputted respectively4、S1、S2、S3。
In addition, according to the frequency characteristic to be realized, can also be to capacitive coupling device CIMPlus buffer, capacitive coupling is exported The voltage of device.
(embodiment 2)
Then, embodiments of the present invention 2 are illustrated.Present embodiment is the balanced device electricity for being connected to multiple embodiments 1 The circuit structure of the structure on road 100.
[structure of equalizer 200 and action]
Fig. 7 is the figure of one of the structure for the equalizer 200 for representing embodiment 2.Equalizer shown in Fig. 7 200 have：IQ frequency mixers 201-1,201-2；Alternate connection unit 202-1,202-2；(control signal is generated clock forming circuit Circuit) 203；And output buffer 204-1~204-4.Clock forming circuit shown in clock forming circuit 203 and Fig. 4 A 103 be same.
The structure of IQ frequency mixers 101 shown in IQ frequency mixers 201-1,201-2 structure and Fig. 4 B is same.In addition, The structure of alternate connection unit 102 shown in alternate connection unit 202-1,202-2 structure and Fig. 4 C is same.But, The control signal for being input to alternate connection unit 202-1 and the control signal for being input to 202-2 are different from each other.
Specifically, on alternate connection unit 202-1 terminal e~h, by input control signal S respectively3、S4、S1、 S2.In this case, alternate connection unit 202-1 capacitive coupling device 1022 is with IB phase paths, QB phase paths, I phase paths, Q The reiteration connection of phase path.Moreover, alternate connection unit 202-1 capacitive coupling device 1022 is with IQ frequency mixers 201-1's Sampling capacitor 1013-3,1013-4,1013-1,1013-2 sequentially carry out electric charge and shared.That is, (the 1st alternate opens the 1st switch Close) 1021-1, the 2nd switch (the 2nd alternate switch) 1021-2, the 3rd switch (the 3rd alternate switch) 1021-3, the 4th switch (the 4th phase Between switch) order of connection of 1021-4 each switch is the ascending order from N (N is one of integer from 1 to 4) switch.And And, the 4th the switch 1021-4, the 1st switch 1021-1 that continue is connected to the access path of 4 phases.4 are connected to repeatedly by switch 1021 The access path of phase, alternate connection unit 202-1 capacitive coupling device 1022 with phase as I phases, Q phases, IB phases, QB phases The same order of rotation is connected to the access path of 4 phases.Moreover, by IQ frequency mixers 201-1 and alternate connection unit In the circuit that 202-1 is constituted, the order of the accumulation of input charge is identical with the order that electric charge is shared.
On the other hand, on alternate connection unit 202-2 terminal e~h, by input control signal S respectively3、S2、S1、 S4.In this case, alternate connection unit 202-2 capacitive coupling device 1022 is with IB phase paths, Q phase paths, I phase paths, QB The reiteration connection of phase path.Moreover, alternate connection unit 202-1 capacitive coupling device 1022 is with IQ frequency mixers 201-2's Sampling capacitor 1013-3,1013-2,1013-1,1013-4 sequentially carry out electric charge and shared.That is, (the 1st alternate opens the 1st switch Close) 1021-1, the 2nd switch (the 2nd alternate switch) 1021-2, the 3rd switch (the 3rd alternate switch) 1021-3, the 4th switch (the 4th phase Between switch) 1021-4 each switch connects from M (M is one of integer from 1 to 4) switch with descending.Moreover, continuing 1st switch 1021-1, the 4th switch 1021-4 is connected to the access path of 4 phases.Connected repeatedly by switch 1021, alternate connection Unit 202-1 capacitive coupling device 1022 relative to phase place as I phases, Q phases, IB phases, QB phases order, with opposite suitable Sequence is connected to the access path of 4 phases.Moreover, in the circuit being made up of IQ frequency mixers 201-2 and alternate connection unit 202-2, The shared order of electric charge is opposite with the order of the accumulation of input charge.
In equalizer 200, it is connected to IQ frequency mixers 201-1 alternate connection unit 202-1 and is connected to IQ and mix Frequency device 201-2 alternate connection unit 202-2 it is respective in switch 1021 the order of connection it is different from each other.
About the action of specific equalizer 200, with the action of the equalizer 100 illustrated in embodiment 1 It is likewise, so the description thereof will be omitted.
In the circuit being made up of IQ frequency mixers 201-1 and alternate connection unit 202-1, capacitive coupling device 1022 with I Phase, Q phases, IB phases, the same order of phase place as QB phases are connected to the access path of 4 phases, so as implemented Illustrate in mode 1, can realize that the peak value of gain is moved to the frequency characteristic of minus side relative to center.In addition, being mixed by IQ In the circuit that frequency device 201-2 and alternate connection unit 202-2 are constituted, capacitive coupling device 1022 with relative to I phases, Q phases, IB phases, The access path of 4 phases is connected to, so such as explanation in embodiment 1 the order reverse order of phase place as QB phases , it can realize that the peak value of gain is moved to the frequency characteristic of positive side relative to center.
In the figure 7, output buffer 204-1~204-4 is connected respectively to and the signal from IQ frequency mixers 201-1 outputs Phase and from IQ frequency mixers 201-2 export signal phase be anti-phase relation path.Output buffer 204-1~204- 4 be by the structure of the difference output of 2 signals of input.For example, output buffer 204-1 be connected to it is defeated from IQ frequency mixers 201-1 Go out the signal of I phases I phase paths and from IQ frequency mixers 201-2 export IB phases signal IB phase paths, export I phases signal and The difference of the signal of IB phases.That is, output buffer 204-1~204-4 is respectively the structure for the difference for exporting inversion signal.
That is, output buffer 204-1~204-4 output embodiment 1, to minus side travel frequency characteristic circuit and to The difference of the inversion signal of the circuit of positive side travel frequency characteristic.
Here, the structure of the output buffer of the difference of output inversion signal is illustrated, but it is also possible to constitute output buffer, So that difference, in-phase signal sum, the inversion signal sum of output in-phase signal.
For example, the output buffer of output in-phase signal sum can also be connected respectively to from IQ frequency mixers 201-1 outputs Signal phase and from IQ frequency mixers 201-2 export signal phase be with phase relation path.Moreover, output buffer 2 signal sums of input are exported.For example, output buffer 204-1, which can also be connected to from IQ frequency mixers 201-1, exports I The I phase paths of the signal of phase and from IQ frequency mixers 201-2 export I phases signal I phase paths, export each IQ frequency mixer output I phases signal sum.
Then, the frequency characteristic of equalizer 200 is specifically described.Fig. 8 is the equalizer for representing embodiment 2 The figure of the result of the circuit simulation of 200 frequency characteristic.Fig. 8 transverse axis represents output frequency, and the longitudinal axis represents gain.Further, defeated Go out frequency with incoming frequency-fCKRepresent.In addition, Fig. 8 is CS=50fF, fCK=60GHz, gm=10mS, by capacitive coupling device Capacitance is as parameter from CIM1=30fF and CIM2=40fF (Fig. 8 solid line (A)), which becomes, turns to CIM1=40fF and CIM2=30fF The frequency characteristic of equalizer 200 in the case of (Fig. 8 dotted line (B)).Here, by alternate connection unit 202-1 The capacitance of capacitive coupling device 1022 is set to CIM1, the capacitance of the capacitive coupling device 1022 in alternate connection unit 202-1 is set For CIM2。
As shown in figure 8, equalizer 200 can realize with relative to off-centring to minus side gain peak value with It is displaced to the frequency characteristic of the peak value of the gain of positive side.That is, equalizer 200 can realize the left and right in the pass-band with fluctuation Asymmetrical frequency characteristic.
Further, equalizer 200 can also be by CIM1And CIM2It is fixed, by CS1And CS2It is used as parameter.CS1It is IQ frequency mixers 201-1 capacitance.Cs2It is IQ frequency mixers 201-2 capacitance.In addition, in the figure 7, illustrating be connected to 2 as an example The equalizer 200 of equalizer 100 shown in Fig. 4 A, but equalizer 200 can also connect the equilibrium of more than 3 Device circuit 100.
Further, in the figure 7, being input to the order of alternate connection unit 202-1 control signal and being input to alternate connection The order of unit 202-2 control signal is reverse order.But, according to the frequency characteristic to be realized, it is input to alternate connection The order of the order of unit 202-1 control signal and the control signal for being input to alternate connection unit 202-2 can also be phase With order.
Further, according to the frequency characteristic of calibration object, can also share the inside of IQ frequency mixers TA (Fig. 4 B's TA1011)。
[effect]
As more than, according to present embodiment, by connecting the structure of multiple embodiments 1, it can be achieved to have in the pass-band The asymmetrical frequency characteristic in left and right of fluctuation.Frequency characteristic accordingly, for the different multistage RF amplifiers of gain peak, There is the frequency characteristic of the propagation path of fluctuation, the equalizer 200 of present embodiment can be reduced in frequency band partially in frequency band Difference.
(embodiment 3)
Then, embodiments of the present invention 3 are illustrated.Equalizer in present embodiment is more simply to realize and real Apply the structure of the equal characteristic of equalizer 100 of mode 1.
[structure of equalizer 300 and action]
Fig. 9 is the figure of one of the structure for the equalizer 300 for representing embodiment 3.Equalizer shown in Fig. 9 300 have：IQ frequency mixers 301 comprising capacitive coupling device 302；Clock forming circuit 303；And output buffer 304-1~ 304-4.The structure of equalizer 300, except capacitive coupling device 302 is connected to the output of the TA3011 in IQ frequency mixers 301 Outside side, the alternate connection unit 102 in equalizer 100 shown in substitution Fig. 4 A~Fig. 4 C, it is with equalizer 100 Same structure, so omitting detailed description.Clock forming circuit 103 shown in clock forming circuit 303 and Fig. 4 A is same Sample.
The present embodiment point different from embodiment 1 is that capacitive coupling device 302 is connected in IQ frequency mixers 301 TA3011 outlet side.Capacitive coupling device 302 is comprised in IQ frequency mixers 301, so in the present embodiment, in balanced device The alternate connection unit illustrated in embodiment 1 is not included in circuit 300.
Capacitive coupling device 302 keeps the electric charge before 1/4 cycle, initial before starting as the action of equalizer 300 State.
[action of equalizer 300]
Then, the action in equalizer 300 is illustrated.
In the same manner as the equalizer 100 of embodiment 1, each cycle T of 300 pairs of equalizerCKElectric charge is carried out to be total to Enjoy and charge accumulation.3 kinds of following electric charges are carried out electric charge and shared by equalizer 300.
(2-a) TA3011 is by input voltage signal VINBe converted to the electric charge (following, to be recited as input charge) obtained by electric current
The electric charge that (2-b) capacitive coupling device 302 is kept
The electric charge that (2-c) sampling capacitor 3013 is kept
Equalizer 300 passes through based on the control signal S shown in Fig. 51~S4Switch 3012-1~3012-4 control (conducting and cut-off), in 1 cycle (1TCK) interior ensuing 4 actions of progress, to each cycle TCKThese actions are repeated.
1st action：Control signal S1During for " height ", input charge is accumulated in capacitive coupling device 302 and sampling In capacitor 3013-1.Before the immediately charge accumulation, the electric charge before 1/4 cycle is kept in capacitive coupling device 302, is being adopted By the electric charge before 1 cycle of accumulation in sample capacitor 3013-1.While the accumulation of input charge, capacitive coupling device 302 and adopt Sample capacitor 3013-1 carries out electric charge and shared.
2nd action：Control signal S2During for " height ", input charge is accumulated in capacitive coupling device 302 and sampling In capacitor 3013-2.Before the immediately charge accumulation, the electric charge before 1/4 cycle is kept in capacitive coupling device 302, is being adopted By the electric charge before 1 cycle of accumulation in sample capacitor 3013-2.While the accumulation of input charge, capacitive coupling device 302 and adopt Sample capacitor 3013-2 carries out electric charge and shared.
3rd action：Control signal S3During for " height ", input charge is accumulated in capacitive coupling device 302 and sampling In capacitor 3013-3.Before the immediately charge accumulation, the electric charge before 1/4 cycle is kept in capacitive coupling device 302, is being adopted By the electric charge before 1 cycle of accumulation in sample capacitor 3013-3.While the accumulation of input charge, capacitive coupling device 302 and adopt Sample capacitor 3013-3 carries out electric charge and shared.
3rd action：Control signal S4During for " height ", input charge is accumulated in capacitive coupling device 302 and sampling In capacitor 3013-4.Before the immediately charge accumulation, the electric charge before 1/4 cycle is kept in capacitive coupling device 302, is being adopted The electric charge accumulated in sample capacitor 3013-4 before 1 cycle.While the accumulation of input charge, capacitive coupling device 302 and adopt Sample capacitor 3013-4 carries out electric charge and shared.
Output buffer 304-1~304-4 is transfused in 4 phases of I phases, Q phases, IB phases, QB phases are respective, input charge Accumulation continuous voltage change, and the shared instantaneous voltage caused of electric charge of sampling capacitor and capacitive coupling device becomes Change, these voltage changes are directly exported, or are multiplied by fixed multiple export output voltage signal.
The each cycle T of 300 pairs of equalizerCKThe 1st action, the 2nd action, the 3rd action, the 4th action is repeated.Pass through The 1st action is repeated to the 4th action, the accumulation of input charge is with sampling capacitor 3013-1,3013-2,3013-3,3013- 4 reiteration is carried out.Moreover, capacitive coupling device 302 and sampling capacitor 3013-1,3013-2,3013-3,3013-4 order Ground carries out electric charge and shared.In this case, the shared order of the order and electric charge of the accumulation of input charge is also identical, input The timing that the timing of the accumulation of electric charge and electric charge are shared is also identical.
For the 1st action to the 4th action, the table mathematically relevant with the discrete system of the core as frequency characteristic Reach, be same with embodiment 1.Thus, in the same manner as embodiment 1, in transfer function HDIn can realize complex coefficient j.Therefore, equalizer 300 can realize the frequency characteristic same with Fig. 6 A.
[effect]
As more than, according to present embodiment, with it is shown in Fig. 6 A, relative to the asymmetrical frequency characteristic in center or so, The wave filter of deviation in adjustable frequency band can be realized.That is, according to present embodiment, for example, can reduce due to Figure 1A institutes Deviation in the frequency band that the frequency characteristic of the RF circuits shown is caused.In addition, by the way that capacitive coupling device 302 is connected into the defeated of TA3011 Go out, so that than the simple structure of embodiment 1, the characteristic same with embodiment 1 can be realized.
(embodiment 4)
Then, embodiments of the present invention 4 are illustrated.Present embodiment is by the phase of the equalizer 100 of embodiment 1 Between connection unit 102 be connected to multiple circuit structures.
[structure of equalizer 400]
Figure 10 is the figure of one of the structure for the equalizer 400 for representing embodiment 4.Balanced device electricity shown in Figure 10 Road 400 has：IQ frequency mixers 401；Alternate connection unit 402-1,402-2；Clock forming circuit 403；And output buffer 404-1~404-4.The structure of IQ frequency mixers 101 shown in the structure and Fig. 4 B of IQ frequency mixers 401 is same.Alternate connection The structure of alternate connection unit 102 shown in unit 402-1,402-2 structure and Fig. 4 C is same.Clock forming circuit 403 be same with the clock forming circuit 103 shown in Fig. 4 A.Output buffer 404-1~404-4 respectively with shown in Fig. 4 A Output buffer 104-1~104-4 is same.
That is, the structure of equalizer 400 is that a phase has been added in the equalizer 100 shown in embodiment 1 Between connection unit structure.
[structure of equalizer 500]
Figure 11 is the figure of one of the structure for the equalizer 500 for representing embodiment 4.Balanced device electricity shown in Figure 11 Road 500 has：IQ frequency mixers 501；Alternate connection unit 502-1,502-2,502-3；Clock forming circuit 503；And output Buffer 504-1~504-4.The structure of IQ frequency mixers 101 shown in the structure and Fig. 4 B of IQ frequency mixers 501 is same.Phase Between connection unit 502-1,502-2,502-3 structure and Fig. 4 C shown in alternate connection unit 102 be same.Clock is generated The structure of circuit 503 is same with the clock forming circuit 103 shown in Fig. 4 A.Output buffer 504-1~504-4 respectively with Output buffer 104-1~104-4 shown in Fig. 4 A is same structure.
That is, the structure of equalizer 500 be added in the equalizer 100 shown in embodiment 12 it is alternate The structure of connection unit.
[structure of equalizer 600]
Figure 12 is the figure of one of the structure for the equalizer 600 for representing embodiment 4.Balanced device electricity shown in Figure 12 Road 600 has：IQ frequency mixers 601；Alternate connection unit 602-1,602-2,602-3,602-4；Clock forming circuit 603；With And output buffer 604-1~604-4.The structure of IQ frequency mixers 601 and the structure of the IQ frequency mixers 101 shown in Fig. 4 B are same 's.The structure of alternate connection unit 102 shown in alternate connection unit 602-1~602-4 structure and Fig. 4 C is same.When Clock forming circuit 103 shown in clock generative circuit 603 and Fig. 4 A is same.Output buffer 604-1~604-4 respectively with Output buffer 104-1~104-4 shown in Fig. 4 A is same.
That is, the structure of equalizer 600 be added in the equalizer 100 shown in embodiment 13 it is alternate The structure of connection unit.
The control signal for the multiple alternate connection units being input in equalizer 400,500,600, it is alternate at each It is different in connection unit.Therefore, the switch 1021-1 for each alternate connection unit that equalizer 400,500,600 has~ The timing of 1021-4 connection is different between alternate connection unit.For example, in equalizer 400, alternate connection unit Control signal S1 is transfused in 402-1 terminal e, so alternate connection unit 402-1 switch 1021-1 is in control signal S1 It is connected in during for " height ".On the other hand, control signal S2 is transfused in alternate connection unit 402-2 terminal e, so Alternate connection unit 402-2 switch 1021-1 is connected in during control signal S2 is " height ".That is, in equalizer In 400, the switch 1021-1 that alternate connection unit 402-1,402-2 each have is connected in timing different from each other.In phase Between be also same in connection unit 402-1,402-2 switch 1021-2,1021-3,1021-4 for each having.In addition, in equilibrium It is also same in device circuit 500,600.
Switch 1021-1~the 1021-4 for each alternate connection unit that equalizer 400,500,600 has connection Timing is different between alternate connection unit, and on the other hand, switch 1021-1~1021-4 of each alternate connection unit is connected repeatedly The order of connection connect is mutually the same.As a result, the order of connection of capacitive coupling device be with as I phases, Q phases, IB phases, QB phases The same order of phase place.Moreover, the shared order of the electric charge of capacitive coupling device and sampling capacitor and sampling electricity The order of the accumulation of input charge in container is identical.
For example, in the case of equalizer 600, the accumulation of input charge with sampling capacitor 1013-1,1013-2, 1013-3,1013-4 reiteration are carried out.
Moreover, alternate connection unit 602-1 capacitive coupling device 1022 is with the sampling capacitor 1013- of IQ frequency mixers 601 1st, 1013-2,1013-3,1013-4 reiteration connection, carry out electric charge and share.Alternate connection unit 602-2 capacitive coupling Device 1022 is connected with sampling capacitor 1013-2,1013-3,1013-4,1013-1 of IQ frequency mixers 601 reiteration, is carried out Electric charge is shared.Alternate connection unit 602-3 capacitive coupling device 1022 with the sampling capacitor 1013-3 of IQ frequency mixers 601, 1013-4,1013-1,1013-2 reiteration connection, carry out electric charge and share.Alternate connection unit 602-4 capacitive coupling device 1022 are connected with sampling capacitor 1013-4,1013-1,1013-2,1013-3 of IQ frequency mixers 601 reiteration, carry out electricity Lotus is shared.
In equalizer 400,500,600, the order of connection of capacitive coupling device with I phases, Q phases, IB phases, QB phases so The order of phase place be identical order, so as described in embodiment 1, the energy of equalizer 400,500,600 Enough realize frequency characteristic of the peak value relative to off-centring to minus side of gain.Moreover, making the connection number of alternate connection unit In the case of increased, amount of movement can be increased.
Further, with relative to connecting phase as I phases, Q phases, IB phases, QB phases the order reverse order of phase place Between capacitor control signal be input into each alternate connection unit in the case of, can make the frequency characteristic of equalizer turns into The peak value for making gain relative to center is moved to positive side.
Specifically, the frequency characteristic of equalizer 400,500,600 is illustrated.Figure 13 is the equilibrium for representing embodiment 4 The figure of the result of the circuit simulation of the frequency characteristic of device circuit 400,500,600.Figure 13 transverse axis represents output frequency, longitudinal axis table Show the gain standardized with maximum gain.Further, output frequency is with incoming frequency-fCKRepresent.In addition, in fig. 13, as than Compared with example, the frequency characteristic of the equalizer 100 shown in embodiment 1 is also illustrated.Figure 13 represents under the same terms, balanced The frequency characteristic of device circuit 100,400,500,600.Condition is CS=50fF, fCK=60GHz, gm=10mS, capacitive coupling device Capacitance CIM=40fF.
As shown in figure 13, the number of the alternate connection unit of equalizer is more, I phases, Q phases, IB phases, QB phases it is respective Phase system in, the connection number of times of capacitive coupling device increase, so in frequency characteristic, with respect to the shifting of the gain peak at center Momentum is bigger.
[effect]
As more than, according to present embodiment, by connecting the structure of multiple alternate connection units in equalizer, i.e., Make identical circuit component values (capacitance of sampling capacitor and capacitive coupling device) also can be by the frequency direction of gain peak Amount of movement increase.
(embodiment 5)
Then, embodiments of the present invention 5 are illustrated.Present embodiment is the balanced device by embodiment 2 and embodiment 4 Circuit is connected to multiple circuit structures.
[structure of equalizer 700 and action]
Figure 14 is the figure of one of the structure for the equalizer 700 for representing embodiment 5.Balanced device electricity shown in Figure 14 Road 700 has：IQ frequency mixers 701-1,701-2,701-3；Alternate connection unit 702-1~702-6；Clock forming circuit 703； And output buffer 704-1~704-8.Clock forming circuit 103 shown in clock forming circuit 703 and Fig. 4 A is same 's.
(the 3rd turn of IQ frequency mixers (the 1st converting unit) 701-1, IQ frequency mixer (the 2nd converting unit) 701-2, IQ frequency mixer Change unit) 701-3 structure and the structure of the IQ frequency mixers 101 shown in Fig. 4 B be same.In addition, alternate connection unit 702- The structure of alternate connection unit 102 shown in 1~702-6 structure and Fig. 4 C is same.But, it is input to alternate connection single Member (the 1st alternate connection unit) 702-1, alternate connection unit (the 2nd alternate connection unit) 702-2, alternate connection unit 702- 3rd, alternate connection unit 702-4, alternate connection unit 702-5, alternate connection unit 702-6 control signal it is respectively different.
Output buffer 704-1~704-8 is the structure of the difference for 2 signals that output is transfused to.In the case of fig. 14, Output buffer 704-1~704-8 is the structure of the difference of output inversion signal.
In equalizer 700, comprising IQ frequency mixers 701-1,701-2, alternate connection unit 702-1,702-2, with And the equalizer 200 of the structure of output buffer 704-1~704-4 part and embodiment 2 is same.
In addition, in equalizer 700, the portion comprising IQ frequency mixers 701-3, alternate connection unit 702-3~702-6 The equalizer 600 of the structure divided and the embodiment 4 for eliminating output buffer is same.
That is, the equalizer 700 of present embodiment is the equalizer 200 and reality for being connected in parallel embodiment 2 Apply the structure of the equalizer 600 of mode 4.The equalizer 200 of embodiment 2 is be connected to 2 embodiments 1 equal The structure of weighing apparatus circuit 100.That is, the equalizer 700 of present embodiment is the structure for being connected to 3 equalizers.Again Have, be same action about the action illustrated in the action of equalizer 700, with the grade of embodiment 1, so omitting detailed Explanation.
Moreover, the equalizer 700 of present embodiment has the anti-phase of the equalizer 200 of output embodiment 2 The structure of the difference of the inversion signal of signal and the equalizer of embodiment 4 400.
Here, the output buffer structure of the difference of output inversion signal is illustrated, but it is also possible to constitute output buffer, make It exports difference, in-phase signal sum, the inversion signal sum of in-phase signal.
In addition, according to the frequency characteristic of calibration object, the TA inside IQ frequency mixers can also be shared.
Specifically, the frequency characteristic of equalizer 700 is illustrated.Figure 15 is the equalizer for representing embodiment 5 The figure of the result of the circuit simulation of 700 frequency characteristic.Figure 15 transverse axis represents output frequency, and the longitudinal axis represents gain.Further, defeated Go out frequency with incoming frequency-fCKRepresent.In addition, the transconductance value of the TA in IQ frequency mixers 701-1~701-3 is set into gm1、 gm2、gm3.The capacitance of capacitive coupling device in alternate connection unit 702-1~702-3 is set to CIM1、CIM2、CIM3.This Outside, in the same manner as alternate connection unit 702-3, the capacitance of the capacitive coupling device in alternate connection unit 702-4~702-6 is CIM3.Figure 15 circuit simulation represents CS=50fF, fCK=60GHz, CIM1=30fF, CIM2=40fF, CIM3=20fF, makes gm1、 gm2、gm3Frequency characteristic in the case of a variety of changes.Figure 15 solid line (A) represents gml=10mS, gm2=5mS, gm3=30mS In the case of frequency characteristic.Figure 15 dotted line (B) represents gm1=gm2=gm3Frequency characteristic in the case of=10mS.Figure 15 Dotted line (C) represent gm1=5mS, gm2=10mS, gm3Frequency characteristic in the case of=30mS.As shown in figure 15, it is known that pass through The connection of the equalizer of 3, obtains multiple fluctuations in frequency characteristic.
[effect]
As more than, according to present embodiment, by the way that the equalizer for carrying out Periodic time-varying continuous time processing is connected It is multiple, the asymmetrical frequency characteristic in left and right in the pass-band with fluctuation can be achieved.Thus, even in different many of gain peak The frequency characteristic of the RF amplifiers of level and broadcast according to Den in the case that channel occurs in that fluctuation in frequency band, according to this embodiment party Formula, can also reduce deviation in frequency band.
Further, in the example of present embodiment, illustrating the equalizer 200 of embodiment 2 (being connected to 2 realities Apply the structure of the equalizer 100 of mode 1) and embodiment 4 the structure that is connected in parallel of equalizer 600, it is but real Apply the number not limited to this of the number of the equalizer 100 of mode 1 and the equalizer 600 of embodiment 4.Pay no attention to arbitrarily Change moves left (minus side movement), moves right (positive side movement), the number of alternate connection unit.That is, can also be multiple accurate in parallel The standby equalizer with the arbitrarily alternate connection unit of number, output is synthesized.According to environment, it can also change what is used The number of equalizer, the number of alternate connection unit, move left and move right, change frequency characteristic.
(embodiment 6)
Illustrate embodiments of the present invention 6.Present embodiment the equalizer of each embodiment is set to by positive and The difference structure that 2 anti-phase systems are constituted.In the case where equalizer is set into difference structure, by positive and anti-phase Each upper each embodiment of connection shown in equalizer, can obtain same with the effect of each embodiment of described above The effect of sample.
In addition, in the case where equalizer is set into difference structure, change capacitive coupling device is with respect to positive and anti-phase Respective I phase paths, Q phase paths, IB phase paths, the link position of the access path of 4 phases of QB phase paths.Thus, it is related Capacitor can be connected with the same order with phase place as I phases, Q phases, IB phases, QB phases, and be carried out inclined The electric charge for moving for 3/4 cycle (that is, -1/4 cycle) is shared.As a result, in the transmission function of equalizer, being added in imaginary number list Sign-inverted on position, so the balanced device of the frequency characteristic with gain peak relative to off-centring to positive side can be realized Circuit.Hereinafter, reference picture 16, illustrate the equalizer 100 shown in embodiment 1 being set to difference structure, relevant capacitor Device is connected with the same order with phase place as I phases, Q phases, IB phases, QB phases, and offset by 3/4 week The shared example of the electric charge of phase (that is, -1/4 cycle).
Figure 16 is the figure of one of the equalizer 800 for representing embodiment 6.Equalizer 800 is by embodiment party The equalizer 100 of formula 1 is set to the circuit of difference structure.Further, representing Figure 16 terminal T1~T4 and terminal T1B~T4B In connection line, omit for convenience of description.
The analog signal of input is input voltage signal V by TA8011INBe converted to positive (Figure 16 just (+) side) and anti-phase The electric current of 2 systems of (Figure 16 negative (-) side) and output.Hereinafter, it will claim in the structure set by the side of the electric current of output positive For positive phase system, reversed-phase system will be referred to as in the structure set by the side of the anti-phase electric current of output.
In positive phase system, switch 8012-1~8012-4, sampling capacitor 8013-1~8013-4 and output buffer 804-1~804-4 respectively with switch 1012-1~1012-4 shown in Fig. 4 A, 4B, sampling capacitor 1013-1~1013-4 and Output buffer 104-1~104-4 is same.In the same manner as embodiment 1, the signal of I phases will be exported in positive phase system Path, path, path, the path of signal that exports QB phases of the signal for exporting IB phases of the signal for exporting Q phases be referred to as I phase paths, Q phase paths, IB phase paths, the QB phase paths of positive phase system.
In reversed-phase system, switch 8012-5~8012-8, sampling capacitor 8013-5~8013-8 and output buffer 804-5~804-8 respectively with switch 1012-1~1012-4 shown in Fig. 4 A, 4B, sampling capacitor 1013-1~1013-4 and Output buffer 104-1~104-4 is same.In the same manner as embodiment 1, the signal of I phases will be exported in reversed-phase system Path, path, path, the path for the signal for exporting QB phases of the signal for exporting IB phases of the signal for exporting Q phases are referred to as instead I phase paths, Q phase paths, IB phase paths, the QB phase paths of phase system.
Clock forming circuit 103 shown in clock forming circuit 803 and Fig. 4 A is 4 phases likewise, shown in supply Fig. 5 Control signal S1, S2, S3 and S4.
The structure of alternate connection unit 102 shown in alternate connection unit 802-1,802-2 structure and Fig. 4 C is same 's.But, alternate connection unit 802-1,802-2 terminal T1~T4, T1B~T4B link position and alternate connection unit The link position of terminal T1~T4 in 102 is different.Then, the link position of the terminal based on alternate connection unit is different, says The action of bright equalizer 800.
Equalizer 800 passes through based on the control signal S shown in Fig. 51~S4 switch 8012-1~8012-8 and open 8021-1~8021-8 control (conducting and cut-off) is closed, in 1 cycle (1TCK) interior ensuing 4 actions of progress, to each week Phase TCKThese actions are repeated.
1st action：Control signal S1During for " height ", the positive that sampling capacitor 8013-1 is connected to TA8011 is defeated Go out side, input charge is accumulated in sampling capacitor 8013-1.In addition, sampling capacitor 8013-5 is connected to the anti-of TA8011 Phase outlet side, input charge is accumulated in sampling capacitor 8013-5.Before the immediately charge accumulation, in sampling capacitor The electric charge before 1 cycle is kept in 8013-1,8013-5 respectively.In the input charge to sampling capacitor 8013-1,8013-5 While accumulation, capacitive coupling device 8022-1 is connected to sampling capacitor 8013-3, and capacitive coupling device 8022-2 is connected to sampling Capacitor 8013-7, carries out electric charge and shares respectively.
2nd action：Control signal S2During for " height ", the positive that sampling capacitor 8013-2 is connected to TA8011 is defeated Go out side, input charge is accumulated in sampling capacitor 8013-2.In addition, sampling capacitor 8013-6 is connected to the anti-of TA8011 Phase outlet side, input charge is accumulated in sampling capacitor 8013-6.Before the immediately charge accumulation, in sampling capacitor The electric charge before 1 cycle is kept in 8013-2,8013-6 respectively.In the input charge to sampling capacitor 8013-2,8013-6 While accumulation, capacitive coupling device 8022-1 is connected to sampling capacitor 8013-8, and capacitive coupling device 8022-2 is connected to sampling Capacitor 8013-4, carries out electric charge and shares respectively.
3rd action：Control signal S3During for " height ", the positive that sampling capacitor 8013-3 is connected to TA8011 is defeated Go out side, input charge is accumulated in sampling capacitor 8013-3.In addition, sampling capacitor 8013-7 is connected to the anti-of TA8011 Phase outlet side, input charge is accumulated in sampling capacitor 8013-7.Before the immediately charge accumulation, in sampling capacitor The electric charge before 1 cycle is kept in 8013-3,8013-7 respectively.In the input charge to sampling capacitor 8013-3,8013-7 While accumulation, capacitive coupling device 8022-1 is connected to sampling capacitor 8013-1, and capacitive coupling device 8022-2 is connected to sampling Capacitor 8013-5, carries out electric charge and shares respectively.
4th action：Control signal S4During for " height ", the positive that sampling capacitor 8013-4 is connected to TA8011 is defeated Go out side, input charge is accumulated in sampling capacitor 8013-4.In addition, sampling capacitor 8013-8 is connected to the anti-of TA8011 Phase outlet side, input charge is accumulated in sampling capacitor 8013-8.Before the immediately charge accumulation, in sampling capacitor The electric charge before 1 cycle is kept in 8013-4,8013-8 respectively.In the input charge to sampling capacitor 8013-4,8013-8 While accumulation, capacitive coupling device 8022-1 is connected to sampling capacitor 8013-6, and capacitive coupling device 8022-2 is connected to sampling Capacitor 8013-2, carries out electric charge and shares respectively.
The each cycle T of 800 pairs of equalizerCKSequentially be repeated the 1st action, the 2nd action, the 3rd action, the 4th move Make.By the way that the accumulation of the input charge in the 1st action to the 4th action, positive phase system is sequentially repeated with sampling capacitor 8013-1,8013-2,8013-3,8013-4 reiteration are carried out.In addition, capacitive coupling device 8022-1 is with the IB of positive phase system Phase path, the QB phase paths of reversed-phase system, the I phase paths of positive phase system, the reiteration of the Q phase paths of reversed-phase system are connected to The access path of 4 phases.Moreover, capacitive coupling device 8022-1 and sampling capacitor 8013-3,8013-8,8013-1,8013-6 are suitable Electric charge is carried out to sequence to share.In addition, capacitive coupling device 8022-2 is with the IB phase paths of reversed-phase system, the QB phases road of positive phase system Footpath, the I phase paths of reversed-phase system, the reiteration of the Q phase paths of positive phase system are connected to the access path of 4 phases.Moreover, alternate Capacitor 8022-2 sequentially carries out electric charge with sampling capacitor 8013-7,8013-4,8013-5,8013-2 and shared.
In positive phase system and reversed-phase system, in each path, phase 180 ° of differences each other.For example, the QB of reversed-phase system The phase of the signal of phase path and the phase of the signal of the Q phases of positive phase system are equal.In addition, the letter of the QB phase paths of positive phase system Number phase and reversed-phase system Q phase paths signal phase it is equal.That is, capacitive coupling device 8022-1 is with the IB of positive phase system Phase path, the QB phase paths of reversed-phase system, the I phase paths of positive phase system, the reiteration of the Q phase paths of reversed-phase system connect this The order of connection of sample, with capacitive coupling device 8022-1 with the IB phase paths of positive phase system, the Q phase paths of positive phase system, positive system The I phase paths of system, such order of connection that is linked in sequence of the QB phase paths of positive phase system are equal.In addition, in capacitive coupling device It is also same in 8022-2.Therefore, capacitive coupling device can while with phase place as I phases, Q phases, IB phases, QB phases Same order is connected, while the electric charge for offset by 3/4 cycle (that is, -1/4 cycle) is shared.As a result, implementing In the transmission function of the equalizer 800 of mode 6, by making to be added in the sign-inverted in imaginary unit, gain can be realized Frequency characteristic of the peak value relative to off-centring to positive side.
(embodiment 7)
Illustrate embodiments of the present invention 7.Present embodiment be for the equalizer 100 of embodiment 1 IQ mix Frequency device 101 and alternate connection unit 102 input the structure of the clocks (control signal) different from embodiment 1.
[structure of equalizer 900 and action]
Figure 17 A are the figures of one of the structure for the equalizer 900 for representing embodiment 7.The IQ of equalizer 900 The equalizer 100 of frequency mixer 101, alternate connection unit 102, output buffer 104 and Fig. 4 A has same structure.Figure The difference of 17A equalizer 900 and Fig. 4 A equalizer 100 is that equalizer 900 has 2 clocks Generative circuit (clock forming circuit 903-1 and clock forming circuit 903-2).
IQ frequency mixers 101 are input into from the clock forming circuit 903-1 control signal L1~L4 exported.From clock generation Control signal S1~S4 of circuit 903-2 outputs is input into alternate connection unit 102.
One of control signal L1~L4 waveform is represented in Figure 17 B.One and Fig. 5 of control signal S1~S4 waveform Shown waveform is same.TL is control signal L1~L4 pulse width.Cycle TLoIt is control signal L1~L4 cycle. Control signal L1~L4 cycle TLoIt is TLo=TCK/M.Wherein TCKIt it is control signal S1~S4 cycle, M is arbitrary positive number.
Control signal L1~L4 is different with control signal S1~S4 frequency.M is determined so that control signal L1~L4 Clock frequency fLO(fLO=1/TLo) it is used for the carrier wave by RF signal frequency conversions for the RF signals of baseband signal with IQ frequency mixers 101 Frequency is consistent.In addition, control signal S1~S4 clock frequency fCK(fCK=1/TCK) be confirmed as baseband signal frequency band number Times or so.Clock forming circuit 903-1 for frequency conversion is acted in high frequency, and clock forming circuit 903-2 is moved at low frequency Make, so clock forming circuit 903-2 design comparison is easy.
But, clock forming circuit 903-1 and clock forming circuit 903-2 can also give birth to as a clock forming circuit Into control signal L1~L4, control signal S1~S4.Clock forming circuit 903-1,903-2 can export the control of blunt waveform Signal processed, can also export the control signal of sine wave and adjust its biasing.Thus, clock forming circuit 903-1,903-2 energy Enough switch conduction times realized equivalent to dutycycle for 25% clock input.
IQ frequency mixers 101 by based on control signal L1~L4 to switch 1012 (1012-1~1012-4) (reference picture 4B) ON-OFF control is carried out, by input signal frequency conversion, and by the signal output after frequency conversion to terminal T1~T4.
Alternate connection unit 102 is based on control signal S1~S4, to be connected to terminal T1~T4 switch 1021-1~ 1021-4 (reference picture 4C) carries out ON-OFF control.Thus, the signal of 4 phases of terminal T1~T4 phase offset passes through alternate Capacitor 1022 is connected.Alternate connection unit 102 often offset by phase 90 degree of signal weighting synthesis, it is achieved that plural Filter characteristic.Terminal T1~T4 current potential is multiplied by fixed multiple and exported by output buffer 104-1~104-4.
Further, the number of alternate connection unit 102 is 1 in Figure 17 A, but not limited to this.The number of alternate connection unit 102 It can also be 2~4, in the case of the number of phases of increase clock, more than 5 can also be connected.
The simulation result of the frequency characteristic of the equalizer 900 of embodiment 7 is represented in Figure 18.Figure 18 transverse axis is represented Output frequency, the longitudinal axis represents gain.Further, condition is fLO=60GHz, fCK=6GHz, gm=10mS, Cs=50fF, CIM= 40fF.As can be seen from Figure 18, equalizer 900 can realize frequency characteristic of the gain peak relative to off-centring to minus side (complex filter characteristic).
In addition, the clock forming circuit 903-1 for frequency conversion is acted in high frequency, but clock forming circuit 903-2 is low Frequency is lower to be acted, so clock forming circuit 903-2 design comparison is easy.
In addition, in the equalizer of each embodiment of described above, the switch of frequency conversion can also use singly balanced Or double-balanced mixer.
In addition, equalizer in each embodiment of described above is as carrying out frequency conversion and circuit is carried out in a balanced way Illustrate, but as long as being the input signal of 4 phases, balanced device can be used only, can also change frequency characteristic and as wave filter or Image removes frequency mixer.
(embodiment 8)
Illustrate embodiments of the present invention 8.Present embodiment is different from other embodiments 1~7, is not frequency conversion input Signal structure.Present embodiment is, for input signal, and CT (Continuous Time)/DT is added without frequency conversion The structure of the complex filter of (Discrete Time) mixed type.That is, 4 phases of the equalizer of present embodiment to input The frequency characteristic of baseband signal be corrected, output be corrected after 4 phases baseband signal.
Figure 19 A are the figures of one of the structure for the equalizer 1000 for representing embodiment 8.Further, shown in Figure 19 A Equalizer 1000 in, pair structure same with equalizer 600 shown in Figure 12 (embodiment 4) is added identical Label, and omit detailed description.The equilibrium shown in equalizer 1000 and Figure 12 (embodiment 4) shown in Figure 19 A The difference of device circuit 600 is that equalizer 1000 has voltage-current converter circuit (TA) 1001-1~1001-4 and adopted Sample capacitor 1002-1~1002-4, substitution IQ frequency mixer 601.
For example, TA1001-1~1001-4 has the structure of the preferable TA shown in Figure 19 B respectively.Further, voltage x current Change-over circuit (TA) 1001-1~1001-4 can also be made up of single or multiple transistor when mounted.
Here, the action of equalizer 1000 is illustrated.Phase often offset by input signal (the voltage letter of 90 degree of 4 phases Number VIN_I、VIN_Q、VIN_IB、VIN_QB) TA1001-1~1001-4 is input into, voltage signal is converted into current signal.Electric current The electric charge of signal is accumulated in sampling capacitor 1002-1~1002-4.Alternate connection unit 602-1~602-4 is based on control Signal S1~S4, is sequentially connected to terminal T1~T4 so that the access path (terminal T1~T4) each connected is not repeated.By The every 90 degree of different signals of this phase are weighted synthesis, so equalizer 1000 can realize complex filter characteristic. When capacitive coupling device 1022 (Fig. 4 C references) in alternate connection unit 602 is connected to terminal T1~T4, terminal T1~T4's Voltage discontinuously changes, and continuously changes when in addition.Output buffer 604-1~604-4 is by terminal T1~T4's Voltage is multiplied by fixed multiple and exported.
Further, the number of alternate connection unit 602, is in fig. 19 a 4, but not limited to this.Alternate connection unit 602 Number can be only 1~3, and more than 5 can also be connected in the case of the number of phases of increase clock.
One of the simulation result of the frequency characteristic of the equalizer 1000 of embodiment 8 is represented in Figure 20.In emulation In, VIN_IAnd 4 phase input signal between phase difference be set to VIN_I：0°、VIN_Q：-90°、VIN_IB：-180°、VIN_QB：- 270°.Figure 20 transverse axis represents output frequency, and the longitudinal axis represents gain (Gain).As can be seen from Figure 20, equalizer 1000 can Realize that gain peak is moved to the frequency characteristic (complex filter characteristic) of positive side relative to center.So, equalizer 1000 can realize complex filter characteristic without variable frequency input signal.
Further, it is same with so far shown embodiment, can be by inverting the input sequence of clock, by gain peak It is moved to positive side.
(embodiment 9)
In embodiment 8, as shown in Figure 19 A, illustrate the equalizer with not variable frequency input signal structure.Implement Other embodiments can be also applicable by the structure of the not variable frequency input signal illustrated in mode 8.Embodiments of the present invention 9 explanations have been applicable the example of the not structure of variable frequency input signal for the equalizer 700 shown in Figure 14.
Figure 21 is the figure of one of the structure for the equalizer 1100 for representing embodiment 9.Further, shown in Figure 21 In equalizer 1100, pair structure same with equalizer 700 shown in Figure 14, additional identical label simultaneously omits detailed Thin explanation.Difference with the equalizer 700 shown in Figure 14 is that equalizer 1100 has TA1101-1~TA1 101-12 and sampling capacitor 1102-1~1102-12, substitution IQ frequency mixer 701.
Further, the action to the input signal in TA1101 and sampling capacitor 1102, and shown in embodiment 8 TA1001 and sampling capacitor 1002 are likewise, so omitting detailed description.
The structure of Figure 21 equalizer 1100 is that the equalizer 1000 shown in Figure 19 A is connected into multiple knots Structure.Therefore, equalizer 1100 is without frequency conversion.In addition, Figure 21 equilibrium. with the equalizer 700 shown in Figure 14 equally The structure of device circuit 1100 can realize frequency characteristic shown in Figure 15 (wherein, without frequency conversion, so the frequency phase of input and output Together).
Further, the number of alternate connection unit, the order of the clock inputted to alternate connection unit are not limited to feelings shown in Figure 21 Condition, can also arbitrarily be changed.
In addition, the equalizer in each embodiment of above-mentioned middle explanation, if the frequency characteristic timeliness to be corrected Ground changes, then component value, the number of alternate connection unit, the input sequence of clock of circuit can also be made temporally to change.
<The summary of the present invention>
The equalizer of the 1st mode of the present invention includes：
More than one alternate connection unit, by inputting respectively, generated by converted input signal, every 90 degree of phase is suitable Sequence different the 1st conversion signal, the 2nd conversion signal, the 3rd conversion signal and the 4th conversion signal, have：1st alternate switch, the 2nd It is alternate switch, the 3rd it is alternate switch and the 4th alternate switch, a terminal be connected respectively to the 1st access path, the 2nd access path, 3rd access path and the 4th access path；And capacitive coupling, be connected to the described 1st it is alternate switch, it is described 2nd it is alternate switch, Another terminal of the 3rd alternate switch and the 4th alternate switch；
Control signal generative circuit, by the reference signal of frequency as defined in conversion, phase sequence every 90 degree it is different, control Make the connection of the described 1st alternate switch, the 2nd alternate switch, the 3rd alternate switch and the 4th alternate switch or open Road, generates the control signal of 4 phases, and the control signal of 4 phase is output into the described 1st alternate switch, the described 2nd alternate opened Pass, the 3rd alternate switch and the 4th alternate switch；And
1st output buffer, the 2nd output buffer, the 3rd output buffer and the 4th output buffer, are connected respectively to institute The 1st access path, the 2nd access path, the 3rd access path and the 4th access path are stated, the output of 4 phases is exported Signal,
The 1st alternate switch, the 2nd alternate switch, the 3rd alternate switch and the 4th alternate switch are based on The control signal of 4 phase, in every 1/4 cycle, is connected repeatedly with defined order,
Order is ascending order or descending from N (N is one of integer from 1 to 4) alternate switch as defined in described.
The equalizer of the 2nd mode of the present invention, in the equalizer of the 1st mode, in addition to：
More than one converting unit, 1st conversion signal of the generation from the input signal, the 2nd conversion Signal, the 3rd conversion signal and the 4th conversion signal, one converting unit above have：Voltage to current transducer Circuit, current signal is converted to by the input signal；
1st sampling switch, the 2nd sampling switch, the 3rd sampling switch and the 4th sampling switch, one end are connected to the voltage electricity The outlet side of change-over circuit is flowed, the other end is connected respectively to the 1st access path, the 2nd access path, the 3rd company Connect path and the 4th access path；And
1st sampling capacitance, the 2nd sampling capacitance, the 3rd sampling capacitance and the 4th sampling capacitance, one end are connected respectively to described 1 access path, the 2nd access path, the 3rd access path and the 4th access path, other end ground connection,
1st sampling switch, the 2nd sampling switch, the 3rd sampling switch and the 4th sampling switch are based on The control signal of 4 phase, every 1/4 cycle, with the 1st sampling switch, the 2nd sampling switch, the 3rd sampling switch And the order of the 4th sampling switch is connected repeatedly.
The equalizer of the 3rd mode of the present invention, in the equalizer of the 1st mode,
Alternate connection unit more than one is connected in parallel to the 1st access path, the 2nd link road Footpath, the 3rd access path and the 4th access path,
The defined order of each of the alternate connection unit more than one is mutually the same,
Each the 1st alternate switch having of alternate connection unit more than one is with timing quilt different from each other Connection.
The equalizer of the 4th mode of the present invention, in the equalizer of the 2nd mode,
Converting unit more than one is set parallel to each other,
Alternate connection unit more than one is connected to each of the converting unit more than one,
In one alternate connection unit above of each for the converting unit being connected to more than one Order is different from each other as defined in described,
The output buffer be connected to the 1st access path, the 2nd access path, the 3rd access path and The phase of the signal of each among 4th access path, converting unit more than one output is anti-phase The more than one access path of relation, exports the difference of the signal of each output of one converting unit above.
The equalizer of the 5th mode of the present invention, in the equalizer of the 2nd mode,
Converting unit more than one is set parallel to each other,
Alternate connection unit more than one is connected to each of the converting unit more than one,
In one alternate connection unit above of each for the converting unit being connected to more than one Order is different from each other as defined in described,
The output buffer be connected to the 1st access path, the 2nd access path, the 3rd access path and The phase of the signal of each among 4th access path, converting unit more than one output is same phase The more than one access path of relation, exports each signal sum exported of the converting unit more than one.
The reception device of the 6th mode of the present invention, has：
Equalizer；
Analog-digital conversion unit, data signal is converted to by the signal exported from the equalizer；And
Digital received processing unit, carries out the reception processing of the data signal, and output receives data,
The equalizer includes：
More than one alternate connection unit, by inputting respectively, generated by converted input signal, every 90 degree of phase is suitable Sequence different the 1st conversion signal, the 2nd conversion signal, the 3rd conversion signal and the 4th conversion signal, have：1st alternate switch, the 2nd It is alternate switch, the 3rd it is alternate switch and the 4th alternate switch, a terminal be connected respectively to the 1st access path, the 2nd access path, 3rd access path and the 4th access path；And capacitive coupling, be connected to the described 1st it is alternate switch, it is described 2nd it is alternate switch, Another terminal of the 3rd alternate switch and the 4th alternate switch；
Control signal generative circuit, by the reference signal of frequency as defined in conversion, phase sequence every 90 degree it is different, control Make the connection of the described 1st alternate switch, the 2nd alternate switch, the 3rd alternate switch and the 4th alternate switch or open Road, generates the control signal of 4 phases, and the control signal of 4 phase is output into the described 1st alternate switch, the described 2nd alternate opened Pass, the 3rd alternate switch and the 4th alternate switch；And
1st output buffer, the 2nd output buffer, the 3rd output buffer and the 4th output buffer, are connected respectively to institute The 1st access path, the 2nd access path, the 3rd access path and the 4th access path are stated, the output of 4 phases is exported Signal,
The 1st alternate switch, the 2nd alternate switch, the 3rd alternate switch and the 4th alternate switch are based on The control signal of 4 phase, in every 1/4 cycle, is connected repeatedly with defined order,
Order is ascending order or descending from N (N is one of integer from 1 to 4) alternate switch as defined in described.
Industrial applicibility
The present invention is useful to the high-frequency signal in radio communication device and base band signal process circuit, for wave filter Processing, equalizer processes or frequency-conversion processing are useful.
Label declaration
10 reception devices
11 antennas
12 low-noise amplifiers
13 reference frequency oscillating units
14th, 100,200,300,400,500,600,700,800,900,1000,1100 equalizer
15 A/D conversion processing units
16 digital received processing units
101st, 201,301,401,501,601,701 IQ frequency mixers
102nd, 202,402,502,602,702,802 alternate connection unit
103rd, 203,303,403,503,603,703,803,903-1,903-2 clock forming circuit
104th, 204,304,404,504,604,704,804 output buffer
302nd, 1022,8022 capacitive coupling device
1001、1101、1011、3011、8011 TA
1012nd, 1021,3012,8012,8021 switch
1002nd, 1013,1102,3013,8013 sampling capacitor

Claims (6)

1. equalizer, including：
More than one alternate connection unit, is inputted the every 90 degree of orders of generated by converted input signal, phase not respectively Same the 1st conversion signal, the 2nd conversion signal, the 3rd conversion signal and the 4th conversion signal, has：It is 1st alternate switch, the 2nd alternate Switch, the 3rd alternate switch and the 4th alternate switch, a terminal are connected respectively to the 1st access path, the 2nd access path, the 3rd company Connect path and the 4th access path；And capacitive coupling, it is connected to the described 1st alternate switch, the 2nd alternate switch, described the Another terminal of 3 alternate switches and the 4th alternate switch；
Control signal generative circuit, by the reference signal of frequency as defined in conversion, every 90 degree different, the control institutes in phase sequence ground Connection or the open circuit of the 1st alternate switch, the 2nd alternate switch, the 3rd alternate switch and the 4th alternate switch are stated, it is raw Into the control signal of 4 phases, the control signal of 4 phase is output to the described 1st alternate switch, the 2nd alternate switch, described 3rd alternate switch and the 4th alternate switch；And
1st output buffer, the 2nd output buffer, the 3rd output buffer and the 4th output buffer, are connected respectively to described 1 access path, the 2nd access path, the 3rd access path and the 4th access path, export the output signal of 4 phases,
The 1st alternate switch, the 2nd alternate switch, the 3rd alternate switch and the 4th alternate switch, based on described The control signal of 4 phases, every 1/4 cycle is connected repeatedly with defined order,
Order as defined in described is ascending order or descending from the alternate switches of N,
Wherein, N is one of integer from 1 to 4.
2. equalizer as claimed in claim 1, in addition to：
More than one converting unit, generation the 1st conversion signal from the input signal, the 2nd conversion signal, 3rd conversion signal and the 4th conversion signal,
Converting unit more than one has：
Voltage-current converter circuit, current signal is converted to by the input signal；
1st sampling switch, the 2nd sampling switch, the 3rd sampling switch and the 4th sampling switch, one end are connected to the voltage x current and turned The outlet side of circuit is changed, the other end is connected respectively to the 1st access path, the 2nd access path, the 3rd link road Footpath and the 4th access path,
1st sampling capacitance, the 2nd sampling capacitance, the 3rd sampling capacitance and the 4th sampling capacitance, one end are connected respectively to the described 1st and connected Path, the 2nd access path, the 3rd access path and the 4th access path are connect, the other end is grounded,
1st sampling switch, the 2nd sampling switch, the 3rd sampling switch and the 4th sampling switch are based on described 4 The control signal of phase, every 1/4 cycle, with the 1st sampling switch, the 2nd sampling switch, the 3rd sampling switch and institute The order for stating the 4th sampling switch is connected repeatedly.
3. equalizer as claimed in claim 1,
Alternate connection unit more than one is connected in parallel to the 1st access path, the 2nd access path, institute The 3rd access path and the 4th access path are stated,
The defined order of each of the alternate connection unit more than one is mutually the same,
Each the 1st alternate switch having of alternate connection unit more than one is connected with timing different from each other Connect.
4. equalizer as claimed in claim 2,
Converting unit more than one is set parallel to each other,
Alternate connection unit more than one is connected to each of the converting unit more than one,
It is described in one alternate connection unit above of each for the converting unit being connected to more than one Defined order is different from each other,
The output buffer is connected to the 1st access path, the 2nd access path, the 3rd access path and described The phase of the signal of each among 4th access path, converting unit more than one output is inverted relationship More than one access path, export the difference of each signal exported of converting unit more than one.
5. equalizer as claimed in claim 2,
Converting unit more than one is set parallel to each other,
Alternate connection unit more than one is connected to each of the converting unit more than one,
It is described in one alternate connection unit above of each for the converting unit being connected to more than one Defined order is different from each other,
The output buffer is connected to the 1st access path, the 2nd access path, the 3rd access path and described The phase of the signal of each among 4th access path, converting unit more than one output is same phase relation More than one access path, export each signal sum exported of the converting unit more than one.
6. reception device, has：
Equalizer；
Analog-digital conversion unit, data signal is converted to by the signal exported from the equalizer；And
Digital received processing unit, carries out the reception processing of the data signal, and output receives data,
The equalizer includes：
More than one alternate connection unit, is inputted the every 90 degree of orders of generated by converted input signal, phase not respectively Same the 1st conversion signal, the 2nd conversion signal, the 3rd conversion signal and the 4th conversion signal, has：It is 1st alternate switch, the 2nd alternate Switch, the 3rd alternate switch and the 4th alternate switch, a terminal are connected respectively to the 1st access path, the 2nd access path, the 3rd company Connect path and the 4th access path；And capacitive coupling, it is connected to the described 1st alternate switch, the 2nd alternate switch, described the Another terminal of 3 alternate switches and the 4th alternate switch；
Control signal generative circuit, by the reference signal of frequency as defined in conversion, every 90 degree different, the control institutes in phase sequence ground Connection or the open circuit of the 1st alternate switch, the 2nd alternate switch, the 3rd alternate switch and the 4th alternate switch are stated, it is raw Into the control signal of 4 phases, the control signal of 4 phase is output to the described 1st alternate switch, the 2nd alternate switch, described 3rd alternate switch and the 4th alternate switch；And
1st output buffer, the 2nd output buffer, the 3rd output buffer and the 4th output buffer, are connected respectively to described 1 access path, the 2nd access path, the 3rd access path and the 4th access path, export the output signal of 4 phases,
The 1st alternate switch, the 2nd alternate switch, the 3rd alternate switch and the 4th alternate switch, based on described The control signal of 4 phases, every 1/4 cycle is connected repeatedly with defined order,
Order as defined in described is ascending order or descending from the alternate switches of N,
Wherein, N is one of integer from 1 to 4.
CN201610892396.4A 2015-12-28 2016-10-13 Equalizer and use its reception device Pending CN107026616A (en)

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Application publication date: 20170808