JP2016184918A - Switch control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a switch control circuit that can implement an operation equivalent to supply of a proper DUTY ratio to even a circuit operating at a high frequency.SOLUTION: A switch control circuit includes a clock generation circuit 120 that generates one or more periodic signals having a predetermined period, a clock adjusting circuit 130 that adjusts a bias voltage for the periodic signal and changes an ON period of the one or more periodic signals to generate one or more control signals, and a switching circuit having one or more switches that are switched to ON when the amplitude of the at least one or more control signals is not less than a threshold value, and switched to OFF when the amplitude of the one or more control signals is less than the threshold value.SELECTED DRAWING: Figure 3

Description

  The present disclosure relates to a switch control circuit that adjusts a control clock with respect to a circuit controlled by turning on / off the switch, a circuit using the switch, and a radio device, for example, frequency conversion or filter processing whose characteristics change according to clock adjustment Related to signal processing.

As a circuit that performs frequency conversion in a wireless device, there is a mixer that includes a switch or the like. It is known that the characteristics of the mixer can be improved by appropriately setting a DUTY ratio (= pulse width Ts / clock period T _CK ) in a local signal that is a signal supplied to the switch.

  A discrete-time analog circuit composed of a switch, a capacitor, and the like is known as a highly variable circuit that is suitable for design in a fine CMOS process. The characteristics of the discrete-time analog circuit are controlled by a clock supplied to the switch.

  In any circuit, it is required to adjust the switch ON / OFF time to a desired value.

  For example, Non-Patent Document 1 describes a mixer configuration using a four-phase clock with a DUTY ratio of 25% as a local signal and a clock generation circuit with a DUTY ratio of 25%.

  FIG. 1A is a diagram showing an overview of a mixer using a clock with a 25% duty ratio disclosed in Non-Patent Document 1, and FIG. 1B generates a clock with a 25% duty ratio disclosed in Non-Patent Document 1. It is a figure which shows the implementation example of the clock generation circuit to perform.

  The clock generation circuit shown in FIG. 1B generates a four-phase DUTY ratio 50% clock that is 90 degrees out of phase from the signal generated by the synthesizer, and two of the generated four-phase DUTY ratio 50% clocks. By taking the AND of the clocks, a clock with a DUTY ratio of 25% is realized.

A. Mirzaei, H. Darabi, JC Leete, X. Chen, K. Juan, and A. Yazdi, “Analysis and optimization of current-driven passive mixers in narrowband direct-conversion receivers,” IEEE J. Solid-State Circuits, vol. 44, no. 10, pp. 2678-2688, Oct. 2009.

  In order for a mixer, a discrete-time analog circuit, etc. to operate at a high frequency, it is necessary to increase the clock frequency of the clock supplied to the circuit.

  However, in the clock generation circuit of Non-Patent Document 1, since the waveform of a signal generated by the synthesizer is lost when the clock frequency is increased, there is a high possibility that the DUTY ratio of the clock will be lower than 25%.

  For example, in the clock generation circuit of FIG. 1B, if two signals input to the AND do not exceed a certain threshold value, the AND output does not occur (that is, the AND result becomes zero). Therefore, the more the waveform of the clock having a DUTY ratio of 50% that is the input signal becomes, the smaller the DUTY ratio of the output signal becomes less than 25%, and in some cases, the output signal does not reach the required voltage value. This causes a situation where the circuit supplied with the clock is difficult to operate at a high frequency.

  A non-limiting embodiment of the present disclosure has been made in view of such a point, and provides a switch control circuit that realizes an operation equivalent to supplying an appropriate DUTY ratio to a circuit that operates at a high frequency. .

  A switch control circuit according to one embodiment of the present disclosure includes a clock generation circuit that generates one or more periodic signals having a predetermined period, an adjustment period of a bias voltage of the periodic signal, and an on period of the one or more periodic signals And the clock adjustment circuit that generates one or more control signals, and the amplitude of the one or more control signals is switched on when the amplitude is greater than or equal to a threshold, and the amplitude of the one or more control signals is less than the threshold And a switching circuit having one or more switches that are switched off.

  These general and specific aspects may be realized by any combination of systems, apparatuses and methods.

  According to the present disclosure, an operation equivalent to supplying an appropriate DUTY ratio to a circuit operating at a high frequency can be realized.

  Further advantages and effects in one aspect of the present disclosure will become apparent from the specification and drawings. Such advantages and / or effects are provided by some embodiments and features described in the description and drawings, respectively, but all need to be provided in order to obtain one or more identical features. There is no.

The figure which shows the outline | summary of the mixer using the clock of 25% of DUTY ratio disclosed by the nonpatent literature 1. The figure which shows the specific implementation example of the clock of 25% of DUTY ratio disclosed by the nonpatent literature 1. The figure which shows the structure of the transmitter which concerns on Embodiment 1 of this indication. The figure which shows the structure of the receiver which concerns on Embodiment 1 of this indication. The figure which shows an example of a structure of the mixer which concerns on Embodiment 1. The figure which shows an example of the clock supplied to a switch The figure which shows an example of the base clock which a clock generation circuit produces | generates FIG. 3 is a diagram illustrating an example of a configuration of a clock adjustment circuit according to the first embodiment. FIG. 3 is a diagram illustrating an example of a configuration of a clock adjustment circuit according to the first embodiment. FIG. 3 is a diagram illustrating an example of a configuration of a clock adjustment circuit according to the first embodiment. The figure which shows the adjustment method of the clock adjustment circuit shown to FIG. 5A The figure which shows the adjustment method of the clock adjustment circuit shown to FIG. 5A The figure which shows the adjustment method of the clock adjustment circuit shown to FIG. 5A The figure which shows the adjustment method of the clock adjustment circuit shown to FIG. 5A The figure which shows the adjustment method of the clock adjustment circuit shown to FIG. 5B The figure which shows the adjustment method of the clock adjustment circuit shown to FIG. 5B The figure which shows an example of a structure of the switch which concerns on Embodiment 1. The figure which shows an example of a structure of the switch which concerns on Embodiment 1. The figure which shows an example of a structure of the switch which concerns on Embodiment 1. The figure which shows an example of a structure of the switch which concerns on Embodiment 1. The figure which shows an example of a structure of a clock generation circuit The figure which shows an example of a structure of a clock generation circuit The figure which shows an example of a structure of a clock generation circuit The figure which shows an example of a structure of a clock generation circuit The figure which shows an example of a structure of a clock generation circuit The figure which shows an example of a structure of the mixer which concerns on Embodiment 1. FIG. 3 is a diagram illustrating an example of a configuration of a clock adjustment circuit according to the first embodiment. FIG. 3 is a diagram illustrating an example of a configuration of a clock adjustment circuit according to the first embodiment. FIG. 3 is a diagram illustrating an example of a configuration of a clock adjustment circuit according to the first embodiment. The figure which shows an example of another structure of a clock generation circuit The figure which shows an example of another structure of a clock adjustment circuit Diagram showing basic single-balanced mixer configuration The figure which shows the structure of the single balance type mixer which implement | achieves the operation | movement similar to the mixer of FIG. 13A with a 1/2 clock frequency. The figure which shows the structure of the single balance type mixer which implement | achieves the operation | movement similar to the mixer of FIG. 13A with the clock frequency of 1 / M. The figure which shows an example of the clock which operates the mixer shown to FIG. 13A The figure which shows an example of the clock which operates the mixer shown to FIG. 13B The figure which shows an example of the clock which operates the mixer shown to FIG. 13C Conceptual diagram of a periodic time-varying continuous-time system Conceptual diagram of a periodic time-varying continuous-time system Conceptual diagram of a periodic time-varying continuous-time system The figure which shows an example of the principal part structure of the discrete time analog circuit which concerns on Embodiment 3. FIG. 5 is a diagram illustrating an example of a configuration of a charge inverting circuit according to a third embodiment. The figure which shows an example of the internal structure of the electric charge inversion circuit which concerns on Embodiment 3. FIG. 5 is a diagram illustrating an example of a configuration of a charge inverting circuit according to a third embodiment. The figure which shows an example of the internal structure of the electric charge inversion circuit which concerns on Embodiment 3. The figure which shows the outline of operation | movement in the discrete time analog circuit 600. The figure which shows the outline of operation | movement in the discrete time analog circuit 600. The figure which shows the outline of operation | movement in the discrete time analog circuit 600. The figure which shows the outline of operation | movement in the discrete time analog circuit 600. The figure which shows the result of the circuit simulation of the low pass characteristic of the discrete time analog circuit FIG. 5 is a diagram illustrating an example of a configuration of a charge inverting circuit according to a third embodiment. The figure which shows an example of the internal structure of the electric charge inversion circuit which concerns on Embodiment 3. FIG. 10 is a diagram illustrating another example of the configuration of the charge inverting circuit according to the third embodiment. The figure which shows another example of the internal structure of the electric charge inversion circuit which concerns on Embodiment 3. FIG. The figure which shows an example of the clock which operates the electric charge inversion circuit shown to FIG. 21B FIG. 5 is a diagram illustrating an example of a configuration of a discrete-time analog circuit according to a third embodiment. FIG. 5 is a diagram illustrating an example of a configuration of a charge inverting circuit according to a third embodiment. The figure which shows an example of the internal structure of the electric charge inversion circuit which concerns on Embodiment 3. FIG. 5 is a diagram illustrating an example of a configuration of a charge retention connection circuit according to a third embodiment. The figure which shows an example of the internal structure of the electric charge retention connection circuit which concerns on Embodiment 3. Timing chart of ideal clock for charge inverting circuit shown in FIG. 23B Timing chart of ideal clock for charge holding connection circuit shown in FIG. 23D FIG. 5 is a diagram illustrating an example of a configuration of a charge inverting circuit according to a third embodiment. The figure which shows an example of the internal structure of the electric charge inversion circuit which concerns on Embodiment 3. FIG. 5 is a diagram illustrating an example of a configuration of a charge retention connection circuit according to a third embodiment. The figure which shows an example of the internal structure of the electric charge retention connection circuit which concerns on Embodiment 3. The figure which shows an example of a structure of a multistage discrete time analog circuit The figure which shows an example of an internal structure of a multistage discrete time analog circuit Block diagram showing a configuration of a receiving apparatus according to Embodiment 4 The figure which shows an example of a structure of the discrete time analog circuit which concerns on Embodiment 4. The figure which shows an example of a structure of PSCF which concerns on Embodiment 4. Timing chart of ideal clock for discrete time analog circuit shown in FIG. 28A The figure which shows an example of a structure of the discrete time analog circuit which concerns on Embodiment 4. Timing chart of ideal clock for discrete time analog circuit shown in FIG. 29A The figure which shows the structure of the mixer with a characteristic control function which concerns on Embodiment 5, or a discrete time analog circuit The figure which shows the structure of the mixer with a characteristic control function which has the clock adjustment circuit of the structure shown to FIG. 5B, or a discrete time analog circuit The figure which shows an example of the control flow of the structure shown to FIG. 30B. The figure which shows the example in which the characteristic monitor circuit which concerns on Embodiment 5 monitors the output of a transmission / reception apparatus The figure which shows an example of the adjustment circuit which adjusts the voltage value of a bias The figure which shows an example of the adjustment circuit which adjusts the voltage value of a bias FIG. 10 is a diagram illustrating an example of a configuration of a clock generation circuit according to a sixth embodiment. The figure which shows operation | movement of the clock generation circuit which concerns on Embodiment 6. The figure which shows operation | movement of the clock generation circuit which concerns on Embodiment 6. The figure which shows operation | movement of the clock generation circuit which concerns on Embodiment 6. The figure which shows operation | movement of the clock generation circuit which concerns on Embodiment 6. Diagram showing an example of the configuration of a variable capacitor The figure which shows an example of a structure of a variable resistance The figure which shows an example of a structure of an inverter circuit

  Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. Each embodiment described below is an example, and the present disclosure is not limited by these embodiments.

(Embodiment 1)
[Configuration of transmitter and receiver]
2A is a diagram illustrating a configuration of the transmission device 10 according to Embodiment 1 of the present disclosure, and FIG. 2B is a diagram illustrating a configuration of the reception device 20 according to Embodiment 1 of the present disclosure.

  2A includes a digital transmission processing unit 11, a D / A (Digital to Analog) conversion processing unit 12, a reference frequency oscillation unit 13, a LO (Local Oscillator) frequency oscillation unit 14, an analog base A band circuit 15, a transmission mixer 16, a power amplifier (PA) 17, and an antenna 18 are included.

  The digital transmission processing unit 11 performs predetermined digital transmission processing including, for example, encoding processing and modulation processing on the transmission data, generates a baseband digital transmission signal, and outputs the baseband digital transmission signal to the D / A conversion processing unit 12.

  The D / A conversion processing unit 12 converts the baseband digital transmission signal into a baseband analog transmission signal and outputs it to the analog baseband circuit 15. The baseband analog transmission signal converted by the D / A conversion processing unit 12 includes an unnecessary signal (for example, a harmonic).

The reference frequency oscillating unit 13 generates a reference frequency signal f _{REF_LO1} used for generating the local oscillation signal f _LO1 and outputs the reference frequency signal f _{REF_LO1} to the LO frequency oscillating unit 14.

The LO frequency oscillating unit 14 generates a local oscillation signal f _LO1 based on the reference frequency signal f _{REF_LO1} and outputs the local oscillation signal f _LO1 to the transmission mixer 16.

  The analog baseband circuit 15 performs gain adjustment and filtering on the baseband analog transmission signal to remove unnecessary signals (for example, harmonic components). The analog baseband circuit 15 outputs the filtered baseband analog transmission signal to the transmission mixer 16.

The analog baseband circuit 15 can also be configured by a discrete time circuit. In this case, the reference frequency oscillating unit 13 generates a reference frequency signal f _REF1 used for discrete time analog signal processing and outputs the reference frequency signal f _REF1 to the analog baseband circuit 15 configured by a discrete time analog circuit. The frequency of the reference frequency signal f _REF1 to the discrete time analog circuit and the reference frequency signal f _{REF_LO1} to the LO frequency oscillating unit 14 may be the same frequency or different frequencies.

  The configuration and operation of the analog baseband circuit 15 when the analog baseband circuit 15 is configured by a discrete time analog circuit will be described later.

The transmission mixer 16 up-converts the filtered baseband analog transmission signal to an RF (radio frequency) frequency based on the local oscillation signal f _LO1 and power-converts the analog transmission signal up-converted to the RF frequency. 17 to output.

  The power amplifier 17 amplifies the power of the analog transmission signal up-converted to the RF frequency and outputs it to the antenna 18.

  The antenna 18 radiates an analog transmission signal after power amplification.

  2B includes an antenna 21, a low noise amplifier (LNA) 22, a reference frequency oscillating unit 23, an LO frequency oscillating unit 24, a receiving mixer (Mixer) 25, an analog base, and the like. A band circuit 26, an A / D (Analog to Digital) conversion processing unit 27, and a digital reception processing unit 28 are included.

  The antenna 21 receives an analog received signal of RF frequency from a transmitting station (not shown) and outputs it to the low noise amplifier 22.

  The low noise amplifier 22 amplifies the received analog reception signal having an RF frequency and outputs the amplified signal to the reception mixer 25.

The reference frequency oscillating unit 23 outputs the reference frequency signal f _{REF_LO2} to the LO frequency oscillating unit 24.

The LO frequency oscillation unit 24 generates a local oscillation signal f _LO2 based on the reference frequency signal f _{REF_LO2} and outputs the local oscillation signal f _LO2 to the reception mixer 25.

Based on the local oscillation signal f _LO2 , the reception mixer 25 frequency-converts the RF frequency analog reception signal into a baseband analog reception signal and outputs the baseband analog reception signal to the analog baseband circuit 26.

  The analog baseband circuit 26 performs filtering on the baseband analog received signal. The analog baseband circuit 26 outputs the filtered baseband analog reception signal to the A / D conversion processing unit 27.

The analog baseband circuit 26 can also be composed of a discrete time circuit. In that case, the reference frequency oscillating unit 23 generates a reference frequency signal f _REF2 used for discrete-time analog signal processing, and outputs the reference frequency signal f _REF2 to an analog baseband circuit 26 configured by a discrete-time analog circuit. The frequency of the reference frequency signal f _REF2 to the discrete time analog circuit and the reference frequency signal f _{REF_LO2} to the LO frequency oscillating unit 24 may be the same frequency or different frequencies.

  The configuration and operation of the analog baseband circuit 26 when the analog baseband circuit 26 is configured by a discrete time analog circuit will be described later.

  The A / D conversion processing unit 27 converts the filtered baseband analog reception signal into a baseband digital reception signal and outputs the baseband digital reception signal to the digital reception processing unit 28.

  The digital reception processing unit 28 performs predetermined digital reception processing including, for example, demodulation processing and decoding processing on the baseband digital signal, and generates reception data.

  Note that the transmitting apparatus 10 shown in FIG. 2A and the receiving apparatus 20 shown in FIG. 2B have been described as configurations of direct conversion. The transmission apparatus 10 or the reception apparatus 20 according to the present embodiment may be a system that adds one or more mixers and uses an intermediate frequency (IF).

Further, the reference frequency signals f _{REF1 and} f _REF2 may share one signal, and the reference oscillation frequency oscillating units 13 and 23 or the LO frequency oscillating units 14 and 24 include the transmitting device 10 and the receiving device 20. May be shared. Note that the structure of this embodiment can be the same as that of the other embodiments.

[Composition of mixer]
Next, the configuration of the transmission mixer 16 and the reception mixer 25 according to the present embodiment will be described.

  FIG. 3 is a diagram illustrating an example of the configuration of the mixer 100 according to the present embodiment. The mixer 100 illustrated in FIG. 3 corresponds to the transmission mixer 16 included in the transmission device 10 illustrated in FIG. 2A and the reception mixer 25 included in the reception device 20 illustrated in FIG. 2B.

  The mixer 100 includes four switches 110-1 to 110-4, a clock generation circuit 120, and a clock adjustment circuit 130, and is a switching circuit that outputs a four-phase signal with respect to a signal input from a terminal IN.

  The switches 110-1 to 110-4 are controlled to be turned on / off by the clocks S1 to S4 from the clock adjustment circuit 130. Specifically, the switches 110-1 to 110-4 are turned on at times when the amplitudes of the clocks S1 to S4 are equal to or greater than the threshold value, and are turned off at other intervals. That is, by adjusting the DUTY ratio, amplitude, and phase of the clocks S1 to S4, the time for which the switches 110-1 to 110-4 are equal to or greater than the threshold can be controlled.

  The threshold values in the switches 110-1 to 110-4 may be different from each other or the same.

  Here, the switches 110-1 to 110-4 are shown as having a configuration using NMOS switches, but other configurations such as a PMOS switch and a complementary switch using NMOS and PMOS may be used.

The clock generation circuit 120 generates base clocks B1 to B4 from the local oscillation signal (f _LO1 or f _LO2 ) output from the LO frequency oscillation unit (see FIG. 2A and FIG. 2B), and outputs it to the clock adjustment circuit 130. The clock generated by the clock generation circuit 120 will be described later.

The clock generation circuit 120 may generate the base clocks B1 to B4 from the reference signal (f _REF1 or f _REF2 or f _{REF_LO1} or f _{REF_LO2} ) from the reference frequency oscillating unit (see FIGS. 2A and 2B).

  The clock adjustment circuit 130 adjusts the DUTY ratio, phase, and amplitude of the base clocks B1 to B4, and supplies the adjusted clocks to the switches 110-1 to 110-4 as clocks S1 to S4.

Here, the clocks S1 to S4 supplied to the switches 110-1 to 110-4 will be described. FIG. 4A is a diagram illustrating an example of clocks S1 to S4 supplied to the switches 110-1 to 110-4. The clocks S1 to S4 in FIG. 4A are four-phase rectangular signals whose phases are shifted by 90 degrees, and the high time is the pulse width Ts and the clock cycle is _TCK . The DUTY ratio 25% of the clocks S1 to S4 is a desired DUTY ratio in the switches 110-1 to 110-4.

  As shown in FIG. 4A, if the rising edge of the clocks S1 to S4 from low to high and the falling edge from high to low are steep, the switches 110-1 to 110-4 are in the interval of the pulse width Ts. Switch on.

However, when the clock frequency (= 1 / T _CK ) is increased to operate the mixer 100 shown in FIG. 3 at a high frequency, the waveform of the clock generated by the clock generation circuit 120 is distorted.

For example, when rectangular signals such as the clocks S1 to S4 in FIG. 4A are rounded, the rise from low to high and the fall from high to low become smooth, and the switches 110-1 to 110-4 are turned on. switching the times (hereinafter, described as the on-time _{T oN),} the different pulse width Ts. That, DUTY ratio of the clock and _{(= Ts / T CK),} DUTY ratio in the switch (= the period _{T CK} of switch on-time _{T ON} / clock) is different.

The clock adjustment circuit 130 according to the present embodiment adjusts the DUTY ratio, amplitude, and phase of the clock even when the waveform of the clock generated by the clock generation circuit 120 is distorted, so that the DUTY ratio (= (T _ON / T _CK ) is controlled to a desired DUTY ratio.

In addition, the clock adjustment circuit 130 according to the present embodiment adjusts the DUTY ratio, amplitude, and phase of the clock to adjust the DUTY ratio (=) in the switch even when the clock generated by the clock generation circuit 120 is a rectangular signal. (T _ON / T _CK ) is controlled to a desired DUTY ratio.

  FIG. 4B is a diagram illustrating an example of the base clocks B1 to B4 generated by the clock generation circuit 120. The base clocks B1 to B4 in FIG. 4B are four-phase sine wave signals whose phases are shifted by 90 degrees. The base clocks B1 to B4 are not limited to sine wave signals.

The clock adjustment circuit 130 adjusts the DUTY ratio, amplitude, and phase of the base clocks B1 to B4 in FIG. 4B and switches the clocks corresponding to the ideal clocks indicated by the clocks S1 to S4 in FIG. 4A to the switches 110-1 to 110-4. The DUTY ratio in the switches 110-1 to 110-4 is controlled to a desired DUTY ratio. Note that the ideal clock indicates a rectangular signal having the same DUTY ratio (Ts // T _CK ) as the DUTY ratio (= T _ON / T _CK ) in the switch of the clock supplied from the clock adjustment circuit 130. That is, the switches 110-1 to 110-4 using the clock supplied from the clock adjustment circuit 130 perform the same operations as the switches 110-1 to 110-4 using the ideal clock.

[Configuration of clock adjustment circuit]
Specifically, the configuration of the clock adjustment circuit 130 will be described. 5A to 5C are diagrams showing an example of the configuration of the clock adjustment circuit 130 according to the present embodiment. 5A to 5C show the configuration of the clock adjustment circuit 130 for one-phase signals. In the case of the clock adjustment circuit 130 for the four-phase signal, the same configuration has four systems, and the N-phase signal has the same configuration N systems. Hereinafter, the clock adjustment circuit 130 in FIGS. 5A to 5C will be described as a configuration connected to the switch 110-1.

  The clock adjustment circuit 130 in FIG. 5A includes a buffer 131, a capacitor 132, and a resistor 133, adjusts the amplitude and bias of the base clock B1 input from the terminal IN, and outputs the clock S1 to the terminal OUT.

  The buffer 131 amplifies or raises the input base clock B1 into a rectangle. Note that the buffer 131 may be replaced with an amplifier.

  The capacitor 132 cuts the DC component of the base clock B1 that is amplified or rectangular. The resistor 133 adjusts the bias of the base clock output from the capacitor 132 when the voltage V1 is applied from one terminal. The clock adjustment circuit 130 illustrated in FIG. 5A supplies the base clock B1 whose bias has been adjusted to the switch 110-1 as the clock S1.

As described above, since the switch 110-1 is turned on when the amplitude of the clock S1 is equal to or greater than the threshold, the switch 110-1 is turned on by adjusting the amplitude of the base clock, specifically, the DC component. _TON can be controlled.

An adjustment method of the clock adjustment circuit 130 illustrated in FIG. 5A will be described. 6A to 6D are diagrams illustrating an adjustment method of the clock adjustment circuit 130 illustrated in FIG. 5A. 6A to 6D, T _SIN indicates the period of a sine wave signal that is a base clock.

FIG. 6A shows a clock S1 in which a bias _VA is added to a base clock B1 as a bias condition A. FIG. 6B shows a clock S1 in which a bias V _B is added to the base clock B1 as the bias condition B. 6A and 6B, Vth is a threshold value of the switch 110-1. The switch 110-1 is turned on when the amplitude of the clock S1 becomes Vth or more. As shown in FIG. 6A and FIG. 6B, by adjusting the bias condition, the time that is equal to or higher than the threshold value Vth of the switch 110-1, that is, the ON time is changed.

In Figure 6A, the base clock B1, by biasing _{V A} is applied, the on-time _{T ON} of the switch 110-1, the _{T A.} In other words, the clock S1 is made to the rectangular signal equivalent to the on-time, as shown in FIG. 6C becomes T _A. At this time, the DUTY ratio in the switch 110-1 is T _A / T _SIN .

Further, in FIG. 6B, the base clock B1, by biasing _{V B} is applied, the on-time _{T ON} of switch 110-1, the _{T B.} In other words, the clock S1 is made to the rectangular signal equivalent to the on-time, as shown in FIG. 6D becomes T _B. At this time, the DUTY ratio in the switch 110-1 is T _B / T _SIN .

That is, the clock generation circuit 130 shown in FIG. 5A adjusts the bias with respect to the base clock, thereby making an arbitrary DUTY ratio (T _ON / T _SIN ) with respect to the base clock of the sine wave signal having the period T _SIN. Can be controlled. The configuration of FIG. 5A is effective when it is desired to control the circuit with a high-frequency clock.

  Next, the clock generation circuit 130 in FIG. 5B will be described. In FIG. 5B, the same reference numerals as those in FIG. 5A are given to components common to FIG. 5A, and the description thereof is omitted. The configuration in FIG. 5B has a variable capacitor 134 in addition to the configuration in FIG. 5A.

  The variable capacitor 134 has a variable capacitance value C1, and smoothes the waveform of the base clock B1. The degree of waveform rounding is controlled by adjusting the capacitance value C1. Note that the capacitance value of the variable capacitor 134 may be fixed.

  Here, an adjustment method of the clock adjustment circuit 130 illustrated in FIG. 5B will be described. 7A and 7B are diagrams illustrating an adjustment method of the clock adjustment circuit 130 illustrated in FIG. 5B.

  7A and 7B, when a rectangular signal is input to the clock adjustment circuit 130 as the base clock B1, the capacitance value C1 of the variable capacitor 134 is adjusted to 0 [fF], 100 [fF], and 200 [fF]. An example is shown. The arrows of the bias conditions C and D indicate a case where the bias is adjusted with respect to the base clock B1 so that the line pointed to becomes the threshold value of the switch 110-1.

  As shown in FIG. 7A, the waveform of the base clock B1 can be smoothed by adjusting the capacitance value C1 of the variable capacitor 134. By adjusting the waveform of the base clock B1 and adjusting the bias condition, the clock adjustment circuit 130 can control the DUTY ratio in the switch 110-1 to a desired DUTY ratio.

  For example, when the capacitance value C1 is adjusted to 200 [fF] and the bias is adjusted to the bias condition C, the ON interval in the switch 110-1 is TC. When the capacitance value C1 is adjusted to 200 [fF] and the bias is adjusted to the bias condition D, the ON interval in the switch 110-1 is TD. That is, by controlling the capacitance and the bias, it is possible to control the section in which the switch is turned on and adjust the DUTY ratio in which the switch 110 is turned on to a desired DUTY ratio.

  Also, as shown in FIG. 7B, depending on the combination of capacitance and bias, adjustment of the DUTY ratio can be omitted and used for phase control. It is also possible to adjust both the DUTY ratio and the phase.

For example, by adjusting the capacitance value C1 to 100 [fF], adjusted for bias to bias condition C, ON zone in the switch 110-1, the _{T C.} Further, by adjusting the capacitance value C1 to 200 [fF], adjusted for bias to the bias condition D, on the section of the switch 110-1, the _{T D.}

Here, on the interval T _C and on interval T _D is a length of substantially the same timing as the on, the timing of the off different. That is, the clock adjustment circuit 130 illustrated in FIG. 5B can adjust the phase by adjusting the capacitance value C1 of the variable capacitor 134 and adjusting the bias condition.
That is, the DUTY ratio and the phase can be adjusted by adjusting the capacitance and the bias condition.

  7A and 7B, the base clock B1 is described as a rectangular signal. However, the clock adjustment circuit 130 illustrated in FIG. 5B is not limited to the rectangular signal, and the DUTY ratio and the arbitrary base clock B1 are not limited. The phase can be adjusted.

  Next, the clock generation circuit 130 in FIG. 5C will be described. In FIG. 5C, the same components as those in FIG. 5B are denoted by the same reference numerals as those in FIG. 5B, and the description thereof is omitted. The configuration of FIG. 5C is different from the configuration of FIG. 5B in the configuration of the switch 110-1.

  The switch 110-1 in FIG. 5C is configured to perform bias adjustment on the switch side. When the switch 110-1 is a MOS switch, the DUTY ratio can be adjusted by adjusting the bias of the switch 110-1. For example, the on-time of the switch 110-1 can be adjusted by adjusting the bias of at least one or both of the drain and source of the switch 110-1 and the bias of the gate. It is also possible to change the on-time by changing the potential of the back gate of the switch 110-1 and changing the threshold value Vth of the switch.

[Switch configuration]
Here, a configuration of a switch for performing bias adjustment will be described. 8A to 8D are diagrams illustrating an example of the configuration of the switch 110 according to the present embodiment.

8A to 8C, capacitors 132-1 to 132-3 are provided at the source, the gate, and the drain, respectively, and remove the DC component of the signal that passes therethrough. The resistor 133-1 has its gate bias adjusted by applying the voltage V ₁ from one terminal. The resistor 133-2 has its drain bias adjusted by applying the voltage V ₂ from one terminal. Resistor 133-3, by the voltage V ₃ from one terminal is applied, the source bias is adjusted. Resistor 133-4, by which the voltage V ₃ is applied from one terminal, the bias of the back gate is adjusted.

  As shown in FIGS. 8A to 8D, the on-time of the switch 110 can be adjusted by adjusting any one of the gate, drain, source, and back gate of the switch 110. The drain and source biases may be applied to one side as shown in FIGS. 8A and 8B, or may be applied to both sides as shown in FIG. 8C. When a bias is applied to both sides of the drain and source, a current may be passed through the switch with a difference between the bias values. The threshold value Vth of the switch may be controlled by applying a potential to the back gate as shown in FIG. 8D.

[Configuration of clock generation circuit]
Here, the configuration of the clock generation circuit 120 that generates a four-phase sine wave signal from one sine wave signal will be described. 9A to 9E are diagrams illustrating an example of the configuration of the clock generation circuit.

  FIG. 9A shows a configuration using a shift register with D-type flip-flop circuits 121-1 to 121-4. In the configuration of FIG. 9A, four-phase signals having different phases are output to the output terminals Q0 to Q3.

  FIG. 9B shows a configuration using resistors 122-1 and 122-2 and capacitors 123-1 and 123-2. By appropriately setting the values of the resistors 122-1 and 122-2 and the capacitors 123-1 and 123-2, a signal having a phase shift with respect to the target frequency can be generated. For example, the signals output from the output terminals OUT1 and OUT2 with respect to the signal input from the terminal IN are generated as signals having a phase difference of 90 degrees. By dividing the signals output from the output terminals OUT1 and OUT2 into signals having a phase difference of 180 degrees using a balun (not shown), four-phase signals having a phase difference of 90 degrees can be generated. In addition, a four-phase signal having a phase difference of 90 degrees can be generated using a combination of RC circuits. For example, as shown in FIG. 9E, a four-phase signal having a phase difference of 90 degrees can be generated from a single input signal by a combination of RC circuits.

  FIG. 9C shows a configuration of a phase shifter that generates a signal having an arbitrary phase. The configuration illustrated in FIG. 9C includes a 90-degree phase difference signal generation circuit 124, variable gain amplifiers 125-1 and 125-2, and a synthesis circuit 126. The 90-degree phase difference signal generation circuit 124 generates two signals having a 90-degree phase difference from the input signal. The variable gain amplifiers 125-1 and 125-2 adjust the amplitudes of the signals output from the 90-degree phase difference signal generation circuit 124 to appropriate values. Finally, the synthesis circuit 126 can generate a signal having an arbitrary phase by synthesizing these signals.

  FIG. 9D shows a configuration using CMOS inverters 127-1 to 127-12. Six CMOS inverters 127-1 to 127-6, four CMOS inverters 127-7 to 127-10, and two CMOS inverters 127-11 to 127-12 are connected to the input / output systems 120A, 120B, and 120C, respectively. Has been. The number of CMOS inverters connected to each input / output system is not limited to this. The CMOS inverters 127-1 to 127-12 give a delay to the passed signal. For this reason, the input / output systems 120A to 120C can generate different output signals of four phases by giving different delay amounts to the input signals by changing the number of connected CMOS process inverters.

[Another mix of mixer]
In FIG. 3, the mixer 100 has been described as a single balance mixer. In the present embodiment, a clock generation circuit and a clock adjustment circuit may be used for the configuration of the double balance mixer.

  FIG. 10 is a diagram illustrating an example of the configuration of the mixer 200 according to the present embodiment. The mixer 200 in FIG. 10 includes a voltage / current conversion circuit (TA) 210, switches 220-1 to 220-8, a clock generation circuit 230, and a clock adjustment circuit 240. The mixer 200 has a double-balance mixer configuration, and outputs a four-phase signal with respect to a positive phase signal and a negative phase signal input from the terminals IN_P and IN_N.

  The TA 210 amplifies an input signal. The TA 210 may be an amplifier or a buffer.

  The switches 220-1 to 220-8 are the same as the switches 110-1 to 110-4 shown in FIG. 3, and are controlled by the clocks S1 to S4 from the clock adjustment circuit 230.

The clock generation circuit 230 is the same as the clock generation circuit 120 shown in FIG. 3, and the base clock B1 is generated from the local oscillation signal (f _LO1 or f _LO2 ) output from the LO frequency oscillation unit (see FIGS. 2A and 2B). ˜B4 are generated and output to the clock adjustment circuit 240.

  The clock adjustment circuit 240 is the same as the clock adjustment circuit 130 shown in FIG. 3, adjusts the DUTY ratio, phase, and amplitude of the base clocks B1 to B4, and uses the adjusted clocks as clocks S1 to S4 as switches 220-1 to 220-1. 220-8.

[Configuration of clock adjustment circuit for adjusting the 4-phase clock]
Here, the configuration of the clock adjustment circuit 240 that adjusts the four-phase clock will be described. 11A to 11C are diagrams showing an example of the configuration of the clock adjustment circuit 240 according to the present embodiment.

  FIG. 11A is a configuration for adjusting the DUTY ratio of each of the clocks S1 to S4. The configuration of FIG. 11A includes four systems that output four-phase clocks S1 to S4 to four-phase base clocks B1 to B4, respectively, and include amplifiers 241-1 to 241-4 and capacitors 242-1 to 242. 4, resistors 243-1 to 243-4 and variable capacitors 244-1 to 244-4. Voltages V1 to V4 are applied to the resistors 243-1 to 243-4 of the four systems.

  In the configuration of FIG. 11A, different biases are adjusted by different voltages V1 to V4 for the base clocks B1 to B4 respectively input to the respective systems, and the capacitance values are adjusted by the variable capacitors 244-1 to 244-4. By doing so, each DUTY ratio can be adjusted. Even when the base clocks B1 to B4 have different DUTY ratios due to the influence of the circuit wiring layout or the like, different bias and capacitance values can be adjusted in each system, so that the clocks S1 to S1 output from each system can be adjusted. S4 can be equivalent to an ideal clock.

  As shown in FIG. 7B, the phase of the four-phase signal can be adjusted with the configuration of FIG. 11A.

  FIG. 11B is a configuration for adjusting the phases of the clocks S1 to S4. In FIG. 11B, the same components as those in FIG. 11A are denoted by the same reference numerals as those in FIG. 11A, and the description thereof is omitted. The configuration in FIG. 11B includes amplifiers 246-1 to 246-4 and capacitors 245-1 to 245-4 in addition to the configuration in FIG. 11A. The voltage V1 is applied to each of the four systems of resistors 243-1 to 243-4.

  In the configuration of FIG. 11B, the variable capacitors 244-1 to 244-4 change the way signals are signaled in each system. Then, each of the amplifiers 246-1 to 246-4 restarts signals having different rounding methods. With this configuration, the rising timing of the signal can be changed in each system, so that the rising timing can be adjusted, that is, the phase can be adjusted. The signals output from the amplifiers 246-1 to 246-4 are adjusted by the capacities 245-1 to 245-4 and the bias of each system so that the DUTY ratio in the switch becomes a desired DUTY ratio.

  FIG. 11C is a configuration for adjusting the phase and the DUTY ratio of each of the clocks S1 to S4. Note that in FIG. 11C, components that are the same as in FIG. 11B are assigned the same reference numerals as in FIG. 11B, and descriptions thereof are omitted. The configuration of FIG. 11C has a configuration in which the capacitors 245-1 to 245-4 in the configuration of FIG. 11B are replaced with variable capacitors 247-1 to 247-4. Voltages V1 to V4 are applied to the resistors 243-1 to 243-4 of the four systems.

  In the configuration of FIG. 11C, similarly to FIG. 11B, the phase of the signal is adjusted by the variable capacitors 244-1 to 244-4 and the amplifiers 246-1 to 246-4 while changing the signal rising timing in each system. Further, as in FIG. 11A, the respective DUTY ratios can be adjusted by adjusting different biases by different voltages V1 to V4 and adjusting capacitance values by the variable capacitors 247-1 to 247-4.

  Note that the adjustment of the four-phase clock can be performed using another configuration. FIG. 12A is a diagram illustrating an example of another configuration of the clock generation circuit. FIG. 12B is a diagram illustrating an example of another configuration of the clock adjustment circuit.

  Note that the clock adjustment circuit shown in FIG. 12B may be added to the clock generation circuit shown in FIG. 12A and the 4-phase signal AND circuit shown in FIG. 1B as the clock adjustment circuit.

  Bias by inserting the clock adjustment circuit shown in FIG. 12B at insertion point A and insertion point A ′ (or insertion point B, insertion point B ′, insertion point C, and insertion point C ′) of the clock generation answer shown in FIG. And the frequency at which the AND operation can be performed can be increased. By inserting the clock adjustment circuit shown in FIG. 12B at the insertion point D or the insertion point E, the frequency of the inverter operation can be increased.

  Further, the on-time of the switch can be adjusted by inserting the clock adjusting circuit shown in FIG. 12B at the insertion point F connected to the switch. Note that the clock adjustment circuit of FIG. 12B inserted into the clock generation circuit of FIG. 12A may be inserted at any position, or a plurality of clock adjustment circuits may be inserted. 12A has six inverters (or buffers), but is not limited thereto.

(Embodiment 2)
In the first embodiment, the clock adjustment circuit that adjusts the bias, phase, and DUTY ratio of the base clock generated by the clock generation circuit has been described. In this embodiment, a structure of a mixer that uses the clock adjustment circuit described in Embodiment 1 and operates with a low-frequency clock will be described with reference to FIGS. 13A to 13C and FIGS. 14A to 14C.

  FIG. 13A is a diagram showing a configuration of a basic single balance type mixer 300. The mixer 300 includes switches 310-1 and 310-2, a clock generation circuit 320, and a clock adjustment circuit 330. In response to a signal input from a terminal IN, the mixer 300 outputs a signal having a positive phase and a reverse phase from the terminals OUT_P and OUT_N, respectively. Output.

  The switches 310-1 and 310-2 are controlled to be turned on / off by the clocks SP and SN from the clock adjustment circuit 330. 14A is a diagram illustrating an example of a clock for operating the mixer 300 illustrated in FIG. 13A. The clocks SP and SN shown in FIG. 14A are equivalent clocks in the switches 310-1 and 310-2, and the switches 310-1 and 310-2 are turned on at high times of the clocks SP and SN, respectively. Switch off at low time.

  FIG. 13B is a diagram illustrating a configuration of a single-balanced mixer 400 that realizes the same operation as the mixer 300 of FIG. 13A at a clock frequency of ½. The mixer 400 includes switches 410-1 to 410-4, a clock generation circuit 420, and a clock adjustment circuit 430. In response to a signal input from the terminal IN, the mixer 400 outputs signals of the positive and negative phases from the terminals OUT_P and OUT_N, respectively. Output.

  The switches 410-1 to 410-4 are controlled to be turned on / off by clocks S1 to S4 from the clock adjustment circuit 430. FIG. 14B is a diagram illustrating an example of a clock for operating the mixer 400 illustrated in FIG. 13B. The clocks S1 to S4 shown in FIG. 14B are equivalent clocks in the switches 410-1 to 410-4, and the switches 410-1 to 410-4 are switched on at the high time of the clocks S1 to S4, respectively. Switch off at low time.

The mixer 300 and the mixer 400 perform the same operation by making the on-time of the clock for operating the mixer 300 shown in FIG. 14A and the clock for operating the mixer 400 shown in FIG. 14B, that is, the pulse width Ts the same. In that case, the period _{T ck} of the clock in Fig. 14B, 2 times the period _{T ck} of the clock in FIG. 14A, that is, the clock frequency is 1/2.

  FIG. 13C is a diagram illustrating a configuration of a single balance type mixer 500 that realizes the same operation as the mixer 300 of FIG. 13A at a clock frequency of 1 / M. The mixer 500 includes switches 510-1 to 510-2 M, a clock generation circuit 520, and a clock adjustment circuit 530, and outputs signals of a normal phase and a reverse phase from the terminals OUT_P and OUT_N, respectively, with respect to a signal input from the terminal IN. Output.

  The switches 510-1 to 510-2M are controlled to be turned on / off by clocks S1 to S (2M) from the clock adjustment circuit 430. FIG. 14C is a diagram illustrating an example of a clock for operating the mixer 500 illustrated in FIG. 13C. Clocks S1 to S (2M) shown in FIG. 14C are equivalent clocks in the switches 510-1 to 510-2M, and the switches 510-1 to 510-2M are high-level clocks S1 to S (2M), respectively. It switches on at time and switches off at low time.

The mixer 300 and the mixer 500 perform the same operation by making the on-time of the clock for operating the mixer 300 shown in FIG. 14A and the clock for operating the mixer 500 shown in FIG. 14C, that is, the pulse width Ts the same. In that case, the period _{T ck} of the clock in FIG. 14C, M times the period _{T ck} of the clock in FIG. 14A, that is, the clock frequency is 1 / M.

  Further, as shown in FIGS. 14A to 14C, the clocks have different DUTY ratios and phases. The clock generation circuits 320 to 520 and the clock adjustment circuits 330 to 530 illustrated in FIGS. 13A to 13C adjust the DUTY ratio and the phase of each clock by adopting the same configuration as that described in the first embodiment.

  The adjustment of the DUTY ratio and the phase uses the configuration of the clock adjustment circuit described in FIGS. 5A to 5C and FIGS. 11A to 11C. The phase adjustment uses the configuration of the clock generation circuit described with reference to FIGS. 9A, 9B, and 9D. Note that the adjustment of the DUTY ratio may use the configuration of the switch described with reference to FIGS. 8A to 8D.

  According to the present embodiment described above, an operation similar to the operation of the mixer with the high frequency clock can be realized with the low frequency clock. In that case, the supplied clock is realized by the clock generation circuit and the clock adjustment circuit adjusting the DUTY ratio and phase.

(Embodiment 3)
In this embodiment, the case where the analog baseband circuit described in FIGS. 2A and 2B is configured by a discrete-time analog circuit using the clock adjustment circuit described in Embodiment 1 will be described. Note that the discrete-time analog circuit described here refers to a cyclic time-varying continuous-time circuit in which a continuous-time system and a discrete-time system are combined.

  15A to 15C are conceptual diagrams of a periodic time-varying continuous time system. FIG. 15A is a continuous-time circuit that receives a continuous time (CT) signal and outputs a CT signal. A continuous-time circuit may have a large inductor size, a large variation in the absolute values of R and C, or an active circuit such as an operational amplifier that is difficult to operate at a low power supply voltage. Is not easy.

  FIG. 15B shows a case where a continuous time input signal is converted into a discrete time (DT) signal by a sampling circuit or the like, the converted signal is processed by a discrete time circuit, and the processed discrete time signal is held by a hold circuit. This is a discrete-time circuit that converts the signal into a continuous-time signal. In a discrete-time circuit, the characteristics are determined by the clock frequency and the capacitance ratio, and the circuit can be designed with a low power supply voltage, so that it is suitable for designing with a fine CMOS. However, a switch and a clock are required for conversion between a continuous system and a discrete system at the input and output, and the number of components of the switch and the clock increases compared to the continuous time system. When considering broadband operation, it is desirable to reduce the number of switches and simplify the configuration as much as possible.

  FIG. 15C shows a circuit configuration of a periodic time-varying continuous time system that can be said to be a hybrid of a continuous time system and a discrete time system. A discrete-time circuit is used as part of the continuous-time circuit. As a result, it is possible to realize a circuit that makes use of the characteristics of the discrete time system with a simple configuration, and it is possible to realize a circuit capable of operating in a wide band suitable for a fine CMOS.

[Configuration and Operation of Discrete Time Analog Circuit 600]
FIG. 16 is a diagram illustrating an example of a main configuration of a discrete-time analog circuit 600 according to the third embodiment. A discrete-time analog circuit 600 illustrated in FIG. 16 includes a TA 610 (Transconductance Amplifier), two capacitors 620 (620-1 and 620-2), a charge inversion circuit 630, a clock generation circuit 640, and a clock. An adjustment circuit 650 is included.

Discrete time analog circuit 600 has an input of the input voltage signal V _in including the positive phase and negative phase of the two systems, a discrete-time analog circuitry differential.

TA610 is a voltage-current conversion circuit, receives the input voltage signal _{V in} including the positive phase and negative phase of the two systems, and converts the input voltage signal _{V in} to the current _{(g m} × _{V in),} a positive phase Outputs two currents of opposite phase. Note that g _m is the value of transconductance (mutual conductance) of TA610.

The capacitor 620-1 is connected to the positive-phase output terminal T_TA _out1 of the TA 610, and the capacitor 620-2 is connected between the negative-phase output terminal T_TA _out2 . The capacitance values of the capacitors 620-1 and 620-2 are C _H1 .

The charge inverting circuit 630 includes a plurality of switches, one terminal is connected to the output terminal T_TA _out1 of the TA 610, and the other terminal is connected to the output terminal T_TA _out2 . The charge inverting circuit 630 is a switching circuit that performs an operation of holding charges and an operation of inverting and connecting charges by controlling on / off of a plurality of switches. The charge inversion circuit 630 performs charge sharing based on the clock supplied from the clock adjustment circuit 650 and performs filtering processing on the input analog signal.

  The clock generation circuit 640 and the clock adjustment circuit 650 have configurations similar to those described in Embodiment 1, and supply the clocks S1 to S4 to the charge inversion circuit 630. The clocks S <b> 1 to S <b> 4 are composed of a high period that is an on time of the switch and a low period that is a time when the switch is off (off time).

[Configuration Example 1 of Charge Inversion Circuit]
Here, a specific configuration of the charge inverting circuit 630 will be described. FIG. 17A is a diagram illustrating an example of the configuration of the charge inverting circuit 630A according to the third embodiment. FIG. 17B is a diagram showing an example of an internal configuration of the charge inverting circuit 630A according to the third embodiment. The charge inverting circuit 630A illustrated in FIG. 17B includes two capacitors 631-1 and 631-2, and eight switches 632-1 to 632-8 that control connection between the capacitors 631-1 and 631-2. The terminal A of the charge inverting circuit 630 is connected to the positive phase output terminal T_TA _out1 of the TA 610, and the terminal B is connected to the negative phase output terminal T_TA _out2 of the TA 610.

  The switch 632-1 controls the connection between the terminal X1 and the terminal A by the clock S1, connects during the high period, and disconnects during the low period. The switch 632-2 controls the connection between the terminal X1 and the terminal B by the clock S3, and is connected during the high period and disconnected during the low period. The switch 632-3 controls the connection between the terminal X2 and the terminal A by the control signal S2, and connects during the high period and disconnects during the low period. The switch 632-4 controls the connection between the terminal X2 and the terminal B by the control signal S4, and connects during the high period and disconnects during the low period. The switch 632-5 controls the connection between the terminal X1 and the terminal B by the clock S3, connects during the high period, and disconnects during the low period. The switch 632-6 controls the connection between the terminal Y1 and the terminal A by the clock S3, connects during the high period, and disconnects during the low period. The switch 632-7 controls connection between the terminal X2 and the terminal B by the clock S4, and connects during the high period and disconnects during the low period. The switch 632-8 controls connection between the terminal Y2 and the terminal A by the clock S4, and connects during the high period and disconnects during the low period.

  In the above, the high period and the low period indicate the ideal clock in FIG. 4A. However, even when the clock generation circuit 640 generates a sine wave signal as in FIG. 4B, the clock adjustment circuit 650 corresponds to FIG. 4A. ON / OFF time of the switch to be realized can be realized.

[Generate clock]
Generation of clocks supplied from the clock generation circuit 640 and the clock adjustment circuit 650 will be described. In this embodiment, the clock generation circuit 640 and the clock adjustment circuit 650 generate a clock corresponding to the ideal clock illustrated in FIG. 4A. In FIG. 4A, the pulse width Ts is the same as the sample interval. The clocks S1 to S4 are four-phase control signals having a DUTY ratio (= pulse width Ts / clock period T _CK ) of 0.25 and shifted in phase by 90 degrees.

  That is, the clock adjustment circuit 650 controls the switch so that the switch to be controlled is turned on while the clock in FIG. 4A is high and the switch to be controlled is turned off during the period when the clock is low. In FIG. 4A, a rectangular clock is shown as an ideal clock waveform, but a switch operation corresponding to a similar waveform can be realized even with a sine wave input. For example, the clock generation circuit 640 generates the four-phase sine wave signal of FIG. 4B, the clock adjustment circuit 650 adjusts the bias and capacitance, and adjusts the period during which the switch is turned on. Generation of signals having different phases in the clock generation circuit 640 can be realized by the configurations of FIGS. 9A to 9D, and adjustment of the bias in the clock adjustment circuit 650 can be realized by the configurations of FIGS. 5A to 5C and FIGS. 11A to 11C. . The adjustment of the bias can be realized using the configuration shown in FIGS. 32A and 32B described later. Adjustment of the threshold value for determining on / off of the switch can also be realized by configuring the switches 632-1 to 632-8 as shown in FIG.

[Operation Example 1 of Discrete-Time Analog Circuit 600]
The operation in the discrete time analog circuit 600 will be described. 18A to 18D are diagrams showing an outline of the operation in the discrete-time analog circuit 600. FIG. 18A to 18D sequentially show connection states of TA 610, capacitors 631-1 and 631-2, and capacitor 620-1. In addition, although the discrete-time analog circuit 600 shown in FIG. 16 has been described as a differential configuration including two systems of a normal phase and a negative phase, FIGS. 18A to 18D are single-phase input / output for simplification of description. This will be described as the system configuration.

  The discrete-time analog circuit 600 repeatedly performs charge sharing at intervals Ts to generate sample values. The discrete-time analog circuit 600 shares the following three types of charges.

(1-a) TA 610 converts the input voltage signal Vin into a current, that is, a charge output to the output terminal T_TA _out of TA 110 (hereinafter referred to as input charge).
(1-b) Charge before one sample held by the capacitor 620 (1-c) Charge before two samples held by the charge inversion circuit 630

  In the three types of sharing, the charge inversion circuit 630 shares the charge by inverting the polarity of the charge held two samples before.

As shown in FIGS. 18A to 18D, the charge inversion circuit 630 controls the switches 632-1 to 632-8 based on the clocks S1 to S4 corresponding to the ideal clock shown in FIG. 4A. One operation is performed within one period (1T _CK ), and is repeated every period T _CK . In addition, the following 1st-4th operation | movement respond | corresponds to FIG.

First operation: During the high period of the clock S1, the terminal X1 of the capacitor 631-1 is connected to the terminal A, and the terminal Y1 is connected to the terminal B (hereinafter referred to as a positive phase connection of the capacitor 631-1). .
Second operation: While the clock S2 is high, the terminal X2 of the capacitor 631-2 is connected to the terminal A, and the terminal Y2 is connected to the terminal B (hereinafter referred to as a positive phase connection of the capacitor 631-2). .
Third operation: While the clock S3 is in the high period, the terminal Y1 of the capacitor 631-1 is connected to the terminal A, and the terminal X1 is connected to the terminal B (hereinafter referred to as a reverse phase connection of the capacitor 631-1). .
Fourth operation: While the clock S4 is in the high period, the terminal Y2 of the capacitor 631-2 is connected to the terminal A, and the terminal X2 is connected to the terminal B (hereinafter referred to as reverse-phase connection of the capacitor 631-2). .

  That is, the first operation in which the capacitor 631-1 is connected in the positive phase and the capacitor 631-2 holds the charge shared by the reverse phase connection, the capacitor 631-2 is connected in the positive phase, and the capacitor 631-1 is connected in the positive phase. A second operation for holding the charge shared by the phase connection; a third operation in which the capacitor 631-1 is connected in reverse phase; and the capacitor 631-2 holds the charge shared in charge by the positive phase connection; Four operations, the fourth operation in which the capacitor 631-2 is connected in reverse phase and the capacitor 631-1 holds the charge shared by the reverse phase connection, are performed every interval Ts.

  The capacitors 631-1 and 631-2 are connected by reversing the polarity of the held charges by connecting the charges shared by the positive phase connection (reverse phase connection) in the reverse phase connection (positive phase connection). Perform the action.

  That is, the charge inversion circuit 630A is connected by inverting the polarity of the charge held by the capacitor 631-1 and the connection of the capacitor 631-2 is released by the first to fourth operations. Are connected by inverting the polarity of the charge held in the capacitor 631-2, and the connection of the capacitor 631-1 is released to hold the charge. The operations (second operation and fourth operation) are alternately repeated every Ts period.

The first to fourth operations will be described mathematically.
An outline of charge sharing at time n in the discrete-time analog circuit 600 can be described by a difference equation of the following equation (1).

ただし、ここで示した数式は回路を離散系と見た場合の伝達関数の概略である。正確な入出力特性の導出は周期時変連続時間系の解析が必要である。 In Expression (1), the first term on the left side corresponds to the input charge, the second term is the charge one sample before held in the capacitor 620, and the third term on the left side is the capacitance 631-1 or 631-2. This is the charge held two samples before. By performing z conversion, the core part of the transfer function of the discrete-time analog circuit 600 is expressed by the following equation (2).

However, the mathematical formula shown here is an outline of the transfer function when the circuit is viewed as a discrete system. Derivation of accurate input / output characteristics requires analysis of a time-varying continuous time system.

  That is, an analysis as a circuit including a discrete time system circuit (or a parallel system having a discrete time relationship with the continuous time system) inside the continuous time system GmC filter shown in FIG. 16 is necessary. The transfer function of the discrete time filter becomes a synthesized transfer function, but the core of the transfer function is the above equation, and the in-band deviation can be adjusted by the effect of the discrete time system.

The frequency characteristics of the discrete time analog circuit 600 will be described. FIG. 19 is a diagram illustrating a result of circuit simulation of the low-pass characteristics of the discrete-time analog circuit 600. In FIG. 19, the horizontal axis represents frequency, and the vertical axis represents Gain. FIG. 19 shows the low-pass characteristics of the discrete-time analog circuit 600 in which C _H1 is 300 fF and C _H2 changes as a parameter. Note that the discrete-time analog circuit 600 may fix C _H2 and use C _H1 as a parameter.

As shown in FIG. 19, the discrete-time analog circuit 600 can pass a wideband signal, and can adjust the in-band deviation (level difference) of the passband by changing C _H2 (or C _H1 ). Furthermore, since the discrete-time analog circuit 600 has a differential configuration, even-order components can be removed after differential synthesis.

[Configuration Example 2 of Charge Inversion Circuit]
Next, another configuration of the charge inverting circuit 630 will be described. FIG. 17C is a diagram illustrating an example of the configuration of the charge inverting circuit 630B according to the third embodiment. FIG. 17D is a diagram illustrating an example of an internal configuration of the charge inverting circuit 630B according to the third embodiment. In FIGS. 17C and 17D, the same reference numerals as those in FIGS. 17A and 17B are attached to the same components as those in FIGS. 17A and 17B, and detailed descriptions thereof are omitted. Further, the clocks S1 to S4 supplied to the charge inverting circuit 630B are the same as the clocks S1 to S4 supplied to the charge inverting circuit 630A described above, and thus the description thereof is omitted.

  The charge inverting circuit 630B is different from the charge inverting circuit 630A in the number of switches and the connection positions of the capacitors 631-1 and 631-2. The operation when the charge inverting circuit 630 in FIG. 16 is replaced with the charge inverting circuit 630B will be described below.

By controlling the switches 632-1 to 632-4 based on the clocks S1 to S4 corresponding to the ideal clocks S1 to S4 shown in FIG. 4A (on and off), the following four operations are performed within one cycle (1T _CK ). And repeat every cycle _TCK .
First operation: The terminal X1 of the capacitor 631-1 is connected to the terminal A while the control signal S1 is in the high period. (Hereinafter referred to as positive phase connection of the capacitor 631-1)
Second operation: The terminal X2 of the capacitor 631-2 is connected to the terminal A while the control signal S2 is high. (Hereinafter referred to as positive phase connection of capacitor 631-2)
Third operation: While the control signal S3 is in the high period, the terminal X1 of the capacitor 631-1 is connected to the terminal B (hereinafter referred to as reverse-phase connection of the capacitor 631-1).
Fourth operation: While the control signal S4 is in the high period, the terminal X2 of the capacitor 631-2 is connected to the terminal B (hereinafter referred to as reverse-phase connection of the capacitor 631-2).

  That is, the first operation in which the capacitor 631-1 is connected in the positive phase and the capacitor 631-2 holds the charge shared by the reverse phase connection, the capacitor 631-2 is connected in the positive phase, and the capacitor 631-1 is connected in the positive phase. A second operation for holding the charge shared by the phase connection; a third operation in which the capacitor 631-1 is connected in reverse phase; and the capacitor 631-2 holds the charge shared in charge by the positive phase connection; Four operations, the fourth operation in which the capacitor 631-2 is connected in reverse phase and the capacitor 631-1 holds the charge shared by the reverse phase connection, are performed every interval Ts.

  The capacitors 631-1 and 631-2 are connected by reversing the polarity of the held charges by connecting the charges shared by the positive phase connection (reverse phase connection) in the reverse phase connection (positive phase connection). Perform the action.

  That is, the charge inversion circuit 630B is connected by inverting the polarity of the charge held by the capacitor 631-1 and the connection of the capacitor 631-2 is released by the first to fourth operations. Are connected by inverting the polarity of the charge held in the capacitor 631-2, and the connection of the capacitor 631-1 is released to hold the charge. The operations (second operation and fourth operation) are alternately repeated every Ts period.

  The mathematical description and frequency characteristics when the charge inverting circuit 630 in FIG. 16 is the charge inverting circuit 630B are the same as those of the charge inverting circuit 630A described above.

  In the configurations of FIGS. 17C and 17D, it is possible to provide ripples in the passband, and it is possible to realize a broadband filter characteristic.

[Configuration Example 3 of Charge Inversion Circuit]
Next, still another configuration of the charge inverting circuit 630 will be described. FIG. 20A is a diagram illustrating an example of the configuration of the charge inverting circuit 630C according to the third embodiment. FIG. 20B is a diagram illustrating an example of an internal configuration of the charge inverting circuit 630C according to the third embodiment. 20A and 20B, components common to those in FIGS. 17C and 17D are denoted by the same reference numerals as in FIGS. 17C and 17D, and detailed description thereof is omitted.

  The charge inversion circuit 630C has the same circuit configuration as the charge inversion circuit 630B. However, the clocks SP and SN for controlling the switches 632-1 to 632-4 are different from the case of the charge inverting circuit 630B.

  When the charge inverting circuit 630 in FIG. 16 is the charge inverting circuit 630C, the clock supplied from the clock adjusting circuit 650 in FIG. 16 is also different from that in the charge inverting circuit 630B.

  Specifically, the clocks SP and SN for controlling the switches 632-1 to 632-4 of the charge inverting circuit 630C are ideally clocks as shown in FIG. 14A.

  The clock adjustment circuit 650 adjusts the bias and phase so that the switch to be controlled is turned on during the period when the clock of FIG. 14A is high and the switch to be controlled is turned off during the period when the clock is low. For example, the clock generation circuit 640 generates a two-phase sine wave signal, the clock adjustment circuit 650 adjusts the bias and phase, and adjusts the period during which the switch is turned on.

An outline of the transfer function H _H of the discrete-time analog circuit 600 when the charge inverting circuit 630 of FIG. 16 is the charge inverting circuit 630C is expressed by the following equation.

As shown in Expression (3), the charge inverting circuit 630C can realize a first-order transfer function. A ripple can be obtained in the frequency characteristics by adjusting C _H1 , C _H2 , and fs. Note that the same operation is possible even in a configuration in which the capacitor 620 (capacitance value C _H1 ) is omitted.

  Further, the same operation as that in FIG. 17D is the same operation even when another configuration is used. FIG. 21A is a diagram showing another example of the configuration of the charge inverting circuit 630D according to the third embodiment. FIG. 21B is a diagram showing another example of the internal configuration of the charge inverting circuit 630D according to Embodiment 3. FIG. 21C is a diagram illustrating an example of a clock for operating the charge inverting circuit 630D illustrated in FIG. 21B.

  The charge inverting circuit 630D illustrated in FIG. 21B performs the same operation as that illustrated in FIG. 17D using the clock illustrated in FIG. 21C.

[effect]
As described above, according to the present embodiment, the configuration shown in FIGS. 16 and 17A to 17D, specifically, TA 610 that is a voltage-current conversion circuit, capacitors (capacitors 620-1 and 620-2, capacitors 631-1 and 631-2), a switch, and control of the ratio of C _H1 and C _H2 in the four types of clocks (S1 to S4), the wide band pass characteristics shown in FIG. An adjustable filter can be realized.

That is, when trying to realize a wide band pass characteristic exceeding several GHz, the influence of the parasitic capacitance of the switch is increased. However, in the present disclosure, since the number of switches is small, the discrete-time analog circuit 600 has a small parasitic characteristic. A circuit can be configured with a capacitance. In addition, since the discrete-time analog circuit 600 can adjust the in-band deviation, the in-band deviation can be reduced including the frequency characteristics of other circuit blocks, and can also function as an equalizer. The discrete-time analog circuit 600 can also be used as a variable gain amplifier (VGA) because the gain can be adjusted by adjusting the values of g _m, C _H1 , and C _H2 . An amplifier may be connected to the input of the TA 610 to increase the gain.

Note that the discrete-time analog circuit 600 uses the capacitors 620-1 and 620-2 (capacitance value C _H1 ) and the capacitors 631-1 and 631-2 (capacitance value C _H2 ) as variable capacitors, thereby improving the characteristics. The change can be facilitated, and the characteristic can be adaptively changed with respect to the influence of communication environment (for example, change in ambient temperature or power supply voltage) or variation in circuit elements.

  Examples of the configuration of the variable capacitor include a method of controlling the number of capacitors connected by a switch, and a method of changing a capacitance value by controlling a voltage value applied to a varactor capacitor by a voltage. The same applies to the following embodiments. That is, in the conventional discrete-time analog circuit, the number of switches increases as the number of capacitors constituting the variable capacitor increases, and as a result, the total amount of parasitic capacitance increases. Since it is smaller than an analog circuit, the total number of switches is also small, and as a result, the total amount of parasitic capacitance is smaller than that of the conventional configuration.

  Further, the switches 632-1 to 632-8 may be configured by transistors. As a general transistor configuration, when manufactured by a fine CMOS process, a configuration using an NMOS transistor, a configuration using a PMOS transistor, and a configuration of a complementary switch using NMOS and PMOS are known.

As a method of monitoring the output terminals T_V _out1 and T_V _out2 , a method of monitoring by connecting a buffer or amplifier such as a VCVS (Voltage-Controlled Voltage Source) that minimizes the movement of the held charge is used. It may be used.

The discrete-time analog circuit 600 may have a configuration in which the capacitor 620 (capacitance value C _H1 ) is omitted. With this configuration, when the charge inverting circuits 630A and 630B are used, a second-order IIR transfer function with C _H1 = 0 in the equation (4) can be realized. In addition, the said effect has the same effect also in other embodiment.

Note that in this embodiment, the capacitors 620-1 and 620-2 are connected to the positive-phase output terminal T_TA _out1 and the negative-phase output terminal T_TA _out2 of the TA 610, respectively. The positive phase output terminal T_TA _out1 and the negative phase output terminal T_TA _out2 may be connected. The values of the two capacitors connected to each of the positive-phase output terminal T_TA _out1 and the negative-phase output terminal T_TA _out2 of the TA 610 are basically the same value, but are different from each other in order to increase the degree of freedom of characteristics. It is good.

[Realization of higher-order transfer functions]
By increasing the period during which the charge inverting circuit holds the charge, a higher-order transfer function can be realized with respect to the denominator (hereinafter referred to as the IIR function) of the IIR part of the transfer function of the discrete-time analog circuit. In the present embodiment described above, the sign of the coefficient of each term of the IIR function can be changed by changing the configuration of the charge inverting circuit. In the present embodiment described above, the number of terms of the IIR function can be changed by changing the number of charge inverting circuits. Below, an example of these variations is demonstrated.

[Configuration of Discrete-Time Analog Circuit 700]
FIG. 22 is a diagram illustrating an example of the configuration of the discrete-time analog circuit 700 according to the third embodiment. The discrete-time analog circuit 700 includes a TA 710, two capacitors 720 (capacitors 720-1 and 720-2), L charge circuits 730 (charge circuits 730-1 to 730-L), and a clock generation circuit 740. And a clock adjustment circuit 750.

  Note that the capacitor 720 can be omitted in the discrete-time analog circuit 700. In the configuration illustrated in FIG. 22, the discrete-time analog circuit 700 includes the capacitor 720. For example, the IIR function includes a first-order term having a negative coefficient due to the capacitor 720. On the other hand, when the capacitor 720 is omitted, the IIR function can select positive and negative coefficients for the first-order term by the L charge circuits 730.

  A TA 710 and a capacitor 720 illustrated in FIG. 22 are the same as the TA 610 and the capacitor 620 illustrated in FIG. 16, respectively.

In the L charge circuits 730-1 to 730-L, the terminals A-1 to A-L are connected to the output terminal T_TA _out1 of the TA 710, and the terminals B- ₁ to BL are connected to the output terminal T_TA _out1 . Is done.

  The charge circuit 730 is a charge inversion circuit that performs an operation of holding the charge without inverting the polarity of the charge after holding the charge in accordance with a desired frequency characteristic. The charge circuit 730 is connected by inverting the polarity of the charge after holding the charge. Any one of the charge holding connection circuits is employed. Note that the discrete-time analog circuit 700 may include a charge holding connection circuit and a charge inversion circuit as the charge circuit 730, or may be configured of either one.

  Here, a configuration in which the charge circuit 730 is used as a charge inverting circuit will be described.

  FIG. 23A is a diagram illustrating an example of the configuration of the charge inverting circuit 730A according to the third embodiment. FIG. 23B is a diagram illustrating an example of an internal configuration of the charge inverting circuit 730A according to the third embodiment. The charge inversion circuit 730A illustrated in FIG. 29B includes M capacitors 731-1 to 731-M and 4M switches 732-1 to 732-4M that control connection between the M capacitors 731-1 to 731-M. Have Since the configuration of the charge inverting circuit 730A is an expanded configuration of the configuration of the charge inverting circuit 630A already described, detailed description thereof is omitted.

A clock generated by the clock generation circuit 740 and the clock adjustment circuit 750 for the configuration of the charge inverting circuit 730A illustrated in FIG. 23B will be described. FIG. 24A is a timing chart of an ideal clock for the charge inverting circuit 730A shown in FIG. 23B. The clock has a pulse width Ts and a period _TCK . The pulse width Ts is the same as the sample interval. In FIG. 24A, a rectangular signal is shown as an ideal clock. However, the clock generation circuit 740 and the clock adjustment circuit 750 turn on the switch to be controlled during the high period of the ideal clock and the switch to be controlled during the low period. Make adjustments to turn it off.

Specifically, the clock generation circuit 740 and the clock adjustment circuit 750 have a DUTY ratio (= switch ON time T _ON / clock cycle T _CK ) in the switch 1/1 with respect to the charge inversion circuit 730A illustrated in FIG. The 2M-phase clocks S1 to S2M that are 2M and out of phase by (360 / 2M) degrees are supplied to the charge inverting circuit 730A.

  The operation of the charge inverting circuit 730A by the clocks S1 to S2M is the same as the operation of the charge inverting circuit 630A having the two capacitors described in Embodiment 1, and thus detailed description thereof is omitted.

  The M capacitors included in the charge inverting circuit 730A alternately repeat the operation of holding the charge-shared charge for the (M−1) Ts period and the operation of inverting the polarity of the held charge and connecting it to the outside. .

  That is, in the charge sharing of the discrete-time analog circuit 700, the charge inverting circuit 730A is connected by inverting the polarity of the held charge before M samples.

  By connecting the charge inverting circuit 730A shown in FIG. 23B as one of the charge inverting circuits 730-1 to 730-L shown in FIG. 22, the IIR function of the discrete time analog circuit 700 shown in FIG. It has M order terms.

  Next, a configuration in which the charge circuit 730 is used as a charge holding connection circuit will be described.

  FIG. 23C is a diagram illustrating an example of the configuration of the charge retention connection circuit 730B according to the third embodiment. FIG. 23D is a diagram illustrating an example of an internal configuration of the charge retention connection circuit 730B according to the third embodiment. The charge holding connection circuit 730B illustrated in FIG. 23D includes 2M pieces of terminals that control connection of the terminals A and B, the M capacitors 731-1 to 731-M, and the M capacitors 731-1 to 731-M. Switches 732-1 to 732-2M are included.

  The configuration and operation of the charge retention connection circuit 730B illustrated in FIG. 23D will be described using the capacitor 731-1 as an example.

  The capacitor 731-1 has a terminal X1 and a terminal Y1, and is connected to the switches 732-1 and 732-2. The switch 732-1 connects the terminal X1 and the terminal A during the high period of the clock S1, and disconnects during the low period of the clock S1. The switch 732-2 connects the terminal Y1 and the terminal B during the high period of the clock S1, and disconnects during the low period of the clock S1.

  The capacity 732-2 to 732-M is the same as the capacity 731-1. However, the connection of each capacitor is controlled by a clock whose phase is shifted by (360 / M) degrees.

FIG. 24B is a timing chart of an ideal clock for the charge holding connection circuit 730B shown in FIG. 23D. The clock has a pulse width Ts and a period _TCK . The pulse width Ts is the same as the sample interval. In FIG. 24B, a rectangular signal is shown as an ideal clock. However, in the clock generation circuit 740 and the clock adjustment circuit 750, the switch to be controlled is turned on in the high period of the ideal clock, and the switch to be controlled is switched in the low period. Make adjustments to turn it off.

As shown in FIG. 24B, the clock generation circuit 740 and the clock adjustment circuit 750 are different from the charge holding connection circuit 730B shown in FIG. 23D in the DUTY ratio in the switch (= switch ON time T _ON / clock cycle T _CK ). Is 1 / M, and M-phase clocks S1 to SM whose phases are shifted by (360 / M) degrees are supplied to the charge holding connection circuit 730B.

  The M capacitors included in the charge holding connection circuit 730B illustrated in FIG. 23D have the operation of holding the charge shared charge for the (M−1) Ts period by the clock illustrated in FIG. 24B and the held charge in phase. The operation of connecting to the outside is repeated alternately.

  That is, the charge holding connection circuit 730B illustrated in FIG. 23D connects the charges before M samples held in the same phase in charge sharing of the discrete-time analog circuit 700.

  By connecting the charge holding connection circuit 730B shown in FIG. 23D as one of the charge circuits 730-1 to 730-L shown in FIG. 22, the IIR of the discrete-time analog circuit 700 shown in FIG. It has the following terms.

  Note that the capacitor 720 is equivalent to the charge holding connection circuit 730B in which M = 1.

The discrete time analog circuit shown in FIG. 22 is obtained by connecting one of the charge inversion circuit 730A shown in FIG. 23B and the charge holding connection circuit 730B shown in FIG. 23D as the charge circuits 730-1 to 730-L shown in FIG. The number of 700 IIR terms, the sign of the coefficient, and the order can be freely designed as in the following equation (4).

  That is, the degree of freedom of filter characteristics that can be realized can be increased by combining the charge inversion circuit 730A shown in FIG. 23B and the charge holding connection circuit 730B shown in FIG. 23D by changing the respective orders.

  Next, another configuration of FIGS. 23A and 23B will be described. FIG. 25A is a diagram illustrating an example of the configuration of the charge inverting circuit 730C according to the third embodiment. FIG. 25B is a diagram illustrating an example of an internal configuration of the charge inverting circuit 730C according to the third embodiment. In FIGS. 25A and 25B, the same reference numerals as those in FIGS. 23A and 23B are attached to the same components as those in FIGS. 23A and 23B, and detailed descriptions thereof are omitted.

  The configuration and operation of the charge inverting circuit 730C is an extension of the configuration and operation of the charge inverting circuit 630B described above in accordance with the number of capacitors, and thus detailed description thereof is omitted. Even when the configuration of the charge inverting circuit 730C is used as the charge circuit 730, the degree of freedom of filter characteristics that can be realized in the same manner as the charge inverting circuit 730A can be increased.

  Next, another configuration of FIGS. 23C and 23D will be described. FIG. 25C is a diagram illustrating an example of the configuration of the charge retention connection circuit 730D according to the third embodiment. FIG. 25D is a diagram illustrating an example of an internal configuration of the charge retention connection circuit 730D according to the third embodiment. In FIG. 25C and FIG. 25D, components common to those in FIG. 23C and FIG. 23D are assigned the same reference numerals as in FIG. 23C and FIG.

  A charge holding connection circuit 730B illustrated in FIG. 23D includes M capacitors 731-1 to 731-M, and the M capacitors 731-1 to 731-M are provided between two switches, respectively. Yes. On the other hand, the charge holding connection circuit 730D illustrated in FIG. 25D includes 2M capacitors 731-1 to 731-2M, and each of the 2M capacitors 731-1 to 731-2M includes a switch serving as a switch. Connected and the other terminal is grounded.

  With this configuration, the charge retention connection circuit 730D performs the same operation as the charge retention connection circuit 730B, and can increase the degree of freedom of filter characteristics that can be realized in the same manner.

[Configuration and Operation of Multistage Discrete Time Analog Circuit 800]
FIG. 26A is a diagram illustrating an example of the configuration of the multi-stage discrete time analog circuit 800. FIG. 26B is a diagram showing an example of the internal configuration of the multistage discrete-time analog circuit 800. A multistage discrete-time analog circuit 800 shown in FIG. 26A has a configuration in which N discrete-time analog circuits 810 are cascaded (810-1 to 810-N), and further includes a clock generation circuit 820 and a clock adjustment circuit 830. And have.

  The discrete-time analog circuit 810 illustrated in FIG. 26B has a configuration similar to that of the discrete-time analog circuit 600 illustrated in FIG. 16, and the TA 811 and the capacitor 812 illustrated in FIG. 26B are respectively TA 610 and the capacitor 620 illustrated in FIG. It is the same.

  The configuration of the charge inverting circuit 813 illustrated in FIG. 26B is the same as the configuration of the charge inverting circuit 630 illustrated in FIGS. 17A to 17D and FIGS.

  Further, the clock generation circuit 820 and the clock adjustment circuit 830 shown in FIG. 26B are the same as the clock generation circuit 640 and the clock adjustment circuit 650 shown in FIG. 16, and the switches having the same waveforms as those shown in FIGS. 14A and 14B are used. A signal for controlling the on / off time is supplied to N discrete-time analog circuits 810-1 to 810 -N.

ここで、ｇ_ｍｋ、Ｃ_Ｈ１ｋ、Ｃ_Ｈ２ｋは、ｋ段目の離散時間アナログ回路３１０−ｋ（Ｎは１以上の整数、ｋ＝１〜Ｎの整数）のＣ_Ｈ１、Ｃ_Ｈ２であり、Ｈ_Ｈｋはｋ段目の離散時間アナログ回路３１０−ｋの伝達関数である。各段においてｇ_ｍ、Ｃ_Ｈ１、Ｃ_Ｈ２の値を適宜変更してもよい。 Since the multi-stage discrete time analog circuit 800 is configured to cascade N discrete time analog circuits 810, the transfer function of the multi-stage discrete time analog circuit 800 is expressed by the following equation (5).

_{Here, g mk, C H1k, C} H2k are discrete time analog circuits 310-k of the k-th stage (N is an integer of 1 or more, integer k = 1 to N) is a _{C H1, C H2} of, H _Hk is a transfer function of the k-th stage discrete-time analog circuit 310-k. The values of g _m , C _H1 , and C _H2 may be appropriately changed in each stage.

Equation (6), in Formula (5), a _{C H1k,} result of changing the _{C H2k} the same value in each stage.

  As shown in the above equation, the multistage discrete-time analog circuit 800 can realize higher-order filter characteristics as the number of cascaded stages is increased, and can realize steep filter characteristics.

[effect]
As described above, steep filter characteristics can be realized by a configuration in which discrete-time analog circuits are connected in cascade. Since the discrete-time analog circuit 810 has a small and simple configuration, the number of switches and capacitors can be suppressed even if the number of stages is increased for higher order. Furthermore, since the multistage discrete-time analog circuit 800 has a differential configuration, even-order components can be removed after differential synthesis.

  Note that the capacitance values of the capacitors included in each of the N discrete-time analog circuits 810-1 to 810 -N may be the same or different.

  In FIG. 26B, the configuration of the discrete-time analog circuit 810 has been described using the configuration of FIG. 16, but the discrete-time analog circuit 810 may use the configuration of FIG.

  Although the third embodiment has been described with respect to the differential configuration, it can also be applied to a single-ended configuration.

  Although an example using a periodic time-varying continuous-time circuit has been described here, a clock generation circuit and a clock adjustment circuit can be used for a discrete-time circuit.

(Embodiment 4)
Next, a fourth embodiment of the present disclosure will be described. In the present embodiment, the mixer operating with the low-frequency clock in the second embodiment is applied to a discrete-time receiver.

[Discrete time receiver with low frequency clock]
FIG. 27 is a block diagram showing a configuration of receiving apparatus 30 according to the fourth embodiment. 27 includes an antenna 31, a low noise amplifier 32, a reference frequency oscillation unit 33, a discrete time analog circuit 34, an A / D conversion processing unit 35, and a digital reception processing unit 36. Have.

  The receiving device 30 has a configuration in which the receiving mixer 25 and the LO frequency oscillating unit 24 are deleted from the receiving device 20 shown in FIG. 3B. The discrete time analog circuit 34 of the reception device 30 has the functions of the discrete time analog circuit 26, the reception mixer 25, and the LO frequency oscillation unit 24 of the reception device 20.

  The antenna 31, the low noise amplifier 32, the reference frequency oscillating unit 33, the A / D conversion processing unit 35, and the digital reception processing unit 36 of the receiving device 30 are the antenna 21, the low noise amplifier 22, the reference frequency oscillating of the receiving device 20, respectively. Since it is the same as the unit 23, the A / D conversion processing unit 27, and the digital reception processing unit 28, description thereof is omitted.

  The discrete time analog circuit 34 performs frequency conversion and filtering of the analog reception signal of the RF frequency output from the low noise amplifier 32.

  27 has been described as a direct conversion configuration. The receiving apparatus 30 according to the present embodiment may be a system that adds one or more mixers and uses an intermediate frequency (IF). The discrete-time analog circuit 34 may be used as any mixer between RF-IF and IF-baseband. When a plurality of IFs are used, they may be used as a mixer between different IFs.

[Direct sampling mixer with clock adjustment circuit]
FIG. 28A is a diagram illustrating an example of a configuration of a discrete-time analog circuit 900 according to Embodiment 4. The discrete time analog circuit 900 corresponds to the discrete time analog circuit 34 in FIG.

  The discrete-time analog circuit 900 includes a TA 910 that converts voltage to current, two local switches 920 (920-1 and 920-2) that perform frequency conversion, and two history capacitors 930 (930-1 and 930-2). Two passive switched capacitor filters (PSCF) 940 (940-1 and 940-2), a clock generation circuit 950, and a clock adjustment circuit 960 are included.

  FIG. 28B is a diagram illustrating an example of a configuration of the PSCF 940 according to Embodiment 4. The PSCF 940 includes a charge sharing switch 941 (941-1, 941-2), a rotation capacitor 942 (942-1, 942-2), a reset switch 943 (943-1, 943-2), and a feedback switch 944 (944-1). 944-2), a dump switch 945 (945-1, 945-2), and a buffer capacitor 946.

  FIG. 28C is an ideal clock timing chart for the discrete-time analog circuit 900 shown in FIG. 28A. In FIG. 28C, a rectangular signal is shown as an ideal clock. However, in the clock generation circuit 950 and the clock adjustment circuit 960, the switch to be controlled is turned on in the high period of the ideal clock, and the switch to be controlled is switched in the low period. Make adjustments to turn it off.

  Here, the operation of the discrete-time analog circuit 900 to which a clock corresponding to the ideal clock shown in FIG. 28C is supplied will be described.

  First, TA 910 converts an input voltage into a current. The history capacitor 930 and the rotation capacitor 942 accumulate input charges while the local switch 920 and the charge sharing switch 941 are turned on. Next, the rotation capacitor 942 and the buffer capacitor 946 share charges while the local switch 920 is turned off and the dump switch 945 is turned on, and the potential of the buffer capacitor 946 becomes an output.

  Next, while the reset switch 943 is turned on, the rotation capacitor 942 discharges the accumulated charge via the reset switch 943. Finally, a bias potential is applied to the rotation capacitor 942 through the feedback switch 944 while the feedback switch 944 is turned on.

  The discrete-time analog circuit 900 performs frequency conversion and filtering by repeating this operation.

  Next, a configuration for realizing the same operation as that of the discrete-time analog circuit 900 described above at a low clock frequency will be described.

[Direct sampling mixer with low frequency clock operation]
FIG. 29A is a diagram illustrating an example of a configuration of a discrete-time analog circuit 1000 according to Embodiment 4. In FIG. 29A, components common to those in FIG. 28A are assigned the same reference numerals as in FIG. 28A, and detailed descriptions thereof are omitted.

  In the discrete-time analog circuit 1000 in FIG. 29A, the local switch 920, the clock generation circuit 950, and the clock adjustment circuit 960 in the discrete-time analog circuit 900 in FIG. It has the structure replaced by.

  The local switch unit 1020 has the configuration of the mixer 500 that operates with the low-frequency clock shown in FIG. 13C. The clock adjustment circuit 960 in FIG. 28A supplies the clocks LO + and LO− to the local switch 920, but the clock adjustment circuit 1060 in FIG. 29A supplies the clocks S1 to S (2M) to the local switch unit 1020. To do.

  FIG. 29B is an ideal clock timing chart for the discrete-time analog circuit 1000 shown in FIG. 29A. FIG. 29B shows the clocks LO + and LO− shown in FIG. 28C for comparison, but the discrete-time analog circuit 1000 does not use these clocks. In FIG. 29B, a rectangular signal is shown as an ideal clock. However, the clock generation circuit 1050 and the clock adjustment circuit 1060 are switched on in the high period of the ideal clock, and controlled in the low period. Adjustments may be made so that the switch is turned off.

The discrete-time analog circuit 900 and the discrete-time analog circuit 1000 perform the same operation by making the ON time (that is, the ideal clock shown in FIG. 28C and the ideal clock pulse width Ts shown in FIG. 29B) in the switch the same. In that case, the period _{T LO} of the clock of Figure 29B, M times the period _{T LO} of the clock in FIG. 28C, that is, the clock frequency _{f LO} is 1 / M, and the discrete time analog circuit 1000 can operate at a low frequency clock .

  With this configuration, the discrete-time analog circuit 1000 can also operate with a low-frequency clock.

(Embodiment 5)
The characteristics of the mixer and discrete time analog circuit described in each of the above embodiments may depend on the DUTY ratio of the clock. In this embodiment, a configuration in which the characteristics of a mixer or a discrete-time analog circuit are monitored and the characteristics are controlled by a clock generation circuit and a clock adjustment circuit will be described.

  FIG. 30A is a diagram illustrating a configuration of a mixer with a characteristic control function or a discrete-time analog circuit 1100 according to the fifth embodiment. The mixer or discrete time analog circuit 1100 with a characteristic control function includes a mixer or discrete time analog circuit 1110, a characteristic monitor circuit 1120, and a characteristic control circuit 1130. The mixer or discrete time analog circuit 1110 includes a clock generation circuit 1140, a clock adjustment circuit 1150, and a target circuit 1160.

  For example, when the mixer or discrete analog circuit 1110 is the mixer 100 shown in FIG. 3, the target circuit 1160 corresponds to a circuit obtained by removing the clock generation circuit 120 and the clock adjustment circuit 130 from the mixer 100. When the mixer or the discrete analog circuit 1110 is the discrete time analog circuit 600 shown in FIG. 16, the target circuit 1160 corresponds to a circuit obtained by removing the clock generation circuit 640 and the clock adjustment circuit 650 from the discrete time analog circuit 600.

  FIG. 30B is a diagram showing a configuration of a mixer with a characteristic control function or a discrete time analog circuit 1200 having the clock adjustment circuit 1150 having the configuration shown in FIG. 5B. The clock adjustment circuit 1150 includes a buffer 1210, a variable capacitor 1220, a resistor 1230, and a capacitor 1240, and receives a base clock from the clock generation circuit 1140 (see FIG. 30A). The operation of the clock adjustment circuit 1120 is the same as that of the clock adjustment circuit described with reference to FIG.

  A control flow of the mixer with the characteristic control function or the discrete time analog circuit 1200 will be described. FIG. 30C is a diagram illustrating an example of a control flow of the configuration illustrated in FIG. 30B.

  In the mixer with characteristic control function or the discrete-time analog circuit 1200, the characteristic monitor circuit 1120 starts monitoring the output power of the target circuit 1160 at an arbitrary frequency f1 (S01).

  The characteristic monitor circuit 1120 causes the characteristic control circuit 1130 to increase the capacitance value of the variable capacitor 1220 until it detects that the gain of the output power at the frequency f1 is changed by adjusting the bias potential V1 (S02).

  Next, the characteristic monitor circuit 1120 causes the characteristic control circuit 1130 to adjust the bias potential V1 so that the gain of the output power of the frequency f1 being monitored becomes the target gain (S03).

  When the characteristic monitor circuit 1120 detects that the output power is within the target range, the characteristic monitor circuit 1120 ends the bias adjustment in the characteristic control circuit 1130 and ends the monitoring (S04).

  With the control described above, the bias and phase of the clock are adjusted while monitoring the output power of the target circuit 1160, and the characteristics of the mixer with the characteristic control function or the discrete-time analog circuit 1200 can be maintained at desired characteristics.

  In the above description, the configuration in which the characteristic monitor circuit 1140 monitors the output power of the target circuit 1160 has been described. Hereinafter, a configuration in which the characteristic monitor circuit 1140 monitors other outputs will be described.

  Specifically, an example in which the characteristic monitor circuit 1140 described with reference to FIGS. FIG. 31 is a diagram illustrating an example in which the characteristic monitor circuit 1140 according to the fifth embodiment monitors the output of the transmission / reception device.

  In FIG. 31, the transmission device 40, the reception device 50, the transmission device 40, the characteristic monitor circuit 61 that monitors the output characteristics of the reception device 50, and the characteristic control that controls the mixer included in the transmission device 40 and the reception device 50. Circuit 60 is shown. Here, a method in which the characteristic monitor circuit 61 compares the input to the transmission apparatus 40 and the output from the reception apparatus 50 in a communication apparatus having both the transmission apparatus 40 and the reception apparatus 50 will be described.

  The configurations of the transmission device 40 and the reception device 50 are the same as the configurations of the transmission device 10 and the reception device 20 described in FIG. 2A and FIG.

  When the analog baseband circuits 45 and 56 are replaced with discrete time analog circuits, the characteristic control circuit 60 controls the replaced discrete time analog circuits 45 and 56.

  The characteristic control circuit 60 and the characteristic monitor circuit 61 are the same as the characteristic control circuit 1130 and the characteristic monitor circuit 1120 described with reference to FIG. 30A, respectively. In FIG. 31, the characteristic control circuit 60 controls at least one of the mixers 46 and 55 and the discrete time analog circuits 45 and 56.

  A specific characteristic monitoring method in the characteristic monitor circuit 61 will be described.

  As an example, the transmission device 40 transmits predetermined transmission data from the antenna 48 through processing from the digital transmission processing unit 41 to the power amplifier 47, and the reception device 50 receives from the antenna 51 and receives the low noise amplifier 52. Through the digital reception processing unit 58, reception data is generated. In the processing, the characteristic monitor circuit 61 compares the characteristics such as the frequency characteristic, SNR, and bit error rate of the transmission data and the reception data. The characteristic monitor circuit 61 controls the mixers 46 and 55 or / and the discrete time analog circuits 45 and 56 by the characteristic control circuit 60 so that the characteristic becomes a desired characteristic.

  As another example, the transmission device 40 performs processing from the digital transmission processing unit 41 to the discrete time analog circuit 45 on predetermined transmission data, and the reception device 50 outputs the output of the discrete time analog circuit 45 to the discrete time analog signal. The data is input to the circuit 56 and processed by the A / D conversion processing unit 57 and the digital reception processing unit 58 to generate reception data. In the processing, the characteristic monitor circuit 61 compares the characteristics such as the frequency characteristic, SNR, and bit error rate of the transmission data and the reception data. The characteristic monitor circuit 61 controls the discrete time analog circuits 45 and 56 by the characteristic control circuit 60 so that the characteristic becomes a desired characteristic.

  Alternatively, the transmission device 40 performs processing from the digital transmission processing unit 41 to the mixer 46 for predetermined transmission data, the reception device 50 inputs the output of the mixer 46 to the mixer 55, and the digital signal is output from the discrete time analog circuit 56. The processing up to the reception processing unit 58 is performed to generate reception data. In the processing, the characteristic monitor circuit 61 compares the characteristics such as the frequency characteristic, SNR, and bit error rate of the transmission data and the reception data. The characteristic monitor circuit 61 controls the mixers 46 and 55 or / and the discrete time analog circuits 45 and 56 by the characteristic control circuit 60 so that the characteristic becomes a desired characteristic.

  In order to monitor the frequency characteristics, a sine wave signal of several frequencies is transmitted as a transmission signal, and each amplitude is observed by reception.

  As the transmission device, a device that actually transmits data may be used in combination, or a simple transmission device may be prepared for characteristic correction.

  Here, an example of an adjustment circuit for adjusting the voltage value of the bias in the first to fifth embodiments described above will be described.

  32A and 32B are diagrams illustrating an example of an adjustment circuit that adjusts the voltage value of the bias. In the configuration of FIG. 32A, a variable reference current Iref is adjusted to obtain a target voltage Vref, and FIG. 32B is a configuration in which a fixed reference current Iref is caused to flow through a plurality of resistors and a target is selected by selecting a resistor and an output position. This is a method for obtaining the voltage Vref.

(Embodiment 6)
In this embodiment, a clock generation circuit that generates a signal having an arbitrary DUTY ratio with a simple configuration by adjusting a bias of an input signal of an inverter will be described.

  FIG. 33 shows a configuration of the clock generation circuit 1300. The clock generation circuit 1300 includes a four-phase signal generation unit 1310 and a DUTY ratio control unit 1320. The DUTY ratio control unit 1320 includes a clock adjustment circuit 1321 and a clock buffer 1322.

  In FIG. 33, the four-phase signal generation unit 1310 includes Rp1311 (1311-1 to 1311-4) that is a resistor and Cp1312 (1312-1 to 1312-4) that is a capacitor.

  34A to 34D are diagrams illustrating the operation of the clock generation circuit 1300.

  The differential signals IN_P and IN_N illustrated in FIG. 34A are input to the four-phase signal generation unit 1310 from the terminals T_IN_P and T_IN_N, respectively. Then, the four-phase signal generation unit 1310 converts the four-phase signals IN_P-45, IN_P + 45, IN_N-45, and IN_N + 45 that are 90 ° out of phase as illustrated in FIG. Output from T_IN_N + 45.

  That is, the four-phase signal generation unit 1310 is input by a combination of Rp1311 and Cp1312 at a frequency of ωp = 1 / (Rp × Cp) where Rp is the resistance value of Rp1311 and Cp is the capacitance value of Cp1312. The phase of the differential signal (IN_P, IN_N) is rotated by + 45 ° or −45 °.

  Specifically, the four-phase signal generation unit 1310 has an equal amplitude signal (IN_P−) obtained by rotating the phase of the input differential signal (IN_P) by −45 ° by the circuit configuration of Rp1311-1 and Cp1312-1. 45) is output. Further, the four-phase signal generation unit 1310 outputs a signal (IN_P + 45) having the same amplitude obtained by rotating the phase of the input differential signal (IN_P) by + 45 ° by the circuit configuration of Cp1312-2 and Rp1311-2.

  The four-phase signal generation unit 1310 outputs an equal amplitude signal (IN_N-45) obtained by rotating the phase of the input differential signal (IN_N) by −45 ° with the circuit configuration of Rp 1311-3 and Cp 1312-3. . The four-phase signal generation unit 1310 outputs a signal (IN_N + 45) having the same amplitude obtained by rotating the phase of the input differential signal (IN_N) by + 45 ° with the circuit configuration of Cp1312-4 and Rp1311-4. (Reference: Behzad Razavi, "RF Microelectronics," Prentice Hall, pp. 236-237, Nov. 1997)

  The four-phase signal generation unit 1310 can generate a signal having an equal amplitude that is rotated by 90 ° with respect to an arbitrary frequency by using at least one of Rp 1311 and Cp 1312 as a variable resistor and a variable capacitor.

  FIG. 35A shows an example of the configuration of the variable capacitor, and FIG. 35B shows an example of the configuration of the variable resistor. Switches controlled by N-bit control signals (B [0] and B [1] to B [N-1] in FIGS. 35A and 35B) are connected in series to the plurality of resistors and the plurality of capacitors, respectively. . In FIG. 35A, a plurality of capacitors are connected in parallel, but may be connected in series. In FIG. 35B, a plurality of resistors are connected in parallel, but may be connected in series. Note that the values of the plurality of resistors and the plurality of capacitors may be the same value or different values.

The four-phase output signals (IN_P-45, IN_P + 45, IN_N-45, IN_N + 45) of the four-phase signal generation unit 1310 are input to the clock adjustment circuit 1321. The clock adjustment circuit 1321 includes capacitors 1321-1 to 1321-4 and resistors 1321-5 to 1321-8, and is a DC of the input four-phase signals (IN_P-45, IN_P + 45, IN_N-45, IN_N + 45). The component is cut by the capacitors 1321-1 to 1321-4, and the bias potential V _DCCK is added to the four-phase signal via the resistors 1321-5 to _1321-8 . That is, the clock adjustment circuit 1321 outputs a four-phase signal in which the bias potential is adjusted to V _DCCK .

  An output signal of the clock adjustment circuit 1321 is input to the clock buffer 1322. The clock buffer includes a plurality of inverter circuits 1322-1 to 1322-8.

As shown in FIG. 34C, when the 4-phase signal input to the clock buffer 1322 exceeds a predetermined threshold voltage _{V TI,} a clock buffer 1322, respectively, and outputs a high signal. The four-phase signal input to the clock buffer 1322 is a four-phase signal whose bias potential has been adjusted by the clock adjustment circuit 1321. That is, the period of the high signal output from the clock buffer 1322 can be controlled by the bias potential V _DCCK supplied from the clock adjustment circuit 1321.

That is, the DUTY ratio control unit 1320 can control the DUTY ratio of the output signal of the clock buffer 1322 by adjusting the potential V _DCCK .

Therefore, the clock generation circuit 1300 sets the potential V _DCCK of the four-phase output signals (IN_P-45, IN_P + 45, IN_N-45, IN_N + 45) of the four-phase signal generation unit 1310, for example, as illustrated in FIG. 34D. A four-phase output signal (OUT1, OUT2, OUT3, OUT4) having a DUTY ratio of 25% can be output from the terminals T_OUT1, T_OUT2, T_OUT3, and T_OUT4.

  The terminals T_OUT1, T_OUT2, T_OUT3, and T_OUT4 from which the four-phase output signals OUT1 to OUT4 of the clock generation circuit 1300 are output are connected to a switching circuit (for example, a mixer) 1330, for example. The four-phase output signals OUT1 to OUT4 control the on / off of the switching circuit 1330. The switching circuit 1330 may use the configuration of the mixer 100 shown in FIG.

Note that the clock generation circuit 1300 can output a four-phase signal having an arbitrary DUTY ratio by setting the potential V _DCCK .

  In FIG. 33, the clock buffer 1322 has a configuration in which the inverter circuits 1322-1 to 132-8 are connected in two stages. However, the clock buffer 1322 may have any number of stages or may be branched in the middle. Note that the configuration illustrated in FIG. 35C may be used as an example of the configuration of the inverter circuit.

  When the frequency of the signal input to the clock buffer 1322 (that is, the output signal of the clock adjustment circuit 1321) is a frequency that is difficult to use for the inverter circuits 1322-1 to 1322-8, the output signal of the clock adjustment circuit 1321 is In order not to be input to the clock buffer 1322, the clock buffer 1322 may be passed through a switch (not shown) and directly connected to the output side terminals T_OUT <b> 1 to T_OUT <b> 4. Thus, the clock buffer 1322 can generate a signal having an arbitrary DUTY ratio with a simple configuration at a frequency where the inverter circuits 1322-1 to 1322-8 can be used.

  Note that the output waveform of each inverter circuit used in the present embodiment may be dull, or by adding a variable capacitor to the output terminal of each inverter circuit as shown in FIGS. As shown in Fig. 5, the waveform dullness may be intentionally adjusted.

As described above, the conventional clock generation circuit shown in FIG. 1B has a configuration in which three or more transistors are vertically stacked using an AND circuit. However, in the clock generation circuit of this embodiment, two transistors are vertically stacked. (For example, a vertical stack of PMOS and NMOS in FIG. 35C), which can operate at a low power supply voltage, and is suitable for mounting in a fine CMOS process. Further, although it is difficult to finely adjust the DUTY ratio in the conventional clock generation circuit shown in FIG. 1B, the clock generation circuit 1300 of this embodiment can finely adjust the DUTY ratio by adjusting the potential V _DCCK .

  Various aspects of the embodiments according to the present disclosure include the following.

  A switch control circuit according to a first disclosure includes: a clock generation circuit that generates one or more periodic signals having a predetermined period; a bias voltage of the periodic signal; and an on period of the one or more periodic signals And the clock adjustment circuit that generates one or more control signals, and the amplitude of the one or more control signals is switched on when the amplitude is greater than or equal to a threshold, and the amplitude of the one or more control signals is less than the threshold And a switching circuit having one or more switches that are switched off.

  A switch control circuit according to a second disclosure is the switch control circuit according to the first disclosure, wherein the clock adjustment circuit has a variable capacitor, and the clock adjustment circuit corresponds to a capacitance value of the variable capacitor. The waveform of the periodic signal is changed to change the ON period of the one or more periodic signals.

  A switch control circuit according to a third disclosure is the switch control circuit according to the first disclosure, wherein the clock adjustment circuit includes an input terminal to which each periodic signal is input and an output terminal to which the control signal is output. And a variable capacitor having one end connected between the two buffers and the other end grounded, and the clock adjusting circuit adjusts the variable capacitor. To adjust the phase of the periodic signal.

  A switch control circuit according to a fourth disclosure is the switch control circuit according to the first disclosure, wherein the clock generation circuit generates a plurality of periodic signals, and the clock adjustment circuit includes each of the plurality of periodic signals. Each of the plurality of systems, and a variable capacitor connected to each of the plurality of systems, and by adjusting the bias voltage and the variable capacitor of the plurality of periodic signals, the bias voltage and the phase of each of the plurality of periodic signals Adjust.

  A switch control circuit according to a fifth disclosure is the switch control circuit according to the first disclosure, wherein the switching circuit includes four switches to which four-phase control signals are respectively supplied, and the clock generation circuit Generates a four-phase periodic signal, and the clock adjustment circuit adjusts the bias voltage and phase of the periodic signal, so that the time for which the four switches are turned on becomes a quarter of the predetermined period. The four control signals are generated with different times when the four switches are turned on.

  A switch control circuit according to a sixth disclosure is the switch control circuit according to the first disclosure, wherein the switching circuit has one input terminal and two output terminals, and one of the two output terminals and M first switches connected in parallel to the input terminal and supplied with M (M is 2 or more) first control signals, respectively, the other of the two output terminals, and the input terminal And M second switches to which M second control signals are respectively supplied, and the clock generation circuit generates a 2M-phase periodic signal, and the clock adjustment The circuit adjusts the bias voltage and the phase of the 2M-phase periodic signal so that the M first switches and the M second switches are turned on by 1 / M of the predetermined period. , The M first switches H and the M second switches are turned on at different times, and the interval between the time when one of the first switches is turned on and the time when one of the second switches is turned on is the predetermined period. The M first control signals and the M second control signals, which are ½ of the above, are generated.

  A switch control circuit according to a seventh disclosure is the switch control circuit according to the first disclosure, wherein the switching circuit is input to a positive-phase first signal input to a first input terminal and to a second input terminal. A discrete-time analog circuit that performs discrete-time analog signal processing on the second signal having the opposite phase, outputs a first output signal to a first output terminal, and outputs a second output signal to a second output terminal. The first signal is input to the first terminal connected to the first input terminal, and the first input charge obtained by converting the first signal from voltage to current is connected to the first output terminal. The second signal is input to the third terminal connected to the second input terminal, and the second input charge obtained by converting the second signal from voltage to current is connected to the second output terminal. A voltage-current conversion circuit that outputs to the fourth terminal, and a fifth terminal And the sixth terminal, the fifth terminal is connected to the first output terminal, the sixth terminal is connected to the second output terminal, and the charge of the first input charge and the second input charge A charge inverting circuit that performs sharing, and the charge inverting circuits include 2M charge inverting capacitors that are provided in parallel with each other and hold the first input charge or the second input charge by charge sharing. (M is an integer greater than or equal to 1) The 2M charge reversal capacitors are the first ones of the 2M charge reversal capacitors that are sequentially held in the 2M charge reversal capacitors at predetermined intervals. The polarity of the input charge or the second input charge is inverted and connected to the fifth terminal and the sixth terminal, and a capacitor other than the one charge inversion capacitor connects the fifth terminal and the sixth terminal. Open.

  A switch control circuit according to an eighth disclosure is the switch control circuit according to the seventh disclosure, wherein the 2M charge inversion capacitors have a seventh terminal and an eighth terminal, and the eighth terminal is grounded. And a second charge reversal capacitor having a ninth terminal and a tenth terminal and grounding the tenth terminal, wherein the charge reversal circuit includes the first charge reversal capacitor at a first timing. The charge reversal capacitor connects the seventh terminal to the fifth terminal for charge sharing, and the second charge reversal capacitor opens the connection between the fifth terminal and the sixth terminal to hold the charge. In the second timing, the second charge reversing capacitor performs charge sharing by connecting the ninth terminal to the fifth terminal, and the first charge reversing capacitor includes the fifth terminal and the sixth terminal. To hold the charge and open the second ( In the (M + 1) timing, the first charge reversal capacitor connects the seventh terminal to the sixth terminal to perform charge sharing, and the second charge reversal capacitor is connected to the fifth terminal and the sixth terminal. At the (2M + 2) timing, the second charge inversion capacitor performs charge sharing by connecting the ninth terminal to the sixth terminal, and the first charge inversion capacitor is Then, the connection between the fifth terminal and the sixth terminal is released to perform charge retention.

A switch control circuit according to a ninth disclosure is the switch control circuit according to the seventh disclosure,
The switching circuit includes a plurality of the charge inverting circuits, the fifth terminals of the plurality of charge inverting circuits are connected to the first output terminal, and the plurality of charge inverting circuits are connected to the second output terminal. The sixth terminal is connected.

  A switch control circuit according to a tenth disclosure is the switch control circuit according to the seventh disclosure, and includes a multistage switching circuit in which at least two of the switching circuits are connected in series.

  A switch control circuit according to an eleventh disclosure is the switch control circuit according to the sixth disclosure, wherein the switching circuit includes a history capacitor connected to each of the two output terminals, and a switched capacitor filter. .

  A switch control circuit according to a twelfth disclosure is the switch control circuit according to the first disclosure, and controls a characteristic monitor circuit that monitors an output characteristic of the switching circuit, the clock generation circuit, and the clock adjustment circuit. And a characteristic control circuit for adjusting the bias voltage and phase magnitude of the periodic signal in the clock adjustment circuit so that the characteristic becomes a desired characteristic.

  A switch control circuit according to a thirteenth disclosure is the switch control circuit according to the first disclosure, wherein at least one inverter circuit is provided between an output of each clock adjustment circuit and an input of a switch of the switching circuit. Also have.

  While various embodiments have been described above with reference to the drawings, it goes without saying that the present disclosure is not limited to such examples. It will be apparent to those skilled in the art that various changes and modifications can be made within the scope of the claims, and these are naturally within the technical scope of the present disclosure. Understood. In addition, each component in the above embodiment may be arbitrarily combined within a scope that does not depart from the spirit of the disclosure.

  In each of the above embodiments, the present disclosure has been described for an example configured using hardware. However, the present disclosure can also be realized by software in cooperation with hardware.

  In addition, each functional block used in the description of each of the above embodiments is typically realized as an LSI that is an integrated circuit. These may be individually made into one chip, or may be made into one chip so as to include a part or all of them. The name used here is LSI, but it may also be called IC, system LSI, super LSI, or ultra LSI depending on the degree of integration.

  Further, the method of circuit integration is not limited to LSI's, and implementation using dedicated circuitry or general purpose processors is also possible. An FPGA (Field Programmable Gate Array) that can be programmed after manufacturing the LSI and a reconfigurable processor that can reconfigure the connection or setting of circuit cells inside the LSI may be used.

  Furthermore, if integrated circuit technology comes out to replace LSI's as a result of the advancement of semiconductor technology or a derivative other technology, it is naturally also possible to integrate function blocks using this technology. Biotechnology can be applied.

  The switch control circuit according to the present disclosure is useful for high-frequency signal and baseband signal processing circuits in radio communication apparatuses and radar apparatuses, and is useful for filter processing or frequency conversion processing.

10, 40 Transmitting device 11, 41 Digital transmission processing unit 12, 42 D / A conversion processing unit 13, 23, 33, 43, 53 Reference frequency oscillating unit 14, 24, 44, 54 LO frequency oscillating unit 15, 26, 45 56 Analog baseband circuit 16, 46 Transmission mixer 17, 47 Power amplifier 18, 21, 31, 48, 51 Antenna 20, 30, 50 Receiving device 22, 32, 52 Low noise amplifier 25, 55 Receiving mixer 27, 35 57 A / D conversion processing unit 28, 36, 58 Digital reception processing unit 34, 600, 700, 810, 900, 1000 Discrete time analog circuit 60, 1130 Characteristic control circuit 61, 1120 Characteristic monitoring circuit 100, 200, 1330 Mixer 110 110-1 to 110-4, 220-1 to 220-8, 310-1, 310- , 410-1 to 410-4, 510-1 to 510-2M, 632-1 to 632-8, 732-1 to 732-4M switch 120, 230, 640, 740, 820, 950, 1050, 1140, 1300 Clock generation circuit 120A to 120C I / O system 121-1 to 121-4 D-type flip-flop circuit 122-1, 122-2, 133, 133-1 to 133-4, 243-1 to 243-4, 1230, 1311 , 1321-5 to 1321-8 resistors 123-1, 123-2, 132, 132-1 to 132-3, 242-1 to 242-24-1, 245-4, 620-1, 620-2, 631 -1, 631-2, 720-1, 720-2, 731-1 to 731- (2M), 812, 1240, 1312, 1321-1 to 1321 4 capacitance 124 90-degree phase difference signal generation circuit 125-1, 125-2 variable gain amplifier 126 synthesis circuit 127-1 to 127-12 CMOS inverter 130, 240, 650, 750, 830, 960, 1060, 1150, 1321 clock Adjustment circuit 131, 241-1 to 241-4, 246-1 to 246-4, 1210 buffer 134, 244-1 to 244-4, 247-1 to 247-4, 1220 variable capacitance 210, 610, 710, 811 910 TA
630, 630A, 630B, 630C, 730A, 730C Charge inversion circuit 730 Charge circuit 730B, 730D Charge holding connection circuit 800 Multistage discrete time analog circuit 920 Local switch 930 History capacitor 940 PSCF
941 Charge Sharing Switch 942 Rotation Capacitor 943 Reset Switch 944 Feedback Switch 945 Dump Switch 946 Buffer Capacitor 1020 Local Switch Unit 1100, 1200 Mixer or Discrete Time Analog Circuit with Characteristic Control Function 1110 Mixer or Discrete Time Analog Circuit 1160 Target Circuit 1310 Four Phase Signal Generation unit 1320 DUTY ratio control unit 1322 clock buffer 1322-1 to 1322-8 inverter circuit

Claims (13)

A clock generation circuit for generating one or more periodic signals having a predetermined period;
A clock adjusting circuit that adjusts a bias voltage of the periodic signal and generates one or more control signals by changing an on period of the one or more periodic signals;
A switching circuit having one or more switches that switch on when the amplitude of the one or more control signals is above a threshold and switch off when the amplitude of the one or more control signals is below a threshold;
Having
Switch control circuit. The clock adjustment circuit has a variable capacitor,
The clock adjustment circuit changes a waveform of the periodic signal according to a capacitance value of the variable capacitor, and changes an ON period of the one or more periodic signals;
The switch control circuit according to claim 1. The clock adjustment circuit includes:
Two buffers provided between an input terminal to which each periodic signal is input and an output terminal to which the control signal is output;
A variable capacitor having one end connected between the two buffers and the other end grounded;
Have
The clock adjustment circuit adjusts the phase of the periodic signal by adjusting the variable capacitor;
The switch control circuit according to claim 1. The clock generation circuit generates a plurality of periodic signals,
The clock adjustment circuit includes:
A plurality of systems receiving each of the plurality of periodic signals;
Having a variable capacity connected to each of the plurality of systems;
Adjusting the bias voltage and phase of each of the plurality of periodic signals by adjusting the bias voltage and the variable capacitance of the plurality of periodic signals;
The switch control circuit according to claim 1. The switching circuit has four switches to which four-phase control signals are supplied,
The clock generation circuit generates a four-phase periodic signal,
The clock adjusting circuit adjusts the bias voltage and the phase of the periodic signal, so that the time for which the four switches are turned on becomes a quarter of the predetermined period, and the time for which the four switches are turned on. Generate the four control signals different from each other,
The switch control circuit according to claim 1. The switching circuit has one input terminal and two output terminals,
M first switches connected in parallel between one of the two output terminals and the input terminal and supplied with M (M is 2 or more) first control signals, respectively.
M second switches connected in parallel between the other of the two output terminals and the input terminal and supplied with M second control signals, respectively.
Have
The clock generation circuit generates a 2M phase periodic signal,
The clock adjustment circuit adjusts a bias voltage and a phase of the 2M-phase periodic signal to thereby turn on the M first switches and the M second switches by 2M of the predetermined period. The time when the M first switches and the M second switches are turned on is different from each other, and the time when one of the first switches is turned on and one of the second switches is turned on. The M first control signals and the M second control signals are generated at an interval with respect to the time to be half of the predetermined period,
The switch control circuit according to claim 1. The switching circuit is
Discrete time analog signal processing is performed on the positive-phase first signal input to the first input terminal and the negative-phase second signal input to the second input terminal, and the first output signal is output to the first output terminal. A discrete time analog circuit that outputs a second output signal to a second output terminal,
The first terminal is connected to the first input terminal, and the first input charge obtained by converting the first signal from voltage to current is connected to the first output terminal. Output to
The second signal is input to a third terminal connected to the second input terminal, and a second input charge obtained by converting the second signal from voltage to current is connected to the second output terminal. A voltage-current conversion circuit that outputs to
A fifth terminal and a sixth terminal; the fifth terminal is connected to the first output terminal; the sixth terminal is connected to the second output terminal; and the first input charge and the second input A charge inversion circuit that performs charge sharing of charges,
The charge inverting circuit
2M charge inversion capacitors provided in parallel with each other and holding the first input charge or the second input charge by charge sharing (M is an integer of 1 or more);
The 2M charge reversal capacitors are arranged such that one charge reversal capacitor among the 2M charge reversal capacitances sequentially holds the polarity of the first input charge or the second input charge held at a predetermined interval. Is connected to the fifth terminal and the sixth terminal, and a capacitor other than the one charge inversion capacitor opens the connection between the fifth terminal and the sixth terminal.
The switch control circuit according to claim 1. The 2M charge reversal capacitors are
A first charge reversal capacitor having a seventh terminal and an eighth terminal and grounding the eighth terminal;
A second charge reversal capacitor having a ninth terminal and a tenth terminal, and grounding the tenth terminal,
The charge inverting circuit
In the first timing,
The first charge reversal capacitor connects the seventh terminal to the fifth terminal for charge sharing,
The second charge reversal capacitor opens the connection between the fifth terminal and the sixth terminal to hold charge;
In the second timing,
The second charge reversal capacitor connects the ninth terminal to the fifth terminal to perform charge sharing;
The first charge reversal capacitor performs charge holding by opening a connection between the fifth terminal and the sixth terminal,
At the (2M + 1) th timing,
The first charge reversal capacitor connects the seventh terminal to the sixth terminal to perform charge sharing,
The second charge reversal capacitor opens the connection between the fifth terminal and the sixth terminal to hold charge;
At the (2M + 2) timing,
The second charge reversal capacitor performs charge sharing by connecting the ninth terminal to the sixth terminal,
The first charge reversal capacitor holds the charge by releasing the connection between the fifth terminal and the sixth terminal;
The switch control circuit according to claim 7. The switching circuit is
A plurality of the charge inverting circuits;
The fifth terminal of the plurality of charge inverting circuits is connected to the first output terminal;
The sixth terminals of the plurality of charge inverting circuits are connected to the second output terminal.
The switch control circuit according to claim 7. A multistage switching circuit in which at least two of the switching circuits are connected in series;
The switch control circuit according to claim 7. The switching circuit is
A history capacitor connected to each of the two output terminals;
A switched capacitor filter;
Having
The switch control circuit according to claim 6. A characteristic monitor circuit for monitoring the output characteristics of the switching circuit;
A characteristic control circuit for controlling the clock generation circuit and the clock adjustment circuit;
Further comprising
The characteristic control circuit adjusts a bias voltage and a phase magnitude of the periodic signal in the clock adjustment circuit so that the characteristic becomes a desired characteristic;
The switch control circuit according to claim 1. At least one inverter circuit is further provided between the output of each clock adjustment circuit and the input of the switch of the switching circuit.
The switch control circuit according to claim 1.

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