JP5182105B2 - Signal processing device - Google Patents

Description

 The present invention relates to a signal processing apparatus that converts an externally input analog signal into a digital signal and performs predetermined signal processing.

  Conventionally, as a form of a signal processing device, in a process control of a chemical plant or the like, a process is performed by receiving analog signals transmitted from various field devices, converting the analog signals into digital signals, and performing predetermined signal processing. Analog input modules that analyze values (temperature, pressure, flow rate, etc.) are known. In general, this analog input module includes a multi-channel AFE (analog front end) that converts an analog signal input through a plurality of analog input terminals into a digital signal, and an insulating element (eg, a digital photocoupler). And an arithmetic unit (digital back end) that analyzes a process value by performing predetermined signal processing based on a digital signal input from the AFE.

  In order to communicate control information between such an analog input module and a field device, a hybrid signal to which a digital signal is added in a frequency band different from the above analog signal may be used. In this case, the frequency component of the hybrid signal (for example, 950 to 2500 Hz) and the frequency component of the commercial power supply (50 or 60 Hz) are superimposed on the analog signal output from the field device as noise. It is necessary to remove frequency components.

  FIG. 10 is a first configuration example of a conventional analog input module. As shown in FIG. 10, the analog input module 100 in the first configuration example includes a multi-channel AFE 110 having n channels CH1 to CHn and an arithmetic unit 120. Since the internal configuration of each channel in the AFE 110 is the same, the following description will be made using the channel CH1 as a representative.

  In the channel CH 1, the analog signal input to the analog input terminal 111 is input to the A / D converter 113 via an analog LPF (Low Pass Filter) 112. The analog LPF 112 removes (strictly attenuates) the frequency component of the hybrid signal superimposed on the analog signal. The A / D converter 113 converts an analog signal into a digital signal and outputs the digital signal to the arithmetic unit 120 via the insulating element 114. The arithmetic unit 120 analyzes the input voltage value or current value (that is, the process value) of the channel CH1 by performing predetermined signal processing based on the digital signal. In addition, the arithmetic unit 120 sends a control signal to the A / D converter 113 via the insulating element 115 and controls the A / D converter 113 at a specified period, so that the frequency of the commercial power to be superimposed on the analog signal. Ingredients are removed.

 FIG. 11 is a second configuration example of a conventional analog input module. As shown in FIG. 11, the analog input module 200 in the second configuration example includes a multi-channel AFE 210 having n channels CH1 to CHn and a calculator 220. In the AFE 210, since the internal configuration of each channel is the same, the following description will be made using the channel CH1 as a representative.

  In the channel CH 1, an analog signal input to the analog input terminal 211 is input to a ΔΣ (delta sigma) modulator 213 through an analog LPF (Low Pass Filter) 212. The ΔΣ modulator 213 converts the analog signal into a 1-bit signal by performing ΔΣ modulation, and outputs the 1-bit signal to the logic circuit 214. The logic circuit 214 includes a moving average filter 214a that performs moving averaging (decimation) of the 1-bit signal input from the ΔΣ modulator 213, and a specific frequency component (hybrid signal and commercial power supply) of the output digital signal of the moving average filter 214a. A specific frequency removal filter 214b that removes the frequency component), and a serial communication device 214c that serializes the output digital signal of the specific frequency removal filter 214b and outputs the digital signal to the arithmetic unit 220 via the insulating element 215. The computing unit 220 analyzes the process value of the channel CH1 by performing predetermined signal processing based on the digital signal. Note that the logic circuit 214 and the arithmetic unit 220 of the AFE 210 operate asynchronously.

JP 2003-163596 A

  In the configuration of the analog input module 100 described above, it is necessary to send a control signal from the computing unit 120 to the A / D converter 113 in order to remove the frequency component of the commercial power supply, and the number of insulating elements per channel increases. Since the analog LPF 112 removes the frequency component of the hybrid signal, there is a problem that high-accuracy noise removal cannot be realized. On the other hand, in the configuration of the analog input module 200, the number of insulating elements per channel can be reduced to one, and the specific frequency elimination filter 214b that is a digital filter is used. realizable.

However, the configuration of the analog input module 200 also has the following problems.
(1) In order to realize the specific frequency removal filter 214b capable of removing the frequency components of both the hybrid signal and the commercial power supply, a high-order digital filter that is complicated in calculation is required, and the circuit scale becomes extremely large. Since such a digital filter having a large circuit scale is provided for each channel, the cost increases.
(2) Since the logic circuit 214 and the arithmetic unit 220 of the AFE 210 operate asynchronously, the digital signal communication cycle is shortened, high performance is required for communication, and an expensive insulating element with good switching characteristics (high switching speed). Is required. In the example of FIG. 11, it is necessary to transmit a 16.2 bit digital signal at a communication cycle of 119 (μs).

  The present invention has been made in view of the above-described circumstances, and in the case of adopting a configuration including a plurality of input units corresponding to a plurality of input analog signals, the cost is required to remove a specific frequency component using a filter. It is an object of the present invention to provide a signal processing device that can be reduced.

In order to solve the above problems, the signal processing apparatus of the present invention converts the input analog signal into a digital signal by a plurality of input units corresponding to the plurality of input analog signals, and delivers the digital signal to the arithmetic unit. In the signal processing apparatus that performs predetermined signal processing, each of the plurality of input units includes a digital filter that attenuates a specific frequency component by a predetermined amount, and the arithmetic unit is sent from each of the plurality of input units. A single digital filter having a function of attenuating a specific frequency component of a digital signal by a predetermined amount in a time division manner is provided .

In the signal processing device of the present invention, the order of the digital filter provided in each of the plurality of input units is set lower than the order of a single digital filter provided in the arithmetic unit. And

In the signal processing device of the present invention, each of the plurality of input units includes an analog input terminal, an analog low-pass filter for attenuating a high-frequency component of the analog signal input through the analog input terminal, From the delta-sigma modulator that converts the analog signal output from the analog low-pass filter into a bit-compressed signal by performing delta-sigma modulation, a moving average filter that functions as a decimation filter for the bit-compressed signal, and the moving average filter A digital filter having a function of attenuating a specific frequency component of an output digital signal and a function of a thinning filter, and a digital signal output from the digital filter are converted into serial data and output to the arithmetic unit via an insulating element A serial communication device is provided. And wherein the door.

Moreover, in the signal processing device of the present invention, the specific frequency component is a frequency component of a hybrid signal and a commercial power supply that are superimposed on the input analog signal, and a digital filter provided in each of the plurality of input units includes: The frequency component of the hybrid signal is configured to attenuate, and the single digital filter provided in the arithmetic unit is configured to attenuate the frequency component of the hybrid signal and the commercial power source. It is characterized by.

According to the present invention, each of the plurality of input units in the signal processing device includes a digital filter that attenuates the specific frequency component by a predetermined amount, and the arithmetic unit in the signal processing device is sent from each of the plurality of input units. Since a single digital filter having a function of attenuating a specific frequency component of a digital signal by a predetermined amount in a time division manner is provided, the circuit scale of the digital filter provided in each of a plurality of input units can be reduced. As a result, it is possible to realize a signal processing device capable of reducing cost when removing a specific frequency component using a filter.

1 is a configuration block diagram of an analog input module (signal processing device) 1 according to an embodiment of the present invention. FIG. 6 is a frequency characteristic diagram of an analog LPF 22 _C1 in the analog input module 1. 6 is a frequency characteristic diagram of a high frequency filter and thinning filter 24b in the analog input module 1. FIG. 6 is a frequency characteristic diagram of a specific frequency removal filter 32 in the analog input module 1. FIG. 6 is a frequency characteristic diagram obtained by adding the frequency characteristics of the analog LPF 22 _C1 , the high frequency filter / thinning filter 24 b and the specific frequency removal filter 32 in the analog input module 1. FIG. 6 is an enlarged view of a range of 45 to 65 Hz on the frequency axis in FIG. 6 is an enlarged view of a range of 950 to 2500 Hz on the frequency axis in FIG. It is the 1st explanatory view about the modification of this embodiment. It is the 2nd explanatory view about the modification of this embodiment. 1 is a first configuration example of a conventional analog input module 100. 2 is a second configuration example of a conventional analog input module 200. FIG.

 Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following, as a signal processing apparatus according to the present invention, an analog signal used in a chemical plant or the like and transmitted from various field devices is input, and the analog signal is converted into a digital signal to perform predetermined signal processing. An analog input module to be performed will be described as an example.

 FIG. 1 is a configuration block diagram of an analog input module 1 of the present embodiment. As shown in FIG. 1, an analog input module 1 of this embodiment includes a multi-channel analog front end (hereinafter abbreviated as AFE) 2 having n channels CH1 to CHn (input units), and a digital back end. It comprises a functional computing unit 3 (calculation unit).

In AFE2, the internal configurations of the channels CH1 to CHn are the same. That is, the channel CH1 is provided with an analog input terminal 21 _C1 , an analog LPF (Low Pass Filter) 22 _C1 , a ΔΣ (delta sigma) modulator 23 _C1 , a logic circuit 24 _C1, and an insulating element 25 _C1 . The channel CH2 is provided with an analog input terminal 21 _C2 , an analog LPF 22 _C2 , a ΔΣ modulator 23 _C2 , a logic circuit 24 _C2, and an insulating element 25 _C2 . Similarly, the channel CHn is provided with an analog input terminal 21 _Cn , an analog LPF 22 _Cn , a ΔΣ modulator 23 _Cn , a logic circuit 24 _Cn, and an insulating element 25 _Cn . Thus, in AFE2, since the internal configuration of each channel is the same, description will be given below using channel CH1 as a representative.

The analog input terminal 21 _C1 is an external input terminal for receiving an analog signal transmitted from a field device installed in a chemical plant or the like. In the following description, it is assumed that the frequency component (for example, 950 to 2500 Hz) of the hybrid signal and the frequency component (50 or 60 Hz) of the commercial power supply are superimposed on the analog signal as noise.

The analog LPF 22 _C1 is a filter for attenuating a high frequency component of an analog signal input via the analog input terminal 21 _C1 . FIG. 2 shows the frequency characteristics (gain with respect to input frequency) of the analog LPF 22 _C1 . FIG. 2 is a frequency characteristic diagram when the analog LPF 22 _C1 is configured by an RC circuit of R = 47 kΩ and C = 47 nF. In other words, the cutoff frequency fc of the analog LPF 22 _C1 is fc = 1 / (2π · R · C) ≈72 Hz.

The ΔΣ modulator 23 _C1 performs ΔΣ modulation on the analog signal output from the analog LPF 22 _C1, thereby converting the analog signal into a 1-bit signal and outputting the 1-bit signal to the logic circuit 24 _C1 . Here, ΔΣ modulation is a technique for generating a pulse train having a density proportional to the amplitude of an input analog signal, although detailed description thereof is omitted because it is a known technique. That is, when the amplitude of the input analog signal is small, the frequency of occurrence of the pulse is small and the data string has a large number of “0”. Conversely, when the amplitude is large, the frequency of the pulse is high and the data string has a large number of “1”. In the present embodiment, it is assumed that the sampling frequency fs is 1.2 kHz, and the ΔΣ modulator 23 _C1 performs oversampling that is 833 times the sampling frequency fs. That is, the frequency of the 1-bit signal output from the ΔΣ modulator 23 _C1 is about 1 MHz, and the bit rate is 1 bit / 1 μs.

The logic circuit 24 _C1 includes a moving average filter 24 a, a high frequency filter / decimation filter 24 b, and a serial communication device 24 c. Moving average filter 24a functions as a decimation filter 1-bit signal of a high bit rate output from the ΔΣ modulator 23 _C1 (bit compressed signal). That is, the moving average filter 24a, by performing the moving average of the 1-bit signal outputted from the ΔΣ modulator 23 _C1, it converts the 1-bit signal to a digital signal of low bit rate. In this embodiment, assuming that the number of tap stages of the moving average filter 24a is 119 (synonymous with the thinning-out rate 119), a 1-bit signal with a bit rate = 1 bit / 1 μs is converted to a digital signal with 6.2 bits / 119 μs. To do.

 The high frequency filter / decimation filter 24b functions as a filter that attenuates a specific frequency component (frequency component of the hybrid signal) of the digital signal output from the moving average filter 24a, and a decimation filter that converts the digital signal into a lower bit rate digital signal. It has the function as. In the present embodiment, the high-frequency filter / decimation filter 24b is configured by an FIR filter of order 13 and a thinning rate of 7. That is, the digital signal of bit rate = 6.2 bits / 119 μs is converted into a digital signal of 10.6 bits / 833 μs by the high frequency filter / decimation filter 24 b (thinning is performed so as to return to the sampling frequency fs at this point). FIG. 3 shows the frequency characteristics of the high frequency filter and thinning filter 24b. As shown in FIG. 3, it can be seen that the frequency components at 950 Hz and 2500 Hz are greatly attenuated, and the frequency components between them are also attenuated by 20 dB or more.

Serial communication unit 24c outputs a digital signal of low bit rate output from the high-frequency filter and decimation filter 24b (10.6bit / 833μs), the serial data of to insulating element _{25 C1.} That is, the communication cycle of the serial communication device 24c is 833 μs, which is the same as the sampling cycle (1 / fs). The insulating element 25 _C1 is, for example, a digital photocoupler. The digital signal input from the serial communication device 24 c is once converted into an optical signal, and then converted back into a digital signal to be converted into a digital signal. Serial communication device 31 _C1 ). The insulating element 25 _C1 electrically insulates the computing unit 3 on the system side from the AFE 2 on the front side (field side).

The arithmetic unit 3 analyzes a process value (temperature, pressure, flow rate, etc.) detected by the field device by performing predetermined signal processing based on the digital signal input from the AFE 2, and each channel CH1. To n serial communication devices 31 _{C1 to} 31 _Cn provided corresponding to CHn and a specific frequency elimination filter 32.

Serial communication device _{31 C1} via the insulating element _{25 C1} channel CH1 AFE 2 (specifically a serial communication unit 24c of the logic circuit _{24 C1)} receiving a digital signal transmitted from the (serial data), the digital signal The data is converted into parallel data and output to the specific frequency removal filter 32. The serial communication unit 31 _C2 outputs a digital signal received via an insulating element 25 _C2 of channel CH2 to a particular frequency rejection filter 32 and the parallel data of. Hereinafter, similarly, the serial communication device 31 _Cn converts the digital signal received via the insulating element 25 _Cn of the channel CHn into parallel data, and outputs the parallel data to the specific frequency removal filter 32.

The specific frequency removal filter 32 is used to perform time-division processing for attenuating a specific frequency component (hybrid signal and frequency component of a commercial power supply) of a digital signal of each channel input from each serial communication device 31 _{C1 to} 31 _Cn . It is a digital filter. In the present embodiment, the specific frequency removal filter 32 is configured by an FIR filter of order 49 that operates at a sampling frequency fs = 1.2 kHz. FIG. 4 shows the frequency characteristics of the specific frequency removal filter 32. As shown in FIG. 4, the specific frequency removal filter 32 has such characteristics that the frequency component between 950 and 2500 Hz that is not sufficiently attenuated by the high-frequency filter and thinning filter 24b is further attenuated. Further, the specific frequency removal filter 32 has such a characteristic that a notch is generated at 50 Hz and 60 Hz which are frequency components of the commercial power supply (see FIG. 6 described later).

 Such a specific frequency elimination filter 32 may be configured by a logic circuit, that is, hardware, or may be configured by software. When the specific frequency removal filter 32 is configured by hardware, a delay circuit or the like may be provided at the input stage of each digital signal in order to perform filtering of the digital signal of each channel in a time division manner. In the case of being configured by software, a specific frequency elimination filter 32 is configured by a memory in which the software is stored and a CPU (Central Processing Unit) that reads the software from the memory and executes a filtering process. By processing, the digital signal filtering processing of each channel may be performed in a time division manner.

 The digital signal (bit rate: 16.2 bits / 833 μs) of each channel from which the specific frequency component has been removed by the specific frequency removal filter 32 is output to a signal processing unit (not shown) to analyze the process value. Is called. When the specific frequency removal filter 32 is configured by software, the filtering process and the process value analysis process may be performed by the same CPU.

Next, the operation of the analog input module 1 of the present embodiment configured as described above will be described.
First, the AFE 2, the analog signal inputted through the analog input terminal _{21 C1} of the channel CH1 after the high frequency components are attenuated by the analog LPF 22 _C1 having a frequency characteristic as shown in FIG. 2, .DELTA..SIGMA modulator _{23 C1} Is output. The ΔΣ modulator 23 _C1 converts the input analog signal into a 1-bit signal having a high bit rate of 1 bit / 1 μs.

  This 1-bit signal is converted into a low bit rate digital signal (6.2 bits / 119 μs) by the moving average filter 24a functioning as a decimation filter, and further, a high frequency filter / decimation having frequency characteristics as shown in FIG. The filter 24b attenuates the frequency component of the hybrid signal and converts it to a lower bit rate digital signal (10.6 bits / 833 μs: the same frequency as the sampling frequency).

Then, by the high frequency filter and decimation filter 24b, a digital signal whose frequency component is attenuated hybrid signal is a serial data by the serial communication device 24c, the serial communication unit 31 _C1 of the arithmetic unit 3 through the insulating element 25 _C1 It is transmitted (communication period is 833 μs). By performing the operation as described above for each channel of the AFE 2, the analog signals input to the channels CH1 to CHn are converted into digital signals and transmitted to the computing unit 3, respectively.

The digital signals of these channels CH1 to CHn are input to the specific frequency elimination filter 32 having the frequency characteristics shown in FIG. 4 via the serial communication devices 31 _{C1 to} 31 _Cn on the arithmetic unit 3 side. And this specific frequency removal filter 32 performs the process which attenuates the frequency component of the hybrid signal and commercial power supply of the digital signal of each channel CH1-CHn by a time division. In other words, by utilizing the long digital signal communication cycle of each channel CH1 to CHn (833 μs), the filtering process of each digital signal is performed in a time-sharing manner, so that one specific frequency removal filter 32 is placed between the channels. They can be shared (one digital filter may be prepared on the arithmetic unit 3 side).

FIG. 5 is a frequency characteristic diagram obtained by adding the frequency characteristic of the analog LPF 22 _C1, the frequency characteristic of the high frequency filter and thinning filter 24b, and the frequency characteristic of the specific frequency removal filter 32. FIG. 6 is an enlarged view of the range of 45 to 65 Hz on the frequency axis of FIG. FIG. 7 is an enlarged view of the range of 950 to 2500 Hz on the frequency axis of FIG.

  As shown in FIGS. 5 to 7, the entire analog input module 1 of the present embodiment achieves 100 dB attenuation with respect to the frequency components 50 Hz and 60 Hz of the commercial power supply, and the frequency of the hybrid signal. It can be seen that attenuation of 100 dB is achieved even with respect to the component 950 to 2500 Hz, and the noise removal performance is sufficient.

  As described above, according to the analog input module 1 of the present embodiment, the function of the digital filter for removing the specific frequency component superimposed as noise on the input analog signal is shared between the AFE 2 side and the computing unit 3 side. By doing so, one large-scale digital filter (specific frequency elimination filter 32) having a high order is prepared on the computing unit 3 side, and a small digital filter (high frequency) having a low order is provided for each channel on the AFE 2 side. Since it is sufficient to prepare the filter / thinning filter 24b), the cost can be greatly reduced.

The AFE2 side digital filter (high frequency filter / decimation filter 24b) not only attenuates the specific frequency component of the digital signal (frequency component of the hybrid signal), but also performs sampling to reduce the amount of data, thereby reducing the sampling frequency fs. By converting the digital signal to a low bit rate digital signal having the same frequency as that, the communication cycle of the digital signal from the AFE 2 to the computing unit 3 can be lengthened, so that an expensive insulating element having a high switching speed is not required, Inexpensive insulating elements can be used. Furthermore, since the circuit scales of the logic circuits 24 _{C1 to} 24 _Cn on the AFE2 side are small and have a low speed, it is possible to use a clock having a lower frequency than in the conventional case.

In addition, this invention is not limited to the said embodiment, The following modifications can be considered.
(1) By adding a function of changing or adjusting the order or multiplication coefficient to the specific frequency removal filter 32 of the arithmetic unit 3, it is possible to take a trade-off between the thinning rate and the noise removal accuracy. That is, by adjusting the filter order and the multiplication coefficient of the specific frequency removal filter 32, highly accurate noise removal and high-speed response filtering processing can be realized. In the present embodiment, the case where the frequency components of the hybrid signal and the commercial power supply are removed as noise has been described. However, the adjustment function may remove noise in a frequency band other than the hybrid signal and the commercial power supply. Is possible.

(2) In the above embodiment, the specific frequency removal filter 32 of the computing unit 3 has been described on the assumption that it has a function of performing time-division processing for attenuating the specific frequency component of the digital signal of each channel. For example, the serial communication device 24c of each channel CH1 to CHn is provided with a function of transmitting a digital signal to the computing unit 3 at different timings, for example, as shown in FIG. Without providing the frequency removal filter 32 with a time division processing function, processing for attenuating a specific frequency component on the computing unit 3 side can be performed in a time division manner.

(3) Utilizing the merit of digital communication, a configuration may be adopted in which intelligent information such as diagnostic information and temperature information is transmitted in addition to a digital signal corresponding to a normal input analog signal. For example, Figure 9 is an illustration of a structure of a case of providing a diagnostic function 24d to the logic circuit 24 _C1.

(4) The above embodiment exemplifies a case where the order of the digital filter on the AFE 2 side (high frequency filter and thinning filter 24b) is 13, and the order of the digital filter on the arithmetic unit 3 side (specific frequency removal filter 32) is 49. However, the present invention is not limited to this, and by setting the order of the digital filter on the AFE 2 side lower than at least the digital filter on the arithmetic unit 3 side, the circuit scale of the digital filter on the AFE 2 side can be reduced, and the effect of cost reduction increases. The specific order allocation may be appropriately changed according to the cost and performance required for the analog input module 1.

(5) In the above-described embodiment, the case where the ΔΣ modulation method is employed as the A / D conversion method on the AFE 2 side is described as an example, but even when an A / D converter of another method is used, The present invention can be applied when it is necessary to provide a digital filter for removing a specific frequency component of a digital signal.

1 ... Analog Input Module (signal processing device), 2 ... multichannel analog front end (AFE), 3 ... _calculator, 21 C1 through 21 _{Cn ...} analog input _terminal, 22 C1 through 22 _{Cn ...} analog LPF (Low Pass Filter) , 23 _C1 to 23 _Cn .DELTA..SIGMA. (Delta sigma) modulator, 24 _{C1 to} 24 _Cn ... Logic circuit, 25 _{C1 to} 25 _Cn .about.insulating element, 24a... Moving average filter, 24b. Communication device, 31 _{C1 to} 31 _Cn ... Serial communication device, 32 ... Specific frequency elimination filter

Claims (4)

In the signal processing apparatus that converts the input analog signal into a digital signal at each of a plurality of input units corresponding to a plurality of input analog signals, delivers the digital signal to a calculation unit, and performs predetermined signal processing,
Each of the plurality of input units includes a digital filter that attenuates a specific frequency component by a predetermined amount.
The arithmetic unit includes a single digital filter having a function of attenuating a specific frequency component of a digital signal transmitted from each of the plurality of input units by a predetermined amount in a time division manner.
Signal processing apparatus characterized by. 2. The signal processing device according to claim 1, wherein the order of the digital filter provided in each of the plurality of input units is set lower than the order of a single digital filter provided in the arithmetic unit. . In each of the plurality of input units,
  An analog input terminal;
  An analog low-pass filter for attenuating a high-frequency component of an analog signal input via the analog input terminal;
  A delta-sigma modulator that converts the analog signal output from the analog low-pass filter into a bit-compressed signal by performing delta-sigma modulation;
  A moving average filter having a function as a thinning filter of the bit-compressed signal;
  A digital filter having both a function of attenuating a specific frequency component of a digital signal output from the moving average filter and a function of a thinning filter;
  A serial communication device that converts a digital signal output from the digital filter into serial data and outputs the digital signal to the arithmetic unit via an insulating element;
  The signal processing apparatus according to claim 1, wherein the signal processing apparatus is provided. The specific frequency component is a frequency component of a hybrid signal and a commercial power source to be superimposed on the input analog signal,
  The digital filter provided in each of the plurality of input units is configured to attenuate the frequency component of the hybrid signal,
  A single digital filter provided in the arithmetic unit is configured to attenuate the frequency components of the hybrid signal and the commercial power source.
  The signal processing device according to claim 1, wherein the signal processing device is a signal processing device.

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