TWI545904B - Cyclic vernier ring time-to-digital converter - Google Patents

Description

Ring micro-scale time digital converter

The present invention relates to a time digital converter, and more particularly to a circular micro-scale time digital converter using a multi-order delay unit.

Press, time-to-digital converter (TDC) is a conversion unit that quantizes the time information relative to a reference event, which is commonly used in digital phase lock loop (PLL), Among the physical and laser range finder (Physics and Laser range finder). Among them, the performance of the time digital converter can be represented by a digitized minimum resolution representing time information.

In general, a time digital converter can typically be implemented by a delay line comprising a plurality of delay units, and the plurality of delay units produce relatively equal intervals of phase. Each delay unit has a characteristic of a transfer delay that limits the digitized minimum unit of the circuit output. Therefore, the performance of the time digital converter is related to the accuracy of the transfer delay of each delay unit. However, in practice, the offset of the delay unit caused by the process variation may cause the performance of the time digital converter to decrease.

Moreover, for the commonly used time digital converter, the delay unit mostly uses a flip-flop, and must be connected in an odd-numbered stage to generate an oscillation to make the circuit operate normally, so a relatively complicated coding circuit is needed. In addition to this, due to the delay of each adjacent node in the loop The waveforms are opposite to each other, so each node needs to additionally set two sets of comparators to compare the phases, one of which compares the phase difference of the rising edge of the signal, that is, the order in which the signals rise; The phase difference of the falling edge of the comparison signal is the order in which the comparison signal drops. Finally, after the loop detection is completed, the reset signal must be reset from the input terminal, and then the reset operation can be completed after all the flip-flops delay the time. Therefore, it takes a long time, which not only makes The design complexity of the circuit is too high, and many design costs are added invisibly.

Therefore, in order to solve the many shortcomings of the prior art, the inventors have felt that the above-mentioned defects can be improved, and based on the relevant experience in this field for many years, carefully observed and studied, and with the use of academic theory, The present invention, which is novel in design and effective in improving the above-mentioned deficiencies, discloses a ring-shaped micro-scale time-digital converter, the specific structure and implementation of which will be described in detail below.

In order to solve the problems of the prior art, it is an object of the present invention to provide a Vernier Ring Time-to-Digital Converter that uses a forward delay unit such that each phase The neighboring nodes do not have the problem of reversing the signal. In this way, each node only needs a single set of comparators to detect the relationship between the two signals, which greatly simplifies the circuit design of the see.

Another object of the present invention is to provide a ring-shaped micro-scale time digital converter which replaces a conventional delay unit by using a multiplexer, which not only meets the requirement that the output signal does not reverse, but also can utilize the multiplexer itself. The auto-zero feature speeds up circuit resets, thereby reducing circuit design complexity and design cost.

A further object of the present invention is to provide a ring-shaped micro-scale time-to-digital converter which simplifies the circuit structure of the prior art and can be further extended to the pulse wave modulation circuit by the circuit design concept. Or in the spread spectrum circuit application, thereby increasing the performance of the circuit.

Therefore, the ring-shaped micro-scale time digital converter according to the present invention converts the received time difference between a leading signal and a backward signal into a digital signal output, and the circular micro-scale time digital converter The method includes: a first multi-order delay loop, a second multi-order delay loop, a plurality of comparators, a computing module, a decoder, and a processing module.

According to an embodiment of the present invention, the first multi-order delay loop receives the leading signal, and controls the leading signal to form a first pulse signal after the multi-step delay periodically to be heavy in the first multi-order delay loop. a second multi-step delay loop receives the backward signal, and controls the backward signal to form a second pulse signal periodically after the multi-step delay to periodically run in the second multi-order delay loop; The comparator is coupled to the first multi-order delay loop and the second multi-order delay loop, and compares the time difference between the first pulse signal and the second pulse signal to output a comparison signal. The operation module is coupled to the first multi-order delay loop and the second multi-order delay loop to count the first pulse signal and the second pulse signal respectively in the first multi-order delay loop and the second The number of runs in the order delay loop. The decoder is coupled to the comparators. When the comparison signal is switched from the high level to the low level, the first pulse signal is synchronized with the second pulse signal, and the decoder compares the comparison signal. Decoded into a decoded signal output. Finally, the processing module is coupled to the decoder and the computing module to receive the decoded signal and the counting result of the computing module, to generate the digital signal output.

In an embodiment, the annular micro-scale time digital converter disclosed in the present invention Further, the pre-processing logic circuit may be included to cooperate with a pre-comparator to determine the position of the backward signal entering the second multi-order delay loop, thereby accelerating the detection speed, and providing a counting redundancy corrector for calibration purposes.

In an embodiment, the computing module further includes a coarse counter, a fine counter, and a count redundancy corrector. Wherein, when the leading signal enters the first multi-stage delay loop, the coarse counter starts counting, until the backward signal enters the second multi-order delay loop, the coarse counter stops counting, and the fine counter starts counting to respectively utilize The coarse counter calculates the number of operations of the first pulse signal in the first multi-order delay loop, and calculates the number of times the second pulse signal is operated in the second multi-order delay loop by using a fine counter.

Moreover, the counting redundancy corrector can further utilize the detection result of the pre-processing logic circuit to determine the time for switching from the above-mentioned coarse counter operation to the operation of the fine counter. With such technical features, the present invention simultaneously reduces the hardware cost of the circuit, achieves low power consumption, and avoids the problem that the converter often has a counting error.

The purpose, technical contents, features and effects achieved by the present invention will be more readily understood by the detailed description of the embodiments and the accompanying drawings.

10‧‧‧Pre-comparator

100‧‧‧ first multi-order delay loop

200‧‧‧ second multi-order delay loop

300‧‧‧ comparator

301a‧‧‧Factor

301b‧‧‧Factor

301c‧‧‧Factor

301d‧‧‧Factor

303a‧‧‧Multiplexer

303b‧‧‧Multiplexer

400‧‧‧ Computing Module

402‧‧‧ coarse counter

404‧‧‧ fine counter

406‧‧‧Counting redundancy corrector

500‧‧‧Decoder

600‧‧‧Processing module

700‧‧‧First pre-processing logic

800‧‧‧Second pre-processing logic

1 is a circuit diagram of a ring-shaped micro-scale time digital converter in accordance with an embodiment of the present invention.

2A is a circuit diagram of a first pre-processing logic circuit in accordance with an embodiment of the present invention.

2B is a circuit diagram of a second pre-processing logic circuit according to an embodiment of the present invention Figure.

Figure 3 is a circuit diagram of a count redundancy corrector in accordance with an embodiment of the present invention.

4A and 4B are diagrams showing the signal waveforms of the nodes in the count redundancy corrector shown in FIG.

Fig. 4C is a diagram showing the early switching of the coarse counter and the fine counter being turned on according to the counting redundancy corrector shown in Fig. 3.

The 4D figure is a schematic diagram in which the counting redundancy corrector delays switching the coarse counter off and the fine counter is turned on according to the third figure.

5 and 6 are detailed time operation diagrams of a ring-shaped micro-scale time digital converter according to an embodiment of the present invention.

The above description of the present invention is intended to be illustrative and illustrative of the spirit and principles of the invention, and to provide further explanation of the scope of the invention. The features, implementations, and utilities of the present invention are described in detail with reference to the preferred embodiments.

Please refer to FIG. 1 , which is a circuit diagram of a circular micro-scale time digital converter according to an embodiment of the invention, comprising: a first multi-order delay loop 100 , a second multi-order delay loop 200 , and a plurality of The comparator 300, the computing module 400, the decoder 500, the processing module 600, a first pre-processing logic circuit 700, and a second pre-processing logic circuit 800. 2A and 2B are circuit diagrams of the first pre-processing logic circuit and the second pre-processing logic circuit, respectively. The following detailed description of the technical contents of the present invention will be made by referring to the first, second, and second embodiments, and will be described in detail below.

According to an embodiment of the invention, the first multi-stage delay loop 100 is configured to receive a lead signal In_a, and the first multi-stage delay loop 100 includes a plurality of first delay units S1 S S8 such that the lead signal In_a passes each time The first delay unit is delayed by a first delay time t _L , and the leading signal In_a is a first pulse signal periodically after the plurality of first delay times t _L periodically in the first multi-order delay loop 100 Repeated operation. In the present embodiment, the number of the first delay units is 8 as an example, but the invention is not limited thereto. The designer can adjust it according to the specifications of the circuit, and the equivalent changes or modifications made in accordance with the spirit of the present invention should still be covered by the patent of the present invention.

Similarly, the second multi-stage delay circuit 200 is configured to receive a backward signal In_b, and the second multi-order delay circuit 200 includes a plurality of second delay units F1 F F8, such that the backward signal In_b passes through a second delay unit. After being delayed by a second delay time t _D , the backward signal In_b is periodically re-run in the second multi-order delay loop 200 after a plurality of the second delay times t _D . .

Each comparator 300 is coupled between each of the first delay unit and the second delay unit, for example, a first delay unit S1 and a second delay unit F1, a first delay unit S2 and a second delay unit F2.. ... between the first delay unit S8 and the second delay unit F8, to compare the first pulse wave signal after each first delay time t _L and the second pulse wave signal after each second delay time t _D The time difference thereafter, and the comparison signal V _c is output based on the time differences. According to an embodiment of the present invention, the first delay units S1 S S8 and the second delay units F1 FF8 may be, for example, a multiplexer (MUX) delay unit.

The computing module 400 is electrically coupled to the first multi-order delay loop 100 and the second multi-step delay loop 200 to count the first pulse signal and the second pulse signal respectively in the first multi-order delay loop. 100 and the number of runs in the second multi-order delay loop 200. According to an embodiment of the present invention, the operation module 400 further includes a coarse counter 402, a fine counter 404, and a counter redundancy corrector 406. When the signal In_a leading into the first multi-stage delay circuit 100 of the first delay unit S1 elapsed after a time t _{1, the} system of the first delay unit S1 is switched to the closed loop, and generates a first pulse width equal to the pulse signal t ₁ Continuously running in the first multi-stage delay loop 100, the detection mode at this time is similar to the conventional digital delay converter of the conventional delay sequence. When the pulse signal passes through the node L8, the value of the coarse counter 402 is incremented by one. As for the backward signal In_b entering the second multi-stage delay loop 200, the time digital converter will change to the micro-scale detection mode, that is, the coarse counter 402 will be turned off, and then switched to the fine counter 404 to start counting. In other words, when the present invention enters the first multi-stage delay loop 100 by using the leading signal In_a, the coarse counter 402 starts counting until the backward signal In_b enters the second multi-stage delay loop 200, and the coarse counter 402 stops counting and switches to fine Counter 404 begins counting. In the present invention, the coarse pulse counter 402 can be used to calculate the number of operations of the first pulse signal in the first multi-order delay loop 100, and the second pulse signal is used to calculate the second pulse signal in the second multi-step delay loop. The number of runs in 200.

The decoder 500 is electrically coupled to the comparator 300 and receives the comparison signal V _c described above. According to the embodiment of the present invention, since the second delay time t _D is designed to be smaller than the first delay time t _L , the second pulse signal in the second multi-order delay loop 200 gradually catches up with the first The first pulse signal of the delay circuit 100 is similar to the conventional micro-scale time digital converter. Therefore, when the comparator 300 detects that the comparison signal V _c is switched from the high level to the low level, it represents that there is no time difference between the first pulse signal and the second pulse signal, that is, the first pulse signal. Has been synchronized to the second pulse signal. At this time, the detection is completed, and the decoder 500 decodes the comparison signal V _c at this time into a decoded signal V _D output. Finally, the processing module 600 coupled to the decoder 500 and the computing module 400 receives the decoded signal V _D and the counting result of the computing module 400 to generate a digital signal V _O output. Therefore, the ring-shaped micro-scale time digital converter disclosed in the present invention can convert the time difference between the leading signal In_a and the backward signal In_b into the digital signal V _O output.

Furthermore, the first pre-processing logic circuit 700 and the second pre-processing logic circuit 800 shown in FIGS. 2A and 2B are respectively composed of a plurality of multi-order delay units. As shown in FIG. 2A, the first pre-processing logic circuit 700 includes a plurality of first pre-delay units P1 to P8, which are similarly described in the present embodiment by an 8-order multiplexer delay unit. Not limited to this. Each of the first pre-delay units P1 - P8 generates a third delay time, and an initial leading signal V _F is received by the first pre-delay unit P1 of the first pre-processing logic circuit 700, and controls the The leading signal V _F becomes the aforementioned leading signal In_a after a plurality of the third delay times. Similarly, the second pre-processing logic circuit 800 includes a plurality of second pre-delay units Q1 - Q8, which are similarly illustrated in the present embodiment by an 8-order multiplexer delay unit, but the present invention does not limit. Each of the second pre-delay units Q1 - Q8 generates a fourth delay time, and a start backward signal V _S is received by the second pre-delay unit Q1 of the second pre-processing logic circuit 800, and controls the The start-and-go signal V _S becomes the aforementioned backward signal In_b after a plurality of the fourth delay time. The present invention controls the delay time (ie, the third delay time and the fourth delay time) in the pre-processing logic circuit to be equal to the first delay time t _L in the ring-shaped micro-scale time digital converter, in order to help select the backward signal In_b. The second delay unit F1 or F5 of the upper circuit can further provide the counting redundancy corrector 406 for judgment, thereby reducing the detection time of the time digital converter and correcting the counting error of the computing module (described later) .

In detail, the entry of the backward signal In_b by the second delay unit F1 or F5 is determined by the pre-processing logic circuit. As shown in FIG. 2B, a pre-comparator 10 is used to compare the half backward signal Q _D4 with a full delay signal L8 to determine the position of the backward signal In_b to enter the second multi-order delay loop 200. As described above, in this embodiment, when the number of the first delay unit, the second delay unit, the first pre-delay unit, and the second pre-delay unit is N, and the value of N is equal to 8, beginning backward signal V _S after (t _L * 8/2) delay time (4t _L) becomes the half backward signal Q _D4, the leading signal In_a after (t _L * 8) the delay time becomes the Full delay signal L8. Therefore, according to the embodiment of the present invention, when the initial backward signal V _S enters the second pre-processing logic circuit 800, the pre-comparator 10 compares the two signals of the half-back signal Q _D4 and the full delay signal L8. The delay signal L8 leads the semi-backward signal Q _D4 , and the backward signal In_b enters the delay loop via the fifth second delay unit F5 of the second multi-stage delay loop 200; as for the half-back signal Q _D4 leads the full delay signal At L8, the backward signal In_b is received by the first second delay unit F1 of the second multi-order delay loop 200. By the judgment of the pre-processing logic circuit, the present invention can greatly reduce the time digital converter. The required detection time, and according to the actual simulation results, the present invention can provide an operating speed of up to 1.5 GHz.

Furthermore, please refer to FIG. 3, which is a circuit diagram of a counting redundancy corrector according to an embodiment of the present invention. The counting redundancy corrector 406 includes a plurality of flip-flops 301a, 301b, 301c, 301d and multiplexers 303a, 303b. As described above, when the leading signal In_a enters the circular micro-scale time-digit converter of the multi-stage delay unit, the coarse counter 402 starts to operate, and the fine counter 404 is turned off. Taking the 8th order delay unit time digital converter as an example, the counting redundancy corrector 406 has the effect of phase error detection, which compares the initial backward signal V _S with the full delay signal L8, and in the second signal V _S and When the L8 phase difference is less than or equal to the buffering time t _{c of the} count redundancy corrector 406, a value is output to the nodes B1 and B2. According to an embodiment of the present invention, the buffering time t _{c of the} counting redundancy corrector 406 can be set, for example, to 100 ps, and the magnitude of the buffering time t _c is not changed in the switching of the coarse counter 402 to the fine counter 404 according to the simulation result of the present invention. Determined if a count error occurs.

4A and 4B are respectively schematic diagrams of the signal waveforms of the nodes L8a and ena in the counting redundancy corrector, wherein the counting redundancy corrector 406 uses the effect of the phase error detection to determine the initial backward signal V _S and The time difference between the full delay signal L8, when the initial backward signal V _S leads the full delay signal L8 for t _c , the node B ₂ will rise to the high potential, and the node B ₁ maintains the 0, and the counting redundancy The corrector 406 will control the coarse counter 402 to close early, and switch to the fine counter 404 to begin counting, as shown in FIG. 4C. Conversely, according to an embodiment of the present invention, when the time of the full delay signal L8 leading the start backward signal V _S is within t _c , the node B ₁ will rise to a high level and the node B _{2 will} remain at 0, in which case As shown in FIG. 4D, the count redundancy corrector 406 controls the time for delaying the switching of the coarse counter 402 to the fine counter 404 to delay the start of the fine counter 404, so that the present invention is utilized. The counting redundancy corrector can not only use less hardware consumption, but also further correct the counting error by phase detection.

In the following, the present invention provides FIG. 5 and FIG. 6 , which are detailed time operation diagrams of a ring-shaped micro-scale time digital converter according to an embodiment of the present invention, to illustrate that between the leading signal In_a and the backward signal In_b a phase difference equal to T _p, cyclic micro time scale digital converter based multi-stage delay unit of how the phase conversion are digital code output. As shown in the figure, T _p is the time difference between the leading signal In_a and the backward signal In_b, N _c is the counting result of the coarse counter, and t _L is the first of the first delay unit in the first multi-stage delay loop 100 The delay time, N _F is the counting result of the fine counter, t _D is the second delay time of the second delay unit in the second multi-order delay loop 200, and V _D is the comparison signal provided by the decoder 500 to the comparator 300 The signal after V _c decoding, T _L is the time difference (T _L =8t _L ) after the delay of the first pulse signal (S1~S8), and the T _D is the second pulse signal passing (F1~ F8) The time difference after delay (T _D =8t _D ), T _S is the remainder of T _p divided by T _L , t _R is equal to t _L -t _D , L1, D1, D5 are the first delay unit respectively S1, the second delay unit and an output waveform F1 to F5, as shown in FIG. 5 and FIG. 6, the invention is explained when there is a phase difference equal to T _p between the leading signal and the backward signal IN_B In_a, multi-step delay The unit's ring-shaped micro-scale time-to-digital converter converts the phase difference into a digital code output.

First, as shown in Figure 5, when T _p - N _c × 8 × t _L < When T _L , the backward signal In_b enters the loop by the first delay unit F1 in the second multi-order delay loop 200, and the phase difference is in accordance with the following formula (1): T _p = N _c × 8 × t _L + N _F × 8 × ( t _L - t _D ) + V _D × ( t _L - t _D ) (1), to determine that the backward signal In_b in the second multi-order delay loop 200 gradually catches up with the leading signal In_a. On the other hand, as shown in Figure 6, when When T _L < T _p - N _c × 8 × t _L < T _L , the backward signal In_b is entered into the loop by the fifth delay unit F5 in the second multi-stage delay loop 200, and the phase difference is in accordance with the next step. Equation (2): T _p = N _c × 8 × t _L + ( N _F + 4) × 8 × ( t _L - t _D ) + [(( V _D +4) mod8) × ( t _L - t _D )] (2)

Therefore, in summary, the present invention greatly simplifies the time digital converter of the prior art, and by the integration of the related control circuits, the circular micro-scale time digital converter disclosed in the present invention can transmit less hard. Body consumption to achieve the operation. In addition, the forward multiplexer is used as the delay unit in the multi-order delay loop, and the adjacent output signals are not in opposition. The problem of the orientation, and each multiplexer delay unit has the characteristics of auto-zeroing and accelerating the reset speed, and further increasing the reset speed of the ring-shaped micro-scale time-digit converter of the present invention, thereby reducing the circuit Design complexity and design cost.

Furthermore, in order to speed up the detection speed, the ring-shaped micro-scale time digital converter disclosed in the present invention can further utilize the pre-processing logic circuit to determine the position of the backward signal into the annular micro-scale delay loop. In addition, by using the detection result of the pre-processing logic circuit, the counting redundancy corrector disclosed by the present invention can further determine the time from the coarse counter to the fine counter, thereby achieving the problem of correcting the counting error. .

The embodiments described above are merely illustrative of the technical spirit and characteristics of the present invention, and the objects of the present invention can be understood by those skilled in the art and are not limited thereto. Equivalent changes or modifications made by the spirit of the present invention should still be included in the scope of the present invention.

100‧‧‧ first multi-order delay loop

200‧‧‧ second multi-order delay loop

300‧‧‧ comparator

400‧‧‧ Computing Module

402‧‧‧ coarse counter

404‧‧‧ fine counter

406‧‧‧Counting redundancy corrector

500‧‧‧Decoder

600‧‧‧Processing module

700‧‧‧First pre-processing logic

800‧‧‧Second pre-processing logic

Claims (15)

An annular micro-scale time-to-digital converter converts a received time difference between a leading signal and a backward signal into a digital signal output, the circular micro-scale time digital converter comprising: a first multi-order delay The loop receives the leading signal and controls the leading signal to form a first pulse signal periodically after the multi-step delay to repeatedly operate in the first multi-order delay loop; a second multi-order delay loop Receiving the backward signal, and controlling the backward signal to form a second pulse signal after the multi-step delay periodically to repeatedly run in the second multi-order delay loop; the plurality of comparators coupled to the first plurality a step delay loop and the second multi-order delay loop, wherein the comparators compare a time difference between the first pulse signal and the second pulse signal, and output a comparison signal; and an operation module coupled to the a first multi-order delay loop and the second multi-order delay loop to count the operation of the first pulse signal and the second pulse signal in the first multi-order delay loop and the second multi-order delay loop, respectively frequency; The decoder is coupled to the comparators, wherein when the comparison signal is switched from a high level to a low level, the first pulse signal is synchronized with the second pulse signal, and the decoder compares the comparison The signal is decoded into a decoded signal output; and a processing module is coupled to the decoder and the computing module. The processing module receives the decoded signal and the counting result of the computing module to generate the digital signal output. The ring-shaped micro-scale time digital converter according to claim 1, wherein the first multi-order delay circuit Further comprising a plurality of first delay units, such that the leading signal is delayed by a first delay time after each of the first delay units, and the leading signal is the first pulse after a plurality of the first delay times a signal, the second multi-step delay loop further includes a plurality of second delay units, such that the backward signal is delayed by a second delay time after each of the second delay units, and the backward signal is subjected to the plurality of the second delays After the time is the second pulse signal, each of the comparators is coupled between each of the first delay units and each of the second delay units to compare the first pulse signals through each of the first The delay time and the time difference of the second pulse signal after each of the second delay times are performed, and the comparison signal is output according to the time differences. The ring-shaped micro-scale time-digit converter of claim 2, wherein the first delay unit and the second delay unit are a multiplexer (MUX) delay unit. The ring-shaped micro-scale time-digit converter according to claim 2, further comprising a first pre-processing logic circuit, wherein the first pre-processing logic circuit comprises a plurality of first pre-delay units, each of the first pre-delay The unit correspondingly generates a third delay time, wherein the first pre-processing logic circuit receives an initial leading signal and controls the initial leading signal to become the leading signal after a plurality of the third delay times. The ring-shaped micro-scale time-digit converter according to claim 4, further comprising a second pre-processing logic circuit, the second pre-processing logic circuit comprising a plurality of second pre-delay units, each of the second pre-delay The unit correspondingly generates a fourth delay time, wherein the second pre-processing logic circuit receives a start backward signal, and controls the start backward signal to become the backward signal after the plurality of the fourth delay time. The ring-shaped micro-scale time-digit converter of claim 5, wherein the third delay time and the fourth delay time are equal to the first delay time, and the second delay time is less than the first delay. The ring-shaped micro-scale time-digit converter according to claim 5, further comprising a pre-comparator, wherein the pre-comparator compares the half backward signal with a full delay signal to determine the backward signal to enter the second multi-order delay a position of the loop, wherein the first delay unit, the second delay unit, the first pre-delay unit, and the second pre-delay units are each N, and N is a positive integer, the first a delay time, the third delay time and the fourth delay time are t _L , and the second delay time is t _D , and the initial backward signal becomes after a delay time of (t _L *N/2) The half-lag signal, the leading signal becomes the full delay signal after a delay time of (t _L *N). The ring-shaped micro-scale time-digit converter of claim 7, wherein the N=8. The ring-shaped micro-scale time-digit converter according to claim 8, wherein the backward signal is caused by the first one of the second multi-order delay circuits when the half-lag signal leads the full delay signal Received. The ring-shaped micro-scale time-digit converter according to claim 8, wherein when the full-delay signal leads the half-lag signal, the backward signal is the fifth one of the second multi-stage delay circuits. Received. The ring-shaped micro-scale time-digit converter of claim 5, wherein the operation module further comprises a coarse counter and a fine counter, each of which is coupled to the first multi-order delay loop and the second multi-step a delay loop, wherein when the leading signal enters the first multi-stage delay loop, the coarse counter starts counting until the backward signal enters the second multi-stage delay loop, the coarse counter stops counting, and the fine counter starts Counting, respectively, using the coarse counter to calculate the number of runs of the first pulse signal in the first multi-order delay loop, and using the fine count The controller calculates the number of operations of the second pulse signal in the second multi-order delay loop. The cyclic micro-scale time digital converter according to claim 11, wherein the operation module further comprises a count redundancy corrector, which compares the start backward signal with a full delay signal to determine whether the fine counter is Starting to count, wherein the number of the first delay unit, the second delay unit, the first pre-delay unit, and the second pre-delay units are each N, and N is a positive integer, the first The delay time, the third delay time and the fourth delay time are t _L , and the second delay time is t _D , and the leading signal becomes the full delay signal after a delay time of (t _L *N). The circular micro-scale time digital converter according to claim 12, wherein when the initial backward signal leads the full delay signal, the coarse counter is turned off early to switch to the fine counter to start counting. The circular micro-scale time digital converter according to claim 12, wherein when the full delay signal leads the start backward signal, the coarse counter is delayed to delay the fine counter to start counting. The circular micro-scale time-digit converter of claim 12, wherein the counting redundancy corrector has a buffering time, and a time difference between the initial backward signal and the full-delay signal is less than or equal to the buffering time.