JP5710543B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit (ASIC: Application Specific Integrated Circuit) that controls the operation of an image forming apparatus such as a copying machine or a printer, and is particularly referred to as a SoC (System On Chip) incorporating a CPU (Central Processing Unit). The present invention relates to a semiconductor integrated circuit.

  In recent years, a semiconductor integrated circuit that controls the operation of an image forming apparatus such as a printer is often developed as a SoC with a built-in CPU from the viewpoint of cost and performance. In selecting a built-in CPU, various parameters such as architecture level, operating frequency, and cache size must be considered, and it is difficult to accurately estimate the CPU usage rate in the development stage of a semiconductor integrated circuit. Therefore, in view of safety, an over-spec CPU is often selected, and if an optimum CPU is not selected from the viewpoint of performance, cost, and power consumption, waste occurs in any one of them.

  Therefore, it is considered that the operation rate of the CPU built in the semiconductor integrated circuit is actually measured, and the measurement result is reflected in the next development, which is useful for selecting an appropriate CPU that does not become over-spec. As a method for measuring the operation rate of the CPU built in the semiconductor integrated circuit, there is a method of measuring with an operation clock or a supplied power supply (for example, see Patent Document 1), and each program (task / thread) such as an idle thread. There is a method of measuring depending on the operating state.

JP 2008-262370 A

  However, the method of measuring by the operation clock or the supplied power supply estimates the CPU operation rate indirectly from the outside of the semiconductor integrated circuit, and the actual operation rate of the CPU can be measured at a detailed level. Can not. In addition, the method of measuring depending on the operating state of each program (task / thread) such as an idle thread is dependent on the OS, and cannot be measured on an unsupported OS, and the software does not operate satisfactorily. In the initial stage, it is impossible to measure the operation rate.

  The present invention has been made in view of such a point, and an object of the present invention is to provide a semiconductor integrated circuit capable of recording an actual operation rate of an internal CPU in a detailed level without depending on software. It is to provide a circuit.

The semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit having a built-in CPU, and event information in which a time required for the interrupt processing and an interrupt factor are recorded by detecting a bus transaction of the CPU related to the interrupt processing. Event information generating means, and a result reading storage means for storing the event information generated by the event information generating means as log information. The event information generating means provides access to the interrupt vector. The feature is that the bus transaction is detected .
Furthermore, in the semiconductor integrated circuit of the present invention, the event information generation means may detect an access to an interrupt factor holding register holding an interrupt factor as the bus transaction.
Further, in the semiconductor integrated circuit of the present invention, the event information generation means includes an access to the interrupt factor holding register for acquiring an interrupt factor, and an access to the interrupt factor holding register for clearing the interrupt factor. May be detected as the bus transaction .

  According to the present invention, it is possible to record the actual operation rate of an internal CPU as event information at a detailed level by grasping the operation state of the CPU at the bus transaction level without depending on software. The obtained event information can be expanded to the next development of the semiconductor integrated circuit, so that it is possible to select a necessary and sufficient CPU that does not become over-specification.

1 is a block diagram showing a schematic configuration of an embodiment of a semiconductor integrated circuit according to the present invention. It is a figure which shows the example of event information memorize | stored in the register for a result reading shown in FIG. It is explanatory drawing for demonstrating the operation rate measurement operation | movement in embodiment of the semiconductor integrated circuit which concerns on this invention.

Next, embodiments of the present invention will be specifically described with reference to the drawings.
A semiconductor integrated circuit 1 of the present embodiment is an ASIC that controls the operation of an image forming apparatus such as a copying machine or a printer. Referring to FIG. 1, a CPU 2, a ROM (Read Only Memory) 3, a RAM (Random) Access Memory) 4, modules 51, 52 to 5 n, interrupt controller 6, and operation rate measurement circuit 7 are connected by a bus 8. The modules 51, 52 to 5n and the interrupt controller 6 are connected by interrupt signal lines 91 and 92 to 9n, respectively, and the interrupt controller 6 and the CPU 2 are connected by an interrupt signal line 10.

  The ROM 3 stores a control program for operating the CPU 2. The CPU 2 reads the control program stored in the ROM 3 and develops it in the RAM 4, and executes an operation based on the control program developed in the RAM 4. In addition, the control program developed in the RAM 4 includes an interrupt vector and an interrupt processing routine whose start address is designated by the interrupt vector as a program for handling interrupt processing.

  The modules 51 and 52 to 5n are various functional blocks such as an HDD controller. When an interrupt factor is generated in the modules 51 and 52 to 5n, the modules 51 and 52 to 5n are interrupted via the interrupt signal lines 91 and 92 to 9n. An interrupt signal to the controller 6 is asserted.

  The interrupt controller 6 controls interrupt priority and prohibits / permits interrupts from the modules 51 and 52 to 5n. When the interrupt signal from the modules 51 and 52 to 5n to which the interrupt is permitted is asserted, Then, an interrupt signal to the CPU 2 is asserted via the interrupt signal line 10. The interrupt controller 6 is provided with an interrupt factor holding register 61 for holding the modules 51, 52 to 5n for which the interrupt signal is asserted as interrupt factors.

  The operation rate measurement circuit 7 is a circuit for measuring the operation rate of the CPU 2 and includes an address information storage register 71, a comparison circuit 72, a timer 73 for counting time, and a result reading register 74. .

  The address information storage register 71 is a storage means for storing address information, and stores the address of the interrupt vector developed in the RAM 4 and the address of the interrupt factor holding register 61 provided in the interrupt controller 6.

  The comparison circuit 72 is connected to the bus 8, monitors a bus transaction on the bus 8, and generates a bus transaction having address information matching the address of the interrupt vector stored in the address information storage register 71. The occurrence of a bus transaction having address information matching the address of the interrupt factor holding register 61 stored in the address information storage register 71 is detected. The comparison circuit 72 functions as event information generation means, generates event information that records the time required for a series of interrupt processing, and stores the generated event information in the result reading register 74.

  The result reading register 74 is storage means for storing event information, and the event information stored in the result reading register 74 is configured to be read out of the semiconductor integrated circuit 1 by an external terminal or a program (not shown). . The event information generated by the comparison circuit 72 and stored in the result reading register 74 includes an interrupt factor column 81 in which an interrupt factor (factor A) is written, an interrupt vector, as shown in FIG. The access time (time C) to the interrupt factor holding register 61 for the first time and the vector access time column 82 in which the access time (time B) is time stamped as the vector access time and the interrupt factor is obtained. The first register access time column 83 that is time stamped as the first register access time and the second access time (time D) to the interrupt factor holding register 61 that is performed to clear the interrupt factor are the second register access time. As the second register access time field 84 which is time stamped as The interrupt processing, one event information is generated.

  Next, the operation rate measurement operation in the semiconductor integrated circuit 1 of the present embodiment will be described in detail with reference to FIG.

  The interrupt controller 6 asserts an interrupt signal to the CPU 2 via the interrupt signal line 10 when an interrupt signal from the modules 51, 52 to 5n to which the interrupt is permitted is asserted (S1).

  When the interrupt signal is asserted, the CPU 2 recognizes the interrupt and accesses the interrupt vector of the control program developed in the RAM 4 via the bus 8 (S2). The comparison circuit 72 detects a bus transaction that accesses the interrupt vector of (S2), that is, a bus transaction having address information that matches the address of the interrupt vector. When the comparison circuit 72 detects the occurrence of the bus transaction (S2), the comparison circuit 72 acquires the time from the timer 73, and uses the acquired time as the interrupt recognition timing when the CPU 2 recognizes the interrupt, and the event time stamped in the vector access time column 82 Information is generated, and the generated event information is stored in the result reading register 74.

  Next, the CPU 2 activates an interrupt processing routine whose start address is specified by the interrupt vector (S3), and accesses the interrupt factor holding register 61 for acquiring the interrupt factor by the interrupt processing routine (S4). The interrupt factor is acquired (S5). The comparison circuit 72 detects a bus transaction that accesses the interrupt factor holding register 61 (S4), that is, a bus transaction having address information that matches the address of the interrupt factor holding register 61. When the comparison circuit 72 detects the occurrence of the bus transaction (S4), the comparison circuit 72 acquires the time from the timer 73, and the acquired time is stored in the result reading register 74 as the processing start timing when the CPU 2 starts the interrupt processing. Time stamps the first register access time field 83 of the event information. Further, the comparison circuit 72 acquires an interrupt factor by the bus transaction of (S5), and records the acquired interrupt factor in the interrupt factor column 81 of event information stored in the result reading register 74.

  Next, the CPU 2 executes the processing of the acquired interrupt factor, and when the processing is completed, the CPU 2 accesses the interrupt factor holding register 61 for clearing the interrupt factor (S6). The comparison circuit 72 detects a bus transaction that accesses the interrupt factor holding register 61 (S6), that is, a bus transaction having address information that matches the address of the interrupt factor holding register 61. When the comparison circuit 72 detects the occurrence of the bus transaction (S6), the comparison circuit 72 acquires the time from the timer 73, and the acquired time is stored in the result reading register 74 as the processing end timing when the CPU 2 ends the interrupt processing. Time stamp the second register access time column 84 of the event information.

  Through the series of operations associated with the above interrupt processing, the interrupt factor acquired in the bus transaction (S5) is entered in the interrupt factor column 81, and the time of the bus transaction (S2) is time stamped in the vector access time column 82. Then, one event information is generated in which the time of the bus transaction (S4) is time stamped in the first register access time column 83, and the time of the bus transaction (S6) is time stamped in the second register access time column 84. Is done. In this way, each time an interrupt process is performed, one event information is generated and stored in the result reading register 74 as log information.

  The event information stored as log information in the result reading register 74 is read out from the semiconductor integrated circuit 1 by an external terminal or program (not shown) and analyzed, so that the time required for interrupt processing can be verified. It becomes possible to know the operating status.

  In this embodiment, the three times (interrupt recognition timing, processing start timing and processing end timing) at which a bus transaction associated with interrupt processing occurs are recorded as event information. Even if any two of the start timing and the process end timing are stored as event information, a certain effect can be obtained.

  In this embodiment, it is configured to record a plurality of times when a bus transaction accompanied by an interrupt process occurs as event information, but the time between each time is important as a response time, and information on the time itself is Not necessarily required. Therefore, as shown in FIG. 2B, the interrupt factor holding register 61 at the processing start timing (S4) is accessed from the bus transaction (time B) that accesses the interrupt vector at the interrupt recognition timing (S2). From the first response time column 85 that records the response time X until the bus transaction (time C) to be performed as the first response time and the bus transaction (time B) that accesses the interrupt vector of (S2) that is the interrupt recognition timing. Event information including a second response time column 86 for recording the response time Y up to the bus transaction (time D) for accessing the interrupt factor holding register 61 (S6), which is the processing end timing, as the second response time is generated. You may make it do.

  As described above, according to the present embodiment, the comparison circuit 72 generates event information that records the time required for interrupt processing and the interrupt factor by detecting the bus transaction of the CPU 2 related to the interrupt processing. Then, the generated event information is stored in the result read register 74 as log information. As a result, by grasping the operation state of the CPU at the bus transaction level without depending on software, the actual operation rate of the CPU to which it belongs can be recorded as event information at a detailed level. As a result, by reading the event information stored as log information in the read register 74 and developing it for the next development of the semiconductor integrated circuit, it becomes possible to select a necessary and sufficient CPU that does not become overspec.

  Furthermore, according to the present embodiment, the comparison circuit 72 accesses the interrupt factor holding register 61 for acquiring the interrupt factor, accesses the interrupt factor holding register 61 for clearing the interrupt factor, The access to the vector is detected as a bus transaction. As a result, the operation status of the CPU 2 can be recorded at the internal bus access level such as access to the interrupt vector and access to the interrupt controller 6 (interrupt factor holding register 61).

  Note that the present invention is not limited to the above-described embodiments, and it is obvious that the embodiments can be appropriately changed within the scope of the technical idea of the present invention.

1 Semiconductor integrated circuit 2 CPU
3 ROM
4 RAM
6 Interrupt controller 7 Operation rate measurement circuit 8 Bus 10 Interrupt signal line 51, 52-5n Module 61 Interrupt factor holding register 71 Address information storage register 72 Comparison circuit 73 Timer 74 Result reading register 81 Interrupt factor column 82 Vector access time column 83 First register access time field 84 Second register access time field 85 First response time field 86 Second response time field 91, 92-9n Interrupt signal line

Claims (3)

A semiconductor integrated circuit incorporating a CPU,
Event information generating means for generating event information that records a time required for the interrupt processing and an interrupt factor by detecting the CPU bus transaction related to the interrupt processing;
A result reading storage means for storing the event information generated by the event information generation means as log information ;
A semiconductor integrated circuit characterized in that the event information generating means detects an access to an interrupt vector as the bus transaction .   2. The semiconductor integrated circuit according to claim 1, wherein the event information generation means detects an access to an interrupt factor holding register holding an interrupt factor as the bus transaction.   The event information generating means detects, as the bus transaction, an access to the interrupt factor holding register for acquiring an interrupt factor and an access to the interrupt factor holding register for clearing the interrupt factor. 3. The semiconductor integrated circuit according to claim 2, wherein the semiconductor integrated circuit is fine.

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