201117009 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種系統管理匯流排（System Management201117009 VI. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a system management bus (System Management)
Bus ’ SMBus)的測試方式’制是關於一種存取SMBus裝置的 SMBus的測試方式。 【先前技術】 測試工作一直在產品的生產過程中占了一個很重要的部分。 由於在生產過程中，很有可能因為一些不特定因素導致生產出有 瑕疵的產品，因此生產完成的產品均需要經過測試方得以出貨或 上市。若沒有經過品管人員的測試，具有瑕疵的產品最終會在瑕 疵仍未被察覺的情況下被運送至市面上去販售。當使用者購買到 這些有問題的產品時，不僅會造成使用者的不變，對生產公司的 形象也會大打折扣。 而對於伺服器或筆記型電腦等計算機系統產品而言，最重要 的部分就是中央處理器(Central Processing Unit，CPU)以及將計算 機系統内其他周邊設備提供給中央處理器的北橋晶片與南橋晶 片其中南橋晶片月色使中央處理Is透過系統管理匯流排(System Management Bus，SMBus)，對大多數的周邊設備介面、多媒體控 制器和通訊介面進行存取。換句話說，若是SMBus本身有瑕疵， 會對整個計算機系統造成非常大的影響。 雖然SMBus應被列為計算機系統中相當重要的測試項目之 一’但針對SMBus的測試卻具有一些難處。由於SMBus係為南 201117009 橋晶片的内部匯流排，故無法用外部的治具對SMBus進行偵測。 這亦造成難以由外部得知SMBus的運作狀況’進而造成測試時難 以判斷SMBus運作是否正常的問題。 【發明内容】 為了解決上述的問題，本發明提供一種系統管理匯流排 (System Management Bus，SMBus)的測試方法。SMBus 的測試方 法係適用於測試一主機板的一 SMBus，其中SMBus係以一測試時 脈頻率運行。測試方法包括：以測試時脈頻率寫入一測試資料於 一 SMBus裝置；由SMBus裝置讀取測試資料；比對原始的測試 資料與讀取的測試資料，以獲得一測試結果；修改測試時脈頻率； 以及以修改過的測試時脈頻率重新執行測試方法。更佳的是，測 ”式方法另可包括讀取該SMBus的一狀態暫存器，以獲得一測試狀 態0 測試資料係可包括一寫入數據，亦可包括複數個寫入數據。 而SMBus裝置可為一串列存在檢測(Serial presence Detect，spD) 或7^ °己憶體。值得注意的是，;SMBus裝置係為主機板上原先具 有的裴置，而非為了測試SMBus另外設置之SMBUS裝置。 以測試時脈頻率寫入測試資料於SMBus裝置的步驟，係為在 寫入時間内持續寫入該測試資料。· 根據本發明之另一實施範例，在以測試時脈頻率寫入測試資 料於SMBus裝置的步驟之後，且在由SMBus裝置讀取测試資料 的步驟之前，SMBus的測試方法另可包括：等待一間隔時間。 201117009 “綜上所述，根據本發明提供之自動安寰作業系統的方法，其 藉由儲存媒體提供多個作鮮、統核d及硬體核心、對照表，並自 動=測而奸作業純之計算機的硬體資訊，再依據硬體資訊查 對…、表以㈣合適的作鮮統核心，以為計算機安裝作業系統。 如此來’可自動提供適當的作業系統核心給具有不同硬體規格 或型號等硬體纽的計额，柯需以人工選擇的方絲 的作業系統核心。 【實施方式】 以下在實施方式中詳細敘述本發明之詳細特徵以及優點，其 内谷足以使任何熟冑相關技藝者了解本發明之技術内容並據以實 % ’且根據本說明書所揭露之内容、申請專利範圍及圖式，任何 熟習相關技藝者可輕易地理解本發明糊之目的及優點。 本發明提供-種系統管理匯流排(System Managemem Bus， SMBus)的測試方法，其適用於測試一主機板的_ smBus，其中 SMBus係以一測試時脈頻率運行。 月·^考·第1圖」’其係為根據本發明一實施範例之主機板之 方塊示意圖。如「第1圖」所繪示，主機板20上具有-南橋晶片 22 ’並有透過SMBus 24與南橋晶片22電性相連的複數個smBus 裝置.26。其中主機板2〇係可被配置於任何的計算機系統中，例如 個人電腦、伺服器或是筆記型電腦。且主機板2〇上另可配置有與 南橋晶片22電性相連的一中央處理器(Central pr〇cessing此红， CRJ ’未繪示）以及一基本輸入輸出系統(Basic Input/Output 201117009The test method of Bus ’ SMBus is a test method for accessing SMBus of SMBus devices. [Prior Art] Test work has always occupied a very important part in the production process of products. Since in the production process, it is very likely that some unspecified factors will result in the production of defective products, the finished products need to be tested and shipped or marketed. Without the test of the quality control personnel, the defective product will eventually be shipped to the market for sale without being detected. When users purchase these problematic products, they will not only cause the user to remain unchanged, but also the image of the production company will be greatly reduced. For computer system products such as servers or notebook computers, the most important part is the Central Processing Unit (CPU) and the Northbridge and Southbridge chips that provide other peripheral devices in the computer system to the central processor. The south bridge chip moonlight allows the central processing Is to access the system management bus (SMBus) through most of the peripheral device interfaces, multimedia controllers and communication interfaces. In other words, if the SMBus itself is flawed, it will have a very large impact on the entire computer system. Although SMBus should be listed as one of the most important test items in computer systems, the testing for SMBus has some difficulties. Since the SMBus is the internal busbar of the South 201117009 bridge chip, it is not possible to detect the SMBus with an external fixture. This also makes it difficult to know the operation status of the SMBus from the outside, which in turn makes it difficult to judge whether the SMBus is functioning properly. SUMMARY OF THE INVENTION In order to solve the above problems, the present invention provides a test method for a system management bus (SMBus). The SMBus test method is suitable for testing an SMBus on a motherboard where the SMBus operates at a test clock frequency. The test method comprises: writing a test data to an SMBus device at a test clock frequency; reading the test data by the SMBus device; comparing the original test data with the read test data to obtain a test result; modifying the test clock Frequency; and re-execute the test method at a modified test clock frequency. More preferably, the method can further include reading a state register of the SMBus to obtain a test state. The test data system can include a write data, and can also include a plurality of write data. The device can be a Serial presence Detect (spD) or a 7^° memory. It is worth noting that the SMBus device is the original device on the motherboard, not the other one for testing the SMBus. SMBUS device. The step of writing the test data to the SMBus device at the test clock frequency is to continuously write the test data during the write time. According to another embodiment of the present invention, the test is performed at the test clock frequency. After the step of testing the data in the SMBus device and before the step of reading the test data by the SMBus device, the test method of the SMBus may further comprise: waiting for an interval. 201117009 "In summary, the automatic installation according to the present invention is provided. The method of the operating system, which provides a plurality of hard-working, unified cores and hardware cores, a comparison table by the storage medium, and automatically detects and reports the hardware information of the pure computer, and then Information on ... body check, (iv) the appropriate table to make fresh core system, that operating system installed on your computer. In this way, the core of the appropriate operating system can be automatically provided to the hardware with different hardware specifications or models. Ke needs the core of the operating system of the manually selected square wire. [Embodiment] Hereinafter, the detailed features and advantages of the present invention are described in detail in the embodiments, which are sufficient to enable any skilled artisan to understand the technical contents of the present invention and to present the contents according to the present disclosure. The subject matter and advantages of the present invention can be readily understood by those skilled in the art. The invention provides a system management system bus (SMBus) test method, which is suitable for testing a motherboard _smBus, wherein the SMBus is operated at a test clock frequency. [0086] Fig. 1 is a block diagram of a motherboard according to an embodiment of the present invention. As shown in Fig. 1, the motherboard 20 has a south bridge wafer 22' and a plurality of smBus devices 26 electrically connected to the south bridge wafer 22 via the SMBus 24. The motherboard 2 can be configured in any computer system, such as a personal computer, a server, or a notebook computer. The motherboard 2 can be further configured with a central processing unit (Central pr〇cessing this red, CRJ ’ not shown) and a basic input/output system (Basic Input/Output 201117009).
System，BIOS)。 中央處理器可透過南橋晶片22以及SMBus對主機板20上的 SMBus裝置26a或SMBus裝置26b等多個SMBus裝置26下達命 令。南橋晶片22包含大多數周邊設備介面、多媒體控制器和通訊 介面功能。例如南橋晶片22可電性相連於周邊組件互連(Peripheral Component Interconnect ’ PCI)控制器、先進技術附件(Advanced Technology Attachment ’ ΑΤΑ)控制器、通用序列匯流排(Universal • SerialBus，USB)控制器、網路控制器或音效控制器。舉例而言， 南橋晶片22可以是英代爾公司(Intel)戶斤生產的ICH9晶片。 而SMBus24係源自於内部整合電路(inter_Integrated Circuit， I C)匯流排’是一種用於晶片内部的匯流排。§mbus 24的規範係 由Intel於1995所定義之由兩條訊號所組成的匯流排，且SMBus 24 包含有一條時脈信號線(SMBCLK)以及一條雙向的資料信號線 (SMBDATA)。SMBus 24係以一測試時脈頻率運行，且測試時脈 ® 頻率係可在100kHz(千赫兹)到1MHz(百萬赫兹)的範圍之間。 SMBus裝置26係為速度較慢之周邊裝置或電源管理裝置，且 SMBus裝置26透過SMBus 24與中央處理器進行溝通。BI〇s亦 能透過SMBus24取得SMBus裝置26的相關資訊，如製造廠商、 型號、控制資訊、錯誤資訊或是狀態等等。舉例而言，SMBus裝 置26可以疋一串列存在檢測(Serial Presence Detect，8卩0)或是一 記憶體。 SPD係為一電子可擦拭記憶體（Electrieally_Erasable 201117009System, BIOS). The central processor can issue commands to the plurality of SMBus devices 26 such as the SMBus device 26a or the SMBus device 26b on the motherboard 20 through the south bridge chip 22 and the SMBus. The Southbridge chip 22 contains most of the peripheral device interfaces, multimedia controllers, and communication interface functions. For example, the south bridge chip 22 can be electrically connected to a Peripheral Component Interconnect 'PCI controller, an Advanced Technology Attachment 'ΑΤΑ controller, a Universal Serial Bus (USB) controller, Network controller or sound controller. For example, the south bridge wafer 22 may be an ICH9 wafer produced by Intel Corporation. The SMBus 24 is derived from an inter_integrated circuit (IC) busbar, which is a busbar for the inside of the wafer. § mbus 24 specification is a bus consisting of two signals defined by Intel in 1995, and SMBus 24 contains a clock signal line (SMBCLK) and a bidirectional data signal line (SMBDATA). The SMBus 24 operates at a test clock frequency and the test clock ® frequency range is from 100 kHz (kilohertz) to 1 MHz (million Hz). The SMBus device 26 is a slower peripheral device or power management device, and the SMBus device 26 communicates with the central processor via the SMBus 24. BI〇s can also obtain information about SMBus device 26 via SMBus24, such as manufacturer, model, control information, error message or status. For example, the SMBus device 26 can perform a Serial Presence Detect (8 卩 0) or a memory. SPD is an electronically erasable memory (Electrieally_Erasable 201117009)
Programmable Read-Only Memoiy，EEPROM)，被配置於記愫體 上。SPD主要係用以協助一北橋晶片調整記憶體的物理參數戈時 脈參數。而SPD内部存有記憶體相關的資訊，例如記憶體運作所 需的電壓、行/列地址數量、或是各種主要操作時脈。這些資訊均 能透過SMBus 24被BIOS讀取或修改。 SMBus裝置26亦可為一基板管理控制器（Baseb〇ard Management Controller ’ BMC)。BMC係為用以管理伺服器之智能 平台管理介面(Intdligent Platf_ Managemem Interface，圧卿的 核心控制器，係被配置於伺服器的主機板2〇。正述透過BMc管 理各個伺服器，且現今一般用於伺服器的主機板2〇均可支援 BMC。此外，SMBus裝置26另可為主機板2〇上的一反對稱彎曲 感測器(antisymmetric flexural sensor)或是一舊有感測器 〇egacy sensor) 〇 本發明提供之SMBus的測試方法係利用待測之主機板2〇原 26 # SMBus 24断職；制試方法不 需額外_卜勒糾峨行。接下來介紹8麻3 _試方法的 夕個實把範例’以解釋利用原有之SMBus裝置％對湖如24 進行測試的步驟。 π參…、第2圖」’其係為根據本發明一實施範例之 的測試方法之流程示意圖。纟「第2圖」可以知悉，的測 式方法可包括步驟S40:以測試時脈頻率寫入一測試資料於露仍 裴置；步驟S50 :由SMBus裝置讀取測試資料；步驟編：比對 201117009 原始的測試資料與讀取_試資料，以獲得—測試結果；以及步 驟S80 :修改測試時脈頻率。 於步驟S 4 0測4方法以測試時脈頻率將測試資料寫入一個 SMBus裝置26。首先為了得到SMBus24的一麵us控制器的基 底位址(base address)，可查詢周邊組件互聯鮮匯流排㈣細d Component Interconnect bus，PCI bus) ^ £ ^ Fa1 (c〇nfigumtl〇n space)。接著配合查詢南橋晶片22的資料表單—sheet)遍歷 PCI ’以制财連接在SMBus Μ上的妓(也就是漏us裝置 26)。再向SMBus控制器指定欲寫入的裝置％所對應的偏 移位址(翻識吵即可_細錄錢移條對特定的 SMBus裝置26進行存取。 將測試資料寫入SMB㈣置26時，可將主機板2〇的一主機 板時脈作為測試時脈頻率，亦可指定與主機板時脈不同的頻率給 SMBCLK作為測試時脈頻率。而測試資料係可為一寫入數據，或 是多個寫人數據…個寫人數射為長度是丨位元師㈣或是！ 字組(爾d)的資料。然不同的雜似裝置％具有不同大小的空間 可供測試方法使用。若欲以多個寫人數據進行戦，則需以 足夠之内部儲存空_ SMBus裝置26方可適任。 '、 =所述，SMBus敍26係為主 2q騎触置。儘管 可此同時有多個SMBUS裝置26，但挑選具有較 SMBUS 26 〇 寫入版前應藉娜書等了解各^ 寫測办料之齡空間或暫翻的涵義，不可任意修改，以兔 9 201117009 造成計算機系統運作異常。舉例而古，Sp 256 ^ ^ ^ BMC 〇 ^ 256 =用=:然而可作為寫入空間的詳細二二 •裝置26而有所不同，進行測物查詢SMBus裝置26 對應的規格書，方能確保測試不會造成計算機係運作、 鳴將^料寫入SMBus裝置26之後，測試方法於步釋 靖取剛寫人關試資料。戦方法可彻在步驟_得到之此 龍us裝置26嶋触购她，岭核人的位置中讀 取出測峨4。最彳_綠於步驟_將原始娜_盘讀 取出的測試倾進行叫並獲制試結果。若由龍㈣置26 頃出的測試資料與原始的測試資料相同，則表示於步雜㈣娜 ，成功地經由SMBUs24對SMBus裝置26存取測試資料。也就 疋說，如此一來，即可得知SMBlls24運作正常。 以步驟S40至步驟S7〇完成一次的測試之後，測試方法更可 於_咖修改測試時脈頻率，再以新的測試時脈頻率重複進行 測試。也就是說’ SMBUS的測試方法可將測試時脈頻率在1〇舰 至1MHZ的範圍内重新調整再進行測試，以確保遞耶Μ能再 各種時脈頻率下正確地運作。 接下來請參照「第3圖」，其係為根據本發明另-實施範例之 SMBus的測試方法之流程示意圖。由「第3圖」可以知悉，雜此 的測試方法可包括步驟S45:以測試時脈鱗在—寫人時__ ^入測試資料於SMBus裝置；步驟S5〇 :由議us裝置讀取測試 資料；步驟S60 :比對原始的測試資料與讀取的測試資料，以獲得 201117009 測I。果’步驟S7〇 :讀取SMBus的狀態暫存器(論s regi㈣， 乂獲^•測„式狀態，以及步驟S80 :修改測試時脈頻率。 步驟S45與步驟料〇的差異在於：步驟弘5係在寫入時間内， 持續向MBus震置26寫入測試資料。寫入時間可以例如是5 .秒 或是1〇移而注意的是，用以進行測試之SMBus裝置26需具有 足夠之内部儲存空間以儲存持續寫人的測試資料。此外，亦可將 測办料刀為數個部分，而在寫入時間内逐一寫入不同的$廳us 裝置26於步驟S5〇再依寫入順序讀出測試資料，以供步驟_ 比對。藉轉續以SMBus24將寫人職f料的方法，可以測試出 SMBus 24是否能在一定時間内持續正確地傳輸資料。 步驟S50 φ持續地將測試資料讀出後，於步驟_比對原始 的測試資料與讀取出的職資料，並制測·果。更佳的是， SMBus的戦綠另包括讀取SMBus %錄㈣約，以獲得 測試狀態(步驟S7G)。SMBUS 24驗騎存ϋ可魏置於南橋晶 片22之中，而測試狀態係可為SMBus 24的運作狀態。測試狀態 可表示例如SMBUS24技處於㈣輸·態，歧SMBus控制器 的暫存器是否發生錯誤。 以Intel的ICH9晶片為例，狀態暫存器的〇χ〇1位元表示 host-busy ; _4 位元絲 deviee—eiTOT ; _8 — 瞻 register ; 0x10 表示 host controller register err〇r。 因此藉由讀取SMBus 24 M狀態暫存器，測試方法不需任何外 部的偵測具，便可辑確且完整财控SMBus24的狀況。 而為了掌控SMBus 24的狀況，無論於步驟S6〇得到的測試結果是 201117009 否二確’剩試方法都可執行步驟 修改測_I列忒方去亦可於步驟S80 ^叫脈頻率’再以新的測試時脈頻率重複進行測試。 的測^照「第4圖」，其絲根據本發明又—實施範例之咖仙 試二t之流程示意圖。由「第4圖」可以知悉，SMBUS的測 ==包括步驟S4G :以測辦脈頻率寫人測試資料於sm^s 乂驟S50 ·由SMBus裝置讀取測試資料；步驟μ5 :等待 間隔時間；步驟S6〇 :比對原始的測試資料與讀取的測試資料， 以獲得1試結果；步驟S70:讀取龍us的狀態暫存器(編 g )以獲彳于測試狀遽，步驟:修改測試時脈頻率。 f只施範例與「第3圖」之實施範例的差異在於：於SM^s 寫入資料後，測試方法等待一段間隔時間(步驟S55)，再讀取寫入 之測試資料。間隔時間可以例如是1〇毫秒(咖)，且在間隔時間中， SMBus24的使用權可以交予測試方法以外的程序^如此一來，便 可以在非連續使用SMfius24存取的狀況下，測試SMBus24是否 月b正吊運作。測試方法的步驟S55並可與步驟S45搭配使用；且 如上所述，測試資料可以是一個或是多個寫入數據，以靈活測試 所需項目。 接著睛參照「第5圖」，其係為根據本發明再一實施範例之 SMBus.的測試方法之流程示意圖。由「第5圖」可以知悉，SMBus 的測試方法可包括步驟S40:以測試時脈頻率寫入測試資料於 」_丨」 · - . .» SMBus.裝置;步驟SS0:由SMBus裝置讀取測試資料；步驟S6〇 : 比對原始的測試資料與讀取的測試資料，以獲得一測試結果；步. 驟S7Q 讀取SMBus的狀態暫存器(status register)，以獲得測試狀 12 201117009 態；以及步驟S80:修改測試時脈頻率。 =謂至步驟S7G完成—次的測試之 修改物脈頻率，再以新的測試時脈頻率重複進行^式。 如此-來，測試方法可得到更高的正確性。a進仃似 綜，述’本發明提供之SMBus的測試方法經由待測的 SMBus在主機板上原有之SMb 牡w〜、b，一 s褒置寫入測试貝枓，再從SMBus 裝置中項取測武-貝料並比對得到測試結果。藉著巧妙地借用原有 SMBus裝置，㈣彳料 對内部匯流狀SMBUS進行測試。且根據狀態暫存器的内容更I 以充分地判斷測試過程中發現的錯誤的内容並據以推測錯誤原 m ° ' '、 此外，上述各實絲例均可互她合執行。舉_言可以 各種頻率重複進仃「第2圖」之實施範例的步驟。又例如測試 方法可以-侧試時職率輪流執行各實絲例的步驟之後，改 變測試時脈鮮並麵輪流執行這些實域例。如此—來，便可 對SMBus進行涵蓋不_時脈頻社全方位的 測試。 雖然本發明以前述之較隹實施例揭露如上，然其並非用以限 定本，明，任何熟f相像技藝者，在不脫離本發明之精神和範圍 内田可作些許之更動與潤飾，因此本發明之專利保護範圍須視 本說明書所附之.申請專機_界定者為準。 【圖式簡單說明】 f1圖係為根據本發明一實施範例之主機板之方塊示意圖； 第2圖係為根據本發明一實施範例之SMBus的測試方法之流 13 201117009 程示意圖； 第3圖係為根據本發明另一實施範例之sMBus的測試方法之 流程示意圖； 第4圖係為根據本發明又一實施範例之SMBus的測試方法之 流程示意圖；以及 第5圖係為根據本發明再一實施範例之smbus的測試方法之 不意圖。 【主要元件符號說明】 20 主機板 22 南橋晶片 24 SMBus 26,26a，26b SMBus裝置Programmable Read-Only Memoiy, EEPROM), is configured on the recording body. The SPD is mainly used to assist a North Bridge wafer to adjust the physical parameters of the memory. The SPD contains internal memory-related information, such as the voltage required for memory operation, the number of row/column addresses, or various major operating clocks. This information can be read or modified by the BIOS via SMBus 24. The SMBus device 26 can also be a Basebard Management Controller (BMC). The BMC is an intelligent platform management interface for managing servers (Intdligent Platf_ Managemem Interface, the core controller of the company is configured on the server board of the server.) The management of each server through the BMc is described. The motherboard for the server can support the BMC. In addition, the SMBus device 26 can also be an antisymmetric flexural sensor or an old sensor on the motherboard 2〇. Sensor) The SMBus test method provided by the present invention utilizes the motherboard 2 to be tested, the original 26 # SMBus 24, and the test method does not require additional _ _ _ _ _ _ _ _ Next, we will introduce the example of the 8 Ma 3 _ test method to explain the steps of testing the lake as 24 using the original SMBus device %. π ”, ” 2” is a schematic flow chart of a test method according to an embodiment of the present invention. As can be seen from "Fig. 2", the method of measuring may include the step S40: writing a test data at the test clock frequency to the display; step S50: reading the test data by the SMBus device; 201117009 Original test data and read_test data to obtain - test results; and step S80: modify test clock frequency. The test method is applied to an SMBus device 26 at the test clock frequency at step S40. First, in order to get the base address of the us controller of the SMBus24, you can query the peripheral component interconnect bus (4) fine d Component Interconnect bus, PCI bus) ^ £ ^ Fa1 (c〇nfigumtl〇n space). Then, in conjunction with querying the data sheet of the south bridge wafer 22, the sheet traverses the PCI ’ to connect to the SMBus 妓 (that is, the drain device 26). Then, the SMBus controller is assigned the offset address corresponding to the device % to be written (the arbitrarily arbitrarily arbitrarily recording the money to access the specific SMBus device 26. The test data is written into the SMB (four) at 26 o'clock. A motherboard clock of the motherboard 2 can be used as the test clock frequency, and a frequency different from the clock of the motherboard can be specified to the SMBCLK as the test clock frequency. The test data can be a write data, or It is a number of write data... The number of people who write is the length is the data of the position (4) or the word group (d). However, different memory devices have different sizes of space for the test method to use. If you want to use multiple data to write, you need to have enough internal storage space _ SMBus device 26 to be suitable. ', =, SMBus Syria 26 is the main 2q riding touch. Although there are multiple SMBUS device 26, but the selection of the SMBUS 26 〇 before writing the version should be borrowed from the book, etc. to understand the meaning of the space or temporary turnover of the writing and testing materials, can not be arbitrarily modified, the computer system is abnormal operation caused by rabbit 9 201117009. For example, the ancient, Sp 256 ^ ^ ^ BMC 〇 ^ 256 = with =: However, it can be used as the detailed two-two device 26 of the write space. The specification of the SMBus device 26 is performed to check whether the test will not cause the computer system to operate, and the device will be written into the SMBus device. After that, the test method is based on the step-by-step interpretation of the data. The method can be used to obtain the us4 from the position of the nucleus. _ Green in the step _ the test of the original Na _ disk read and call test results. If the test data from the Dragon (four) set 26 is the same as the original test data, it means that in the step (four) Na, The test data is successfully accessed to the SMBus device 26 via the SMBUs 24. In other words, it can be known that the SMBlls 24 is operating normally. After the test is completed in steps S40 to S7, the test method is more _ Modify the test clock frequency and repeat the test with the new test clock frequency. That is to say, 'SMBUS test method can re-adjust the test clock frequency from 1 ship to 1MHZ to test Jesus can be more than ever Please operate correctly at the pulse frequency. Please refer to "3rd figure", which is a schematic flow chart of the SMBus test method according to another embodiment of the present invention. It can be known from "Fig. 3" that the test method of this is different. The method may include the step S45: testing the clock scale to write the test data to the SMBus device; the step S5: reading the test data by the device; the step S60: comparing the original test data with the reading Test data to obtain 201117009 test I. Fruit 'Step S7〇: Read SMBus state register (on s regi (4), capture ^• test state, and step S80: modify test clock frequency. The difference between the step S45 and the step material is that the step 5 is continuously writing the test data to the MBus shake 26 during the writing time. The write time can be, for example, 5 seconds or 1 shift. Note that the SMBus device 26 used for testing needs to have sufficient internal storage space to store the test data for continued writing. In addition, the test knives may be divided into several parts, and the different $ s unit devices 26 are written one by one during the writing time. In step S5, the test data is read out in the order of writing for the step _ comparison. By continuing to use SMBus24 to write a job, you can test whether SMBus 24 can continue to transmit data correctly and for a certain period of time. Step S50 φ continuously reads the test data, and compares the original test data with the read job data in step _, and produces a test result. More preferably, the green of the SMBus additionally includes reading the SMBus % record (four) approximation to obtain the test status (step S7G). The SMBUS 24 test can be placed in the South Bridge wafer 22, and the test status can be the operating state of the SMBus 24. The test status can indicate, for example, that the SMBUS 24 technology is in the (four) input state, and whether the SMBus controller's scratchpad has an error. Taking Intel's ICH9 chip as an example, the 暂1 bit of the state register indicates host-busy; _4 bit line deviee-eiTOT; _8 - register register; 0x10 means host controller register err〇r. Therefore, by reading the SMBus 24 M status register, the test method eliminates the need for any external detection device and can accurately and completely control the status of the SMBus24. In order to control the status of SMBus 24, the test result obtained in step S6〇 is 201117009. No. 2 The remaining test method can be performed to modify the test. _I can also be used in step S80. The new test clock frequency is repeated for testing. The measurement of Fig. 4 is a schematic diagram of the flow of the method according to the present invention. It can be known from "Fig. 4" that the measurement of SMBUS == includes step S4G: writing the test data at the measurement pulse frequency to sm^s step S50. The test data is read by the SMBus device; step μ5: waiting interval; Step S6: comparing the original test data with the read test data to obtain 1 test result; Step S70: reading the state register of the dragon us (edit g) to obtain the test condition, step: modify Test the clock frequency. The difference between the f example and the implementation example of "Fig. 3" is that after the data is written by SM^s, the test method waits for an interval (step S55), and then reads the written test data. The interval time can be, for example, 1 millisecond (coffee), and in the interval, the usage right of the SMBus 24 can be given to a program other than the test method. Thus, the SMBus 24 can be tested under non-continuous use of the SMfius 24 access. Whether the month b is hanging and operating. Step S55 of the test method can be used in conjunction with step S45; and as described above, the test data can be one or more write data for flexible testing of the required items. Next, reference is made to "figure 5", which is a schematic flow chart of a test method of SMBus. according to still another embodiment of the present invention. It can be known from "Figure 5" that the SMBus test method may include step S40: writing the test data at the test clock frequency to "_丨" · - . . . SMBus. device; step SS0: reading the test by the SMBus device Data; step S6: comparing the original test data with the read test data to obtain a test result; step S7Q reads the status register of the SMBus to obtain the test pattern 12 201117009 state; And step S80: modifying the test clock frequency. = to the step S7G is completed - the modified test pulse frequency is repeated, and then repeated with the new test clock frequency. So - the test method can get more correctness. a method of SMBus provided by the present invention is described in the SMBus device. The item is taken from the test - the material is compared and the test results are obtained. By subtly borrowing the original SMBus device, (4) diverting the internal confluence SMBUS. And according to the content of the state register, I can fully judge the content of the error found during the test and estimate the error m ° ' ', and in addition, each of the above-mentioned silk examples can be executed together. The _ 言 can repeat the steps of the implementation example of "Figure 2" at various frequencies. For example, the test method can be performed after the steps of each of the wire examples are alternately performed in the side trial time, and the test time clocks are alternately performed in parallel to perform these real-world examples. In this way, SMBus can be tested in all aspects of the coverage of the SMBus. Although the present invention has been described above in the above-described embodiments, it is not intended to limit the scope of the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of patent protection of the invention shall be subject to the application of the special machine_as defined in this specification. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a motherboard according to an embodiment of the present invention; FIG. 2 is a schematic diagram of a flow of a test method for an SMBus according to an embodiment of the present invention; FIG. 4 is a flow chart showing a test method of an SMBus according to another embodiment of the present invention; and FIG. 5 is a flow chart showing a test method of an SMBus according to still another embodiment of the present invention; and FIG. 5 is a further embodiment according to the present invention. The smbus test method of the example is not intended. [Main component symbol description] 20 Motherboard 22 Southbridge wafer 24 SMBus 26, 26a, 26b SMBus device