TW201623987A - Dynamic memory testing apparatus and testing method thereof - Google Patents

Abstract

A dynamic memory test apparatus and method are provided. The dynamic memory test apparatus includes a SOC (system on chip), and the SOC is coupled to the dynamic memory. The SOC includes a control unit and an embedded memory apparatus. The control unit is coupled to the dynamic memory. The embedded memory apparatus stores a memory testing program code, and the control unit reads the memory testing program code and tests the dynamic memory by executing the memory testing program code.

Description

Dynamic memory test device and test method thereof

The invention relates to a dynamic memory testing device and a testing method, and in particular to a testing device and a testing method for external dynamic memory testing using a system integrated chip.

Please refer to FIG. 1. FIG. 1 is a block diagram of a prior art dynamic memory testing device. In FIG. 1, the controller 110 is coupled to the dynamic memory 120 and performs a test action for the dynamic memory 120. Controller 110 is a system integrated wafer. In this architecture, when the controller 110 tests the external dynamic memory, the controller 110 reads the test code 121 from the dynamic memory 120 and executes the test code 121 to perform the dynamic memory 120. Test action.

As can be seen from the above description, in the dynamic memory test device of the prior art shown in FIG. 1, since the test code 121 is stored in the dynamic memory device 120, the dynamic memory 120 is used to store the test program. The content of the memory block of the code 121 cannot be destroyed, and therefore, it is necessary to store the test code 121. It is impossible to test the memory block. That is to say, such an architecture cannot perform a complete test action on the dynamic memory 120.

Furthermore, if the memory block storing the test code 121 of the dynamic memory device 120 cannot be tested and tested, if the memory block storing the test code 121 is damaged, the stored test code 121 is also stored. It must be incorrect information. When the controller 110 executes the wrong test code 121, the test action will not be performed effectively, and the system may be down or restarted.

The invention provides a dynamic memory testing device and a testing method, which can improve the testing performance of the dynamic memory.

The dynamic memory testing device of the present invention includes a system integrated chip for coupling to a dynamic memory. The system integrated chip includes a control unit and an embedded memory device. The control unit is coupled to the dynamic memory. The embedded memory device stores the memory test code, wherein the control unit reads the memory test code and performs a test action on the dynamic memory by executing the memory test code.

In an embodiment of the invention, the dynamic memory testing device further includes a connection interface. The connection interface is coupled to the embedded memory device, wherein the embedded memory device is coupled to the external storage unit through the connection interface, and the memory test code is read by the external storage unit.

In an embodiment of the invention, the connection interface includes an internal system At least one of a bus interface and a universal serial bus interface.

In an embodiment of the invention, the control unit includes a central processing unit and a dynamic memory controller. The dynamic memory controller is coupled to the central processing unit, wherein the central processing unit executes the memory test code to perform a test action on the dynamic memory through the dynamic memory controller.

In an embodiment of the invention, the embedded memory device includes a static memory and a static memory controller. Static memory is used to store the memory test code. The static memory controller is coupled to the static memory, the static memory controller receives the memory test code, and stores the memory test code in the static memory, and reads the memory test code from the static memory. Provide memory test code to the central processing unit.

In an embodiment of the invention, the static memory further includes initialization information for storing the dynamic memory and test mode startup information of the dynamic memory.

The method for testing a dynamic memory provided by the present invention comprises: providing a system integrated chip, and storing the memory test code in an embedded memory device of the system integrated chip; reading by the embedded memory device a memory test program; and executing a memory test program to perform test actions on dynamic memory.

Based on the above, the present invention places the test code on the outside of the dynamic memory to be tested, so that the dynamic memory can be completely tested, and the test code executed by the system integrated chip is not likely to occur. The wrong state allows the dynamic memory test action to be performed without risk.

In order to make the above features and advantages of the present invention more apparent, the following is a special The embodiments are described in detail below in conjunction with the drawings.

110‧‧‧ Controller

120‧‧‧Dynamic memory

121‧‧‧Test code

200‧‧‧Dynamic memory test device

300‧‧‧Dynamic memory test device

210‧‧‧System Integrated Chip

310‧‧‧System Integrated Chip

400‧‧‧System Integrated Chip

220, 320‧‧‧ dynamic memory

211, 311, 410‧‧‧ control unit

TCODE‧‧‧ memory test code

D3‧‧‧ memory test code

212‧‧‧Inline memory device

312‧‧‧Inline memory device

313‧‧‧Connection interface

330‧‧‧External storage unit

411‧‧‧Central Processing Unit

412‧‧‧Dynamic Memory Controller

420‧‧‧Inline memory device

422‧‧‧ Static memory

D1‧‧‧Initial Information

D2‧‧‧ test mode start information

S710~S730‧‧‧ memory test procedure

FIG. 1 illustrates a prior art dynamic memory testing device.

2 is a schematic diagram of a dynamic memory testing device according to an embodiment of the invention.

3 is a schematic diagram of a dynamic memory testing device according to another embodiment of the present invention.

FIG. 4 illustrates an embodiment of a system-integrated wafer 400 in accordance with an embodiment of the present invention.

FIG. 5 is a schematic diagram showing the stored content of the static memory in the embodiment of the present invention.

6 is a schematic diagram showing a logical address configuration of a dynamic memory testing device according to an embodiment of the present invention.

FIG. 7 is a flow chart of a dynamic memory test according to an embodiment of the invention.

Please refer to FIG. 2. FIG. 2 is a schematic diagram of a dynamic memory testing device according to an embodiment of the present invention. The dynamic memory testing device 200 includes a system integrated wafer 210. The system integrated chip 210 is coupled to the dynamic memory 220 and can perform a test operation on the dynamic memory 220. The dynamic memory 220 may be a Dynamic Random Access Memory (DRAM).

The system integrated wafer 210 includes a control unit 211 and an embedded memory device 212. The control unit 211 is coupled to the dynamic memory 220, and the embedded memory The device 212 is coupled to the control unit 211. In the test aspect of the dynamic memory 220, the embedded memory device 212 can store the memory test code TCODE, and when the test operation of the dynamic memory 220 is to be performed, the control unit 211 can be embedded in the memory device. 212 reads the memory test code TCODE stored therein, and performs a test operation on the dynamic memory 220 by executing the memory test code TCODE.

In this embodiment, the memory test code TCODE can be provided by an external component of the system integrated chip 210, wherein the embedded memory device 212 can receive the memory test code TCODE by an external component and Stored in the embedded memory device 212. When the control unit 211 is to perform the test operation of the dynamic memory 220, the embedded memory device 212 can provide the stored memory test code TCODE to the control unit 211 for the control unit 211 to perform the corresponding dynamic memory. Test action of body 220.

It should be noted that the memory test code TCODE of the embodiment of the present invention is not provided by the measured dynamic memory 220. That is to say, the memory test code TCODE does not occupy part of the memory area of the dynamic memory 220. When the control unit 211 performs a test operation on the dynamic memory 220, all the memory areas of the dynamic memory 220 can be completely tested. In addition, the memory test code TCODE of the embodiment of the present invention can be provided by a reliable (tested) external component, and therefore, the memory test code TCODE can determine the correct test code. The control unit 211 executes the memory test code TCODE to correctly perform the test operation of the dynamic memory 220, and the system integrated chip 210 does not have a The possibility of a reboot when the opportunity occurs.

Please refer to FIG. 3. FIG. 3 is a schematic diagram of a dynamic memory testing device according to another embodiment of the present invention. The dynamic memory testing device 300 includes a system integrated wafer 310. The system integrated chip 310 is coupled to the dynamic memory 320 and can perform a test action on the dynamic memory 320.

The system integrated chip 310 includes a control unit 311, an embedded memory device 312, and a connection interface 313. The in-cell memory device 312 of the present embodiment is coupled to the connection interface 313 and is connected to the external storage unit 330 through the connection interface 313. External storage unit 330 is another storage element than dynamic memory 320. The memory test code is pre-stored in the external storage unit 330, and the memory test code is provided to the embedded memory device 312 through the connection interface 313.

Incidentally, the connection interface 313 may be an internal system bus (Universal System Bus) or a Universal Serial Bus (USB) interface, and the external storage unit 330 may be, for example, a flash memory. In addition, in this embodiment, the system integrated chip 310 and the dynamic memory 320 may be on the same or different circuit boards as the external storage unit 330.

The connection interface 313 can be in the form of an internal system bus interface of the system-integrated chip 310. The memory test code in the external storage unit 330 (which can be constructed by a NAND or a NOR type flash memory) can be directly read and stored. The embedded memory device 312 of the wafer 310 is systematically integrated and provided by the control unit 311. Under such an architecture, the system integrated wafer 310 of the present embodiment, Both the dynamic memory 320 and the external storage unit 330 can be constructed on the same circuit board.

In addition, the connection interface 313 can also be coupled to the external USB interface form, and the memory test code is transmitted to the embedded memory device 312 of the system integrated chip 310 through the USB OTG (On-The-Go) interface. A controller 311 is provided to perform. It is worth mentioning that under such an architecture, an external USB-type connection interface 313 can be connected to an external storage unit 330 that is not disposed on the same circuit board.

Of course, the connection interface 313 can also include an internal system bus interface and an external USB interface, and the user can select a desired interface to connect according to requirements.

Please refer to FIG. 4, which illustrates an embodiment of a system-integrated wafer 400 in accordance with an embodiment of the present invention. The system-integrated wafer 400 includes a control unit 410 and an embedded memory device 420. The control unit 410 includes a central processing unit 411 and a dynamic memory controller 412. The embedded memory device 420 includes a static memory controller 421 and static memory 422.

The static memory controller 421 can externally read the memory test code TCODE and store the memory test code TCODE in the static memory 422. When the central processing unit 411 is to perform external dynamic memory testing, the central processing unit 411 can read the memory test code TCODE from the static memory 422 through the static memory controller 421, and the central processing unit 411 can borrow The external dynamic memory is tested by executing the memory test code TCODE.

In addition, when the dynamic memory is tested, the dynamic memory controller 412 can perform a test operation on the measured dynamic memory according to the execution action of the memory test code TCODE, for example, performing address setting on the measured dynamic memory. , data writing and data reading and other related actions.

It should be noted that the memory test action corresponding to the memory test code TCODE in this embodiment may be a dynamic memory test action well known to those skilled in the art without particular limitation.

In addition, please refer to FIG. 5. FIG. 5 is a schematic diagram showing the storage content of the static memory in the embodiment of the present invention. The static memory 422 can store the initialization information D1 about the dynamic memory and the test mode startup information D2 about the dynamic memory, in addition to the memory test program D3.

As can be seen from FIG. 5, when the central processing unit 411 is to perform a dynamic memory test operation, the initialization information D1 can be read from the static memory 422, whereby the central processing unit 411 can first measure the dynamics. The action of initializing the memory. Then, the central processing unit 411 reads the test mode start information D2 of the dynamic memory in the static memory 422, and starts the test operation of the measured dynamic memory by the test mode start information D2. Finally, the central processing unit 411 reads the memory test program D3 and performs a test action on the measured dynamic memory.

It is worth mentioning that, in the embodiment of the present invention, in addition to performing the data writing and the data reading verification action on the measured dynamic memory to test the dynamic memory, the dynamic memory to be tested can also be changed by initializing the information D1. Internal storage Take time information (such as changing the BITQ Delay Time (Bit line equalization Delay Time)) and/or change the core voltage of the dynamic memory to test. The test time of the memory can be shortened, and the test operation of the dynamic memory can be performed using different voltages.

Please refer to FIG. 6. FIG. 6 is a schematic diagram showing the logical address configuration of the dynamic memory testing device according to the embodiment of the present invention. In Figure 6, the area above the logical address 0x4000_0000 can be configured as the memory address used by the input/output device (I/O), and the logical address between 0x4000_0000 and 0x3000_0000 can correspond to the measured dynamic memory. The physical address of the body; between the logical addresses 0x3000_0000 to 0x1000_0000, the memory address used for the input/output device (I/O) and the logical address between 0x1000_0000 and 0x0001_0000 configured as the only memory. In addition, between logical addresses 0x0001_0000 to 0x0000_0000 is configured as an address used by the static memory in the embedded memory device.

In the address configuration mode of FIG. 6, the logical address 0x0001_0000 to 0x0000_0000 can be used to correspond to the physical address of the memory test code stored in the static memory. When the external dynamic memory is to be tested, the logical address can be set according to the memory test code between logical addresses 0x4000_0000 to 0x3000_0000, and corresponding to the physical address of the dynamic memory to be tested. And by this, the test dynamic memory is tested.

Please refer to FIG. 7. FIG. 7 illustrates a dynamic memory test according to an embodiment of the present invention. Flow chart. First, in step S710, a system integrated chip is provided, and the memory test code is stored in the embedded memory device of the system integrated chip, and when the dynamic memory to be tested is tested, In step S720, the memory test program is read by the embedded memory device, and in step S730, the dynamic memory is tested in accordance with the execution of the memory test program.

The implementation details in the embodiments of the present invention are described in detail in the foregoing embodiments and embodiments, and are not described in detail below.

It is worth mentioning that, through the test method of the dynamic memory described in the above embodiments, the test device and the test method of the system end can immediately pass through the dynamic memory when a situation in which the dynamic memory is found to be wrong occurs. The electronic fuse (e-Fuse) performs dynamic memory repairing actions to improve the proper rate of dynamic memory.

In summary, the present invention provides a memory test code by using a non-measurement dynamic memory as a storage medium, and stores the memory test code in an embedded memory device in the system integrated chip. When the external dynamic memory test operation is to be performed, the control unit in the system integrated chip executes the memory test code to perform a complete test operation on the measured dynamic memory. The important point is that the measured dynamic memory does not need to provide part of the storage area to store the memory test code, and all the dynamic memory storage areas can be tested during the test. In addition, the memory test code comes from a reliable storage medium, and the system integrated chip does not run the risk of crashing or restarting due to the execution of unreliable memory test code.

200‧‧‧Dynamic memory test device

210‧‧‧System Integrated Chip

220‧‧‧ Dynamic Memory

211‧‧‧Control unit

TCODE‧‧‧ memory test code

212‧‧‧Inline memory device

Claims (8)

A dynamic memory testing device includes: a system integrated chip coupled to the dynamic memory, comprising: a control unit coupled to the dynamic memory; and an embedded memory device for storing a memory The test code, wherein the control unit reads the memory test code and performs a test action on the dynamic memory by executing the memory test code. The dynamic memory test device of claim 1, further comprising: a connection interface coupled to the embedded memory device, wherein the embedded memory device is coupled by the connection interface An external storage unit, and the memory test code is read by the external storage unit. The dynamic memory testing device of claim 2, wherein the connection interface comprises at least one of an internal system bus interface and a universal serial bus interface. The dynamic memory testing device of claim 1, wherein the control unit comprises: a central processing unit; and a dynamic memory controller coupled to the central processing unit, wherein the central processing unit executes the The memory test code performs a test action on the dynamic memory through the dynamic memory controller. The dynamic memory testing device according to claim 1, wherein The embedded memory device includes: a static memory for storing the memory test code; and a static memory controller coupled to the static memory, the static memory controller receiving the memory test a code, and storing the memory test code in the static memory, the static memory controller reads the memory test code from the static memory to provide the memory test code to the central memory Processing unit. The dynamic memory testing device of claim 5, wherein the static memory further comprises initialization information for storing the dynamic memory and test mode startup information of the dynamic memory. A method for testing a dynamic memory, comprising: providing a system integrated chip, and storing a memory test code in an embedded memory device of the system integrated chip; the embedded memory device Reading the memory test program; and executing the memory test program to perform a test action on the dynamic memory. The method for testing a dynamic memory according to claim 7, wherein the step of storing the memory test code in the embedded memory device of the system integrated chip comprises: testing the memory The code is stored in an external storage unit outside the integrated chip of the system; the memory test code is read by the external storage unit through the integrated chip of the system, and the memory test code is stored in the embedded In a memory device.