CN102073568A - Method for testing system management bus - Google Patents
Method for testing system management bus Download PDFInfo
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- CN102073568A CN102073568A CN200910226133XA CN200910226133A CN102073568A CN 102073568 A CN102073568 A CN 102073568A CN 200910226133X A CN200910226133X A CN 200910226133XA CN 200910226133 A CN200910226133 A CN 200910226133A CN 102073568 A CN102073568 A CN 102073568A
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Abstract
The invention relates to a method for testing a system management bus, which is suitable for testing the system management bus of a mainboard, wherein the system management bus operates at a test clock frequency. The test method comprises the steps of: writing a test datum into a system management bus device at the test clock frequency; reading the test datum by utilizing the system management bus device; comparing the original test datum with the read test datum to obtain a test result; modifying the test clock frequency; and then executing the test method again at the modified test clock frequency.
Description
Technical field
(System Management Bus, test mode SMBus) is particularly about the test mode of a kind of SMBus of access SMBus device to the present invention relates to a kind of System Management Bus.
Background technology
Test job has accounted for a very part and parcel always in the production run of product.Because in process of production, very possible because some not specific factor cause producing product defective, producing therefore that the product of finishing all needs could shipment or listing through test.If do not pass through QC personnel's test, the product with flaw finally can be transported to the market and get on to peddle under the still unperceived situation of flaw.When the user buys these problematic products, not only can cause the constant of user, also can have a greatly reduced quality to the image of production company.
And for calculator system products such as server or notebook, most important parts be exactly central processing unit (Central Processing Unit, CPU) and the north bridge chips and the South Bridge chip that other interfacing equipment in the calculator system are offered central processing unit.Wherein, South Bridge chip can make central processing unit pass through System Management Bus (System Management Bus SMBus), carries out access to most interfacing equipment interface, multimedia controller and communication interface.In other words, if SMBus itself has flaw, can cause very large influence to whole calculator system.
Though SMBus should be listed in one of considerable test event in the calculator system, have some difficulties at the test of SMBus.Because SMBus is the internal bus of South Bridge chip, so can't SMBus be detected with the anchor clamps of outside.This also causes the running situation that is difficult to be learnt by the outside SMBus, and then causes test the time to be difficult to judge whether normal problem of SMBus running.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of System Management Bus (System Management Bus, SMBus) method of testing, providing the appropriate operating system core automatically, and do not need to select the operating system kernel that needs in the mode of artificial selection to counter with hardware informations such as different hardware specification or models.
In order to solve the problems of the technologies described above, the invention provides a kind of method of testing of System Management Bus, be applicable to a System Management Bus of test one motherboard, wherein this System Management Bus is with a test clock pulse frequency operation, this method of testing comprises: with this test clock pulse frequency, write a test data in a System Management Bus device; Read this test data by this System Management Bus device; This more original test data and this test data that reads are to obtain a test result; Revise this test clock pulse frequency; And, re-execute this method of testing with this test clock pulse frequency of revising.
The method of testing of said system management bus, its characteristics are, comprising: read a status register of this System Management Bus, to obtain a test mode.
The method of testing of said system management bus, its characteristics are that writing this test data with this test clock pulse frequency is to continue to write this test data in a write time in the step of this System Management Bus device.
The method of testing of said system management bus, its characteristics are that this test data comprises that one writes data.
The method of testing of said system management bus, its characteristics are that this test data comprises a plurality of data that write.
The method of testing of said system management bus, its characteristics are, write this test data at this after the step of this System Management Bus device with this test clock pulse frequency, and before this reads the step of this test data by this System Management Bus device, also comprise: wait for an interval time.
The method of testing of said system management bus, its characteristics are that this test data comprises a plurality of data that write.
The method of testing of said system management bus, its characteristics are that this System Management Bus device is that a serial exists a detection or an internal memory.
In sum, method according to the automatic installing operating system that the invention provides, it provides a plurality of operating system kernels and the hardware core table of comparisons by Storage Media, and Auto-Sensing needs the hardware information of the counter of installing operating system, again according to the hardware information check table to obtain suitable operating system kernel, be the counter installing operating system.Thus, can provide the appropriate operating system core automatically, and not need to select the operating system kernel of needs in the mode of artificial selection to counter with hardware informations such as different hardware specification or models.
Describe the present invention below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
Description of drawings
Fig. 1 implements the block schematic diagram of the motherboard of example for the present invention one;
Fig. 2 is the schematic flow sheet of the method for testing of the SMBus of the present invention's one enforcement example;
Fig. 3 is the schematic flow sheet of the method for testing of another SMBus that implements example according to the present invention;
Fig. 4 is the schematic flow sheet of the method for testing of the SMBus of another enforcement example according to the present invention; And
Fig. 5 is the schematic flow sheet of the method for testing of the SMBus of another enforcement example according to the present invention.
Wherein, Reference numeral:
20 motherboards
22 South Bridge chips
24 SMBus
26,26a, 26b SMBus device
Embodiment
Below in embodiment, be described in detail detailed features of the present invention and advantage, its content is enough to make those of ordinary skill in the art to understand technology contents of the present invention and implements according to this, and according to the disclosed content of this instructions, claim scope and accompanying drawing, any those of ordinary skills can understand purpose and the advantage that the present invention is correlated with easily.
(it is applicable to a SMBus of test one motherboard for System Management Bus, method of testing SMBus), and wherein SMBus is with a test clock pulse frequency operation to the invention provides a kind of System Management Bus.
Please refer to Fig. 1, it implements the block schematic diagram of the motherboard of example for the present invention one.As shown in Figure 1, have a South Bridge chip 22 on the motherboard 20, and a plurality of SMBus devices 26 that are electrical connected by SMBus 24 and South Bridge chip 22 are arranged.Wherein motherboard 20 can be configured in any calculator system, for example personal computer, server or notebook.And on the motherboard 20 in addition configurable have the central processing unit that is electrical connected with South Bridge chip 22 (Central Processing Unit, CPU, not shown) and a Basic Input or Output System (BIOS) (Basic Input/Output System, BIOS).
Central processing unit can be issued an order to a plurality of SMBus devices 26 such as SMBus device 26a on the motherboard 20 or SMBus device 26b by South Bridge chip 22 and SMBus.South Bridge chip 22 comprises most of interfacing equipment interfaces, multimedia controller and communication interface function.For example South Bridge chip 22 can be electrical connected in peripheral assembly interconnect (Peripheral Component Interconnect, PCI) controller, advanced technology attachment (Advanced Technology Attachment, ATA) controller, universal serial bus (Universal Serial Bus, USB) controller, network controller or sound effect control device.For example, South Bridge chip 22 can be the ICH9 chip that Intel company (Intel) is produced.
And SMBus 24 stems from the internal integration circuit (Inter-Integrated Circuit, I2C) bus is a kind of bus that is used for chip internal.In the 1995 defined buses of being made up of two barss, and SMBus 24 includes a frequency signal line (SMBCLK) and a two-way data signal line (SMBDATA) to the standard of SMBus 24 by Intel.SMBus 24 is with a test clock pulse frequency operation, and test clock pulse frequency can be at 100kHz (KHz) between the scope of 1MHz (MHz).
SPD is that (Electrically-Erasable Programmable Read-Only Memory EEPROM), is configured on the internal memory electronics erasable internal memory.SPD mainly is in order to assist a north bridge chips to adjust the physical parameter or the frequency parameter of internal memory.And there is the relevant information of internal memory SPD inside, for example the required voltage of internal memory running, OK/column address quantity or various main operating frequency.These information all can be read or revise by BIOS by SMBus 24.
The method of testing of SMBus provided by the invention is that the 26 couples of SMBus 24 of SMBus device that utilize motherboard to be measured 20 originally just to have test; So method of testing does not need additionally to connect outer clamp and can carry out.Next introduce a plurality of enforcement examples of the method for testing of SMBus, the step of utilizing 26 couples of SMBus 24 of original SMBus device to test with explanation.
Please refer to Fig. 2, it is the schematic flow sheet of the method for testing of the SMBus of the present invention's one enforcement example.As shown in Figure 2, the method for testing of SMBus can comprise step S40: write a test data in the SMBus device with test clock pulse frequency; Step S50: by SMBus device read test data; Step S60: more original test data and the test data that reads, to obtain a test result; And step S80: revise test clock pulse frequency.
In step S40, method of testing writes a SMBus device 26 with test clock pulse frequency with test data.At first for the base address (base address) of the SMBus controller that obtains SMBus 24, can inquire about the configuration space (configuration space) of perimeter component interconnect standard bus (Peripheral Component Interconnect bus, PCI bus).Data forms (data sheet) the traversal PCI that then cooperates inquiry South Bridge chip 22 is connected device (just the SMBus device 26) on the SMBus 24 to obtain all.Specify the SMBus device 26 pairing offset addresss of desiring to write (offset address) to the SMBus controller again, can utilize base address and offset address that specific SMBus device 26 is carried out access.
When test data is write SMBus device 26, can also can specify the frequency different to give SMBCLK with a motherboard frequency of motherboard 20 as test clock pulse frequency as test clock pulse frequency with the motherboard frequency.And can be one, test data writes data, or a plurality of data that write.One writes data and can be the data that length is 1 byte (byte) or 1 word group (word).The space that right different SMBus device 26 has different sizes can be used for method of testing.If desire to test with a plurality of data that write, then needing can eligibility with the SMBus device 26 with enough interior storage space.
As mentioned above, SMBus device 26 is motherboard 20 original devices.Although a plurality of SMBus devices 26 may be arranged simultaneously, select and have big storage area or internal data and often do not need by the SMBus device 26 of access for good.Be noted that, before SMBus device 26 is write data, should can not revise arbitrarily, in order to avoid cause the calculator system running unusual by desiring to write the connotation of the storage area or the buffer of test data in each device of understandings such as specifications.For example, the address of SPD inside is 0 or 256 places, or the address of BMC inside is that 0 or 256 places all can be used as and write the space and be applicable to step S40.Yet it is different according to SMBus device 26 can be used as the detailed physical address that writes the space, needs the specifications of inquiry SMBus device 26 correspondences before testing, and just can guarantee to test and can not cause the running of counter unusual.
Test data is write after the SMBus device 26, and method of testing reads the test data that has just write in step S50.Method of testing can be utilized the base address and the offset address of this SMBus device 26 that obtains at step S40, by reading out test data in the position that writes just now.The last test method compares original test data and the test data that reads out in step S60, and obtains test result.If the test data of being read by SMBus device 26 is identical with original test data, then being shown in has among step S40 and the S50 successfully by 24 pairs of SMBus devices of SMBus, 26 access test data.That is to say, thus, can learn that SMBus 24 runnings are normal.
After step S70 finished once test, method of testing more can be revised test clock pulse frequency in step S80, repeat test with new test clock pulse frequency again with step S40.That is to say that the method for testing of SMBus can be readjusted test clock pulse frequency again and test in the scope of 100kHZ to 1MHZ, can correctly operate under the various again clock pulse frequencies to guarantee SMBus 24.
Next please refer to Fig. 3, it is the schematic flow sheet of the method for testing of another SMBus that implements example according to the present invention.As shown in Figure 3, the method for testing of SMBus can comprise step S45: continue to write test data in the SMBus device in a write time with test clock pulse frequency; Step S50: by SMBus device read test data; Step S60: more original test data and the test data that reads, to obtain a test result; Step S70: read the status register (status register) of SMBus, to obtain a test mode; And step S80: revise test clock pulse frequency.
The difference of step S45 and step S40 is: step S45 is in the write time, continues to write test data to SMBus device 26.Write time can for example be 5 seconds or 10 seconds.Be noted that to have enough interior storage space to store the test data that continues to write in order to the SMBus device of testing 26.In addition, also test data can be divided into a plurality of parts, and in the write time, write different SMBus devices 26 one by one.S50 reads test data according to write sequence again in step, for step S60 relatively.By continuing to write the method for test data, can test out SMBus 24 and whether can continue correctly to transmit data within a certain period of time with SMBus 24.
After step S50 also reads test data constantly,, and obtain test result in step S60 more original test data and the test data that reads out.More preferably, the method for testing of SMBus also comprises: step S70, read the status register of SMBus 24, to obtain test mode.The status register of SMBus 24 can be configured among the South Bridge chip 22, and test mode can be the operating state of SMBus 24.Test mode can represent for example whether SMBus 24 is in busy state, or whether the buffer of SMBus controller makes a mistake.
ICH9 chip with Intel is an example, 0 * 01 bit representation host_busy of status register; 0x04 bit representation devce_error; 0 * 08 expression smbus error register; 0 * 10 expression hostcontroller register error.
Therefore, by reading the status register of SMBus 24, method of testing does not need the detecting device or the anchor clamps of any outside, just can be accurately and intactly control the situation of SMBus 24.And in order to control the situation of SMBus 24, whether the test result that no matter obtains in step S60 is correct, but method of testing execution in step S70 all.And method of testing also can be revised test clock pulse frequency in step S80, repeats test with new test clock pulse frequency again.
Please refer to Fig. 4, it is the schematic flow sheet of the method for testing of the SMBus of another enforcement example according to the present invention.As shown in Figure 4, the method for testing of SMBus can comprise step S40: write test data in the SMBus device with test clock pulse frequency; Step S50: by SMBus device read test data; Step S55: wait for an interval time; Step S60: more original test data and the test data that reads, to obtain a test result; Step S70: read the status register (status register) of SMBus, to obtain test mode; Step S80: revise test clock pulse frequency.
The difference of the enforcement example of present embodiment and Fig. 3 is: step S55, after SMBus write data, method of testing was waited for the spacer segment time, reads the test data that writes again.Can for example be 10 milliseconds (ms) interval time, and in interval time, the right to use of SMBus 24 can be given the program beyond the method for testing.Thus, just can be under the situation of discontinuous use SMBus 24 accesses, whether test SMBus 24 can normal operation.The step S55 of method of testing also can use with step S45 collocation; And as mentioned above, test data can be one or a plurality of data that write, with the required project of flexible test.
Then please refer to Fig. 5, it is the schematic flow sheet of the method for testing of the SMBus of the another enforcement example of the present invention.As shown in Figure 5, the method for testing of SMBus can comprise step S40: write test data in the SMBus device with test clock pulse frequency; Step S50: by SMBus device read test data; Step S60: more original test data and the test data that reads, to obtain a test result; Step S70: read the status register (status register) of SMBus, to obtain test mode; And step S80: revise test clock pulse frequency.
After step S70 finished once test, method of testing was revised test clock pulse frequency in step S80, repeats test with new test clock pulse frequency again with step S40.Thus, method of testing can obtain higher correctness.
In sum, the method for testing of SMBus provided by the invention writes test data by SMBus to be measured original SMBus device on motherboard, and the read test data also relatively obtain test result from the SMBus device again.By using original SMBus device dexterously, method of testing need not used outer clamp need not install detecting device additional yet and just can the SMBus of internal bus be tested.And, be enough to judge fully the content of the mistake of finding in the test process and infer error reason according to this according to the content of status register.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection domain of claim of the present invention.
Claims (8)
1. the method for testing of a System Management Bus is applicable to a System Management Bus of testing a motherboard, and wherein this System Management Bus is with a test clock pulse frequency operation, and this method of testing comprises:
With this test clock pulse frequency, write a test data in a System Management Bus device;
Read this test data by this System Management Bus device;
This more original test data and this test data that reads are to obtain a test result;
Revise this test clock pulse frequency; And
Re-execute this method of testing with this test clock pulse frequency of revising.
2. according to the method for testing of claim 1 a described System Management Bus, it is characterized in that, comprising:
Read a status register of this System Management Bus, to obtain a test mode.
3. the method for testing of System Management Bus according to claim 1 is characterized in that, writing this test data with this test clock pulse frequency is to continue to write this test data in a write time in the step of this System Management Bus device.
4. the method for testing of System Management Bus according to claim 1 is characterized in that, this test data comprises that one writes data.
5. the method for testing of System Management Bus according to claim 1 is characterized in that, this test data comprises a plurality of data that write.
6. the method for testing of System Management Bus according to claim 1, it is characterized in that, write this test data at this after the step of this System Management Bus device with this test clock pulse frequency, and before this reads the step of this test data by this System Management Bus device, also comprise:
Wait for an interval time.
7. the method for testing of System Management Bus according to claim 6 is characterized in that, this test data comprises a plurality of data that write.
8. the method for testing of System Management Bus according to claim 1 is characterized in that, this System Management Bus device is that a serial exists a detection or an internal memory.
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| CN200910226133XA CN102073568A (en) | 2009-11-20 | 2009-11-20 | Method for testing system management bus |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108279929A (en) * | 2016-12-30 | 2018-07-13 | 技嘉科技股份有限公司 | Memory body clock frequency method of adjustment, motherboard and computer operating system |
| CN108536557A (en) * | 2018-04-02 | 2018-09-14 | 郑州云海信息技术有限公司 | A kind of server S MBUS scanning means and method |
| CN111930582A (en) * | 2020-08-17 | 2020-11-13 | 成都海光微电子技术有限公司 | System management bus detection platform, processor and system management bus detection method |
-
2009
- 2009-11-20 CN CN200910226133XA patent/CN102073568A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108279929A (en) * | 2016-12-30 | 2018-07-13 | 技嘉科技股份有限公司 | Memory body clock frequency method of adjustment, motherboard and computer operating system |
| CN108536557A (en) * | 2018-04-02 | 2018-09-14 | 郑州云海信息技术有限公司 | A kind of server S MBUS scanning means and method |
| CN111930582A (en) * | 2020-08-17 | 2020-11-13 | 成都海光微电子技术有限公司 | System management bus detection platform, processor and system management bus detection method |
| CN111930582B (en) * | 2020-08-17 | 2024-08-06 | 成都海光微电子技术有限公司 | System management bus detection platform, processor and system management bus detection method |
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Application publication date: 20110525 |