JP2006227668A - Memory model, program and logic circuit verification method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a convenient memory model that increases the efficiency of debugging a logic circuit. <P>SOLUTION: The memory model 22 compares an actual value of accessed address output from an ASIC 10 (memory accessing logic circuit) when the ASIC 10 accesses the memory model 22 with a preset expected value of accessed address to check whether or not both values match, and if both values do not match, reports error information including the actual value of accessed address and the expected value of accessed address. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a memory model having a function equivalent to the memory for verifying a logic circuit such as an ASIC (Application Specific Integrated Circuit) that accesses the memory, a program for causing a computer to realize the function as the memory model, And a logic circuit verification method in the memory model.

As a data processing apparatus such as an image forming apparatus, in addition to a CPU (central processing unit) that controls the entire apparatus and a memory such as a RAM that is used when the CPU processes data, a dedicated logic for accessing the memory Some have a circuit (such as an ASIC).
Such a logic circuit outputs (issues) an address to be accessed, a mask signal, or data when executing access to the memory, but due to a bug (error) in the circuit, an abnormal address, mask signal, or Data may be output.

Therefore, before the logic circuit is mounted on the data processing device, the logic circuit is verified by a computer or a dedicated device to find a bug and perform a debugging process to correct the bug.
As a logic circuit verification (design verification) apparatus and verification method, for example, there is one found in Patent Document 1.
JP 2003-150662 A

However, in the conventional logic circuit verification (design verification) apparatus and verification method, the verification result is output. However, the error occurrence location and the error content in the logic circuit cannot be immediately identified from the verification result. The debugging process could not be performed efficiently.
The present invention has been made in view of the above points, and an object thereof is to improve the efficiency of debug processing for a logic circuit.

In order to achieve the above object, the present invention provides a memory model, a program, and a logic circuit verification method.
A memory model according to a first aspect of the present invention is a memory model having a function equivalent to that of the memory for verifying a logic circuit that accesses the memory, and when the logic circuit performs access to the memory model, An actual value of the access target address to be output is compared with a preset expected value of the access target address to check whether or not both values match, and both the above-mentioned addresses are checked by the address check unit. When it is determined that the values do not match, there is provided error notifying means for notifying error information including the actual value of the access target address and the expected value of the access target address at that time.

  A memory model according to a second aspect of the present invention is a memory model having a function equivalent to that of the memory for verifying a logic circuit that accesses the memory, and when the logic circuit executes a write access to the memory model, the logic circuit The mask signal check means for comparing the actual value of the mask signal output from the value and the preset expected value of the mask signal to check whether or not both values match, and the mask signal check means When it is determined that the two values do not match, there is provided error notifying means for notifying error information including the actual value of the mask signal and the expected value of the mask signal at that time.

A memory model according to a third aspect of the invention is a memory model having a function equivalent to that of the memory for verifying a logic circuit that accesses the memory, and the logic circuit is executed when the logic circuit executes a write access to the memory model. The data check means for comparing the actual value of the data output from the data and the preset expected value of the data to check whether the two values match, and the two values match by the data check means When it is determined that the error is not to be performed, error notification means is provided for notifying error information including the actual value of the data at that time and the expected value of the data.
A program according to a fourth aspect of the invention is a program for causing a computer to realize the functions as the respective means constituting the memory model of any one of the first to third aspects.

  A logic circuit verification method according to a fifth aspect of the present invention is a logic circuit verification method in a memory model having a function equivalent to that of the memory for verifying a logic circuit that accesses the memory. When the access is executed, the actual value of the access target address output from the logic circuit is compared with the preset expected value of the access target address to check whether or not both values match. In this case, error information including the actual value of the access target address and the expected value of the access target address at that time is notified.

  A logic circuit verification method according to a sixth aspect of the present invention is a logic circuit verification method in a memory model having a function equivalent to that of the memory for verifying a logic circuit that accesses the memory. The actual value of the mask signal output from the logic circuit at the time of write access is compared with the preset expected value of the mask signal to check whether or not the two values match. In this case, error information including the actual value of the mask signal at that time and the expected value of the mask signal is notified.

  A logic circuit verification method according to a seventh aspect of the present invention is a logic circuit verification method in a memory model having a function equivalent to that of the memory for verifying a logic circuit that accesses the memory. When the write access is executed, the actual value of the data output from the logic circuit is compared with the preset expected value of the data to check whether the two values match. The error information including the actual value of the data at that time and the expected value of the data is notified.

  According to the present invention, the actual value of the access target address output from the logic circuit and the preset expected value of the access target address when the logic circuit (logic circuit for memory access) executes access to the memory model. By comparing the two values and checking whether or not both values match, and if both values do not match, by notifying error information including the actual value of the access target address and the expected value of the access target address at that time The error occurrence location and error content in the logic circuit can be immediately identified from the content of the error information, and the debugging process for the logic circuit can be performed efficiently.

  Alternatively, when the logical circuit performs a write access to the memory model, the actual value of the mask signal output from the logic circuit is compared with the preset expected value of the mask signal to determine whether the two values match. If the two values do not match, the error information location including the actual value of the mask signal and the expected value of the mask signal at that time is also notified from the content of the error information. The error contents can be immediately identified, and the debugging process for the logic circuit can be performed efficiently.

  Alternatively, when a write access to the memory model is performed by the logic circuit, the actual value of the data output from the logic circuit is compared with the preset expected value of the data to check whether both values match. If the two values do not match, the error information including the actual value of the data and the expected value of the data at that time can be notified from the contents of the error information. Can be immediately identified, and the debugging process for the logic circuit can be performed efficiently.

The best mode for carrying out the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram showing a configuration example of an ASIC as a logic circuit to be verified of a memory model for implementing the present invention.

  The ASIC 10 includes a CPU / I / F (interface) controller 11, a memory arbiter 12, a memory control unit 13, a compression / decompression unit 14, a rotator 15, write DMA controllers 16 and 17, and read DMA controllers 18 and 19. This is a logic circuit (multifunctional device board) that is an IC circuit that supports sharing of devices to be controlled by the CPU 1 to be described later, and supports high efficiency in the development of applications (application software) from the viewpoint of architecture. .

The ASIC 10, together with the CPU 1 and the memory 2, is an image reading device such as a data processing device such as a digital copying machine, a printer, a facsimile device, a scanner, or a digital multifunction device that integrates the functions of these devices. Installed in the device.
The CPU / I / F / controller 11 is an interface circuit that controls communication with the CPU 1.
The memory arbiter 12 performs arbitration for input / output requests from the CPU / I / F / controller 11, memory control unit 13, write DMA controllers 16 and 17, and read DMA controllers 18 and 19, and inputs / outputs data This is an arbitration circuit.

The memory control unit 13 is a control circuit that controls input / output of signals and data between the memory 2 and the memory arbiter 12 used when the CPU 1 processes data.
The compression / decompression unit 14 is a circuit that compresses data from the read DMA controller 18 and outputs the compressed data to the write DMA controller 16.
The rotator 15 is a circuit that rotates the data from the read DMA controller 19 and outputs it to the write DMA controller 17.

The write DMA controller 16 issues a write address (access target address) and a mask signal (a signal indicating whether or not data can be written) to the memory 2 via the memory arbiter 12 and the memory control unit 13. This is a circuit for executing write access for writing data from the compression / decompression unit 14 to the memory 2.
The write DMA controller 17 issues a write access for writing data from the rotator 15 to the memory 2 by issuing a write address and a mask signal to the memory 2 via the memory arbiter 12 and the memory control unit 13. Circuit.

The read DMA controller 18 issues a read address to the memory 2 via the memory arbiter 12 and the memory control unit 13, thereby executing read access for reading the data in the memory 2 and outputting it to the compression / decompression unit 14. Circuit.
The read DMA controller 19 issues a read address to the memory 2 via the memory arbiter 12 and the memory control unit 13, thereby executing read access for reading data in the memory 2 and outputting it to the rotator 15. Circuit.

  The CPU 1 is a central processing unit that comprehensively controls the entire data processing device (actual machine) according to a program in the memory 2. The CPU 1 sets a register value including a start address and a transfer size (data size) for the write DMA controllers 16 and 17 or the read DMA controllers 18 and 19 so that the write DMA controllers 16 and 17 store the memory 2. The write DMA can be executed, and the read DMA controllers 18 and 19 can execute read access to the memory 2.

  The memory 2 is a storage medium that stores various programs (software) including a plurality of application programs and data. As the memory 2, a RAM, a hard disk device (HDD) including a hard disk, a flexible disk device provided with a removable flexible disk, or MO, CD-R, CD-RW, DVD + R, DVD + RW, DVD-R, DVD- An optical disk device equipped with a removable optical disk such as RW or DVD-RAM can be used.

FIG. 2 is a block diagram showing a configuration example of an ASIC test bench including the memory model for implementing the present invention and the ASIC 10 shown in FIG.
The ASIC 10 shown in FIG. 1 needs to be verified (sumilane) before being mounted on a data processing apparatus as a product.
Therefore, when verifying the ASIC 10, as shown in FIG. 2, the CPU model 21 having the same function as the CPU 1 of FIG. Memory models 22 having functions equivalent to those of the memory 2 are connected to each other.

  Here, the environment for verification of the ASIC 10 is constructed as a virtual system including the ASIC 10 to be verified. Among them, the CPU model 21 is virtually created as a CPU that is planned to be connected to the ASIC 10 in the data processing device (actual machine), and the memory model 22 is virtually created as a memory that is scheduled to be connected to the ASIC 10 in the data processing device. is doing.

Therefore, the test bench includes a program for causing a computer such as a personal computer to implement a virtual system including the CPU model 21, the memory model 22, and the test scenario (verification program) 23, and the computer.
The CPU model 21 and the memory model 22 perform processing related to the verification of the ASIC 10 according to the test scenario 23.
Therefore, the memory model 22 functions as an address check unit, a mask signal check unit, a data check unit, and an error notification unit.
Note that the CPU model 21 or the memory model 22 can be configured only by hardware.

Next, verification processing of the ASIC 10 by the test bench shown in FIG. 2 will be specifically described with reference to FIGS.
FIG. 3 is a flowchart showing a first example of the verification process of the ASIC 10 by the test bench.

In step S 1, a start address and a transfer address are set in the DMA controller (any of the write DMA controllers 16 and 17 and the read DMA controllers 18 and 19) in the ASIC 10 through the CPU model 21 according to the test scenario 23.
In step S 2, the register value such as the start address and transfer size set in the DMA controller in the ASIC 10 is transferred to the memory model 22 from the test scenario 23. The memory model 22 calculates (predicts) an expected value of the access target address to be output from the ASIC 10 based on the received register value.

In step S 3, the DMA controller is activated via the CPU model 21 from the test scenario 23. As a result, the DMA controller executes access to the memory model 22 (which may be either write access or read access). At this time, the access target address (write address or read address) is given to the memory model 22. Issue.
In step S4, the memory model 22 prepares in advance the expected value of the access target address calculated based on the register value received in step S2, and compares it with the actual value of the access target address issued by the ASIC 10. To check whether both values match.

In step S5, when it is determined that the two values do not match, a message to that effect is displayed on a display device (not shown). That is, error information (for example, “### Error Memory address = 0x1000 (exp 0x1004)”) including the actual value of the access target address that did not match at that time and the expected value of the access target address is displayed on a computer (not shown) Display (notify) on the device (display).
In step 6, the verification processing (simulation) of the ASIC 10 is stopped (for example, “$ stop or $ finish for Verilog”).

FIG. 4 is a flowchart showing a second example of the verification process of the ASIC 10 by the test bench.
In step S 11, a start address and a transfer address are set in the write DMA controller (which may be either the write DMA controller 16 or 17) in the ASIC 10 through the CPU model 21 according to the test scenario 23.

In step S 12, the register value such as the start address and transfer size set in the write DMA controller in the ASIC 10 is transferred to the memory model 22 from the test scenario 23. The memory model 22 calculates an expected value of the mask signal to be output from the ASIC 10 based on the received register value.
In step S13, the write DMA controller is activated via the CPU model 21 from the test scenario 23. As a result, the write DMA controller performs a write access to the memory model 22 and issues a mask signal to the memory model 22 at that time.

In step S14, the memory model 22 prepares in advance the expected value of the mask signal calculated based on the register value received in step S12, and compares it with the actual value of the mask signal issued by the ASIC 10. Check if both values match.
In step S15, if it is determined that the two values do not match, a message to that effect is displayed on a display device (not shown). That is, error information including the actual value of the mask signal that did not match at that time and the expected value of the mask signal (for example, "### Error Memory write mask = 4'b1000 (exp 4'b1100) address = 0x10000") Is displayed on the display device of the computer.
In step 16, the verification processing (simulation) of the ASIC 10 is stopped (for example, “$ stop or $ finish for Verilog”).

FIG. 5 is a flowchart showing a third example of the verification process of the ASIC 10 by the test bench.
In step S21, a start address and a transfer address are set in the write DMA controller (which may be either of the write DMA controllers 16 and 17) in the ASIC 10 through the CPU model 21 according to the test scenario 23.

In step S 22, the register value such as the start address and transfer size set in the write DMA controller in the ASIC 10 is passed to the memory model 22 from the test scenario 23. The memory model 22 calculates an expected value of data to be output from the ASIC 10 based on the received register value.
In step S23, the write DMA controller is activated from the test scenario 23 via the CPU model 21. As a result, the write DMA controller executes write access to the memory model 22 and issues data to the memory model 22 at that time.

In step S24, the memory model 22 prepares in advance the expected value of the data calculated based on the register value received in step S22, compares it with the actual value of the data issued from the ASIC 10, and both values Check if they match.
In step S25, if it is determined that the two values do not match, a message to that effect is displayed on a display device (not shown). In other words, error information (for example, “### Error Memory write data = 0x1234 (exp 0xffe4) address = 0x10014”) including the actual value of the mismatched data and the expected value of the data is displayed on the computer display device. indicate.
In step 26, the verification processing (simulation) of the ASIC 10 is stopped (for example, “$ stop or $ finish for Verilog”).

  When error information is displayed on the display device by the verification process shown in FIGS. 3 to 5, the verification time (elapsed time from when the verification process of the ASIC 10 is started until an error occurs) is set to a clock or ns or the like. Can be displayed simultaneously in any unit. In addition, the error information can be output by a sound device (not shown).

  As described above, when the memory model 22 performs an access to the memory model 22 by the ASIC 10 (memory access logic circuit), the actual value of the access target address output from the ASIC 10 and the access target address set (calculated) in advance. The expected value of the access target address is checked to see if both values match. If the two values do not match, error information including the actual value of the access target address and the expected value of the access target address at that time is displayed. By notifying, it is possible to immediately identify the error occurrence location and the error content in the ASIC 10 from the content of the error information, and the debugging process for the ASIC 10 can be performed efficiently.

  Alternatively, the memory model 22 compares the actual value of the mask signal output from the ASIC 10 and the preset expected value of the mask signal when the ASIC 10 performs a write access to the memory model, and whether or not both values match. If the two values do not match, error information including the actual value of the mask signal at that time and the expected value of the mask signal is also notified, and an error occurs in the ASIC 10 from the content of the error information. The location and error content can be immediately identified, and the debugging process for the ASIC 10 can be performed efficiently.

Alternatively, the memory model 22 compares the actual value of the data output from the ASIC 10 when the ASIC 10 executes the write access to the memory model and the preset expected value of the data to determine whether the two values match. When the two values do not match, the error information including the actual value of the data and the expected value of the data at that time is also notified from the contents of the error information. The contents can be immediately identified, and the debugging process for the ASIC 10 can be performed efficiently.
As described above, the embodiment in which the present invention is applied to the test bench including the memory model for verifying the ASIC has been described. However, the present invention is not limited thereto, and the present invention is also applied to the test bench including the memory model for verifying the logic circuit other than the ASIC. Is possible.
The program according to the present invention is a program for causing a computer functioning as a memory model to realize various functions according to the present invention (address check means, mask signal check means, data check means, and error notification means). By causing a computer to execute such a program, the above-described effects can be obtained.

Such a program may be stored in a storage means such as a ROM or HDD from the beginning, but a non-volatile recording medium (memory such as a CD-ROM or flexible disk, SRAM, EEPROM, or memory card) as a recording medium. ) Can be recorded and provided. Each procedure described above can be executed by causing a computer to execute a program recorded in the memory or causing the computer to read and execute the program from the memory.
Furthermore, it is also possible to download and execute an external device that is connected to a network and includes a recording medium that records the program, or an external device that stores the program in a storage unit.

  As is apparent from the above description, according to the present invention, an error occurrence location and error content in a logic circuit can be immediately identified, and a debugging process for the logic circuit can be performed efficiently. Therefore, if the present invention is used, a convenient memory model can be provided.

It is a block diagram which shows the structural example of ASIC as a logic circuit of the verification object of the memory model which implements this invention. It is a block diagram which shows the structural example of the ASIC test bench containing the memory model and ASIC which implements this invention. It is a flowchart which shows the 1st example of the ASIC verification process by the test bench shown in FIG. It is a flowchart which similarly shows the 2nd example of an ASIC verification process. It is a flowchart which similarly shows the 3rd example of an ASIC verification process.

Explanation of symbols

1: CPU 2: Memory 10: ASIC 11: CPU / I / F / Controller 12: Memory Arbiter 13: Memory Control Unit 14: Compression / Expansion Unit 15: Rotator 16, 17: Write DMA Controller 18, 19: Read DMA Controller 21: CPU model 22: Memory model 23: Test scenario

Claims (7)

A memory model having a function equivalent to the memory for verifying a logic circuit that accesses the memory,
Compares the actual value of the access target address output from the logic circuit and the preset expected value of the access target address when the logic circuit performs access to the memory model, and whether both values match Address checking means to check,
Error notification means for notifying the error information including the actual value of the access target address at that time and the expected value of the access target address when it is determined by the address check means that the two values do not match; A memory model characterized by A memory model having a function equivalent to the memory for verifying a logic circuit that accesses the memory,
Compare the actual value of the mask signal output from the logic circuit with the expected value of the mask signal set in advance when the logical circuit performs a write access to the memory model, and determine whether the two values match. Mask signal checking means for checking,
Error notification means for notifying the error information including the actual value of the mask signal at that time and the expected value of the mask signal when the mask signal check means determines that the two values do not match. A featured memory model. A memory model having a function equivalent to the memory for verifying a logic circuit that accesses the memory,
When the logical circuit performs a write access to the memory model, the actual value of data output from the logic circuit is compared with a preset expected value of the data to check whether the two values match. Data check means,
Error notification means for notifying the error information including the actual value of the data at that time and the expected value of the data when the data check means determines that the two values do not match. Memory model.   The program for making a computer implement | achieve the function as each means which comprises the memory model as described in any one of Claims 1 thru | or 3. A logic circuit verification method in a memory model having a function equivalent to the memory for verifying a logic circuit that accesses the memory,
Whether or not both values match by comparing the actual value of the access target address output from the logic circuit and the preset expected value of the access target address when executing the access to the memory model by the logic circuit A logic circuit verification method in a memory model, characterized in that, when both values do not match, error information including an actual value of the access target address and an expected value of the access target address at that time is notified. A logic circuit verification method in a memory model having a function equivalent to the memory for verifying a logic circuit that accesses the memory,
Compare the actual value of the mask signal output from the logic circuit with the expected value of the mask signal set in advance when the write access to the memory model is executed by the logic circuit and check whether both values match When the two values do not coincide with each other, error information including an actual value of the mask signal at that time and an expected value of the mask signal is notified. A logic circuit verification method in a memory model having a function equivalent to the memory for verifying a logic circuit that accesses the memory,
Compares the actual value of the data output from the logic circuit and the preset expected value of the data when performing a write access to the memory model by the logic circuit, and checks whether both values match, A method of verifying a logic circuit in a memory model, characterized in that, when the two values do not match, error information including an actual value of the data at that time and an expected value of the data is notified.

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