JP2011059953A - Logic verification device and logic verification method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a logic verification device verifying a logic in accordance with memories of various specifications, without omitting a corner case. <P>SOLUTION: The logic verification device 100 is configured to verify a logic of a memory controller 106 which converts a first command issued by a CPU into a second command, and supplies it to a memory 107. The logic verification device 10 is provided with: a memory specification information storage means 103 for storing specification information of the memory 107; an expected value generation means 108 for generating an expected value of the second command converted from the first command according to address association information in the specification information; a command issuing means 101 for issuing the first command to the memory controller 106; and a monitoring means 104 for monitoring the second command converted from the first command by the memory controller 106, and for comparing it with the expected value. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a logic verification apparatus and a logic verification method for verifying a memory controller that accesses a memory such as DDR.

  In order to access memory chips mounted on various information processing apparatuses, an access request (writing or reading to the memory) to the memory generated from the CPU is made an access request (address designation, access) adapted to the memory circuit. Unit). The memory controller performs this conversion. Since this memory controller performs a logical operation for converting an access request such as an address, it is necessary to perform a logical verification for verifying whether the logical operation is properly performed at the time of designing or testing for verifying the design. (For example, refer to Patent Document 1).

  Japanese Patent Application Laid-Open No. 2004-133867 discloses a technique for logically verifying a memory control circuit using a transaction generated on a system bus by an access requested by a CPU and a transaction generated by a memory model in response to an access from the memory control circuit. It is disclosed.

  However, logic verification of a memory controller of a large capacity memory such as DDR-SDRAM (Double Date Rate Synchronous Dynamic Random Access) is performed internally by combining a large capacity address and command, or externally. Needs to be executed in combination with various DDR-SDRAM types and DDR-SDRAM frequencies, etc., and the number of logic verification items is enormous, and the contents of logic verification are large.

  Conventionally, the logic verification environment and the logic verification scenario tend to depend on the contents (processing contents, logic path, etc.) of the verification target (DUT: Design Under Test). In other words, the logic verification scenario often depends on how the DUT is created, such as verifying the boundary of a certain address from the structure of the DUT. For this reason, for example, the contents of the DUT are used as they are for the generation of expected values (data that will be output when the DUT is normal) (it is natural that the expected values match the test results). ), There was a problem that the original failure could not be detected.

  In the logic verification scenario, it is verified whether or not the output of the DUT when the user side command is input (access request) is correct. Even if it is carried out randomly, it is difficult to verify sufficiently. For example, in each mode (frequency, burst mode, etc.) of each memory, it becomes difficult to generate user-side commands without omissions for memory delimiters (address boundaries, CS boundaries, BANK boundaries, etc.). ing.

  In the verification method described in Patent Document 1, it is assumed that the user side command and the memory side command are one-to-one. However, generally the memory controller has burst access, and the number of commands on the memory side may vary depending on the bus width between the user side and the memory controller and the relationship between the memory bus width. Therefore, the user side command and the memory side command are not necessarily one-to-one. In this case, it is difficult to determine whether or not the user-side command is correctly converted into a plurality of memory-side commands using only the address output from the memory controller.

  It is an object of the present invention to provide a logic verification apparatus and a logic verification method that enable logic verification corresponding to memories of various memory standards and that can perform logic verification without leaving a corner case.

  In view of the above problems, the present invention is a logic verification device 100 that verifies the logic of the memory controller 106 that converts the first command issued by the CPU into the second command and supplies the second command to the memory 107. A memory standard information storage unit 103 that stores the standard information, an expected value generation unit 108 that generates an expected value of the second command converted from the first command according to the address correspondence information included in the standard information, A command issuing unit 101 for issuing the command to the memory controller 106, and a monitoring unit 104 that monitors the second command converted from the first command by the memory controller 106 and compares it with an expected value. To do.

  To provide a logic verification device and a logic verification method that enable logic verification corresponding to memories of various memory standards and that can perform logic verification without leaving a corner case.

It is an example of the whole block diagram of a logic verification apparatus. It is an example of the figure which shows the production | generation of an expected value typically. It is a figure which illustrates an example of an address table typically. It is an example of the flowchart figure which shows the procedure in which an expected value production | generation model produces | generates an expected value by converting a user side command into a memory side command. It is an example of the figure which shows the verification by a monitor model typically. It is an example of the figure which shows the production | generation of a scenario (user side command) typically. It is an example of the flowchart figure which shows the procedure in which the command generation model produces | generates the user side command which covered the address near a boundary. An example of the flowchart figure which shows the procedure in which a logic verification apparatus performs logic verification is shown.

Hereinafter, modes for carrying out the present invention will be described.
The logic verification apparatus 100 of this embodiment reduces the load of expected value generation by automatically generating an expected value that will be output when the DUT (Design Under Test) is normal from the memory standard. In addition, by automatically generating from the memory standard, the range of logic verification that can cover the expected value is wider than generating the expected value depending on the contents of the DUT, and logic verification corresponding to memories of various memory standards can be performed. It becomes possible. Further, even if an address randomly selected from a large number of addresses is input, logic verification can be performed. That is, not only the expected value is automatically generated from the specified user side command, but also logic verification in a random scenario becomes possible.

  In addition, by creating the logic verification scenario and the expected value for the result based on the memory standard, the verification target can be clarified and defects caused by misunderstanding of specifications can be reduced without being influenced by the contents of the DUT. it can.

  In addition, the logic verification device 100 according to the present embodiment automatically extracts memory delimiter positions (address boundary, CS boundary, BANK boundary, etc.) from the memory standard, and comprehensively includes user-side commands corresponding to the delimiter positions. To generate. As a result, the corner verification of the logic verification items (verification items that tend to be overlooked) can be logically focused, so that logic verification without omission becomes possible.

  And, by performing logic verification in parallel using user-side commands corresponding to automatically generated corner cases and randomly generated user-side commands, more logic verification scenarios can be implemented in a short period of time. , DUT quality can be improved.

  FIG. 1 shows an example of an overall configuration diagram of the logic verification device 100. The logic verification device 100 includes a scenario storage unit 105, a memory standard parameter storage unit 103, a command transmission / control model 101, a command generation model 102, an expected value generation model 108, a verification target (DUT) 106, a DDR-SDRAM opposing model 107, And a monitor model 104. The scenario storage unit 105 is connected to the command transmission / control model 101, the memory standard parameter storage unit 103, the expected value generation model 108, and the command generation model 102. The command transmission / control model 101 is connected to the verification target 106, the command generation model 102, the expected value generation model 108, and the monitor model 104. The command generation model 102 and the expected value generation model 108 are connected to the monitor model 104. The verification target 106 is connected to the monitor model 104 and the DDR-SDRAM opposing model 107.

  The logic verification apparatus 100 is a computer, and includes a CPU, RAM, ROM, HDD, ASIC, bus, and the like (not shown). The logic verification device 100 includes an input device such as a mouse and a keyboard, a display for displaying the result of logic verification, and a NIC (Network Interface Card) connected to a network such as the Internet or a LAN. In addition, a program to be executed by the CPU is stored in the ROM or the HDD. This program is stored in a storage medium such as a memory card and distributed, or distributed from a server (not shown) via the NIC.

  The scenario storage unit 105 and the memory standard parameter storage unit 103 are mounted on a computer RAM, HDD, or the like. The command transmission / control model 101, the command generation model 102, the expected value generation model 108, the monitor model 104, and the DDR-SDRAM opposite model 107 are provided by, for example, a function block generated by an emulator or a CPU executing a program. Function block. The verification target 106 is preferably a real machine, but may also be provided by an emulator or CPU executing a program in the same manner.

  The verification target 106 is, for example, a memory control circuit or a memory controller. The verification target 106 generates a memory side command from the user side command and supplies the memory side command to the DDR-SDRAM opposing model 107, and receives a response corresponding to the memory side command from the DDR-SDRAM opposing model 107.

  The verification of the verification target 106 will be briefly described. The command transmission / control model 101 transmits a user side command to the verification target 106. The verification target 106 converts the user side command into a memory side command in order to access (write and read data) the address space of the DDR-SDRAM opposite model 107 requested by the user side command. The DDR-SDRAM opposing model 107 returns a response (for example, read data, write result, etc.) according to the memory side command to the verification target 106.

  An expected value, which will be described later, is sent from the expected value generation model 108 to the monitor model 104. The monitor model 104 monitors the memory side command output from the verification target 106 to the DDR-SDRAM opposing model 107. The monitor model 104 compares the expected value with the memory side command and determines whether or not they match. If they match, the verification target 106 is operating as specified. In this embodiment, one feature is that the expected value is generated from the memory standard.

  The scenario storage unit 105 stores at least one user side command. The memory standard parameter storage unit 103 stores memory standard parameters of the DDR-SDRAM opposing model 107. The memory standards are, for example, DDR1, DDR2, DDR3, and the like, and the memory standard parameter storage unit 103 stores memory standard parameters for each memory standard.

  The memory standard parameters include, for example, an address table 1031 and a memory bus width 1032. The address table 1031 is a table that associates the memory address space of the DDR-SDRAM opposite model 107 with the address space on the system side (= user side command, application side, CPU side address). The memory bus width 1032 is the number of bits of the memory bus such as 8 bits, 16 bits, 32 bits, 64 bits, and the like.

[Generation of expected values]
The generation of the expected value will be described. First, the command transmission / control model 101 reads user-side commands one by one from the scenario storage unit 105 and sends them to the verification target 106. This user side command is generated randomly by the command transmission / control model 101, for example. The command transmission / control model 101 also sends the same user-side command to the expected value generation model 108. As will be described later, the scenario storage unit 105 also includes a user-side command generated from the address table 1031 and the memory bus width 1032.

  When the expected value generation model 108 receives a user side command from the command transmission / control model 101, the expected value generation model 108 reads the address table 1031 and the memory bus width 1032 from the memory standard parameter storage unit 103 simultaneously or before and after. The command generation model 102 generates a memory side command from a user side command based on the address table 1031 and the memory bus width 1032.

  FIG. 2 is an example of a diagram schematically illustrating generation of an expected value. 2, the same parts as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted. The user side command (scenario) includes a read / write signal, an address, the number of bursts, and a byte enable. The read / write signal specifies whether to read or write data from the DDR-SDRAM opposite model 107. The address is an address in an address space on the system side such as a CPU or OS.

  The number of bursts is the number of bytes of data that are read / written continuously by one read / write. For example, if the number of bursts is 8 and the width of the address bus is 16 bits, 16 bits × 8 = 16 bytes are read / written in one burst. The byte enable specifies valid data (for example, upper 8 bits and lower 8 bits) out of all data buses (for example, 16 bits).

  First, the expected value generation model 108 determines the read / write of the memory side command based on the read / write signal. Next, the expected value generation model 108 refers to the address table 1031 and determines the address of the memory side command (ROW address, Column address, or BANK address) from the address of the user side command.

  FIG. 3 is a diagram schematically illustrating an example of the address table 1031. The row direction in FIG. 3 means the memory address space of the DDR-SDRAM opposing model 107, and the column direction means the memory device (memory type). In FIG. 3, “Rxx” means a ROW address, “Cxx” means a Column address, and “Bxx” means a BANK address. “Na” means NonAvailable (unusable).

  Note that “× 8” and “× 16” of “memory size × 8” and “memory size × 16” in the column direction indicate the memory bus width 1032. As described above, the address of the DDR-SDRAM opposing model 107 differs with respect to the same system side address depending on the type of memory. Since the address table 1031 is closer to the specification than the standard, each ROW / Column / BANK address naturally changes when the address table 1031 changes.

  On the other hand, if the type of memory is determined and the address of the DDR-SDRAM opposite model 107 is known, the address on the system side is also uniquely determined.

  As shown in FIG. 3, when the memory bus width 1032 is “× 8” and “× 16”, the addresses specified on the DDR-SDRAM opposite model 107 side change even if the addresses on the system side are the same. Therefore, by referring to the address table 1031, the expected value generation model 108 has also adjusted according to the memory bus width 1032.

  If the byte enable of the user side command is changed, the start address (start point) of the address of the memory side command is changed.

  As described above, how the user-side command is converted into the memory-side command depends on the memory standard. In other words, the memory-side command is uniquely determined from the user-side command according to the memory standard.

  The DDR-SDRAM opposite model 107 has a CS (chip select) signal terminal for designating whether or not the access request is valid. This is because a plurality of DDR-SDRAM opposing models 107 are often mounted on one verification device. The DDR-SDRAM opposite model 107 is allowed to read or write when the CS signal is “Low”.

  The verification target 106 includes a plurality of CS terminals for specifying an access target from the plurality of DDR-SDRAM opposing models 107. For this reason, CS information specifying the CS terminal is required for the memory side command. The expected value generation model 108 generates CS information for selecting a chip to be accessed based on the address table 1031 and the like.

  The above three addresses and CS information are one memory side command. Since a plurality of memory side commands are transmitted to the DDR-SDRAM opposing model 107 according to the number of bursts, the command generation model 102 generates all of them (for the number of bursts) as expected values for one user side command. . This expected value is sent to the monitor model 104, and the monitor model 104 stores the expected value in a storage area (hereinafter simply referred to as “queue array”) of a queue structure (FIFO method).

  As will be described later, since the command generation model 102 generates a user side command from the memory standard, the expected value generation model 108 also generates an expected value from the user side command generated by the command generation model 102. By doing so, the monitor model 104 can be verified not only for the user command in the corner case but also for the user side command for designating an address at random.

  When the user side command requests access to the outside of the memory area of the DDR-SDRAM opposing model 107, the verification target 106 should receive an error signal from the DDR-SDRAM opposing model 107. Therefore, when the user side command requests access to the outside of the memory area of the DDR-SDRAM opposing model 107, the expected value generation model 108 refers to the address table 1031 and sends an error signal (for example, receiving an interrupt). Generate as expected value.

  FIG. 4 is an example of a flowchart illustrating a procedure in which the expected value generation model 108 generates an expected value by converting a user side command into a memory side command.

  First, the expected value generation model 108 determines whether or not the received user-side command is an access outside the memory area (S10). That is, the expected value generation model 108 converts the address of the user side command into the address of the memory side command with reference to the address table 1031, and whether or not the converted address is included in the address space of the DDR-SDRAM facing model 107. Determine whether. In the case of access outside the memory area (Yes in S10), the expected value generation model 108 generates “interrupt type” or the like as an expected value (S50).

  When the access is not outside the memory area (No in S10), the expected value generation model 108 determines the number n of memory side commands issued (S20). As described above, the number n of memory-side commands issued is a function of the number of bursts. In FIG. 2, n = 3 issuance numbers.

  Next, the expected value generation model 108 generates n memory side commands. That is, until n = 1 to n = 3 (S30), memory side commands are generated (S40).

  As described above, the expected value generation model 108 generates CS information and memory-side command addresses from user-side command addresses. Since CS information selects one DDR-SDRAM opposing model 107 from a plurality of DDR-SDRAM opposing models 107, it can be generated from the address of the user side command and the address table 1031. The address of the memory side command is generated from the address of the user side command and the address table 1031 (and the memory bus width 1032 included therein) of FIG.

  The expected value generation model 108 generates a data mask. The data mask is for generating a signal that designates only valid data designated as byte enable. Since the data mask is a mask applied to data read from the DDR-SDRAM opposite model 107, it is not included in the illustrated expected value.

  When the expected value generation model 108 generates n memory side commands (Yes in S30), the expected value generation model 108 sends the command to the monitor model 104. The monitor model 104 stores a plurality of memory side commands as expected values in the queue array (S50).

[Verification by monitor model 104]
FIG. 5 is an example of a diagram schematically showing verification by the monitor model 104. In FIG. 5, the same parts as those in FIG. With the processing in FIG. 4, the expected values are stored in the queue array of the monitor model 104.

  The verification target 106 is expected to generate the same memory side command as the command generation model 102. For this reason, the monitor model 104 monitors the interface between the verification target 106 and the memory model, and determines whether or not the memory-side command generated by the verification target 106 is the same as the expected value.

  The monitor model 104 stores the user side command sent from the command transmission / control model 101 and the expected value sent from the expected value generation model 108 in a queue structure list in association with each other. Therefore, even when the memory-side command corresponding to the user-side command input to the verification target 106 is not output from the verification target 106 in the input order, the monitor model 104 compares the expected value with the memory-side command to determine whether it is correct. Can be confirmed.

  Further, since the queue structure is stored, it is possible to confirm whether or not all commands that should be issued to the memory side command have been issued at the end of logic verification (simulation).

[Generate parameter combination list for user command]
What becomes important regarding the verification of the address by the memory controller that is the verification target 106 is whether or not the address of the memory delimiter (address boundary, CS boundary, BANK boundary, etc.) has been verified. Therefore, the command generation model 102 generates boundary addresses of these boundaries or near the boundaries from the address table 1031 and acquires them as boundary addresses of the DDR-SDRAM opposing model 107. By converting this into the address of the user side command, the address of the user side command corresponding to the corner case at the time of logic verification can be generated.

  Also, by combining parameters other than the user side command address (read / write signal, burst count, byte enable) with the user side command address corresponding to the boundary address, user parameters for comprehensive verification of the corner case Can be generated. Therefore, the user side command address corresponding to a plurality of boundary addresses, the read signal or write signal, various burst numbers, and various byte enables are the parameter combination list of the user side command.

  FIG. 6 is an example of a diagram schematically illustrating generation of a scenario (user side command). The command generation model 102 reads the address table 1031 from the memory standard parameter storage unit 103 and determines the boundary address corresponding to the memory delimiter position.

  First, the command generation model 102 is based on the address table 1031 and the memory bus width 1032 of the DDR-SDRAM facing model 107 and near the boundary of the address (ROW / Column / BANK) and the boundary of one chip (DDR-SDRAM facing model 107). Extract the address.

  Taking “512M × 8” in FIG. 3 as an example, the boundary between na and R12, the boundary between R11 and C8, the boundary between C8 and B2, the boundary between B0 and C7, and the boundary between C9 and na are respectively near the address boundary. A boundary address. Also, the uppermost and lowermost na are boundary addresses near the chip boundary.

  These boundary addresses near the address boundary and the boundary addresses near the chip boundary are the addresses of the DDR-SDRAM facing model 107. On the other hand, what is desired to be generated is the address of the user side command (system side). For this reason, the command generation model 102 generates an address of a user-side command that is converted into a boundary address near the address boundary and near the chip boundary. As described above, since the user side command is converted into the memory side command based on the address table 1031 and the memory bus width 1032, the memory side command is reversed to the user side command based on the address table 1031 and the memory bus width 1032. By converting, the address of the user side command can be generated.

  In the example of FIG. 3, the address of the user side command at the boundary between na and R12 is “A28, A27”, the address of the user side command at the boundary between R11 and C8 is “A15, A14”, and the boundary of the boundary between C8 and B22 The address of the user side command is “A14, A13”, the address of the user side command at the boundary between B0 and C7 is “A11, A10”, and the address of the user side command at the boundary between C9 and na is “A5, A4”. Similarly, the addresses of the user side commands at the boundary between the top and bottom na are “A31” and “a”.

  Further, in the parameter combination list of the user side command, two types of read / write signals, read and write, eight types of bursts of about 1 to 8, and byte enable of about 4 to 8 types may be assumed. These can be stored in advance in the scenario storage unit 105 or the like.

  The command generation model 102 generates a user-side command by taking out one from each of a plurality of user-side command addresses, read signals or write signals, various burst numbers, and various byte enables and combining them. By generating all combinations in the parameter combination list of user-side commands, it is possible to generate user-side commands that comprehensively verify the corner case addresses.

  The command generation model 102 stores the parameter combination list of the generated user side commands in the scenario storage unit 105. You may memorize | store as a user side command combining beforehand. At the time of verification, the command transmission / control model 101 or the command generation model 102 executes all combinations in the parameter combination list of the user side command to generate a user side command.

  FIG. 7 is an example of a flowchart illustrating a procedure in which the command generation model 102 generates a user-side command that covers the boundary address. The flowchart in FIG. 7 starts when, for example, the user instructs the logic verification apparatus 100 to generate a user-side command.

  First, the command generation model 102 reads the address table 1031 and the memory bus width 1032 from the memory standard parameter storage unit 103 (S110).

  Next, the command generation model 102 generates a boundary address of the DDR-SDRAM facing model 107 (S120). The command generation model 102 extracts boundary addresses near the address (ROW / Column / BANK) boundary and the boundary of the chip based on the memory standard parameters.

  Next, the command generation model 102 converts the boundary address back to the address of the user side command based on the address table 1031 (S130). A plurality of user-side command addresses are generated.

  The command generation model 102 attaches a read / write signal, various burst numbers, and various byte enables to this address, and generates a parameter combination list of the user side command (S140).

  Note that the expected value generation model 108 generates expected values by combining the parameter combination lists.

[Logic verification by combining parameter combinations of user side commands, logical verification by randomly generated user side commands]
By generating the user side command using the parameter combination list of the user side command, the corner case can be comprehensively verified, and further, by randomly generating the user side command, the logical verification can be performed for a large number of addresses.

  FIG. 8 shows an example of a flowchart showing a procedure of logical verification performed by the logical verification apparatus 100 of the present embodiment. The flowchart of FIG. 8 starts when, for example, the user instructs the start of logic verification. You may start automatically following the flowchart of FIG.

First, the command transmission / control model 101 determines one of the following termination conditions (S210).
(A) Is the user-side command issued a specified number of times? (B) Is the user-side command issued for all combinations in the parameter combination list of the user-side command and whether a sufficient number of user-side commands have been issued at random? When (a) is set as the end condition, the user inputs the specified number of times to the logic verification device 100 via the input device. The logic verification apparatus 100 accepts a specified number of times that is greater than the minimum number of times that can be input, considering a margin for random issuance of user-side commands to the number of times required for all combinations of parameter combination lists of user-side commands. .

  If the end condition is not satisfied (No in S210), the command transmission / control model 101 determines whether the counter m has reached the number of elements (S220). The number of elements is “4” because it is the number of parameters of the user side command. The counter m takes values 1, 2, 3, and 4.

  When the counter m has not reached the number of elements (No in S220), the command transmission / control model 101 determines whether it is “combination reading” or “random reading” (S230). The command transmission / control model 101 automatically switches between “combination reading” and “random reading”. For example, when the issuance of the user side command is completed by all the combinations in the parameter combination list of the user side command, the process proceeds to random reading.

  In the case of “read combination”, the command transmission / control model 101 reads one element of each parameter combination list stored in the scenario storage unit 105 (S240). Therefore, this is repeated four times.

  In the case of “random reading”, the command transmission / control model 101 determines an appropriate value from one of the elements of the user side command (S250). The command transmission / control model 101 randomly determines an arbitrary address from an address on the system side, an arbitrary one from a read / write signal, an arbitrary burst number, and an arbitrary byte enable. Arbitrary upper and lower limits that can be taken are predetermined. By repeating this four times, an arbitrary user side command can be generated.

  In step S220, when the counter m reaches the number of elements (Yes in S220), the command transmission / control model 101 executes a command issuing function for issuing a user side command (S260).

  Thereafter, the command transmission / control model 101 waits for a waiting time to provide an interval between commands (S270). The standby time is determined by the response time (read time / write time) of the DDR-SDRAM opposing model 107. Further, the user may set from the input device.

  The logic verification device 100 repeats steps S210 to S270, and ends the logic verification when the above end condition ends.

  As described above, the logic verification apparatus 100 according to the present embodiment generates the expected value based on the memory standard parameter, so that the logic value can cover the expected value rather than generating the expected value depending on the contents of the DUT. This makes it possible to verify the logic even for random input parameters from a large number of addresses.

  In addition, the logic verification device 100 according to the present embodiment can perform the logic verification without missing the corner case of the logic verification item by generating the parameter of the user side command from the memory standard parameter. Since the memory corner case parameters can be automatically generated, the number of omissions is reduced and the circuit quality is improved. For example, logic verification can be performed for DDR1, DDR2, and DDR3 in the same environment. Logic verification can be performed in the same environment by adding / updating memory standard parameters to memory of new standards in the future.

  In addition, since it supports outside the address area, logic verification can be performed for any combination of user commands. It is possible to perform logic verification of various parameters by allowing random input without giving any input restriction to the user side command, thereby improving circuit quality.

  In addition, the creation time of expected values can be shortened, leading to shortening of the logic verification process. In addition, the verification target can be clarified and defects caused by individual differences and misunderstanding of specifications can be reduced.

DESCRIPTION OF SYMBOLS 100 Logic verification apparatus 101 Command transmission and control model 102 Command generation model 103 Memory standard parameter memory | storage part 104 Monitor model 105 Scenario memory | storage part 106 Verification object (DUT)
107 DDR-SDRAM opposite model 108 Expected value generation model

JP 2002-31416 A

Claims (5)

A logic verification device that verifies the logic of a memory controller that converts a first command issued by a CPU into a second command and supplies the converted command to a memory,
Memory standard information storage means for storing the standard information of the memory;
Expected value generating means for generating an expected value of the second command converted from the first command according to the address correspondence information for each standard included in the standard information;
Command issuing means for issuing a first command to the memory controller;
Monitoring means for monitoring a second command converted from the first command by the memory controller and comparing with the expected value;
A logic verification device comprising: Command generating means for specifying a specific second address of the memory with reference to the standard information, and determining a first address included in the first command from the second address based on the address correspondence information;
The logic verification device according to claim 1, further comprising: The command issuing means generates a first command by combining the first address generated by the command generating means and values that other parameters of the first command can take.
The logic verification device according to claim 2, wherein: The second address is an address near a boundary of a physical structure of the memory.
The logic verification apparatus according to claim 2 or 3, wherein A logic verification method for verifying a logic of a memory controller that converts a first command issued by a CPU into a second command and supplies the converted command to a memory,
In accordance with address correspondence information included in the memory standard information stored in the memory standard information storage unit, the expected value generation unit generates an expected value of the second command converted from the first command;
Command issuing means for issuing a first command to the memory controller;
Monitoring means for monitoring a second command converted from the first command by the memory controller and comparing with the expected value;
A logic verification method characterized by comprising:

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