JP5695948B2 - Field effect transistor, method of manufacturing the same, and semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device including a field-effect transistor (FET) and a manufacturing technique thereof, and more particularly to a semiconductor device including a field-effect transistor having a lateral double-diffused structure and a manufacturing method thereof. Regarding technology.

  With the recent progress of miniaturization and high performance of electronic components, there is a demand for higher integration of power elements such as bipolar elements and DMOS (Double-diffused MOS) in an IC chip mounted on the electronic parts. There are two known DMOS structures, VDMOS (Vertical DMOS) and LDMOS (Lateral DMOS). Since the VDMOS has a source region formed on the front surface side of the semiconductor substrate and a drain region formed on the back surface side, the VDMOS has a structure in which carriers flow in the thickness direction (vertical direction) of the semiconductor substrate. On the other hand, since the LDMOS has a structure in which both the source region and the drain region are formed on the front side, carriers flow laterally along the main surface of the semiconductor substrate. Such a DMOS structure is disclosed in, for example, Japanese Unexamined Patent Application Publication No. 2007-103672 (Patent Document 1) and Japanese Unexamined Patent Application Publication No. 2007-287798 (Patent Document 2).

JP 2007-103672 A (FIG. 4 etc.) Japanese Unexamined Patent Publication No. 2007-287798 (FIGS. 5 and 6 etc.)

  As described above, in the conventional LDMOS, since both the source region and the drain region are formed on the front surface side, the lateral dimension is large compared to the VDMOS structure, and there is a limit to high integration. For example, when a CMOS circuit is formed by arranging a P-channel LDMOS and an N-channel LDMOS, there is a problem that the lateral dimension of the entire CMOS circuit is increased and the element area of the CMOS circuit in the IC chip is increased.

  In view of the above, an object of the present invention is to provide a field effect transistor, a method for manufacturing the same, and a semiconductor device that enable high integration of a field effect transistor having a lateral double diffusion structure such as an LDMOS.

The field effect transistor according to the first aspect of the present invention has a semiconductor substrate and a main surface of the semiconductor substrate that extends in a predetermined direction parallel to the main surface and has a width in a direction crossing the predetermined direction. A gate insulating film interposed between the semiconductor substrate and the gate electrode, the semiconductor substrate extending along the predetermined direction on one side of both sides of the gate electrode in the width direction. A P-type body region having an end in a region immediately below the gate electrode, and extending along the predetermined direction on the other side of both sides in the width direction of the gate electrode, and immediately below the gate electrode An N-type body region having an end in the region, a first P-type impurity diffusion region formed in the vicinity of the main surface on the one side and joined to the P-type body region, and the first side on the other side The first P-type impurity in the vicinity of the main surface A first N-type impurity diffusion region formed at a position facing the diffusion region and joined to the N-type body region; and a first N-type impurity diffusion region formed near the main surface on the one side and joined to the P-type body region. Two N-type impurity diffusion regions and a second P-type impurity formed on the other side in the vicinity of the main surface at a position facing the second N-type impurity diffusion region and joined to the N-type body region a diffusion region seen including, wherein the first P-type impurity diffusion region and the second N-type impurity diffusion regions, wherein are formed spaced apart and a position adjacent to each other in a predetermined direction, said first The N-type impurity diffusion region and the second P-type impurity diffusion region are formed at positions adjacent to each other in the predetermined direction .
The field effect transistor according to the second aspect of the present invention includes a semiconductor substrate and a width extending in a direction parallel to the main surface on the main surface of the semiconductor substrate and intersecting the predetermined direction. And a gate insulating film interposed between the semiconductor substrate and the gate electrode, the semiconductor substrate along the predetermined direction on one side of both sides in the width direction of the gate electrode A P-type body region having an end in a region immediately below the gate electrode, and extending along the predetermined direction on the other side of both sides in the width direction of the gate electrode, An N-type body region having an end in a region immediately below the first side, a first P-type impurity diffusion region formed in the vicinity of the main surface on the one side and joined to the P-type body region, and the other side In the vicinity of the main surface, the first P-type A first N-type impurity diffusion region formed at a position facing the pure material diffusion region and bonded to the N-type body region; and formed in the vicinity of the main surface on the one side, and bonded to the P-type body region A second N-type impurity diffusion region that is formed on the other side in the vicinity of the main surface at a position facing the second N-type impurity diffusion region and joined to the N-type body region The field effect transistor according to claim 1, wherein the N-type body region and the P-type body region include a center line of the gate electrode. The first N-type impurity diffusion region and the first P-type impurity diffusion region are symmetrical to each other in the width direction with respect to the center line of the gate electrode. Before and And the second P-type impurity diffusion region and the second N-type impurity diffusion region, and having a symmetrical shape each other in the widthwise direction with respect to the center line of the gate electrode.

A semiconductor device according to a third aspect of the present invention includes first and second field effect transistors sharing a gate electrode formed on a semiconductor substrate, and the first field effect transistor according to the first aspect. The field effect transistor or the field effect transistor according to the second aspect has the same structure, and the second field effect transistor is the same as the field effect transistor according to the first aspect or the field effect transistor according to the second aspect. It has a structure.

A field effect transistor manufacturing method according to a fourth aspect of the present invention includes a step of forming a gate insulating film on a main surface of a semiconductor substrate, and the main surface of the semiconductor substrate via the gate insulating film, Forming a gate electrode extending in a predetermined direction parallel to the main surface and having a width in a direction crossing the predetermined direction; and selectively applying N-type impurities and P-type impurities in the semiconductor substrate, respectively. And introducing a P-type body region extending along the predetermined direction on one side of both sides of the gate electrode in the width direction and having an end portion in a region immediately below the gate electrode; Forming an N-type body region extending along the predetermined direction on the other side of both sides in the width direction of the electrode and having an end portion in a region directly below the gate electrode; and the main body in the semiconductor substrate P-type impurities near the surface A first P-type impurity diffusion region bonded to the P-type body region is formed on the one side, and the second P is bonded to the N-type body region on the other side. Forming a n-type impurity diffusion region, selectively introducing an n-type impurity in the vicinity of the main surface in the semiconductor substrate, and at a position facing the first p-type impurity diffusion region on the other side Forming a first N-type impurity diffusion region to be joined to the N-type body region, and joining the P-type body region to a position facing the second P-type impurity diffusion region on the one side; Forming the N-type impurity diffusion region, and the first P-type impurity diffusion region and the second N-type impurity diffusion region are formed at positions adjacent to each other in the predetermined direction. , Before the first N-type impurity diffusion region And the second P-type impurity diffusion region, characterized in that it is formed at a position adjacent the predetermined direction spaced apart from each other and.

  According to the present invention, since the ratio of the area occupied by the field effect transistor in the IC chip is reduced, high integration is possible.

1 is a plan view schematically showing a configuration of a semiconductor device which is an example of a first embodiment according to the present invention. FIG. 2 is a schematic cross-sectional view taken along line II-II of the semiconductor device of FIG. 1. 1 is a schematic cross-sectional view taken along line III-III of the semiconductor device of FIG. 1, and FIG. 3 is a schematic cross-sectional view taken along line III-III of the semiconductor device 1N of FIG. It is a figure which shows an N channel field effect transistor. FIG. 6 is a cross sectional view schematically showing a first manufacturing step for the semiconductor device of the first embodiment. FIG. 6 is a cross sectional view schematically showing a second manufacturing step of the semiconductor device of First Embodiment. FIG. 10 is a cross sectional view schematically showing a third manufacturing step of the semiconductor device of First Embodiment. FIG. 10 is a cross sectional view schematically showing a fourth manufacturing step of the semiconductor device of First Embodiment. FIG. 10 is a cross sectional view schematically showing a fifth manufacturing step for the semiconductor device of the first embodiment. FIG. 10 is a cross sectional view schematically showing a sixth manufacturing step of the semiconductor device of First Embodiment. FIG. 10 is a cross sectional view schematically showing a seventh manufacturing step for the semiconductor device of the first embodiment. FIG. 10 is a plan view schematically showing a configuration of a semiconductor device which is another example of the first embodiment. FIG. 13 is a schematic cross-sectional view of the semiconductor device of FIG. 12 taken along line XIII-XIII. FIG. 14 is a schematic cross-sectional view of the semiconductor device of FIG. 12 taken along line XIV-XIV. It is a figure which shows a P-channel field effect transistor. It is sectional drawing which shows schematically the LDMOS structure of a comparative example. It is a top view which shows roughly the structure of the semiconductor device which has the CMOS structure of Embodiment 2 which concerns on this invention. FIG. 18 is a schematic sectional view taken along line XVIII-XVIII of the semiconductor device of FIG. 17. FIG. 6 is a diagram showing an equivalent circuit of the semiconductor device of the second embodiment.

  Hereinafter, various embodiments according to the present invention will be described with reference to the drawings.

Embodiment 1 FIG.
FIG. 1 is a plan view schematically showing a configuration of a semiconductor device 1N which is an example of the first embodiment according to the present invention. 2 is a schematic cross-sectional view taken along line II-II of the semiconductor device 1N of FIG. 1, and FIG. 3 is a schematic cross-sectional view taken along line III-III of the semiconductor device 1N of FIG. For convenience of explanation, the interlayer insulating film 60 of FIGS. 2 and 3 is not shown in FIG. As will be described below, in this embodiment, one N-channel field effect transistor element having a lateral double diffusion structure is configured by the combination of the cross-sectional structure of FIG. 2 and the cross-sectional structure of FIG.

2 and 3, the transistor structure of the semiconductor device 1N according to the present embodiment is formed on a P-type support substrate 10 made of a single crystal silicon material. An N ⁺ type buried layer (NBL: N ⁺ -type buried layer) 11 is formed on the upper surface of the P type support substrate 10. An N type epitaxial layer 12 is formed on the N ⁺ type buried layer 11. Inside the N-type epitaxial layer 12, P-type element isolation layers 15A and 15B extending in the vertical direction from the upper surface of the N-type epitaxial layer 12 to the P-type support substrate 10 are formed. These P-type element isolation layers 15A and 15B have an element isolation function by a pn junction. Instead of the P-type element isolation layers 15A and 15B, a trench isolation structure such as an STI (Shallow Trench Isolation) structure may be formed. The P-type support substrate 10, the N ⁺ type buried layer 11, and the N-type epitaxial layer 12 can constitute the semiconductor substrate of the present invention.

  Field oxide films 13A and 13B are formed on the upper layer portion of the N-type epitaxial layer 12 by a LOCOS (Local Oxidation of Silicon) method. On the N-type epitaxial layer 12, a gate structure including a gate insulating film 16 and a gate electrode 17 extends along the upper surface of the P-type support substrate 10 in the Y-axis direction of FIG. The gate insulating film 16 is a thin film made of a high dielectric constant material such as silicon oxide, and the gate electrode 17 is formed using a polycrystalline silicon material doped with an impurity such as boron or phosphorus at a high concentration. be able to.

  Side wall spacers 18A and 18B made of an insulating material are formed on both side walls in the X-axis direction of the gate electrode 17, respectively. The X-axis direction is a direction parallel to the upper surface of the P-type support substrate 10 and orthogonal to the Y-axis direction. These sidewall spacers 18A and 18B extend in the Y-axis direction together with the gate electrode 17 as shown in FIG.

  The gate electrode 17 extends in the Y-axis direction over the entire element region of FIG. 1 and has an elongated rectangular shape having a certain width in the X-axis direction intersecting the Y-axis direction. On both sides of the X-axis direction (width direction) of the gate electrode 17, an N-type body region (N-type well) 20N and a P-type body region (P-type well) 20P are formed in relatively shallow regions of the N-type epitaxial layer 12, respectively. Is formed. As shown in FIGS. 2 and 3, the end of the P-type body region 20P and the end of the N-type body region 20N face each other in the X-axis direction and are joined to each other immediately below the gate electrode 17. ing. Also, as shown in FIG. 1, the P-type body region 20P extends along the Y-axis direction on one side (right side) of both sides of the gate electrode 17, and the N-type body region 20N 17 extends along the Y-axis direction on the other side (left side) of both sides. The distribution of the P-type body region 20P and the distribution of the N-type body region 20N is, for example, that an N-type impurity atom and a P-type impurity atom are separately provided in the vicinity of the upper surface in the N-type epitaxial layer 12, respectively. This can be realized by diffusing and activating the ion-implanted N-type impurity atoms and P-type impurity atoms by drive-in treatment (heat treatment for a relatively long time).

  As shown in FIG. 1, in the region on the left side of the gate electrode 17, the impurity diffusion layers 30N, 31P, 32N, and so on are surrounded and joined by the N-type body region 20N near the upper surface of the N-type epitaxial layer 12. 33P, 34N, 35P, and 36N are formed. These impurity diffusion layers 30N, 31P, 32N, 33P, 34N, 35P, and 36N are spaced apart from each other and are arranged at regular intervals along the Y-axis direction. Of these impurity diffusion layers, the impurity diffusion layers 30N, 32N, 34N, and 36N are N-type impurity diffusion regions, and the impurity diffusion layers 31P, 33P, and 35P are P-type impurity diffusion regions. Therefore, N-type impurity diffusion regions and P-type impurity diffusion regions are alternately arranged on the left side of the gate electrode 17 along the Y-axis direction.

  The impurity diffusion layers 30P, 31N, 32P, 33N, 34P, 35N, and 36P are also formed in the region on the right side of the gate electrode 17 so as to be surrounded and joined by the P-type body region 20P near the upper surface of the N-type epitaxial layer 12. Is formed. The impurity diffusion layers 30P, 31N, 32P, 33N, 34P, 35N, and 36P are spaced apart from each other and are arranged at regular intervals along the Y-axis direction. Of these impurity diffusion layers, the impurity diffusion layers 31N, 33N, and 35N are N-type impurity diffusion regions, and the impurity diffusion layers 30P, 32P, 34P, and 36P are P-type impurity diffusion regions. Therefore, N-type impurity diffusion regions and P-type impurity diffusion regions are alternately arranged along the Y-axis direction also on the right side of the gate electrode 17.

  Further, the pair of impurity diffusion layers 30N and 30P facing the gate electrode 17 have different conductivity types. Similarly, a pair of impurity diffusion layers 31P and 31N, a pair of impurity diffusion layers 32N and 32P, a pair of impurity diffusion layers 33P and 33N, a pair of impurity diffusion layers 34N and 34P, and a pair of impurity diffusion layers 35P, 35N and the pair of impurity diffusion layers 36N and 36P have different conductivity types.

  In the semiconductor device 1N of the present embodiment, the P-type body region 20P and the N-type body region 20N have substantially symmetric shapes with respect to the center line of the gate electrode 17. Similarly, the shape of the left impurity diffusion layers 30N, 31P, 32N, 33P, 34N, 35P, and 36N and the shape of the right impurity diffusion layers 30P, 31N, 32P, 33N, 34P, 35N, and 36P are the gate electrode. It is almost symmetrical with respect to the 17 center line.

  On the N-type epitaxial layer 12, contact plugs (leading electrodes) 50, 52, 54, and 56 that are electrically connected to the impurity diffusion layers 30N, 32N, 34N, and 36N on the left side are formed. Contact plugs (leading electrodes) 40, 41, 42, 43, 44, 45, and 46, which are electrically connected to the impurity diffusion layers 30P, 31N, 32P, 33N, 34P, 35N, and 36P, are formed. Contact plugs are not formed in the left impurity diffusion regions 31P, 33P, and 35P. The upper end portions of the left contact plugs 50, 52, 54, and 56 are connected to an upper layer wiring 71 such as copper and aluminum, and the upper end portions of the right contact plugs 40 to 46 are connected to an upper layer wiring 70 such as copper and aluminum. Has been.

  Of the contact plugs, contact plugs 50, 52, 54, and 56 are used as drain electrodes, contact plugs 41, 43, and 45 are used as source electrodes, and contact plugs 40, 42, 44, and 46 are used as back gate electrodes. An N-channel field effect transistor 2N as shown in FIG. 4 can be configured. The N-channel field effect transistor 2N has a gate 2g, a source 2s, a drain 2d, and a back gate 2g.

  In the case of an N-channel field effect transistor element configured by a combination of the cross-sectional structure of FIG. 2 and the cross-sectional structure of FIG. 3, a channel region is formed in the body region 20P of FIG. Thus, a drift region (electric field relaxation region) is formed in body region 20N. The breakdown voltage performance of this field effect transistor element depends on the length of the drift region, but the drift region is not in the width direction (X-axis direction) of the gate electrode 17 but in an oblique direction along the line II-II in FIG. Therefore, a relatively long electric field relaxation region can be secured.

  Next, a method for manufacturing the semiconductor device 1N will be described with reference to FIGS. 5 to 11 are cross-sectional views schematically showing an example of the manufacturing process of the semiconductor device 1N, and correspond to the cross-sectional structure (FIG. 3) along the line III-III in FIG.

First, a silicon substrate is prepared as a support substrate, and the surface of the silicon substrate is thermally oxidized to form a thermal oxide film 19 (FIG. 5) having a film thickness of about several tens of nanometers. Then, a P-type impurity such as arsenic or boron is selectively ion-implanted into the silicon substrate. As a result, as shown in FIG. 5, a P-type support substrate 10 including a P-type impurity layer 11d near the surface can be obtained. The P-type impurity layer 11d becomes the N ⁺ -type buried layer 11 when activated by heat treatment. More specifically, a resist pattern (not shown) is formed on the surface of the prepared silicon substrate, and arsenic is implanted into a region (relatively shallow region) near the upper surface of the single crystal silicon substrate using this resist pattern as a mask. Thus, the P-type impurity layer 11d is formed. Thereafter, the resist pattern is removed, and boron ions are implanted into the entire silicon substrate. When the introduced boron is activated by heat treatment, a P-type support substrate 10 is obtained.

  Thereafter, the thermal oxide film 19 is removed, and an N-type epitaxial layer 12 having a thickness of about 1 μm to several tens of μm is grown on the P-type support substrate 10. As a result, the semiconductor substrate 10B shown in FIG. 6 can be obtained.

  Next, field oxide films 13A and 13B are formed on the N-type epitaxial layer 12 using a known LOCOS method, as shown in FIG. For example, a field oxide film is formed by forming a silicon nitride film (not shown) having an opening on the N-type epitaxial layer 12 and thermally oxidizing the exposed surface of the N-type epitaxial layer 12 using the silicon nitride film as a mask. 13A and 13B can be formed.

  Further, a resist pattern (not shown) for forming P-type element isolation layers 15A and 15B is formed on N-type epitaxial layer 12, and P-type impurities such as phosphorus are formed on N-type epitaxial layer 12 using this as a mask. Ion implantation. The P-type element isolation layers 15A and 15B in FIG. 7 are formed by activating the ion-implanted P-type impurities by heat treatment.

  Next, an insulating film such as a silicon oxide film is formed on the N-type epitaxial layer 12 of FIG. Thereafter, a polycrystalline silicon film doped with a high concentration of P-type impurities such as phosphorus is deposited on the insulating film by using, for example, a CVD (Chemical Vapor Deposition) method. Then, the insulating film and the polycrystalline silicon film are patterned by semiconductor lithography (such as photolithography and extreme ultraviolet lithography) and anisotropic etching, so that the gate structure (gate insulating film 16 and gate electrode 17) of FIG. Can be formed.

Next, in order to form the N-type body region 20N, a resist pattern (not shown) that exposes the formation region of the N-type body region 20N and covers the formation region of the P-type body region 20P by semiconductor lithography. ) Is formed on the N-type epitaxial layer 12 of FIG. Next, using this resist pattern and the gate structure of FIG. 8 as a mask, P-type impurities such as boron are ion-implanted into the N-type epitaxial layer 12. At this time, for example, boron may be ion-implanted under the conditions of an acceleration voltage of 20 keV and an impurity concentration of about 5 × 10 ¹³ atoms / cm ² . Thereafter, the resist pattern is removed. Further, in order to form the P-type body region 20P, a resist pattern (not shown) that exposes the formation region of the P-type body region 20P and covers the formation region of the N-type body region 20N is formed by semiconductor lithography. It is formed on the N type epitaxial layer 12. Using this resist pattern and the gate structure of FIG. 8 as a mask, N-type impurities such as phosphorus are ion-implanted into the N-type epitaxial layer 12. At this time, phosphorus may be ion-implanted under the conditions of an acceleration voltage of 80 keV and an impurity concentration of about 1.5 × 10 ¹³ atoms / cm ² , for example. Thereafter, the resist pattern is removed. Then, the N-type impurity and the P-type impurity introduced into the N-type epitaxial layer 12 are diffused and activated by a drive-in process. As a result, as shown in FIG. 9, a P-type body region 20P and an N-type body region 20N are formed on both sides of the gate electrode 17.

  Thereafter, an insulating film made of an insulating material such as silicon oxide is deposited on the structure of FIG. 9 by, for example, CVD, and this insulating film is etched back by anisotropic etching. As a result, the side wall spacers 18A and 18B shown in FIG.

Further, in order to form the N-type impurity diffusion regions 30N to 36N of FIG. 1, the regions where the N-type impurity diffusion regions 30N to 36N are to be formed are exposed and the P-type impurity diffusion regions 30P to 36P are formed by semiconductor lithography. A resist pattern (not shown) for covering the predetermined area is formed. Then, N-type impurities such as arsenic are ion-implanted into the N-type epitaxial layer 12 using the resist pattern, the gate electrode 17 and the side wall spacers 18A and 18B as a mask. At this time, for example, arsenic can be ion-implanted under conditions of an acceleration voltage of 40 keV and an impurity concentration of about 5 × 10 ¹⁵ atoms / cm ² . Thereafter, the resist pattern is removed. Further, in order to form the P-type impurity diffusion regions 30P to 36P, the formation regions of the P-type impurity diffusion regions 30P to 36P are exposed and the formation regions of the N-type impurity diffusion regions 30N to 36N are formed by semiconductor lithography. A resist pattern (not shown) to be coated is formed. Then, P-type impurities such as boron and boron fluoride (BF ₂ ) are ion-implanted into the N-type epitaxial layer 12 using the resist pattern, the gate electrode 17 and the side wall spacers 18A and 18B as a mask. At this time, for example, boron fluoride can be ion-implanted under the conditions of an acceleration voltage of 40 keV and an impurity concentration of about 5 × 10 ¹⁵ atoms / cm ² . Thereafter, the resist pattern is removed. The N-type impurity and the P-type impurity individually ion-implanted in this way are activated by heat treatment. As a result, the structure of FIG. 10 is formed.

  Next, an interlayer insulating film 60 is deposited over the entire surface of the structure of FIG. Next, contact holes 61, 62, and 63 are formed in the interlayer insulating film 60 by semiconductor lithography and etching, as shown in FIG. By embedding a conductive material such as tungsten in these contact holes 61, 62, 63, the semiconductor device 1N of the present embodiment is completed.

  FIG. 12 is a plan view schematically showing a configuration of a semiconductor device 1P which is another example of the first embodiment. 13 is a schematic cross-sectional view taken along line XIII-XIII of the semiconductor device 1P of FIG. 12, and FIG. 14 is a schematic cross-sectional view taken along line XIV-XIV of the semiconductor device 1P of FIG. For convenience of explanation, the interlayer insulating film 60 of FIGS. 13 and 14 is not shown in FIG.

  Since the semiconductor device 1P has the same structure as the semiconductor device 1N except for the wiring form of the contact plugs 90 to 96, 80, 82, 84, 86, the semiconductor device 1P is manufactured by almost the same manufacturing process as the semiconductor device 1N. Can be produced. As shown in FIG. 12, the semiconductor device 1P includes contact plugs (lead electrodes) 90, 91, 92 electrically connected to the left impurity diffusion layers 30N, 31P, 32N, 33P, 34N, 35P, 36N, respectively. , 93, 94, 95, 96, and contact plugs (lead electrodes) 80, 82, 84, 86 electrically connected to the right impurity diffusion layers 30P, 32P, 34P, 36P, respectively. Contact plugs are not formed in the impurity diffusion regions 31N, 33N, and 35N. The upper ends of the contact plugs 80, 82, 84, 86 are connected to the upper layer wiring 73, and the upper ends of the contact plugs 90 to 96 are connected to the upper layer wiring 74.

  Of the contact plugs, contact plugs 80, 82, 84, 86 are used as drain electrodes, contact plugs 91, 93, 95 are used as source electrodes, and contact plugs 90, 92, 94, 96 are used as back gate electrodes. As shown in FIG. 15, a P-channel field effect transistor 3P having a gate 3g, a source 3s, a drain 3d, and a back gate 3g can be formed.

  In the case of a P-channel field effect transistor element constituted by a set of the cross-sectional structure of FIG. 13 and the cross-sectional structure of FIG. 14, during its operation, the body region 20N of FIG. 13 is along the line XIII-XIII of FIG. A channel region is formed, and a drift region (electric field relaxation region) is formed in body region 20P. Although the breakdown voltage performance of the field effect transistor element depends on the length of the drift region, the drift region is not in the width direction (X-axis direction) of the gate electrode 17 but in the oblique direction along the line XIII-XIII in FIG. Therefore, a relatively long electric field relaxation region can be secured.

  As described above, the semiconductor devices 1P and 1N according to the first embodiment have the same structure except for the contact plug wiring form, and only by changing the contact plug wiring form, the N-channel field effect transistor (semiconductor device). 1N) and a P-channel field effect transistor (semiconductor device 1P) can be selectively formed. Therefore, when the N-channel field effect transistor and the P-channel field effect transistor are integrated on the substrate, the manufacturing process can be simplified.

In addition, as shown in FIG. 1, the drain electrode 52, the source electrode 41, and the back gate electrode 42 constituting the N-channel field effect transistor are formed without being arranged in a line, so that the field effect transistor can be highly integrated. It can be easily realized. This point will be described below with reference to FIG. FIG. 16 is a cross-sectional view schematically showing an N-channel LDMOS structure 200N of a comparative example. In the LDMOS structure 200N of FIG. 16, an N ⁺ type buried layer 211, an N type epitaxial layer 212, an interlayer insulating film 26, and contact plugs (lead electrodes) 270, 271, and 272 are formed on a P type substrate 210. Near the upper surface of the N-type epitaxial layer 212, an N ⁺ -type drain region 231D, a P-type body region 220P, an N ⁺ -type source region 231S, and a P ⁺ -type back gate region 231B are formed. These N ⁺ -type drain region 231D, P-type body region 220P, N ⁺ -type source region 231S, and P ⁺ -type back gate region 231B are impurity diffusion regions distributed in the lateral direction. A gate electrode 217 is formed on the N-type epitaxial layer 212 via a gate oxide film 216. The contact plug (lead electrode) 272 is connected to the N ⁺ type source region 231S and the P ⁺ type back gate region 231B. Further, the contact plug 271 is connected to the gate electrode 217, and the contact plug 270 is connected to the N ⁺ type drain region 231D.

In such an N-channel LDMOS structure 200N, the N ⁺ type drain region 231D, the N ⁺ type source region 231S, and the P ⁺ type back gate region 231B are arranged in a row in the horizontal direction, so that the horizontal dimension is increased. There is a drawback. On the other hand, in the semiconductor device 1N of the present embodiment, the impurity diffusion regions 31N, 32N, and 32P connected to the source electrode 41, the drain electrode 52, and the back gate electrode 42 are not aligned in a line. Compared with 16 LDMOS structures, the lateral dimension can be reduced.

  Further, the carriers do not flow in the width direction (X-axis direction) of the gate electrode 17 but are oblique to the X-axis direction and the Y-axis direction (II-II line in FIG. 1 or XIII-XIII in FIG. 12). Therefore, a relatively long electric field relaxation layer (drift layer) can be provided in the lateral direction. Therefore, the field effect transistors can be highly integrated without degrading the withstand voltage performance.

Embodiment 2. FIG.
Next, a second embodiment according to the present invention will be described. FIG. 17 is a plan view schematically showing the configuration of the semiconductor device 1C of the second embodiment. FIG. 18 is a schematic cross-sectional view taken along line XVIII-XVIII of the semiconductor device 1C of FIG.

  As shown in FIGS. 17 and 18, the semiconductor device 1 </ b> C of the present embodiment has a trench isolation structure 14 that electrically isolates and isolates two element regions. One upper element region in FIG. 17 has an N-type body region 20Na and a P-type body region 20Pa on both sides in the X-axis direction of the gate electrode 17, and the other lower element region in FIG. N-type body region 20Nb and P-type body region 20Pb are provided on both sides in the X-axis direction. The P-type body regions 20Pa and 20Nb and the N-type body regions 20Na and 20Pb are formed in a region sandwiched between the P-type element isolation layers 15C and 15D in FIG.

  The trench isolation structure 14 is formed in the semiconductor substrate 10B of FIG. Specifically, a trench having a depth from the surface of the N-type epitaxial layer 12 of the semiconductor substrate 10B to the P-type support substrate 10 is formed by semiconductor lithography and anisotropic etching, and silicon oxide or the like is formed in the trench. The trench isolation structure 14 can be formed by embedding the insulating material. For example, the trench isolation structure 14 can be formed using a known STI (Shallow Trench Isolation) technique.

  This semiconductor device 1C has the same structure as the semiconductor device 1N of the first embodiment except for the wiring form of the contact plugs 90, 92, 94 to 96, 100 to 103, 104, and the trench isolation structure 14. Therefore, the semiconductor device 1C can be manufactured using substantially the same manufacturing process as the semiconductor device 1N. As shown in FIG. 17, in the element region above the drawing, the semiconductor device 1C has contact plugs 100, 101, 102, 103 electrically connected to the left impurity diffusion layers 30N, 31P, 32N, 33P, respectively. And contact plugs 90 and 92 electrically connected to the right impurity diffusion layers 30P and 32P, respectively. Contact plugs are not formed for the impurity diffusion layers 31N and 33N. The upper end portions of the left contact plugs 100 to 103 are connected to the upper layer wiring 77, and the upper end portions of the right contact plugs 90 and 92 are connected to the upper layer wiring 76.

  In the element region below the drawing, the semiconductor device 1C is electrically connected to the contact plugs 104 and 106 electrically connected to the left impurity diffusion layers 34N and 36N, respectively, and to the right impurity diffusion layers 34P, 35N and 36P, respectively. Contact plugs 94, 95, and 96 connected to each other. No contact plug is formed for the impurity diffusion region 35P. The upper ends of the left contact plugs 104 and 106 are connected to the upper layer wiring 79, and the upper ends of the right contact plugs 94, 95, and 96 are connected to the upper layer wiring 78.

  Among the contact plugs, a P-channel field effect transistor is configured by using the contact plugs 90 and 92 as drain electrodes, the contact plugs 101 and 103 as source electrodes, and the contact plugs 100 and 102 as back gate electrodes. Can do. On the other hand, by using the contact plugs 104 and 106 as drain electrodes, the contact plug 95 as a source electrode, and the contact plugs 94 and 96 as back gate electrodes, an N-channel field effect transistor can be configured. Further, the upper layer wiring 77 is connected to the VDD power source, the upper layer wiring 78 is connected to the VSS power source, and the upper layer wiring 76 and the upper layer wiring 79 are connected to each other, thereby forming the inverter circuit 6 as shown in FIG. be able to.

  In the inverter circuit 6 of FIG. 19, an N-channel field effect transistor 5N and a P-channel field effect transistor 4P are connected in series. The P-channel field effect transistor 4P has a source 4s to which a power supply voltage (VDD) is applied, a gate 4g, a drain 4d, and a back gate 4b. A power supply voltage (VDD) is also applied to the back gate 4b. On the other hand, the N-channel field effect transistor 5N has a source 5s to which a VSS voltage (ground potential) is applied, a gate 5g, a drain 5d, and a back gate 5b. A ground potential is also applied to the back gate 5b. When the input voltage is supplied to the gates 4g and 5g, the inverter circuit 6 outputs a voltage having a logical value obtained by inverting the logical value of the input voltage from the terminal 110.

  As described above, in the semiconductor device 1C of the present embodiment, the N-channel field effect transistor and the P-channel field effect transistor having different conductivity types and sharing the gate electrode 17 are formed on both sides of the trench isolation structure 14. it can. By forming the trench isolation structure 14 in this way, the integration degree of the field effect transistor can be improved. Therefore, the ratio of the field effect transistor to the IC chip is reduced, and as a result, the IC chip can be reduced in size.

  Although various embodiments of the present invention have been described above with reference to the drawings, these are examples of the present invention, and various forms other than those described above can also be adopted. For example, the layout design of the semiconductor device can be simplified by applying the configurations of the first and second embodiments to a standard cell.

1N, 1P, 1C semiconductor device, 6 inverter circuit, 10P type support substrate, 11N ⁺ type buried layer (NBL), 12N type epitaxial layer, 14 trench isolation structure, 15A-15D P type element isolation layer, 16 gate Insulating film, 17 gate electrode, 18A, 18B sidewall spacer, 20PP type body region, 20N N type body region, 30P-36PP type impurity diffusion layer, 30N-36N N type impurity diffusion layer, 40-46, 50, 52, 54, 56, 80, 82, 84, 86, 90 to 96 Contact plug (lead electrode), 60 Interlayer insulating film, 70, 71, 73, 74, 76 to 79 Upper layer wiring, 90, 92, 94 to 96 , 100 to 103, 104, 106 Contact plug (extraction electrode).

Claims (15)

A semiconductor substrate;
A gate electrode extending in a predetermined direction parallel to the main surface on the main surface of the semiconductor substrate and having a width in a direction intersecting the predetermined direction;
A gate insulating film interposed between the semiconductor substrate and the gate electrode;
The semiconductor substrate is
A P-type body region extending along the predetermined direction on one side of both sides in the width direction of the gate electrode, and having an end in a region immediately below the gate electrode;
An N-type body region extending along the predetermined direction on the other side of both sides in the width direction of the gate electrode, and having an end in a region immediately below the gate electrode;
A first P-type impurity diffusion region formed in the vicinity of the main surface on the one side and joined to the P-type body region;
A first N-type impurity diffusion region formed in a position facing the first P-type impurity diffusion region in the vicinity of the main surface on the other side and joined to the N-type body region;
A second N-type impurity diffusion region formed in the vicinity of the main surface on the one side and joined to the P-type body region;
The formed at a position opposed to the second N-type impurity diffusion region in the main surface vicinity, saw including a second P-type impurity diffusion regions to be bonded to the N-type body region at the other side,
The first P-type impurity diffusion region and the second N-type impurity diffusion region are formed at positions separated from each other and adjacent to each other in the predetermined direction,
The field effect transistor, wherein the first N-type impurity diffusion region and the second P-type impurity diffusion region are formed at positions adjacent to each other in the predetermined direction. . The field effect transistor according to claim 1,
A source electrode formed on the main surface of the semiconductor substrate and electrically connected to the second N-type impurity diffusion region;
A field effect transistor, further comprising: a drain electrode formed on the main surface of the semiconductor substrate and electrically connected to the first N-type impurity diffusion region.   3. The field effect transistor according to claim 2, further comprising a back gate electrode formed on the main surface of the semiconductor substrate and electrically connected to the first P-type impurity diffusion region. A characteristic field effect transistor. The field effect transistor according to claim 1,
A source electrode formed on the main surface of the semiconductor substrate and electrically connected to the second P-type impurity diffusion region;
A field effect transistor, further comprising: a drain electrode formed on the main surface of the semiconductor substrate and electrically connected to the first P-type impurity diffusion region.   5. The field effect transistor according to claim 4, further comprising a back gate electrode formed on the main surface of the semiconductor substrate and electrically connected to the first N-type impurity diffusion region. A characteristic field effect transistor.   6. The field effect transistor according to claim 1, wherein the end portion of the N-type body region and the end portion of the P-type body region are directly below the gate electrode. A field effect transistor characterized by facing each other. A semiconductor substrate;
A gate electrode extending in a predetermined direction parallel to the main surface on the main surface of the semiconductor substrate and having a width in a direction intersecting the predetermined direction;
A gate insulating film interposed between the semiconductor substrate and the gate electrode;
With
The semiconductor substrate is
A P-type body region extending along the predetermined direction on one side of both sides in the width direction of the gate electrode, and having an end in a region immediately below the gate electrode;
An N-type body region extending along the predetermined direction on the other side of both sides in the width direction of the gate electrode, and having an end in a region immediately below the gate electrode;
A first P-type impurity diffusion region formed in the vicinity of the main surface on the one side and joined to the P-type body region;
A first N-type impurity diffusion region formed in a position facing the first P-type impurity diffusion region in the vicinity of the main surface on the other side and joined to the N-type body region;
A second N-type impurity diffusion region formed in the vicinity of the main surface on the one side and joined to the P-type body region;
A second P-type impurity diffusion region formed at a position facing the second N-type impurity diffusion region in the vicinity of the main surface on the other side and joined to the N-type body region;
Including
The N-type body region and the P-type body region have shapes symmetrical to each other in the width direction with respect to a center line of the gate electrode,
The first N-type impurity diffusion region and the first P-type impurity diffusion region have shapes symmetrical to each other in the width direction with respect to a center line of the gate electrode,
The field effect transistor, wherein the second P-type impurity diffusion region and the second N-type impurity diffusion region have shapes symmetrical to each other in the width direction with respect to a center line of the gate electrode. Comprising first and second field effect transistors sharing a gate electrode formed on a semiconductor substrate;
The first field effect transistor has the same structure as the field effect transistor according to any one of claims 1 to 7 ,
The second field effect transistor has the same structure as the field effect transistor according to any one of claims 1 to 7 ,
A semiconductor device. 9. The semiconductor device according to claim 8 , wherein the semiconductor substrate has an element isolation structure for electrically insulating and isolating the first field effect transistor and the second field effect transistor from each other. Semiconductor device. The semiconductor device according to claim 9 ,
The element isolation structure is
A trench formed in the semiconductor substrate between a formation region of the first field effect transistor and a formation region of the second field effect transistor;
A semiconductor device comprising: an insulating film embedded in the trench. Forming a gate insulating film on the main surface of the semiconductor substrate;
Forming on the main surface of the semiconductor substrate via the gate insulating film a gate electrode extending in a predetermined direction parallel to the main surface and having a width in a direction intersecting the predetermined direction;
N-type impurities and P-type impurities are selectively introduced into the semiconductor substrate, and extend along the predetermined direction on one side of both sides in the width direction of the gate electrode, and directly below the gate electrode. Forming a P-type body region having an end in the region, extending along the predetermined direction on the other side of both sides in the width direction of the gate electrode, and forming an end in the region directly under the gate electrode Forming an N-type body region having:
A P-type impurity is selectively introduced in the vicinity of the main surface in the semiconductor substrate to form a first P-type impurity diffusion region joined to the P-type body region on the one side, and the other side Forming a second P-type impurity diffusion region joined to the N-type body region on the side;
A first N-type impurity is selectively introduced in the vicinity of the main surface in the semiconductor substrate, and joined to the N-type body region at a position facing the first P-type impurity diffusion region on the other side. Forming a second N-type impurity diffusion region to be joined to the P-type body region at a position opposite to the second P-type impurity diffusion region on the one side. It equipped with a door,
The first P-type impurity diffusion region and the second N-type impurity diffusion region are formed at positions separated from each other and adjacent to each other in the predetermined direction,
The field effect transistor according to claim 1, wherein the first N-type impurity diffusion region and the second P-type impurity diffusion region are formed at positions adjacent to each other in the predetermined direction . Production method. 12. The method for manufacturing a field effect transistor according to claim 11 , wherein a source electrode electrically connected to the second N-type impurity diffusion region is formed on the main surface of the semiconductor substrate, and the first A method for manufacturing a field effect transistor, further comprising forming a drain electrode electrically connected to the N-type impurity diffusion region. 13. The method of manufacturing a field effect transistor according to claim 12 , further comprising: forming a back gate electrode electrically connected to the first P-type impurity diffusion region on the main surface of the semiconductor substrate. A method of manufacturing a field effect transistor comprising: 12. The method of manufacturing a field effect transistor according to claim 11 , wherein a source electrode electrically connected to the second P-type impurity diffusion region is formed on the main surface of the semiconductor substrate, and the first A method of manufacturing a field effect transistor, further comprising the step of forming a drain electrode electrically connected to the P-type impurity diffusion region. 15. The method of manufacturing a field effect transistor according to claim 14 , further comprising: forming a back gate electrode electrically connected to the first N-type impurity diffusion region on the main surface of the semiconductor substrate. A method of manufacturing a field effect transistor comprising:

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