JP5691715B2 - FPGA, circuit reconfiguration system, method and program using FPGA - Google Patents

Description

  The present invention relates to an FPGA, a circuit reconfiguration system using an FPGA, a circuit reconfiguration method using an FPGA, and a circuit reconfiguration program using an FPGA.

  There is a strong demand for miniaturization of various electronic devices, and the mounting area of the substrate tends to be limited. Under such circumstances, it is promising to reduce the circuit scale by applying a logic design to the field programmable gate array (FPGA). The FPGA is easy to design flexibly, and can implement many functional parts from an important functional part of the device to various functional parts.

  Such superior features of FPGAs can sometimes cause fatal injury to electronic devices. Even if a relatively important functional part of the device has a problem, even if a part of a miscellaneous functional part has a problem, it is considered that the FPGA constituting these functional parts has failed. This is because there is a case where it will be.

  In an electronic device that requires reliability, a technique is adopted in which the board to be used is made redundant and the operation of the electronic device is continued by duplicating the system even when a failure occurs. In an electronic device that does not employ such duplication, there is a possibility that the operation of the device may be stopped due to a malfunction that has occurred in the FPGA. In such a case, when the operation of the apparatus is stopped, it can be recovered by replacing the board on which the FPGA is mounted. However, there is a problem that the time until the recovery work is wasted and the labor cost of the worker is increased.

  In order to prevent such a problem from occurring, it has been studied to duplicate the FPGA by arranging a plurality of identical FPGAs on a substrate built in the electronic device. However, disposing a plurality of identical FPGAs not only increases the size of the substrate, but also may increase the cost of the electronic device.

  Thus, as a related technique related to the present invention, it has been proposed to use an FPGA capable of partial reconfiguration (see, for example, Patent Document 1 and Patent Document 2).

FIG. 11 shows a functional configuration of an FPGA mounted on a substrate (not shown) as one of related techniques of the present invention. The FPGA 100 is divided into a constantly operating portion 101 that always functions as a circuit, and a free resource portion 102 as an area other than that. In the free resource portion 102, an electronic device designer can configure an arbitrary circuit portion. In the example shown in FIG. 11, first to third static reconfiguration portions 103 _{1 to} 103 ₃ are configured as part of the free resource portion 102. Here, the static reconfigurable portions 103 _{1 to} 103 ₃ are circuits configured by combining circuit components without particularly considering the timing of input / output signals. In the example shown in FIG. 11, a signal is input to the _first static reconstruction portion 103 _1, and signal processing is sequentially performed up to the third static reconstruction portion 103 ₃ , and the third static reconstruction portion 103 ₃ from the processing results are outputted.

Each of the _first to third static reconfigurable parts 103 _{1 to} 103 ₃ is the same as other general circuits, but there is a possibility of causing a problem in signal processing for some reason. Therefore, the free resource portion 102 includes the first to third monitoring units 104 for monitoring to detect when any of the _first to third static reconfiguration portions 103 _{1 to} 103 ₃ is defective. _{1-104 3} is provided.

Further, in the free resource portion 102, the first to third static reconfigurable areas 105 are prepared in case a failure is detected in any of the _first to third static reconfigurable portions 103 _{1 to} 103 _{3. 1-105 3} are prepared. The first to third static reconfigurable areas 105 _{1 to} 105 ₃ are areas provided as spares. Therefore, the circuit does not operate as a specific circuit in a state where no malfunction occurs in the first to third static reconfiguration portions 103 _{1 to} 103 ₃ .

FIG. 12 shows a change in the circuit configuration of the FPGA when a failure occurs in the first static reconfigurable area in the related technique of the present invention. When a failure occurs in the first static reconfiguration portion 103 ₁ , the first monitoring unit 104 ₁ detects this. Then, based on this detection result, the always-operating part 101 configures a circuit part in place of the first static reconfigurable part 103 ₁ in which a malfunction has occurred in the first static reconfigurable area 105 ₁ . Then, as indicated by an arrow 111, the first static reconfigurable area 105 ₁ is switched as a circuit portion instead of the _first static reconfigurable portion 103 ₁ .

As a result, for example, the signal processing in which the first to third static reconfigurable portions 103 _{1 to} 103 ₃ are sequentially passed through the first static reconfigurable region 105 ₁ , the second and third static reconfigurable regions The signal processing is changed through the reconstruction parts 103 ₂ and 103 ₃ in order. As described above, even if a failure occurs in a part of the circuit of the FPGA 100, the entire FPGA 100 can continue to operate without causing a system down.

  However, if the fault function is reconfigured in the area that is defined as the free resource 102, the circuit portion after the reconfigured function unit may not be able to exhibit sufficient capability. This is because an error may occur in the timing of the optimized internal clock and the output delay due to, for example, the reconfigured functional unit.

Problems associated with the related art will be described with reference to FIGS. In FIG. 13A, the first to third logic units 121 to 123 are circuit portions corresponding respectively to the first to third static reconfiguration portions 103 _{1 to} 103 ₃ in FIG. The first to third logic units 121 to 123 are configured by appropriately combining components from a large number of circuit components (not shown) that constitute the FPGA 120.

  An internal clock 124 is supplied to each of the first to third logic units 121 to 123. The first logic unit 121 is supplied with a signal 125 and outputs a signal 126 as a result of performing predetermined processing. The signal 126 is input to the second logic unit 122. The second logic unit 122 outputs a signal 127. The signal 127 is input to the third logic unit 123. The third logic unit 123 outputs a signal 128.

The first to third reconfigurable units 131 to 133 in the FPGA 120 are circuit portions respectively corresponding to the _first to _third static reconfigurable regions 105 _{1 to} 105 ₃ in FIG. FIG. 13A shows a state in which no defect has occurred in the first to third logic units 121 to 123. Therefore, none of the first to third reconfigurable units 131 to 133 is supplied with an internal clock, and there is no input / output of a signal to be processed.

  In FIG. 13A, a transmission path through which the signal 126 between the first logic unit 121 and the second logic unit 121 is transmitted and a signal between the second logic unit 122 and the third logic unit 123 are transmitted. It is assumed that the transmission path through which 127 is transmitted is composed of a good conductor such as wiring and has a short path. Therefore, for example, the signal output from the first logic unit 121 and the signal input to the second logic unit 122 can be treated as having the same electrical characteristics. It represents as. The same applies to the signal 127.

  FIG. 13B shows the operation timing at the connection point of the first and second logic units when the first to third logic units are operating normally. As shown in FIG. 6A, an internal clock 124 having a predetermined period is supplied to the second logic unit 122. As shown in FIGS. 6A and 6B, the internal clock 124 rises at a substantially central position of the signal 126 output from the first logic unit 121. Therefore, when the second logic unit 122 inputs the signal 126 in synchronization with the rising edge of the internal clock 124, the input process of the signal 126 is stabilized.

  FIG. 14 shows a state immediately after some trouble occurs in the first logic unit 121 in the FPGA 120. Since it is immediately after the occurrence of the problem, there is no particular change in the figure (A) and the figure (B).

  FIG. 15 shows a circuit configuration and its operation when the first reconfiguration logic unit starts processing in place of the first logic unit in which a problem has occurred. When the first logic unit 121 cannot be used due to a malfunction, the first reconfigurable unit 131 is configured as the first reconfigurable logic unit as indicated by an arrow 140 in FIG. When a net list (not shown) representing connection information data between terminals in the FPGA 120 is changed, the signal 125 input to the first logic unit 121 is transferred to the first reconfiguration logic unit 131. The input destination is changed.

  As a result, a signal 141 is newly output from the first reconfiguration logic unit 131. Compared with the example of FIG. 14, the signal 141 changes its characteristics through the “excessive” transmission path portion 142 and is input to the second logic unit 122 as the signal 143.

  FIG. 15B shows the operation timing at the connection point between the first reconfiguration logic unit and the second logic unit after the circuit change shown in FIG. 15A is performed. As shown in FIG. 6A, the internal clock 124 input to the first reconfiguration logic unit 131 is the same as that input to the first logic unit 121. Therefore, if the first reconfiguration logic unit 131 itself is reconfigured as a logic unit having exactly the same characteristics as the first logic unit 121, the signal 141 is as shown in FIG. The signal is output from the first reconfiguration logic unit 131 at exactly the same timing as the signal 126 shown in FIG.

JP 2001-136058 A (paragraph 0012, paragraph 0013, FIG. 1) JP 2009-140353 A (paragraphs 0033 to 0041, FIGS. 1 to 3)

  However, the first reconfiguration logic unit 131 is configured at a location different from the location where the first logic unit 121 is configured in the FPGA 120. For this reason, the length of the “excessive” transmission path portion 142 that connects the output side of the first reconfiguration logic unit 131 and the input side of the second logic unit 122 and the circuit components that constitute the transmission line portion are used for signal transmission. Affects timing. As a result, for example, as shown in (B) and (C) of FIG. 15B, the signal 143 input to the second logic unit 122 is the signal 141 delayed by, for example, a half cycle of the internal clock 124. It becomes.

  Of course, the transmission path between the first reconfiguration logic unit 131 and the second logic unit 121 actually has a simpler circuit configuration, and the first logic unit 121 and the second logic unit 121 In some cases, the transmission path between the first and second logic units 121 causes more delay. However, even in this case, the difference in signal transmission time between the two transmission paths due to the difference in the transmission paths is the same. Therefore, here, it is assumed that an amount of delay as shown in (C) of FIG.

  Depending on the degree of delay of the signal 143, the second logic unit 122 is likely to malfunction. This becomes an illegal factor of the signal 128 output from the third logic unit 123. The same may occur when the second logic unit 122 or the third logic unit 123 is switched to the second reconfiguration logic unit 132 or the third reconfiguration logic unit 133.

  The case where one circuit is configured by three logic units has been described above, but the same problem occurs regardless of the number of logic units configuring one circuit. That is, even if each logic part is configured as a circuit having the same characteristics by combining circuit parts of the same type in terms of circuit, the transmission line connecting them is not necessarily composed only of a conductive line. There is a possibility that a circuit component that may shift the timing of the switching element or the like is interposed. Therefore, for example, if the transmission paths connecting the logic units are different, the signal transmission timing may be different, which causes a malfunction in a device using the FPGA.

  Accordingly, an object of the present invention is to prevent a problem in timing of a signal transmitted in relation to a new circuit when a problem occurs in a part of the circuit and a new circuit is reconfigured on the same substrate. An FPGA, a circuit reconfiguration system using FPGA, a circuit reconfiguration method using FPGA, and a circuit reconfiguration program using FPGA are provided.

  In the present invention, (a) several logic units each functioning as a logic circuit having desired characteristics are configured by appropriately selecting and combining from a large number of circuit components formed in a specific region on the same substrate. A desired number of circuit blocks each having a group of circuit functions can be obtained by configuring a connection part as a part for electrically connecting the above-described logic parts from the above-described many circuit parts. Circuit block initial configuration means configured initially, and (b) a circuit including a logic unit in which a malfunction occurs by monitoring these operations when each circuit block configured by the circuit block initial configuration means is in operation A circuit block monitoring means for detecting a block; and (c) when a circuit block including a failed logic unit is detected by the circuit block monitoring means. A circuit block comprising a new logic unit having the same circuit characteristics as each of the above-described logic units constituting the block, a new connection unit having the same connection timing as possible, and a signal transmission timing as described above And (d) a new circuit block configured by the optimization processing execution means is configured by optimization processing from an unused portion of a large number of circuit components formed in the specific area. The FPGA (Field Programmable Gate Array) includes circuit block replacement means for starting a new operation by replacing the circuit block including the failed logic unit with the circuit block monitoring means.

  In the present invention, (a) an FPGA (Field Programmable Gate Array) in which a large number of circuit components are formed in a specific area on the same substrate, and (b) an appropriate selection from the above-mentioned numerous circuit components of the FPGA. As a part for electrically connecting the above-mentioned logic parts from among the above-mentioned many circuit parts, the logic parts functioning as logic circuits having desired characteristics can be formed by combining them. Circuit block initial configuration means for initially configuring a desired number of circuit blocks each having a circuit function of a single unit by configuring a connection section; and (c) each circuit configured by the circuit block initial configuration means. A circuit block that receives this notification when a circuit block that includes a failed logic part is detected as a monitoring result of these operations while the block is in operation. Monitoring means, and (d) when the circuit block monitoring means notifies that a circuit block including a failed logic unit has been detected, each of the above-described logic units constituting the circuit block as a circuit A circuit block having a new logic part having the same characteristics and a new connection part having the same timing as that of signal transmission with the above-described connection part is formed in a large number of circuit components formed in the specific region. And (e) a new circuit block configured by the optimization processing execution unit includes a logic unit in which a failure has occurred in the circuit block monitoring unit. A circuit reconfiguration system using FPGA includes circuit block replacement means for replacing a circuit block and starting a new operation.

  Furthermore, in the present invention, (a) a logic circuit having desired characteristics can be obtained by appropriately selecting and combining from a large number of circuit components formed in a specific area on a substrate constituting an FPGA (Field Programmable Gate Array). And a plurality of circuit parts, and a connection part as a part for electrically connecting the logic parts among the many circuit parts described above. (B) Initially configuring a desired number of circuit blocks having functions in a desired number of circuit blocks, and (b) monitoring these operations when each circuit block configured in this circuit block initial configuration step is in operation. A circuit block monitoring step for detecting a circuit block including a failed logic part, and (c) the circuit block monitoring step When a circuit block including a logic unit in which a failure occurs is detected, the timing of signal transmission between the new logic unit having the same circuit characteristics as each of the above-described logic units constituting the circuit block and the above-described connection unit An optimization processing execution step for configuring a circuit block having a new connection portion that is as identical as possible by an optimization process from unused portions of a large number of circuit components formed in the specific region, (D) a circuit block replacement step for starting a new operation by replacing a circuit block including a logic unit in which a failure has occurred in the circuit block monitoring step with a new circuit block configured by the optimization processing execution step. A circuit reconfiguration method using an FPGA is provided.

  Furthermore, in the present invention, as a circuit reconfiguration program using an FPGA, the computer appropriately selects (i) a large number of circuit components formed in a specific area on a substrate constituting an FPGA (Field Programmable Gate Array). As a part for electrically connecting between the above-mentioned logic parts among the above-mentioned many circuit parts, the logic parts functioning as logic circuits having desired characteristics can be configured by combining them. Circuit block initial configuration processing for initially configuring a desired number of circuit blocks each having a group of circuit functions, and (b) each of the circuit blocks configured by this circuit block initial configuration processing. A circuit block monitor that monitors these operations when a circuit block is in operation and detects a circuit block that includes a failed logic unit. (C) When a circuit block including a failed logic unit is detected by this circuit block monitoring process, a new logic having the same circuit characteristics as each of the logic units constituting the circuit block is detected. Circuit block with a new connection portion where the signal transmission timing is the same as possible with the above-mentioned connection portion and the above-described connection portion is optimal from the unused portion among the many circuit components formed in the specific region described above And (d) a new circuit block configured by the optimization process execution process is replaced with a circuit block including a logic unit in which a failure has occurred in the circuit block monitoring process. Circuit block replacement processing for starting a simple operation.

  As described above, according to the present invention, not only is a logical unit selected from a large number of circuit components formed in a specific area on a substrate constituting an FPGA, but also a logical unit is connected. Since the operation timing of the connection unit is optimized, the electrical characteristics of the circuit block reconfigured by combining a plurality of logic units can be brought as close as possible to the original circuit block. As a result, stable operation and long life of the apparatus using the FPGA can be achieved.

It is a claim correspondence figure of FPGA of this invention. It is a claim correspondence diagram of a circuit reconfiguration system using the FPGA of the present invention. It is a claim corresponding | compatible figure of the circuit reconfiguration | reconstruction method using FPGA of this invention. It is a claim corresponding | compatible figure of the circuit reconfiguration program using FPGA of this invention. It is a functional block diagram showing the outline | summary of the functional structure of FPGA in embodiment of this invention. It is the block diagram and timing diagram which showed the timing relationship of the structure and principal part about an example of the circuit block before the factory shipment of this Embodiment, and the monitoring circuit part corresponding to this. FIG. 6 is a block diagram and a main part timing diagram showing a state immediately after some trouble occurs in the first logic part in the FPGA of the present embodiment. In the block diagram and the principal part timing diagram which showed the 1st-3rd logic part comprised as a new circuit block in the logic part configurable area | region by malfunction having generate | occur | produced in the 1st logic part of this Embodiment is there. It is a flowchart showing the mode of the failure processing which the control part performs in FPGA of this Embodiment. It is explanatory drawing which showed the method of detecting generation | occurrence | production of the malfunction of the logic part of the modification of this invention. It is explanatory drawing showing the functional structure of FPGA mounted on the board | substrate which is not illustrated as one of the related arts of this invention. It is explanatory drawing which showed the mode of the change of the circuit structure of FPGA when a malfunction generate | occur | produces in the 1st statically reconfigurable area | region of the related technology of this invention. FIG. 12 is a block diagram and a timing diagram illustrating a configuration of circuit portions corresponding to first to third static reconfiguration portions in FIG. FIG. 14 is a block diagram and a timing diagram showing the configuration of the circuit part shown in FIG. 13 and the timing relationship of the main part immediately after a failure occurs in the first logic part in the FPGA shown in FIG. FIG. 14 is a block diagram and a timing diagram showing a configuration of a circuit part shown in FIG. 13 and a timing relationship between main parts when the first reconfiguration logic part starts processing in place of the first logic part in which a problem has occurred. .

  FIG. 1 shows a claim correspondence diagram of an FPGA (Field Programmable Gate Array) of the present invention. The FPGA 10 of the present invention includes a circuit block initial configuration unit 11, a circuit block monitoring unit 12, an optimization processing execution unit 13, and a circuit block replacement unit 14. Here, the circuit block initial configuration means 11 includes several logic units each functioning as a logic circuit having a desired characteristic by appropriately selecting and combining from a large number of circuit components formed in a specific region on the same substrate. In addition, a circuit block having a group of circuit functions can be obtained by configuring a connection unit as a component for electrically connecting the above-described logic units from among the many circuit components described above. Configure the desired number initially. The circuit block monitoring means 12 monitors these operations when each circuit block configured by the circuit block initial configuration means 11 is in operation, and detects a circuit block including a logic unit in which a failure has occurred. When the circuit block monitoring unit 12 detects a circuit block including a failed logic unit, the optimization processing execution unit 13 has a new circuit that has the same circuit characteristics as each of the logic units included in the circuit block. Circuit block having a new logic unit and a new connection unit in which the timing of signal transmission is the same as possible with the above-described connection unit, and an unused part among many circuit components formed in the specific region To configure by optimization processing. The circuit block replacement unit 14 replaces the new circuit block configured by the optimization processing execution unit 13 with the circuit block including the logic unit in which the failure has occurred in the circuit block monitoring unit 12, and starts a new operation.

  FIG. 2 shows a claim correspondence diagram of a circuit reconfiguration system using an FPGA (Field Programmable Gate Array) of the present invention. The circuit reconfiguration system 20 using the FPGA of the present invention includes an FPGA 21, a circuit block initial configuration unit 22, a circuit block monitoring unit 23, an optimization process execution unit 24, and a circuit block replacement unit 25. Here, the FPGA 21 is a device in which a large number of circuit components are formed in a specific region on the same substrate. The circuit block initial configuration means 22 constitutes several logic units each functioning as a logic circuit having a desired characteristic by appropriately selecting and combining the circuit components of the FPGA 21 as described above. A desired number of circuit blocks each having a group of circuit functions are initially configured by configuring a connection unit as a component for electrically connecting the above-described logic units from among the circuit components. . The circuit block monitoring unit 23 notifies this when a circuit block including a logic unit in which a failure has occurred is detected as a monitoring result of these operations when each circuit block configured by the circuit block initial configuration unit 22 is in operation. Receive. When the optimization processing execution means 24 is notified by the circuit block monitoring means 23 that a circuit block including a failed logic part has been detected, the optimization process execution means 24 is configured as a circuit and each of the aforementioned logic parts constituting the circuit block. Circuit parts having a new logic part having the same characteristics and a new connection part having the same timing as that of the above-mentioned connection part and the signal transmission as much as possible are formed in the specific region described above. It is constituted by an optimization process from an unused portion of the. The circuit block replacement unit 25 replaces the new circuit block configured by the optimization processing execution unit 24 with the circuit block including the logic unit in which the failure has occurred in the circuit block monitoring unit 23, and starts a new operation.

  FIG. 3 is a diagram corresponding to a claim of the circuit reconfiguration method using the FPGA (Field Programmable Gate Array) of the present invention. The circuit reconfiguration method 30 using the FPGA of the present invention includes a circuit block initial configuration step 31, a circuit block monitoring step 32, an optimization processing execution step 33, and a circuit block replacement step 34. Here, in the circuit block initial configuration step 31, several functions function as logic circuits having desired characteristics by appropriately selecting and combining from among a large number of circuit components formed in a specific region on the substrate constituting the FPGA. In addition to the above-described logic unit, a connection unit as a component for electrically connecting the above-described logic units among the above-described many circuit components is configured, thereby having a group of circuit functions. A desired number of circuit blocks are initially configured. In the circuit block monitoring step 32, when each circuit block configured in the circuit block initial configuration step 31 is in operation, these operations are monitored to detect a circuit block including a logic unit in which a failure has occurred. In the optimization processing execution step 33, when a circuit block including a failed logic unit is detected by the circuit block monitoring step 32, a new circuit having the same circuit characteristics as each of the aforementioned logic units constituting the circuit block is detected. Circuit block having a new logic unit and a new connection unit in which the timing of signal transmission is the same as possible with the above-described connection unit, and an unused part among many circuit components formed in the specific region To configure by optimization processing. In the circuit block replacement step 34, the new circuit block configured in the optimization processing execution step 33 is replaced with the circuit block including the logic unit in which the failure occurred in the circuit block monitoring step 32, and a new operation is started.

  FIG. 4 shows a claim correspondence diagram of a circuit reconfiguration program using an FPGA (Field Programmable Gate Array) of the present invention. The circuit reconfiguration program 40 using the FPGA of the present invention causes the computer to execute a circuit block initial configuration process 41, a circuit block monitoring process 42, an optimization process execution process 43, and a circuit block replacement process 44. ing. Here, in the circuit block initial configuration processing 41, several functions that function as logic circuits having desired characteristics are selected by appropriately selecting from a number of circuit components formed in a specific region on the substrate constituting the FPGA. In addition to the above-described logic unit, a connection unit as a component for electrically connecting the above-described logic units among the above-described many circuit components is configured, thereby having a group of circuit functions. A desired number of circuit blocks are initially configured. In the circuit block monitoring process 42, when each circuit block configured in the circuit block initial configuration process 41 is in operation, these operations are monitored to detect a circuit block including a logic unit in which a failure has occurred. In the optimization process execution process 43, when a circuit block including a failed logic unit is detected by the circuit block monitoring process 42, a new circuit having the same circuit characteristics as each of the logic units constituting the circuit block is detected. Circuit block having a new logic unit and a new connection unit in which the timing of signal transmission is the same as possible with the above-described connection unit, and an unused part among many circuit components formed in the specific region To configure by optimization processing. In the circuit block replacement process 44, a new circuit block configured by the optimization process execution process 43 is replaced with a circuit block including a logic unit in which a failure has occurred in the circuit block monitoring process 42, and a new operation is started.

  <Embodiment of the Invention>

  Next, an embodiment of the present invention will be described.

  FIG. 5 shows an outline of a functional configuration of the FPGA according to the embodiment of the present invention. The FPGA 200 includes a constant operation unit 201, a logic unit configurable area 202, and a monitoring unit configuration area 203. Here, the constantly operating unit 201 is a part that always functions as a circuit device.

  The constant operation unit 201 includes a CPU (Central Processing Unit) 211, a control unit 213 including a memory 212 that stores a control program executed by the CPU 211, an optimization processing unit 214, and a circuit block correspondence table 215. . Here, the optimization processing unit 214 is a part that performs processing for optimization in consideration of the timing of signal processing when reconfiguring the logic unit as a result of the occurrence of a defect in some of the logic units described later. is there. The optimization processing unit 214 may be previously created in the FPGA 200 as unique hardware, or the control unit 213 may be realized by software.

  The circuit block correspondence table 215 is a table in which circuit blocks that are candidates for replacing one circuit block including a logic unit in which a failure has occurred are prepared in advance as a table. In the case of the present embodiment, candidate circuit blocks are optimized in advance so as to realize the timing of signal processing that was realized when the logic unit in which the failure occurred is normal. Therefore, if a circuit block prepared in the circuit block correspondence table 215 is selected, it is possible to prevent generation of a signal having a shifted timing, such as the signal 143 described with reference to FIG. In this embodiment, “static reconfiguration” is not performed by simply combining logic portions having the same circuit function, but “dynamic reconfiguration” is performed in consideration of signal delay between the logic portions constituting the circuit block. This is because “configuration” is performed.

  In this specification, each “circuit block” is a logic cell including a plurality of logic units and a signal transmission path connecting them, such as the first to third logic units 121 to 123 shown in FIG. And an assembly of circuit components such as internal wiring. The circuit block correspondence table 215 can be composed of a nonvolatile memory area that constitutes a part of the memory 212.

  In addition to the normal operation unit 201, a clock generation circuit that inputs an external reference clock to generate an internal clock, a normal operation unit monitoring unit (both not shown) that detects a malfunction in the normal operation unit 201, and the like. There are several circuit parts that operate constantly.

  It is assumed that there is a case where a failure occurs in the logic unit, and the circuit blocks constituting this are not registered in the circuit block correspondence table 215. In such a case, the optimization processing unit 214 obtains a circuit block having the same characteristics as much as possible with a circuit block having a failed logic unit by calculation based on a combination of circuit components. Therefore, depending on the FPGA 200, the circuit block correspondence table 215 can be enriched, so that the optimization processing by the optimization processing unit 214 can be substantially omitted, and conversely, the circuit block correspondence table 215 can be provided only by the optimization processing unit 214. Can be eliminated.

  The logic section configurable area 202 and the monitoring section configuration area 203 are composed of circuit parts such as the above-described logic cells and internal wiring, and a logic section and a monitoring section circuit are formed by appropriately combining them. Of these, the area allocated to configure the logic unit is the logic unit configurable area 202, and the remaining area is the monitoring unit configuration area 203 for configuring the monitoring unit. The monitoring unit configuration area 203 is configured to monitor whether or not a failure has occurred in each of the configured logic units based on the signal input / output state. In a part of the monitoring unit configuration area 203, a monitoring data storage unit 221 that stores monitoring data for detecting occurrence of a failure in each logical unit is arranged.

  FIG. 6 shows the timing relationship between the configuration and main parts of an example of a circuit block before shipment from the factory and an example of a monitoring circuit portion corresponding to the circuit block. This will be described with reference to FIG.

  In FIG. 6A, the first to third logic units 231 to 233 show an example of one circuit block, and a large number of circuit parts (not shown) constituting the logic unit configurable area 202 in the FPGA 200 are shown. It is configured by appropriately combining parts from the inside. The first logic unit 231 is monitored by the first monitoring unit 241 configuring the monitoring unit configuration area 203. Similarly, the second logic unit 232 is monitored by the second monitoring unit 242 configuring the monitoring unit configuration area 203, and the third logic unit 233 is monitored by the third monitoring unit 243 configuring the monitoring unit configuration area 203. Is done. The first to third monitoring units 241 to 243 are configured in accordance with the first to third logic units 231 to 233 before they are shipped from the factory. The first to third monitoring units 241 to 243 are also configured by appropriately combining components from a large number of circuit components (not shown) constituting the monitoring unit configuration area 203.

  An internal clock 251 is supplied to each of the first to third logic units 231 to 233. The first logic unit 231 is supplied with a signal 255 and outputs a signal 256. The signal 256 is input to the second logic unit 232. The second logic unit 232 outputs a signal 257. The signal 257 is input to the third logic unit 233. The third logic unit 233 outputs a signal 258.

  On the other hand, the first monitoring unit 241 receives monitoring data 261 output from the first logic unit 231 during operation. The first monitoring unit 241 compares the monitoring data 261 with the monitoring collation data 271 for the first logic unit 231 stored in the monitoring data storage unit 221, and a failure occurs in the first logic unit 231. Monitor whether you did.

  Similarly, the second and third monitoring units 242 and 243 receive the corresponding ones of the monitoring data 262 and 263 output from the second and third logic units 232 and 233 during operation. The second and third monitoring units 242 and 243 monitor the second or third logic units 232 and 233 in which the corresponding ones of the monitoring data 262 and 263 are stored in the monitoring data storage unit 221. In comparison with the verification data 272, 273, whether or not a failure has occurred in the second or third logic unit 232, 233 is monitored.

  As the monitoring collation data 271 stored in the monitoring data storage unit 221, for example, the monitoring data 261 that is output when the first logic unit 231 normally operates normally is used. Then, after the first logic unit 231 starts operation, the monitoring data 261 to be sequentially output is collated with the monitoring collation data 271, and there is a problem with the first logic unit 231 while the two match. It is determined that it has not occurred. Also, if the monitoring data 261 and the monitoring collation data 271 do not match, it is determined that a problem has occurred in the first logic unit 231. The same applies to the other monitoring verification data 272 and 273 stored in the monitoring data storage unit 221.

  FIG. 6B shows the operation timing at the connection location of the first and second logic units in a state where the first to third logic units are operating normally. As shown in FIG. 6A, an internal clock 251 having a predetermined cycle is supplied to the second logic unit 232. As shown in FIGS. 6A and 6B, the internal clock 251 rises at approximately the center position of the signal 256 output from the first logic unit 231. As described above, the second logic unit 232 inputs the signal 256 in synchronization with the rising edge of the internal clock 251, so that the input process is stable.

  FIG. 7 shows a state immediately after some trouble has occurred in the first logic unit in the FPGA. Since this time is immediately after the occurrence of a problem, the first monitoring unit 241 that inputs the monitoring data 261 has not yet detected a problem in the first logic unit 231. In addition, the internal clock 251 shown in FIGS. 7B and 12B, the signal 256 output from the first logic unit 231 shown in (B) and the signal 256 input to the second logic unit 232 shown in (C). There is no change.

  FIG. 8A shows the first to third logic units configured as new circuit blocks in the logic unit configurable area due to the occurrence of a problem in the first logic unit. This will be described with reference to FIG. In the logic part configurable area 202 shown in FIG. 5, several circuit blocks such as circuit blocks including the first to third logic parts 231 to 233 shown in FIG. 6 in this example are configured prior to factory shipment. Has been. However, for convenience of explanation, only the new circuit blocks corresponding to the first to third logic units 231 to 233 are not shown. Among the circuit blocks including the first to third logic units 231 to 233, in this example, the first logic unit 231 generates a problem and is in an unusable state.

  In this embodiment, in such a case, the unused part 281 in the logic unit configurable area 202, that is, the circuit component existing in the space area in which the circuit block can be newly configured is used and used up to now. The circuit block is configured completely separately from the circuit block. This is a circuit block including first to third logic units 291 to 293.

  In the circuit block correspondence table 215, several circuit blocks are registered in association with the circuit blocks constituting the first to third logic units 231 to 233 shown in FIG. For circuit blocks (not shown) already configured in the logic section configurable area 202 in FIG. 5, the arrangement contents of specific circuit components constituting the substitute circuit blocks are registered in the circuit block correspondence table 215. Yes. For example, in the case of circuit blocks constituting the first to third logic units 291 to 293, these alternative circuit blocks are the same as those for configuring the first to third logic units 231 to 233 shown in FIG. The circuit characteristics are optimized by selecting the location where the circuit component is placed.

  If a plurality of circuit blocks that are candidates for substitution are registered in the circuit block correspondence table 215 for each circuit block including a logic part in which a defect has occurred, other circuit blocks have a defect and are used for replacement. Even if some of the circuit components are used for the first circuit block, it is possible to select another circuit block arranged in a place where the circuit components do not overlap.

  The above is a description of the case where a circuit block in which a failure has occurred in the logic unit is replaced with another circuit block using the circuit block correspondence table 215. Of course, using the optimization processing unit 214 shown in FIG. 5, the first to third logic units 231 to 233 and the first to first logics having characteristics similar to the circuit characteristics as much as possible to the circuit block composed of the transmission path connecting them. The three logic units 291 to 293 may be configured by selecting from circuit components in the unused area 281.

  As a result of the above processing, when a failure occurs in the first logic unit 231, a circuit block including the first to third logic units 291 to 293 in the unused area 281 is newly configured. become. The internal clock 251 is supplied to each of the first to third logic units 291 to 293, and the signal 255 is supplied to the first logic unit 291. As a result, a signal 301 is output from the newly configured first logic unit 291, and this is supplied as a signal 302 to the newly configured second logic unit 292.

  A signal 303 is output from the second logic unit 292, and this signal is supplied as a signal 304 to the newly configured third logic unit 293. A signal 305 is output from the third logic unit 293. If the circuit block including the first to third logic units 291 to 293 has characteristics as close as possible to the circuit blocks constituting the first to third logic units 231 to 233 shown in FIG. The signal 305 has characteristics as close as possible to those of the signal 258 output from the third logic unit 233 in FIG.

  FIG. 8B shows the timing of the signal output from the first logic unit and the signal supplied to the second logic unit. Of these, FIG. 4A shows the internal clock 251. As shown in FIGS. 6A and 6B, the internal clock 251 rises at approximately the center position of the signal 301 output from the first logic unit 291. Further, as shown in FIGS. 6A and 6C, the second logic unit 292 inputs a signal 302 in synchronization with the rising edge of the internal clock 251. As a result, the input processing of the signal 302 is stabilized, and illegal signal processing as described with reference to FIG. 15 is avoided.

  FIG. 9 shows a state of failure processing performed by the control unit in the FPGA having the above outline. Here, the term “failure” refers to a concept that encompasses various problems of the FPGA 200 including the problems of the first to third logic units 231 to 233 shown in FIG. 6, for example. When a failure is detected in the monitoring result (FIG. 6) by the monitoring unit (FIG. 6) such as the first monitoring unit 241 configured in the monitoring unit configuration area 203 shown in FIG. 5, the detected content is notified to the control unit 213 as a failure. The The above-described constantly operating unit monitoring unit detects a malfunction in the constantly operating unit 201 and notifies the control unit 213 of the result. Hereinafter, FIG. 9 will be described together with FIG. 5 and FIG.

  The control unit 213 waits for failure detection (step S401). When a failure is detected (Y), the control unit 213 determines whether or not the constantly operating unit 201 has failed (step S402). This is because it is determined whether the failure part is always the operation part 201 or the logic part configurable area 202 or the monitoring part configuration area 203 as other parts.

  When it is determined that the constantly operating unit 201 has failed (step S402: Y), the control unit 213 determines a logic unit that has been notified of a failure in the past or a circuit part that has been found to have a failure in the always operating unit 201. Using the entire removed FPGA 200, the reconfiguration is performed. For this reason, the optimization processing unit 214 performs optimization calculation for configuring necessary circuit portions in all regions of the FPGA 200 except for the portions where these failures are found (step S403). Then, the FPGA 200 is reset to reconfigure necessary circuit portions (step S404), the processing is ended (end), and the operation can be resumed. Here, the necessary circuit parts are a constantly operating unit 201, a necessary circuit block in the logic unit configurable area 202, and a monitoring unit that detects a defect in the circuit block in the monitoring unit configuration area 203.

  On the other hand, if it is determined in step S402 that there is a failure other than the constant operation unit 201 (N), the control unit 213 checks whether the circuit block that has been notified of the failure is already registered in the circuit block correspondence table 215 ( Step S405). If it is registered in the circuit block correspondence table 215 (Y), it is determined whether the circuit block indicated as the circuit block to be replaced can be replaced at the time of determination (step S406). This is because the circuit block that is the current alternative candidate is used when another circuit block has previously failed and the circuit components that make up the circuit block that is the current alternative candidate are already in use. Because it becomes impossible. Of course, when two or more alternative candidates are registered in the circuit block correspondence table 215, there are alternative circuit block candidates that can be used unless all the circuit blocks that are alternative candidates have been used. become.

  When a replaceable circuit block exists (step S406: Y), the control unit 213 reconfigures the circuit block in the logic unit configurable area 202 (step S407). At this time, when there are a plurality of replaceable circuit blocks, one of them is selected as a circuit block for replacement. In this case, when a priority order is determined for reasons such as circuit characteristics, the selection of the circuit block is followed.

  When a circuit block that replaces the failed circuit block is reconfigured in this way, the control unit 213 reconfigures the transmission path of that part so that the monitoring unit used before the failure is connected to the reconfigured circuit block. Configure (step S408). Alternatively, the monitoring unit connected to the reconfigured circuit block can be reconfigured in the monitoring unit configuration area 203. With the process in step S408, the FPGA 200 ends the process for resuming the operation by reconfiguring the circuit block (end).

  On the other hand, the failed circuit block may not be registered in the circuit block correspondence table 215 (step S405: N). As an example, there is a case where a failed circuit block is a circuit block that has been reconfigured once. In such a case, or when it is found that even a circuit block registered in the circuit block correspondence table 215 cannot be reconfigured as a replacement candidate (step S406: N), the optimization processing unit 214 is set. The used circuit block is reconfigured (step S409).

  This circuit block reconfiguration processing is similar to the processing in steps S403 and S404. That is, in step S409, the entire logic unit configurable area 202 excluding the circuit portion in which a failure has been found in the logic unit for which a failure has been notified in the past is used to reconfigure the corresponding circuit block. . For this reason, the optimization processing unit 214 performs optimization calculation for constructing a necessary circuit part in all unused areas of the logical part configurable area 202 excluding the part where the failure is found. Then, the FPGA 200 is reset, a new circuit block is reconfigured, and the processing is ended (END).

  The optimization processing in step S403 or step S409 is performed by the control unit 213 having a compiler installed and compiling data relating to circuit components existing in the target region. By performing the optimization process using the compiler, it is possible to omit the process of calculating the reconstruction candidate circuit blocks corresponding to the individual circuit blocks in advance and registering them in the circuit block correspondence table 215. In addition, since the minimum operation of the corresponding circuit block is guaranteed by performing the optimization process, the FPGA 200 does not cause a fatal system down, and it is possible to provide functions equivalent to those before the failure. Of course, when the optimization processing is performed using the optimization processing unit 214, the larger the capacity of the FPGA 200, the longer the compilation time of various data for the optimization processing, so the operation of the FPGA 200 is resumed. It will take a long time.

  In the present embodiment, the method using the circuit block correspondence table 215 and the method using the optimization processing unit 214 are used together. Therefore, in many cases of reconfiguring the circuit block in the logic unit configurable area 202, the time can be shortened, and a failure that cannot be dealt with can be dealt with.

  In the embodiment, the reconfiguration is performed in units of circuit blocks. As a result, as compared with the case where only some of the logic units are reconfigured, the transmission that connects the newly reconfigured logic unit to the logic unit in which no defect has occurred in the previous circuit block in the logic unit configurable area 202 In many cases, it is possible to reduce the occurrence of a situation in which a road becomes long or largely detours. As a result, it is possible to reduce the occurrence of malfunctions due to deterioration of circuit characteristics such as signal delays caused by circuit portions constituting the transmission path portion. As a result, it is possible to extend the lifetime of the FPGA 200 and the apparatus using the FPGA 200 at a low cost.

  In the circuit block correspondence table 215 according to the embodiment described above, a new circuit block corresponding to the circuit block in which the failure has occurred is selected without determining which logic part of the circuit block has failed. I decided to reconstruct it. The present invention is not limited to this, and it is determined which logic part of a circuit block in which a failure has occurred, a new circuit block is selected according to the determination result, and the reconfiguration is performed. It may be. In this case, a detailed failure state such as whether a failure has occurred in all of the plurality of logic parts constituting the circuit block in which the failure has occurred, which logic unit and which logic unit has the failure And the circuit block to be reconfigured according to this can be made more specific.

  Further, in the embodiment described above, the FPGA 200 is configured to include the control unit 213 including the CPU 211 and the like in the always-on operation unit 201, but is not limited thereto. Even for an FPGA in which the CPU 211 is not incorporated, by connecting and controlling an externally arranged CPU, the normal operation unit 201 is reconfigured as in the embodiment, or the circuit block is reconfigured in the same manner. be able to. Not only the CPU 211 but also the memory 212, the optimization processing unit 214, and the circuit block correspondence table 215 may be arranged outside. In other words, the constantly operating unit 201 itself may be arranged outside the FPGA 200.

  Further, in the embodiment, collation data such as the monitoring collation data 271 is stored in the monitoring data storage unit 221 shown in FIG. 5, and the monitoring unit such as the first monitoring unit 241 is the first logic unit 231. The failure is detected by comparing the data such as the monitoring data 261 output from the logic unit such as the monitoring data 261 and the like, and comparing the coincidence and the inconsistency. The failure detection of the present invention is not limited to this. Of course, the monitoring data storage unit 221 may be arranged outside the FPGA 200.

  FIG. 10 is a diagram for explaining another method for detecting the occurrence of a malfunction in the logic unit. It is assumed that the first to third logic units 231 to 233 are configured in the FPGA 200A of this modified example, as in the previous embodiment. Of these, the first logic unit 231 inputs the monitoring data 261A to the first monitoring unit 241A. Similarly, the second and third logic units 232 and 233 also input the monitoring data 262A or 263A to the second monitoring unit 242A or the third monitoring unit 243A. In this modified example, the first to third monitoring units 241A to 243A include first to third logic unit failure factor registers 311A to 313A.

  The first logic unit failure factor register 311A will be specifically described as an example. The first logic unit failure factor register 311A includes the value “0b0000” as the monitoring data 261A input to the first monitoring unit 241A when the first logic unit 231 is normal, and for each factor of the failure. A value is registered. For example, the value of the monitoring data 261A when a failure occurs due to the first factor is “0b0001”, and the value of the monitoring data 261A when a failure occurs due to the second factor is “0b0010”.

  Assuming that the first logic unit failure factor register 311A registers the first to fourth factors and normal values, the first monitoring unit 241A sequentially determines which value the monitoring data 261A matches. Compare. Then, the comparison result is notified to the control unit not shown in FIG. In this way, the control unit of the FPGA 200A can always monitor the factors at the time of occurrence of the malfunction for the first to third logic units 231 to 233, and determines when the circuit block needs to be reconfigured. can do.

  For example, if the first factor is a relatively severe failure factor for the first logic unit 231, the control unit determines the reconfiguration of the circuit block including the first logic unit 231 when this is confirmed. In addition, assuming that the second factor is a relatively light failure factor for the first logic unit 231, the reconfiguration of the circuit block is postponed while the second and third logic units 232 and 233 are normal. For example, when a relatively minor failure factor occurs in the second logic unit 232, if these combinations meet the criteria for circuit block reconfiguration, the first and second logic units The reconfiguration of the circuit block including 231 and 232 is determined.

  In the embodiment and the modifications thereof, the dynamic reconfiguration of the logic unit for the FPGAs 200 and 200A has been described. However, the present invention can naturally be applied to an information communication apparatus and an information processing apparatus using the FPGA. It is.

  Some or all of the embodiments described above are described as in the following supplementary notes, but are not limited to the following descriptions.

(Appendix 1)
A number of circuit parts functioning as logic circuits having desired characteristics are configured by appropriately selecting and combining from a number of circuit parts formed in a specific area on the same substrate, and A desired number of circuit blocks each having a group of circuit functions are initially configured by appropriately selecting from among them and configuring connection portions as components for electrically connecting the logic portions. Circuit block initial configuration means;
A circuit block monitoring means for detecting a circuit block including a logic unit in which a failure has occurred by monitoring these operations when each circuit block configured by the circuit block initial configuration means is in operation;
When a circuit block including a failed logic unit is detected by the circuit block monitoring means, a new logic unit, a connection unit, and a signal having the same circuit characteristics as each of the logic units constituting the circuit block Execution of an optimization process in which a circuit block having a new connection portion with the same timing as possible is configured by an optimization process from unused portions of a large number of circuit components formed in the specific region Means,
Circuit block replacement means for starting a new operation by replacing a new circuit block constituted by the optimization processing execution means with a circuit block including a logic unit in which a failure has occurred in the circuit block monitoring means. FPGA (Field Programmable Gate Array).

(Appendix 2)
For each circuit block that is initially configured by the circuit block initial configuration means, when a failure occurs in the logic unit that configures these circuit blocks and replacement by the circuit block replacement means is required, 2. The FPGA according to appendix 1, wherein a table describing information related to circuit parts necessary for configuring a circuit block is prepared.

(Appendix 3)
The circuit block after the change is such that the connection part that connects the logic parts constituting the circuit block and the corresponding connection part of the circuit block before the change have the same timing as possible. The FPGA according to appendix 2, wherein the FPGA is selected in advance from unused parts among a large number of circuit parts formed in a specific region.

(Appendix 4)
When a plurality of pieces of information relating to circuit parts necessary for configuring a plurality of circuit blocks after replacement with respect to one of the initially configured circuit blocks is described in the table, these are selected in accordance with a priority order. The FPGA according to appendix 2, further comprising priority order selection means.

(Appendix 5)
An FPGA (Field Programmable Gate Array) in which a large number of circuit components are formed in a specific area on the same substrate;
By selecting and combining from among the many circuit components of this FPGA, several logic units each functioning as a logic circuit having a desired characteristic are formed, and selecting from among the many circuit components as appropriate. Circuit block initial configuration means for initially configuring a desired number of circuit blocks each having a group of circuit functions by configuring a connection section as a component for electrically connecting the logic sections; ,
Circuit block monitoring means for receiving a notification when a circuit block including a failed logic unit is detected as a monitoring result of these operations when each circuit block configured by the circuit block initial configuration means is in operation; and ,
When it is notified by the circuit block monitoring means that a circuit block including a failed logic unit has been detected, a new logic unit having the same circuit characteristics as each of the logic units constituting the circuit block And a circuit block provided with a new connection portion where the signal transmission timing is the same as possible, by an optimization process from unused portions of a large number of circuit components formed in the specific region An optimization processing execution means to be configured;
Circuit block replacement means for starting a new operation by replacing a new circuit block constituted by the optimization processing execution means with a circuit block including a logic unit in which a failure has occurred in the circuit block monitoring means. A circuit reconfiguration system using an FPGA.

(Appendix 6)
For each circuit block that is initially configured by the circuit block initial configuration means, when a failure occurs in the logic unit that configures these circuit blocks and replacement by the circuit block replacement means is required, 6. A circuit reconfiguration system using an FPGA as set forth in appendix 5, wherein a table in which information relating to circuit components necessary for configuring a circuit block is prepared.

(Appendix 7)
The specified circuit block after the replacement is specified so that the timing at which signals are transmitted is the same as possible with the connection unit that connects the logic units constituting the block with the corresponding connection unit of the circuit block before the replacement. The circuit reconfiguration system using the FPGA according to appendix 6, wherein the circuit reconfiguration system is previously selected from unused parts among a large number of circuit parts formed in the region.

(Appendix 8)
When a plurality of pieces of information relating to circuit parts necessary for configuring a plurality of circuit blocks after replacement with respect to one of the initially configured circuit blocks is described in the table, these are selected in accordance with a priority order. The circuit reconfiguration system using the FPGA according to appendix 5, further comprising priority order selection means.

(Appendix 9)
Configures several logic units that each function as a logic circuit with desired characteristics by appropriately selecting and combining from a large number of circuit components formed in a specific area on a substrate constituting an FPGA (Field Programmable Gate Array) In addition, a circuit block having a group of circuit functions can be obtained by configuring a connection part as a part for electrically connecting the logic parts by appropriately selecting from among the many circuit parts. Circuit block initial configuration steps for initial configuration of a desired number;
A circuit block monitoring step for detecting a circuit block including a logic unit in which a malfunction has occurred by monitoring these operations when each circuit block configured in this circuit block initial configuration step is in operation;
When a circuit block including a failed logic unit is detected by this circuit block monitoring step, a new logic unit, the connection unit, and a signal having the same circuit characteristics as each of the logic units constituting the circuit block Execution of an optimization process in which a circuit block having a new connection portion with the same timing as possible is configured by an optimization process from unused portions of a large number of circuit components formed in the specific region Steps,
And a circuit block replacement step for starting a new operation by replacing a new circuit block constituted by the optimization processing execution step with a circuit block including a logic unit in which a failure has occurred in the circuit block monitoring step. A circuit reconfiguration method using an FPGA.

(Appendix 10)
Computer
Configures several logic units that each function as a logic circuit with desired characteristics by appropriately selecting and combining from a large number of circuit components formed in a specific area on a substrate constituting an FPGA (Field Programmable Gate Array) In addition, a circuit block having a group of circuit functions can be obtained by configuring a connection part as a part for electrically connecting the logic parts by appropriately selecting from among the many circuit parts. Circuit block initial configuration processing for initial configuration of a desired number;
A circuit block monitoring process for detecting a circuit block including a logic unit in which a malfunction has occurred by monitoring these operations when each circuit block configured in the circuit block initial configuration process is in operation; and
When a circuit block including a failed logic unit is detected by the circuit block monitoring process, a new logic unit, a connection unit, and a signal having the same circuit characteristics as each of the logic units constituting the circuit block are detected. Execution of an optimization process in which a circuit block having a new connection portion with the same timing as possible is configured by an optimization process from unused portions of a large number of circuit components formed in the specific region Processing,
A circuit block replacement process for starting a new operation by replacing a new circuit block configured by the optimization process execution process with a circuit block including a logic unit in which a defect has occurred in the circuit block monitoring process is performed. A circuit reconfiguration program using an FPGA.

10, 21, 200, 200A FPGA
DESCRIPTION OF SYMBOLS 11, 22 Circuit block initial configuration means 12, 23 Circuit block monitoring means 13, 24 Optimization processing execution means 14, 25 Circuit block replacement means 20 Circuit reconfiguration system using FPGA 30 Circuit reconfiguration method using FPGA 31 Circuit Block initial configuration step 32 Circuit block monitoring step 33 Optimization processing execution step 34 Circuit block replacement step 40 Circuit reconfiguration program using FPGA 41 Circuit block initial configuration processing 42 Circuit block monitoring processing 43 Optimization processing execution processing 44 Circuit block replacement Processing 201 Constant operation unit 202 Logic unit configurable area 203 Monitoring unit configuration area 211 CPU
212 Memory 213 Control unit 214 Optimization processing unit 215 Circuit block correspondence table 221 Monitoring data storage unit 231 First logic unit 232 Second logic unit 233 Third logic unit 241, 241 A First monitoring unit 242, 242 A Second monitoring unit 243, 243A Third monitoring unit 251 Internal clock 261, 261A, 262, 262A, 263, 263A Monitoring data 271, 272, 273 Monitoring verification data 291 (after reconfiguration) First logic Part 292 Second logic part 293 (after reconfiguration) Third logic part 301, 302 signal (after reconfiguration)

Claims (10)

Configures several logic units that function as logic circuits with desired characteristics by appropriately selecting and combining from a number of circuit components formed in a specific area on the substrate that constitutes the FPGA (Field Programmable Gate Array) In addition, a circuit block having a group of circuit functions can be obtained by configuring a connection part as a part for electrically connecting the logic parts by appropriately selecting from among the many circuit parts. Circuit block initial configuration means for initially configuring a desired number;
And a circuit block monitoring means for detecting a circuit block including a logical unit that the circuit blocks each of the circuit blocks constituting the initial configuration means has occurred malfunction by monitoring these operations when in operation,
A constantly operating region monitoring means for monitoring the operation of the constantly operating region on the substrate constituting the FPGA to detect a failure in the constantly operating region and detecting a component of the constantly operating region that is a cause of the failure; ,
When a circuit block including a failed logic unit is detected by the circuit block monitoring unit, a new logic unit, the connection unit, and a signal having the same circuit characteristics as each of the logic units constituting the circuit block the circuit block and a new connecting portion in which the timing for transmitting is identical as possible, the unused portion of a number of circuit components formed in the specific region is calculated by processing optimization, When a malfunction in the constantly operating area is detected by the constantly operating area monitoring means and a component of the constantly operating area that is a cause of the malfunction is detected, a new configuration of the FPGA that eliminates the malfunction is The component of the constantly operating area that is the cause of the malfunction, all the logic units that have malfunctioned in the past, and And optimization process executing means for calculating by treating optimize the entire area on the substrate constituting the components of all of the constantly operating region became cause of case, the FPGA excluding,
A circuit block calculated by the optimization processing execution means optimizing an unused portion of a large number of circuit components formed in the specific area is converted into a logic part in which a failure occurs in the circuit block monitoring means. FPGA control means for starting a new operation of the FPGA with a new configuration of the FPGA calculated by the optimization processing execution means performing an optimization process by switching to a circuit block including the circuit block < An FPGA A characterized by comprising :   For each circuit block that is initially configured by the circuit block initial configuration means, when a failure occurs in the logic unit that configures these circuit blocks and replacement by the circuit block replacement means is required, 2. The FPGA according to claim 1, wherein a table in which information relating to circuit parts necessary for constituting a circuit block is described is prepared.   The circuit block after the change is such that the connection part that connects the logic parts constituting the circuit block and the corresponding connection part of the circuit block before the change have the same timing as possible. 3. The FPGA according to claim 2, wherein the FPGA is previously selected from unused parts among a large number of circuit parts formed in a specific region.   When a plurality of pieces of information relating to circuit parts necessary for configuring a plurality of circuit blocks after replacement with respect to one of the initially configured circuit blocks is described in the table, these are selected in accordance with a priority order. 3. The FPGA according to claim 2, further comprising priority order selection means. FPGA (Field Programmable Gate Array) in which a number of circuit components are formed in a specific area on the same substrate;
By selecting and combining from among the many circuit components of the FPGA as appropriate, several logic units each functioning as a logic circuit having desired characteristics are formed, and from among the many circuit components, they are selected as appropriate. Circuit block initial configuration means for initially configuring a desired number of circuit blocks each having a group of circuit functions by configuring a connection section as a component for electrically connecting the logic sections; ,
And a circuit block monitoring means for receiving the notification when the circuit block including a logical unit caused problems as the monitoring result of these operations when in said circuit blocks each of the circuit blocks constituting the initial configuration means operate is detected ,
A normal operation region monitoring means for monitoring the operation of the constant operation region on the same substrate and detecting a defect of the normal operation region, and detecting a component of the normal operation region which is a cause of the failure;
When it is notified by the circuit block monitoring means that a circuit block including a failed logic unit has been detected, a new logic unit having the same circuit characteristics as each of the logic units constituting the circuit block the connecting portion and the circuit block and a new connecting portion in which the timing for transmitting become identical as possible to the signal, the optimization process of the unused portion of a number of circuit components formed in the specific region and When the malfunction of the constantly operating area is detected by the constantly operating area monitoring means and the component of the constantly operating area that is the cause of the malfunction is detected, the malfunction is resolved. The new configuration of the FPGA includes a component of the constantly operating area that is the cause of the failure, all the logic units that have failed in the past, Optimization processing execution means for calculating by optimizing the entire area on the board constituting the FPGA excluding all the components of the constantly operating area that have caused a failure in the past in the production area When,
A circuit block calculated by the optimization processing execution means optimizing an unused portion of a large number of circuit components formed in the specific area is converted into a logic part in which a failure occurs in the circuit block monitoring means. FPGA control means for starting a new operation of the FPGA with a new configuration of the FPGA calculated by the optimization processing execution means performing an optimization process by switching to a circuit block including the circuit block < a circuit reconfiguration system using an FPGA.   For each circuit block that is initially configured by the circuit block initial configuration means, when a failure occurs in the logic unit that configures these circuit blocks and replacement by the circuit block replacement means is required, 6. A circuit reconfiguration system using an FPGA according to claim 5, wherein a table in which information relating to circuit components necessary for configuring a circuit block is prepared.   The specified circuit block after the replacement is specified so that the timing at which signals are transmitted is the same as possible with the connection unit that connects the logic units constituting the block with the corresponding connection unit of the circuit block before the replacement. 7. The circuit reconfiguration system using an FPGA according to claim 6, wherein the circuit reconfiguration system is preselected from unused parts among a large number of circuit parts formed in the region.   When a plurality of pieces of information relating to circuit parts necessary for configuring a plurality of circuit blocks after replacement with respect to one of the initially configured circuit blocks is described in the table, these are selected in accordance with a priority order. 6. The circuit reconfiguration system using FPGA according to claim 5, further comprising priority order selection means. Configures several logic units that function as logic circuits with desired characteristics by appropriately selecting and combining from a number of circuit components formed in a specific area on the substrate that constitutes the FPGA (Field Programmable Gate Array) In addition, a circuit block having a group of circuit functions can be obtained by configuring a connection part as a part for electrically connecting the logic parts by appropriately selecting from among the many circuit parts. Circuit block initial configuration steps for initial configuration of a desired number;
A circuit block monitoring step of detecting a circuit block including a logical unit that the circuit block initial configuration respective circuit blocks configured in step occurred problems by monitoring these operations when in operation,
A normal operation region monitoring step of monitoring the operation of the normal operation region on the substrate constituting the FPGA to detect a defect in the normal operation region and detecting a component of the normal operation region that is a cause of the failure; ,
When a circuit block including a failed logic unit is detected by the circuit block monitoring step, a new logic unit, a connection unit, and a signal having the same circuit characteristics as each of the logic units constituting the circuit block the circuit block and a new connecting portion in which the timing for transmitting is identical as possible, the unused portion of a number of circuit parts formed in the specific region is calculated by processing optimization, When a malfunction in the constantly operating area is detected by the constantly operating area monitoring step and a component of the constantly operating area, which is a cause of the malfunction, is detected, a new configuration of the FPGA that eliminates the malfunction, The component of the constantly operating area that is the cause of the malfunction, all the logic units that have malfunctioned in the past, and the constantly operating area And optimization process execution step of calculating by optimization an overall region of the substrate constituting the components of all of the constantly operating region became defect generation factor to, the FPGA excluding,
In the optimization process execution step, the circuit block calculated by optimizing the unused part of the many circuit components formed in the specific area is converted into a logic part in which the circuit block monitoring means has failed. An FPGA control step for starting a new operation of the FPGA with a new configuration of the FPGA calculated by performing an optimization process in the optimization process execution step by switching to a circuit block including the circuit block < a circuit reconfiguration method using an FPGA. Computer
Configures several logic units that function as logic circuits with desired characteristics by appropriately selecting and combining from a number of circuit components formed in a specific area on the substrate that constitutes the FPGA (Field Programmable Gate Array) In addition, a circuit block having a group of circuit functions can be obtained by configuring a connection part as a part for electrically connecting the logic parts by appropriately selecting from among the many circuit parts. Circuit block initial configuration processing for initial configuration of a desired number;
A circuit block monitoring processing of detecting a circuit block including a logical unit that the circuit block initial configuration respective circuit blocks configured in step occurred problems by monitoring these operations when in operation,
A constantly operating region monitoring process for monitoring the operation of the constantly operating region on the substrate constituting the FPGA to detect a failure in the constantly operating region, and detecting a component of the constantly operating region that is a cause of the failure; ,
When a circuit block including a failed logic unit is detected by the circuit block monitoring process, a new logic unit, the connection unit, and a signal having the same circuit characteristics as each of the logic units constituting the circuit block the circuit block and a new connecting portion in which the timing for transmitting is identical as possible, the unused portion of a number of circuit components formed in the specific region is calculated by processing optimization, When a malfunction in the constantly operating area is detected by the constantly operating area monitoring process, and a component of the constantly operating area that is a cause of the malfunction is detected, a new configuration of the FPGA that eliminates the malfunction, The component of the constantly operating area that is the cause of the malfunction, all the logic units that have malfunctioned in the past, and The components of all of the constantly operating region became cause of engagement, and optimization process executing processing for calculating by optimization an overall region of the substrate constituting the FPGA excluding,
A circuit block calculated by the optimization process execution process optimizing unused portions of a large number of circuit components formed in the specific area is converted into a logic part in which a failure occurs in the circuit block monitoring means. An FPGA control process for starting a new operation of the FPGA with a new configuration of the FPGA calculated by performing an optimization process in the optimization process execution step by replacing a circuit block including the circuit block < A circuit reconfiguration program using an FPGA, wherein

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