JP7287651B2 - DISTRIBUTED PROCESSING APPARATUS, DISTRIBUTED PROCESSING METHOD, AND PROGRAM - Google Patents

Description

The present invention relates to a distributed processing device, a distributed processing method, and a program that perform distributed processing using a reconfigurable circuit.

2. Description of the Related Art In recent years, a distributed processing system has been proposed that realizes high-speed data processing by executing data processing devices in parallel. Apache Hadoop (registered trademark), for example, is known as such a distributed processing system.

As a related technique, Patent Literature 1 discloses a distributed database system that distributes data processing to a plurality of computing devices to reduce data processing time. Further, it is disclosed that an FPGA (Field Programmable Gate Array) or the like is used as a computing device. Specifically, according to this distributed database system, data processing is distributed among computing devices according to the difference in computational capacity of the computing devices.

WO2018/158819

However, distributed processing systems must ensure robustness. Therefore, in the conventional distributed processing system, robustness is ensured by, for example, providing the distributed processing system with a standby device having functions equivalent to those of the distributed processing system. However, since the distributed processing system is provided with a spare machine, the distributed processing system becomes expensive.

Patent Literature 1 does not disclose how to ensure the robustness of the distributed database system. In addition, in order to ensure robustness in the distributed database system disclosed in Patent Document 1, it is necessary to take measures such as providing a backup device as described above. It should be noted that, as a general rule, it is necessary to stop the entire system when the standby machine is put into operation.

An example of an object of the present invention is to provide a distributed processing device, a distributed processing method, and a program that ensure robustness at low cost without stopping the system.

In order to achieve the above object, a distributed processing device according to one aspect of the present invention includes:
a data processing unit having a reconfigurable circuit;
a reconfiguration control unit that controls dynamic circuit reconfiguration for each of the plurality of data processing units using circuit information corresponding to each of the distributed data processing;
characterized by having

Further, in order to achieve the above object, a distributed processing method according to one aspect of the present invention includes:
(a) transmitting circuit information corresponding to each distributed data processing to a data processing unit having a reconfigurable circuit; and (b) using the received circuit information for each of the data processing units. dynamically reconfiguring the circuit with
characterized by having

Furthermore, in order to achieve the above object, the program in one aspect of the present invention is
to the computer,
(a) transmitting circuit information corresponding to each distributed data processing to a data processing unit having a reconfigurable circuit; and (b) using the received circuit information for each of the data processing units. dynamically reconfiguring the circuit with
is characterized by executing

As described above, according to the present invention, robustness can be ensured at low cost without stopping the system.

FIG. 1 is a diagram showing an example of a distributed processing device. FIG. 2 is a diagram showing an example of a specific distributed processing device. FIG. 3 is a diagram for explaining Modification 2. FIG. FIG. 4 is a diagram for explaining Modification 4. FIG. FIG. 5 is a diagram illustrating an example of the operation of the distributed processing device; FIG. 6 is a diagram illustrating an example of the operation of the distributed processing device in Modification 1; FIG. 7 is a diagram illustrating an example of the operation of the distributed processing device in modification 2; FIG. 8 is a diagram illustrating an example of the operation of the distributed processing device according to Modification 3; FIG. 9 is a diagram illustrating an example of the operation of the distributed processing device in modification 4; FIG. 10 is a block diagram showing an example of a computer that implements the reconfiguration control unit.

(Embodiment)
BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to FIGS.

[Device configuration]
First, using FIG. 1, the configuration of the distributed processing device 1 according to the present embodiment will be described. FIG. 1 is a diagram showing an example of a distributed processing device.

The distributed processing device 1 shown in FIG. 1 is a device (or system) that can secure robustness at a low cost. ) and a reconstruction control unit 3 .

Among them, the data processing unit 2 has a reconfigurable circuit 4 (4a, 4b, 4c). The reconfiguration control unit 3 uses the circuit information 5 (5a, 5b, 5c) corresponding to each of the distributed data processing (processing a, b, c) to provide each of the plurality of data processing units 2a, 2b, 2c with Control to dynamically reconfigure the circuit.

The data processing unit 2 executes processing corresponding to the data processing unit 2 . In the example of FIG. 1, the data processing unit 2a executes the process a, the data processing unit 2b executes the process b, and the data processing unit 2c executes the process c. The processes a, b, and c are processes in which the data processing is distributed so that, for example, data processing conventionally performed by one reconfigurable circuit can be performed by a plurality of reconfigurable circuits 4a, 4b, and 4c. .

Further, the data processing unit 2 is provided with a programmable device (circuit reconfiguring device) such as an FPGA having a reconfigurable circuit 4, for example. The circuit reconfiguration device is a dynamically reconfigurable circuit capable of partial reconfiguration that dynamically rewrites the circuit.

In the example of FIG. 1, the reconfigurable circuit 4a is reconfigured with a circuit for executing the process a, the reconfigurable circuit 4b is reconfigured with a circuit for executing the process b, and the reconfigurable circuit 4c is reconfigured with a circuit for executing the process b. A circuit for performing process c is reconfigured.

The reconfiguration control unit 3 reconfigures circuit information 5a used to reconfigure the circuit corresponding to the process a, circuit information 5b used to reconfigure the circuit corresponding to the process b, and reconfigures the circuit corresponding to the process c. The circuit information 5c used for this purpose is transmitted to each of the corresponding data processing units 2a, 2b, and 2c.

The circuit information 5a, 5b, and 5c are stored in the storage unit provided in the reconfiguration control unit 3 in the example of FIG. may be stored in the device.

Specifically, the reconfiguration control unit 3 transmits the circuit information 5 to the data processing unit 2 associated with the circuit information 5 in advance. After receiving the circuit information 5 from the reconfiguration control unit 3 , the data processing unit 2 reconfigures the circuit corresponding to the received circuit information 5 in the reconfigurable circuit 4 .

As described above, in this embodiment, the circuits can be dynamically reconfigured for each of the plurality of data processing units 2 by using the circuit information 5 corresponding to each of the distributed data processing. In this case, robustness can be ensured at a lower cost than before.

The reason for this is that, conventionally, when a failure occurs, an expensive backup device having the same function as the distributed processing device is used. However, in this embodiment, if a failure occurs, only the failed data processing unit 2 needs to be replaced, so robustness can be ensured at a low cost. In other words, since a programmable device such as an inexpensive FPGA with a small capacity can be used for the data processing unit 2, inexpensiveness and robustness can be ensured. Also, the distributed processing device 1 can be constructed at a low cost.

Also, when a spare machine is used, it is usually necessary to stop the entire system. can only be replaced.

[System configuration]
Next, with reference to FIG. 2, the configuration of the distributed processing device 1 according to this embodiment will be described more specifically. FIG. 2 is a diagram showing an example of a specific distributed processing device.

As shown in FIG. 2, the distributed processing device 1 in this embodiment has a data processing unit 2 (2a, 2b, 2c), a reconfiguration control unit 3, and a backup data processing unit 2d. Also, the data processing unit 2 and the reconfiguration control unit 3 are connected via a network 21 .

Each of the data processing units 2a, 2b, 2c and the spare data processing unit 2d has a communication unit 22 (22a, 22b, 22c, 22d) as shown in FIG. The reconfiguration control unit 3 has a communication unit 23 . The reconfiguration control unit 3 further transmits the circuit information 5d to the preliminary data processing unit 2d.

The data processing unit 2 executes processes a, b, and c using reconfigurable circuits 4a, 4b, and 4c. Specifically, the data processing unit 2a first receives the circuit information 5a transmitted from the reconfiguration control unit 3 via the communication unit 23 using the communication unit 22a. Subsequently, the data processing unit 2a acquires the circuit information 5a from the communication unit 22a, and reconfigures the reconfigurable circuit 4a into a circuit for executing the process a based on the circuit information 5a.

For the data processing units 2b and 2c as well, the data processing unit 2 uses the circuit information 5b and 5c transmitted from the reconfiguration control unit 3 via the communication unit 23 to process the reconfigurable circuits 4b and 4c. Reconfigure the circuit that implements c.

Although the number of data processing units 2 is three in the example of FIG. 2, the number of data processing units 2 is not limited to three.

The preliminary data processing unit 2d executes the process d using the reconfigurable circuit 4d. The reconfigurable circuit 4d is, for example, a circuit having a programmable device (circuit reconfiguration device) such as FPGA. Specifically, the preliminary data processing unit 2d first receives the circuit information 5d transmitted from the reconfiguration control unit 3 via the communication unit 23 using the communication unit 22d.

Subsequently, the preliminary data processing unit 2d acquires the circuit information 5d from the communication unit 22d, and reconfigures the circuit that executes the process d based on the circuit information 5d. Process d is, for example, the same process as any one of processes a, b, and c.

In the example of FIG. 2, the number of spare data processing units 2d is one, but the number of spare data processing units 2d may be plural.

The reconfiguration control unit 3 uses the circuit information 5 corresponding to the process to dynamically reconfigure the reconfigurable circuit 4 of the data processing unit 2 . Specifically, when the reconfiguration control unit 3 reconfigures the circuit corresponding to the process a in the data processing unit 2a, the reconfiguration control unit 3 transmits the circuit information 5a to the communication unit 22a of the data processing unit 2a via the communication unit 23. do.

Also for the data processing units 2b, 2c, and 2d, the reconfiguration control unit 3 transmits the circuit information 5b, 5c, and 5d from the reconfiguration control unit 3 through the communication unit 23 to the data processing units 2b, 2c, preliminary data processing, and so on. It transmits to the communication units 22b, 22c, and 22d of the unit 2d.

[Modification 1]
In the distributed processing apparatus of Modification 1, if any of the data processing units 2 fails, the spare data processing unit 2d is used instead of the failed data processing unit 2. FIG.

When the reconfiguration control unit 3 acquires failure detection information indicating that a failure has been detected from the data processing unit 2 that has detected the failure, the reconfiguration control unit 3 selects the failed data processing unit 2 and performs the selected (failed) data processing. A circuit equivalent to the circuit reconfigured in the unit 2 is reconfigured in the spare data processing unit 2d.

Specifically, when the failure detection information is acquired, the reconfiguration control unit 3 detects the failure in order to reconfigure the circuit reconfigured in the failed data processing unit 2 to the spare data processing unit 2d. The circuit information 5 corresponding to the circuit reconfigured in the data processing unit 2 is transmitted through the communication unit 23 to the communication unit 22d of the spare data processing unit 2d.

Subsequently, the spare data processing unit 2d reconfigures based on the circuit information 5 corresponding to the circuit reconfigured in the reconfigurable circuit 4 of the data processing unit 2 in which the failure is detected, which is received by the communication unit 22d. Reconstruct the circuit into a possible circuit 4d.

In the configuration of FIG. 2, for example, when the reconfiguration control unit 3 detects a failure in the data processing unit 2a, the circuit reconfigured in the data processing unit 2a is changed to the reconfigurable circuit 4d of the backup data processing unit 2d. 2, the circuit information 5a corresponding to the data processing unit 2a is transmitted through the communication unit 23 to the communication unit 22d of the preliminary data processing unit 2d.

Subsequently, the preliminary data processing unit 2d reconfigures the reconfigurable circuit 4d as a circuit for executing the process a based on the circuit information 5a received by the communication unit 22d. Then, after the circuit that executes the process a is reconfigured into the reconfigurable circuit 4d, the operation of the data processing unit 2a is stopped and the backup data processing unit 2d is activated. That is, the preliminary data processing unit 2d substitutes for the data processing unit 2a.

After the backup data processing unit 2d replaces the data processing unit 2a, the user replaces the failed data processing unit 2a with a new data processing unit 2a. Then, the distributed processing device 1 is returned to the initial operating state.

As described above, in the modified example 1, the distributed processing device 1 is further provided with the spare data processing unit 2d having the reconfigurable circuit 4, so that even if one of the data processing units 2a, 2b, and 2c fails, , a circuit equivalent to the faulty data processing unit 2 can be reconfigured into the spare data processing unit 2d. Therefore, the failed data processing unit 2 can be easily switched to the spare data processing unit 2d.

Furthermore, since the faulty data processing unit 2 can be switched to the backup data processing unit 2d in a short period of time after the detection of the fault until the circuit is reconfigured, the distributed processing device 1 minimizes deterioration in data processing performance. can be suppressed to

The failure detection of the data processing unit 2 described above is performed using a failure detection circuit. Specifically, the reconfiguration control unit 3 reconfigures a fault detection circuit for detecting a fault in the reconfigurable circuit 4 in one of the data processing units 2 . Note that the failure detection circuit may be any circuit that can detect failures of programmable devices such as FPGAs.

[Modification 2]
In the distributed processing apparatus of Modification 2, a case of performing failure detection (diagnosis) of the data processing unit 2 and the spare data processing unit 2d will be described.

In Modified Example 2, the circuit information 5d shown in FIG. The reconfiguration control unit 3 selects the data processing unit 2 and the backup data processing unit 2d in the order set in advance at the date and time set in advance, and can reconfigure the selected data processing unit 2 and the backup data processing unit 2d. A fault detection circuit is reconfigured in circuit 4 .

Specifically, in Modification 2, the circuit information 5d shown in FIG.

FIG. 3 is a diagram for explaining Modification 2. FIG. When the date and time for executing diagnosis 1 come, the reconfiguration control unit 3 causes the data processing unit 2 and the preliminary data processing unit 2d to execute the diagnosis.

In diagnosis 1, the reconfiguration control unit 3 first transmits the circuit information 5a to the preliminary data processing unit 2d. After that, the preliminary data processing unit 2d reconfigures the circuit of the process a in the reconfigurable circuit 4d based on the received circuit information 5a.

Subsequently, the data processing section 2a is switched to the spare data processing section 2d, and data processing is continued. Subsequently, the reconfiguration control unit 3 transmits the circuit information 5d to the data processing unit 2a. After that, the data processing unit 2a reconfigures the failure detection circuit in the reconfigurable circuit 4a based on the received circuit information 5d.

Subsequently, the data processing unit 2a diagnoses the reconfigurable circuit 4a, and transmits failure detection information to the reconfiguration control unit 3 when a failure is detected. If no failure is detected, the diagnosis 1 is terminated, the data processing unit 2a is returned to its original state, that is, the state in which the process a can be executed, and the next diagnosis 2 is performed.

Subsequently, in diagnosis 2, the data processing unit 2b is diagnosed, in diagnosis 3, the data processing unit 2c is diagnosed, and in diagnosis 4, the preliminary data processing unit 2d is diagnosed. The order of diagnosing the data processing unit 2 and the spare data processing unit 2d is not limited.

As described above, in the second modification, it is possible to execute failure detection while continuing data processing using the spare data processing unit 2d.

[Modification 3]
In the distributed processing device of Modification 3, a case where new processing is added to the distributed processing device will be described.

In Modified Example 3, the circuit information 5d shown in FIG. 2 is used as information (process d) used for reconfiguring a circuit for executing a new process in the reconfigurable circuit 4 . The reconfiguration control unit 3 selects the spare data processing unit 2d and reconfigures the reconfigurable circuit 4 of the selected spare data processing unit 2d to perform a new process.

In Modified Example 3, the reconfiguration control unit 3 first transmits the circuit information 5d to the preliminary data processing unit 2d. After that, the preliminary data processing unit 2d reconfigures the reconfigurable circuit 4d with a circuit that executes a new process based on the received circuit information 5d.

Specifically, in order to reconfigure the circuit corresponding to the new processing in the spare data processing unit 2d, the reconfiguration control unit 3 transmits the circuit information 5d corresponding to the circuit corresponding to the new processing to the communication unit 23 to the communication unit 22d of the preliminary data processing unit 2d.

Subsequently, the preliminary data processing unit 2d reconfigures the circuit corresponding to the new process in the reconfigurable circuit 4d based on the circuit information 5d corresponding to the circuit corresponding to the new process received by the communication unit 22d. .

As described above, in the modification 3, by providing the preliminary data processing unit 2d having the reconfigurable circuit 4 in the distributed processing device 1, new processing can be easily added to the preliminary data processing unit 2d.

[Modification 4]
In Modification 4, the reconfigurable circuit 4 described in the above embodiments and Modifications 1, 2, and 3 is capable of partial reconfiguration in which part of the reconfigurable region is dynamically rewritten. use a dynamic reconfigurable circuit.

A specific description will be given with reference to FIG. FIG. 4 is a diagram for explaining Modification 4. FIG. For example, the process a can be further divided into processes a1, a2, and a3, the process a is a process in which the processes a1, a2, and a3 are executed in order, and the dynamically reconfigurable circuit has areas 41a and 41b. Explain the case.

In state 1, the data processing unit 2a acquires circuit information corresponding to the processes a1 and a2, and reconfigures the circuit corresponding to the process a1 in the region 41a of the reconfigurable circuit 4 based on the acquired circuit information. Then, the circuit corresponding to the process a2 is reconfigured in the area 41b.

Subsequently, the data processing unit 2a acquires circuit information corresponding to the process a3 in the state 2, and when the process of the process a1 is completed, the circuit corresponding to the process a3 is displayed in the area 41a based on the acquired circuit information. to reconfigure.

Subsequently, the data processing unit 2a acquires the circuit information corresponding to the process a1, reconfigures the circuit for the process a1 in the area 41a, and reconfigures the circuit for the process a2 in the area 41b, as in state 1 described above. do. By repeatedly executing the processes a1, a2, and a3 in this way, the process a is executed.

Also, the above-described processes b, c, and d can be performed in the same manner as the above-described processes as long as they can be divided.

As described above, in Modification 4, by using a dynamically reconfigurable circuit for the reconfigurable circuit 4, the circuit scale of the reconfigurable circuit 4 can be further reduced. This is because the distributed processing can be further divided and the circuits corresponding to the divided circuits can be dynamically reconfigured as needed.

Although the number of regions is two in the example of FIG. 4, the number is not limited to two and may be two or more.

[Device operation]
Next, the operation of the distributed processing device 1 according to the embodiment and modifications 1 to 4 of the present invention will be described with reference to FIGS. 5, 6, 7, 8 and 9. FIG. FIG. 5 is a diagram illustrating an example of the operation of the distributed processing device; FIG. 6 is a diagram illustrating an example of the operation of the distributed processing device in Modification 1; FIG. 7 is a diagram illustrating an example of the operation of the distributed processing device in modification 2; FIG. 8 is a diagram illustrating an example of the operation of the distributed processing device according to Modification 3; FIG. 9 is a diagram illustrating an example of the operation of the distributed processing device in modification 4;

1 to 4 will be appropriately referred to in the following description. Further, in this embodiment, the distributed processing method is implemented by operating the distributed processing apparatus. Therefore, the description of the distributed processing method in this embodiment is replaced with the description of the operation of the distributed processing apparatus below.

As shown in FIG. 5, first, the reconfiguration control unit 3 transmits circuit information 5 corresponding to each distributed data processing to the data processing unit 2 having the reconfigurable circuit 4 (step A1). Specifically, in step A1, the reconfiguration control unit 3 transmits the circuit information 5 to the data processing unit 2 associated with the circuit information 5 in advance, as shown in FIG.

For example, the reconfiguration control unit 3 stores circuit information 5a used for reconfiguring a circuit corresponding to process a, circuit information 5b used for reconfiguring a circuit corresponding to process b, and a circuit corresponding to process c. The circuit information 5c used for reconstruction is transmitted to the data processing units 2a, 2b and 2c corresponding to the circuit information 5a, 5b and 5c.

Next, the reconfiguration control unit 3 uses the transmitted circuit information 5 to dynamically reconfigure the circuit for each data processing unit 2 (step A2). Specifically, in step A2,
After the data processing unit 2 receives the circuit information 5 from the reconfiguration control unit 3, the reconfiguration control unit 3 reconfigures the circuit corresponding to the received circuit information 5 in the reconfigurable circuit 4 of the data processing unit 2. control to let

As shown in FIG. 1, the reconfigurable circuit 4a is reconfigured with a circuit for executing the process a, the reconfigurable circuit 4b is reconfigured with a circuit for executing the process b, and the reconfigurable circuit 4c is reconfigured. A circuit for executing the process c is reconfigured.

In this way, by using the circuit information 5 corresponding to each distributed data processing, the circuit can be dynamically reconfigured for each of the plurality of data processing units 2. Therefore, even if a failure occurs, the cost is lower than before. can ensure robustness.

The reason for this is that, conventionally, when a failure occurs, an expensive backup device having the same function as the distributed processing device is used. However, in the present embodiment, if a failure occurs, only the failed data processing unit 2 needs to be replaced, so it is possible to secure robustness at a low cost. In other words, since a programmable device such as an inexpensive FPGA with a small capacity can be used for the data processing unit 2, inexpensiveness and robustness can be ensured. Also, the distributed processing device 1 can be constructed at a low cost.

[Modification 1]
The operation of the distributed processing device 1 in Modification 1 will be described. In Modification 1, if any of the data processing units 2 fails, the backup data processing unit 2d is used instead of the failed data processing unit 2. FIG.

As shown in FIG. 6, first, the reconfiguration control unit 3 acquires failure detection information (step B1). Specifically, in step B1, the reconfiguration control unit 3 acquires failure detection information indicating that a failure has been detected from the data processing unit 2 that has detected the failure. Subsequently, the reconfiguration control unit 3 selects the failed data processing unit 2 (step B2).

Subsequently, the reconfiguration control unit 3 transmits the circuit information 5 corresponding to the circuit reconfigured in the failed data processing unit 2 to the backup data processing unit 2d (step B3). Specifically, in step B3, the reconfiguration control unit 3 sends the circuit information 5 corresponding to the reconfigured circuit to the data processing unit 2 that detected the failure via the communication unit 23 to the backup data processing unit 2d. to the communication unit 22d.

Subsequently, when the spare data processing unit 2d receives the circuit information 5 corresponding to the circuit reconfigured in the reconfigurable circuit 4 of the data processing unit 2 in which the failure has been detected, the spare data processing unit 2d reconfigures based on the received circuit information 5. The circuit is reconfigured in the configurable circuit 4d (step B4).

As described above, in the modified example 1, the distributed processing device 1 is further provided with the spare data processing unit 2d having the reconfigurable circuit 4, so that even if one of the data processing units 2a, 2b, and 2c fails, , a circuit equivalent to the faulty data processing unit 2 can be reconfigured into the spare data processing unit 2d.

Therefore, the failed data processing unit 2 can be easily switched to the spare data processing unit 2d. Furthermore, since the faulty data processing unit 2 can be switched to the backup data processing unit 2d in a short period of time after the detection of the fault until the circuit is reconfigured, the distributed processing device 1 minimizes deterioration in data processing performance. can be suppressed to

It should be noted that failure detection of the data processing unit 2 is performed using a failure detection circuit. Specifically, the reconfiguration control unit 3 reconfigures a fault detection circuit for detecting a fault in the reconfigurable circuit 4 in one of the data processing units 2 . Note that the failure detection circuit may be any circuit that can detect failures of programmable devices such as FPGAs.

[Modification 2]
The operation of the distributed processing device 1 in Modification 2 will be described. In Modified Example 2, a case of performing failure detection (diagnosis) of the data processing section 2 and the spare data processing section 2d will be described.

As shown in FIG. 7, the reconfiguration control unit 3 first acquires the date and time of diagnosis (step C1). Specifically, in step C1, the reconfiguration control unit 3 starts diagnosis (failure detection) at a preset date and time (diagnosis date and time).

Subsequently, the reconfiguration control unit 3 selects the data processing unit 2 or the spare data processing unit 2d (step C2). Subsequently, the reconfiguration control unit 3 transmits the circuit information 5 corresponding to the circuit reconfigured in the selected data processing unit 2 to the preliminary data processing unit 2d (step C3). Subsequently, the spare data processing unit 2d reconfigures the circuit reconfigured in the selected data processing unit 2 as the reconfigurable circuit 4d of the spare data processing unit 2d (step C4).

Subsequently, the reconfiguration control unit 3 transmits circuit information corresponding to the failure detection circuit to the selected data processing unit 2 (step C5). Subsequently, the reconfiguration control unit 3 reconfigures the failure detection circuit in the selected data processing unit 2 (step C6).

Subsequently, the selected data processing unit 2 performs diagnosis (fault detection) using the reconfigured fault detection circuit (step C7). If there is a failure in the selected data processing unit 2 (step C7: Yes), the process proceeds to step C8 to notify the user of the failure. If the selected data processing unit 2 has no failure (step C7: No), the process proceeds to step C9.

Subsequently, the reconfiguration control unit 3 restores the state to the initial state (step C9). Specifically, in step C9, the reconfiguration control unit 3 restores the states of the reconfigurable circuits 4 of the data processing unit 2 and the spare data processing unit 2d to the states at the start of the diagnosis.

Subsequently, when all diagnosis (failure detection) is completed (step C10: Yes), the reconfiguration control unit 3 ends data processing. If there is still an undiagnosed data processing unit 2 or backup data processing unit 2d (step C10: No), the process proceeds to step C2. Then, in step C2, the undiagnosed data processing unit 2 or spare data processing unit 2d is selected.

By repeating the processing of steps C1 to C9 described above, the diagnosis of the data processing unit 2 and the preliminary data processing unit 2d is performed.

As described above, in the second modification, it is possible to execute failure detection while continuing data processing using the spare data processing unit 2d.

[Modification 3]
The operation of the distributed processing device 1 in Modification 3 will be described. In Modified Example 3, a case where new processing is added to the distributed processing device 1 will be described.

As shown in FIG. 8, first, the reconfiguration control unit 3 transmits circuit information 5 corresponding to new processing to the data processing unit 2 having the reconfigurable circuit 4 (step D1). Specifically, in step D1, as shown in FIG. 2, the reconfiguration control unit 3 causes the preliminary data processing unit 2d to
Circuit information 5d corresponding to new processing is transmitted.

Next, the preliminary data processing unit 2d uses the received circuit information 5d to reconfigure the circuit corresponding to the new process (step D2). Specifically, in step D2, after receiving the circuit information 5 from the reconfiguration control unit 3, the preliminary data processing unit 2d sends the reconfigurable circuit 4d of the preliminary data processing unit 2d a circuit corresponding to the received circuit information 5d. Reconfigure the circuit that

As described above, in the modification 3, by providing the preliminary data processing unit 2d having the reconfigurable circuit 4 in the distributed processing device 1, new processing can be easily added to the preliminary data processing unit 2d.

[Modification 4]
The operation of the distributed processing device 1 in Modification 4 will be described. In Modification 4, a dynamically reconfigurable circuit is used as the reconfigurable circuit 4 described in the embodiment and Modifications 1, 2, and 3 above. Specifically, as the reconfigurable circuit 4, a dynamically reconfigurable circuit capable of partial reconfiguration that dynamically rewrites part of the reconfigurable area is used.

As shown in FIG. 9, first, the reconfiguration control unit 3 selects a process obtained by further dividing the distributed process (step E1). Subsequently, the reconstruction control unit 3 selects regions corresponding to the divided processes (step E2). Subsequently, the reconfiguration control unit 3 transmits the circuit information 5 corresponding to the divided processing to the data processing unit 2 having the reconfigurable circuit 4 (dynamically reconfigurable circuit) (step E3). Subsequently, the data processing section 2 or the preliminary data processing section 2d uses the received circuit information 5 to reconfigure the circuit corresponding to the divided processing in the selected area (step E4).

The distributed processing is executed by repeating the processing of steps E1 to E4 described above.

Thus, in Modification 4, by using a dynamically reconfigurable circuit that can dynamically rewrite part of the reconfigurable area in the reconfigurable circuit 4, the reconfigurable circuit 4 circuit scale can be reduced. This is because the distributed processing can be further divided and the circuits corresponding to the divided circuits can be dynamically reconfigured as needed.

[Effects of this embodiment]
As described above, according to the present embodiment, the circuits can be dynamically reconfigured for each of the plurality of data processing units 2 by using the circuit information 5 corresponding to each of the distributed data processing. If it does occur, it is cheaper than before and robustness can be ensured.

The reason for this is that, conventionally, when a failure occurs, an expensive backup device having the same function as the distributed processing device is used. However, in this embodiment, if a failure occurs, only the failed data processing unit 2 needs to be replaced, so robustness can be ensured at a low cost. In other words, since a programmable device such as an inexpensive FPGA with a small capacity can be used for the data processing unit 2, inexpensiveness and robustness can be ensured. Also, the distributed processing device 1 can be constructed at a low cost.

Also, when a spare machine is used, it is usually necessary to stop the entire system. can only be replaced.

Further, according to Modification 1, even if any of the data processing units 2a, 2b, and 2c fails, by providing the backup data processing unit 2d having the reconfigurable circuit 4 in the distributed processing device 1, A circuit equivalent to the faulty data processing unit 2 can be reconfigured into the spare data processing unit 2d.

Therefore, the failed data processing unit 2 can be easily switched to the spare data processing unit 2d. Furthermore, since the faulty data processing unit 2 can be switched to the backup data processing unit 2d in a short period of time after the detection of the fault until the circuit is reconfigured, the distributed processing device 1 minimizes deterioration in data processing performance. can be suppressed to

Further, according to Modification 2, it is possible to perform failure detection while continuing data processing using the spare data processing unit 2d.

Further, according to Modification 3, by providing the preliminary data processing unit 2d having the reconfigurable circuit 4 in the distributed processing device 1, new processing can be easily added to the preliminary data processing unit 2d.

Further, according to Modification 4, by using a dynamically reconfigurable circuit for the reconfigurable circuit 4, the circuit scale of the reconfigurable circuit 4 can be further reduced. This is because the distributed processing can be further divided and the circuits corresponding to the divided circuits can be dynamically reconfigured as needed.

Furthermore, even if programmable devices such as FPGAs used in the data processing unit 2 and the spare data processing unit 2d become unavailable due to reasons such as discontinuation of manufacture, a different programmable device such as an FPGA can be easily adopted at a low cost. The data processing unit 2 can be replaced with the The reason for this is that the data processing unit 2 reconfigures a small-scale circuit into a reconfigurable circuit 4, so that even if different programmable devices such as FPGAs are used, the time required for circuit design can be shortened. be.

[program]
The program according to the embodiment of the present invention causes a computer to perform steps A1 to A2 shown in FIG. 5, steps B1 to B4 shown in FIG. 6, steps C1 to C10 shown in FIG. 7, or steps D1 to D1 shown in FIG. D2, steps E1 to E4 shown in FIG. 9, or a program for executing a combination of two or more thereof may be used. By installing this program in a computer and executing it, the distributed processing apparatus and distributed processing method according to the present embodiment can be realized. In this case, the processor of the computer functions as the reconfiguration control unit 3 and performs processing.

[Physical configuration]
Here, a computer that implements the reconfiguration control unit 3 of the distributed processing device 1 by executing the programs in the first, second, third, and fourth embodiments will be described with reference to FIG. FIG. 10 is a block diagram showing an example of a computer that implements a reconfiguration control unit according to the embodiment of the present invention;

As shown in FIG. 10, a computer 110 includes a CPU (Central Processing Unit) 111, a main memory 112, a storage device 113, an input interface 114, a display controller 115, a data reader/writer 116, and a communication interface 117. and These units are connected to each other via a bus 121 so as to be able to communicate with each other. The computer 110 may include a GPU (Graphics Processing Unit) or an FPGA (Field-Programmable Gate Array) in addition to the CPU 111 or instead of the CPU 111 .

The CPU 111 expands the programs (codes) of the present embodiment stored in the storage device 113 into the main memory 112 and executes them in a predetermined order to perform various calculations. Main memory 112 is typically a volatile storage device such as a DRAM (Dynamic Random Access Memory). Also, the program in the present embodiment is provided in a state stored in computer-readable recording medium 120 . It should be noted that the program in this embodiment may be distributed on the Internet connected via communication interface 117 .

Further, as a specific example of the storage device 113, in addition to a hard disk drive, there is a semiconductor storage device such as a flash memory. Input interface 114 mediates data transmission between CPU 111 and input devices 118 such as a keyboard and mouse. The display controller 115 is connected to the display device 119 and controls display on the display device 119 .

Data reader/writer 116 mediates data transmission between CPU 111 and recording medium 120 , reads programs from recording medium 120 , and writes processing results in computer 110 to recording medium 120 . Communication interface 117 mediates data transmission between CPU 111 and other computers.

Specific examples of the recording medium 120 include general-purpose semiconductor storage devices such as CF (Compact Flash (registered trademark)) and SD (Secure Digital); magnetic recording media such as flexible disks; An optical recording medium such as a ROM (Compact Disk Read Only Memory) can be mentioned.

[Appendix]
Further, the following additional remarks are disclosed with respect to the above embodiment. Part or all of the above-described embodiments can be expressed by (Appendix 1) to (Appendix 15) described below, but are not limited to the following description.

(Appendix 1)
a data processing unit having a reconfigurable circuit;
a reconfiguration control unit that controls dynamic circuit reconfiguration for each of the plurality of data processing units using circuit information corresponding to each of the distributed data processing;
A distributed processing device comprising:

(Appendix 2)
The distributed processing device according to Supplementary Note 1,
further comprising a preliminary data processing unit comprising a reconfigurable circuit;
The distributed processing device, wherein the reconfiguration control unit causes the backup data processing unit provided separately from the plurality of data processing units to reconfigure the circuit corresponding to the circuit information.

(Appendix 3)
The distributed processing device according to Supplementary Note 2,
The distributed processing device, wherein the reconfiguration control unit causes the data processing unit or the backup data processing unit to reconfigure a fault detection circuit that detects a fault in the reconfigurable circuit.

(Appendix 4)
The distributed processing device according to Supplementary Note 3,
The reconfiguration control unit selects the data processing unit and the backup data processing unit in a preset order on a preset date and time, and reconfigures the failure detection circuit.

(Appendix 5)
The distributed processing device according to any one of appendices 1 to 4,
A distributed processing device, wherein the reconfigurable circuit is a dynamically reconfigurable circuit.

(Appendix 6)
(a) transmitting circuit information corresponding to each distributed data processing to a data processing unit having a reconfigurable circuit; and (b) using the received circuit information for each of the data processing units. dynamically reconfiguring the circuit with
A distributed processing method characterized by comprising:

(Appendix 7)
The distributed processing method according to appendix 6,
(c) A distributed processing method, comprising the step of reconfiguring a circuit corresponding to the circuit information in a spare data processing unit provided separately from the plurality of data processing units.

(Appendix 8)
The distributed processing method according to Supplementary Note 7,
(d) The distributed processing method, further comprising the step of reconfiguring a fault detection circuit for detecting a fault in the reconfigurable circuit in the data processing unit or the backup data processing unit.

(Appendix 9)
The distributed processing method according to Appendix 8,
The distributed processing method, wherein in step (d), the failure detection circuit is reconfigured by selecting the data processing unit and the backup data processing unit in a preset order on a preset date and time. .

(Appendix 10)
The distributed processing method according to any one of Appendices 6 to 9,
A distributed processing method, wherein the reconfigurable circuit is a dynamically reconfigurable circuit.

(Appendix 11)
to the computer,
(a) transmitting circuit information corresponding to each distributed data processing to a data processing unit having a reconfigurable circuit; and (b) using the received circuit information for each of the data processing units. dynamically reconfiguring the circuit with
A program characterized by causing the execution of

(Appendix 12)
The program according to Supplementary Note 11,
to the computer;
(c) A program for causing a backup data processing unit provided separately from the plurality of data processing units to reconfigure a circuit corresponding to the circuit information.

(Appendix 13)
The program according to Appendix 11 or 12,
to the computer;
(d) A program that causes the data processing unit or the backup data processing unit to reconfigure a fault detection circuit that detects a fault in the reconfigurable circuit.

(Appendix 14)
The program according to Appendix 13,
A program, wherein in the step (d), the failure detection circuit is reconfigured by selecting the data processing unit and the backup data processing unit in the order set in advance on a date and time set in advance.

(Appendix 15)
15. The program according to any one of appendices 11 to 14,
A program, wherein the reconfigurable circuit is a dynamically reconfigurable circuit.

As described above, according to the present invention, robustness can be ensured at low cost. INDUSTRIAL APPLICABILITY The present invention is useful in the field of distributed processing using a plurality of programmable devices.

1 distributed processing unit 2, 2a, 2b, 2c data processing unit 2d preliminary data processing unit 3 reconfiguration control unit 4, 4a, 4b, 4c, 4d reconfigurable circuit 5, 5a, 5b, 5c, 5d circuit information 21 network 22a, 22b, 22c, 22d communication unit 23 communication unit 41a, 41b area 110 computer 111 CPU
112 Main memory 113 Storage device 114 Input interface 115 Display controller 116 Data reader/writer 117 Communication interface 118 Input device 119 Display device 120 Recording medium 121 Bus

Claims (4)

a plurality of data processing units having dynamically reconfigurable circuits capable of dynamic partial reconfiguration;
one or more spare data processing units having a dynamically reconfigurable circuit provided separately from the plurality of data processing units;
a reconfiguration control unit that dynamically reconfigures the circuits of the data processing unit and the preliminary data processing unit using circuit information corresponding to each of the distributed data processing units ; ,
The reconfiguration control unit
Select the data processing units in the order set in advance at the date and time set in advance,
cause the selected data processing unit to reconfigure a fault detection circuit that detects a fault in the dynamically reconfigurable circuit and execute diagnosis for detecting the fault;
When failure detection information indicating that a failure has been detected in the selected data processing unit is acquired from the failure detection circuit, a circuit equivalent to the reconfigured circuit in the data processing unit that has detected the failure, causing the preliminary data processing unit to reconfigure;
A distributed processing device characterized by: The distributed processing device according to claim 1,
When the reconfiguration control unit acquires failure detection information indicating that no failure is detected in the selected data processing unit from the failure detection circuit, the reconfiguration control unit restores the circuit of the selected data processing unit to the state before diagnosis. to reconfigure to
A distributed processing device characterized by: a plurality of data processing units having dynamically reconfigurable circuits capable of dynamic partial reconfiguration;
one or more spare data processing units having a dynamically reconfigurable circuit provided separately from the plurality of data processing units;
a reconfiguration control unit that controls dynamic circuit reconfiguration of each of the data processing unit and the backup data processing unit using circuit information corresponding to each of the distributed data processing A processing device,
The reconfiguration control unit
Select the data processing units in the order set in advance at the date and time set in advance,
cause the selected data processing unit to reconfigure a fault detection circuit that detects a fault in the dynamically reconfigurable circuit, and execute diagnosis for fault detection;
When failure detection information indicating that a failure has been detected in the selected data processing unit is acquired from the failure detection circuit, a circuit equivalent to the reconfigured circuit in the data processing unit that has detected the failure, causing the preliminary data processing unit to reconfigure;
A distributed processing method characterized by: a plurality of data processing units having dynamically reconfigurable circuits capable of dynamic partial reconfiguration;
one or more spare data processing units having a dynamically reconfigurable circuit provided separately from the plurality of data processing units;
A distributed processing apparatus comprising: a computer that dynamically reconfigures the circuits of the data processing unit and the preliminary data processing unit using circuit information corresponding to each of the distributed data processing units; There is
to the computer;
causing the data processing units to be selected in the order set in advance on a date and time set in advance;
cause the selected data processing unit to reconfigure a fault detection circuit that detects a fault in the dynamically reconfigurable circuit and execute diagnosis for detecting the fault;
When failure detection information indicating that a failure has been detected in the selected data processing unit is acquired from the failure detection circuit, a circuit equivalent to the reconfigured circuit in the data processing unit that has detected the failure, causing the preliminary data processing unit to reconfigure;
A program characterized by

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