JP5691285B2 - Manufacturing method of display device - Google Patents

Description

  The present invention relates to a method for crystallizing an amorphous semiconductor film, a thin film transistor (hereinafter referred to as TFT), a semiconductor device, a display device, and a method for manufacturing the same.

  In recent years, a liquid crystal display called a driving circuit integrated type in which a driving circuit including a driving TFT formed simultaneously with a pixel TFT arranged in a pixel is formed in the peripheral portion of the pixel portion, and a driving IC mounted outside is omitted. Devices have been put into practical use and are increasingly used in small liquid crystal display devices and the like. In such a liquid crystal display device, since it is necessary to achieve the driving speed required for the operation of the driving circuit for the driving TFT, amorphous silicon TFTs (hereinafter referred to as amorphous silicon TFTs) conventionally used for pixel TFTs are required. In many cases, a polycrystalline silicon TFT having a driving capability superior to that of a TFT) is used. Furthermore, since it is advantageous in manufacturing cost to form the pixel TFT and the driving TFT at the same time, a polycrystalline silicon TFT is often used as the pixel TFT in accordance with the demand for the driving TFT. However, the pixel TFT does not require the high field effect mobility and low threshold voltage shift that the polycrystalline silicon TFT has, and conversely, the characteristic variation and the leakage current are larger than those of the amorphous TFT. In this case, it is not always easy to use a polycrystalline silicon TFT as a pixel TFT. Therefore, in addition to using a polycrystalline silicon TFT as a driving TFT, in order to use a polycrystalline silicon TFT as a pixel TFT, the introduction of the latest technology to suppress the polycrystalline silicon TFT characteristic variation and leakage current has been introduced. Manufacturing management that would not be necessary became necessary, and the manufacturing cost was very high. In other words, the pixel TFT and the driving TFT are different in required TFT characteristics, but in order to manufacture a pixel TFT that satisfies the requirements for both simultaneously with the same TFT, a great amount of labor and manufacturing cost are required. It was supposed to be.

  In order not to increase the manufacturing cost as described above, in parallel to forming an amorphous TFT using an amorphous semiconductor film for a pixel TFT, an amorphous semiconductor film for a driving TFT is formed. A method is desired in which a polycrystalline silicon TFT is formed by converting the film into a polycrystalline semiconductor film, and an amorphous TFT and a polycrystalline silicon TFT are separately formed on the same substrate. As a method of solving such a problem, in Patent Document 1, a part of an amorphous semiconductor film is irradiated with a strong energy beam such as laser light by partially selecting the amorphous semiconductor film. A crystallization annealing method for converting into a crystalline semiconductor film is disclosed.

  Further, as disclosed in Patent Document 1, a silicon nitride film (SiN film) is suitable for the amorphous TFT as the gate insulating film on the side in contact with the semiconductor film, and in the case of the polycrystalline silicon TFT. A silicon oxide film is suitable. For example, when the gate insulating film of the amorphous TFT is a silicon oxide film, a threshold voltage shift occurs when a negative bias is applied to the gate electrode in addition to the problem that the threshold voltage is enhanced. Conversely, when the gate insulating film of a polycrystalline silicon TFT is a silicon nitride film, the trap density and defect level near the interface cannot be lowered even if adjustments such as increasing the laser irradiation power are made. Therefore, there arises a problem that the threshold voltage is shifted to the depletion side.

  In Patent Document 1, a polycrystalline silicon TFT is formed by selectively irradiating a laser. For example, a polycrystalline silicon TFT is selectively irradiated by irradiating a laser to a driving circuit region of a liquid crystal display device. When trying to form the drive circuit region, the drive circuit region is not continuously arranged. That is, it is necessary to align each drive circuit area and selectively irradiate a specific area with laser. Of course, the positions and regions of the drive circuits are different on the transparent insulating substrate for each liquid crystal display device. In particular, in the case of a small-sized liquid crystal display device used for a mobile phone or the like, the drive circuit area becomes narrow, and higher laser irradiation position accuracy is required. On the other hand, if the current laser irradiation position accuracy is taken into account and only the drive circuit area is converted to polycrystalline silicon, the drive circuit area and the display area need to be separated greatly in consideration of the deviation amount of the laser irradiation position. There is. Therefore, the frame area other than the display area becomes large, and the narrow frame at the level required in recent liquid crystal display devices cannot be achieved. Furthermore, when manufacturing a small-sized liquid crystal display device, a manufacturing method in which a very large number of units are taken (simultaneously formed) more than a single transparent insulating substrate is generally used from the viewpoint of mass production efficiency. When manufacturing by multi-cavity like this, a plurality of liquid crystal display devices are arranged in an array on a transparent insulating substrate. Since it is necessary to irradiate the laser to the drive circuit areas provided in the individual liquid crystal display devices arranged in this array, each drive circuit area is aligned and specified. The process of selectively irradiating a region with a laser and moving to the next region must be repeated very many times per transparent insulating substrate. Therefore, adopting such a method is not practical because it takes too much time for the laser irradiation treatment and there is a problem in productivity. In other words, even if a laser apparatus having a position accuracy exceeding the position accuracy of the drive circuit region is made, it is not easy to put it into practical use including mass production.

In addition, as a method of selectively irradiating an energy beam, a method of irradiating an energy beam through a mask having a partial opening is also conceivable. rapid thermal annealing to heat raised to 1000~1200 ℃ (R apid T hermal a nnealing: RTA) method is also applicable to a method of irradiating energy to the entire substrate surface, such as. However, the method of irradiating an energy beam through a mask having a partially opened mask can avoid the productivity problem described above, but the problem of the accuracy of alignment between the mask and the substrate is the laser irradiation position described above. Since it exists in the same manner as the problem of the amount of deviation, it also hinders the narrowing of the frame.

JP-A-5-107560

  The present invention has been made to solve the problems as described above, and an object of the present invention is to provide an amorphous TFT having an amorphous semiconductor film suitable for use in a pixel TFT or the like as an active layer, It is possible to form a polycrystalline silicon TFT having a crystalline semiconductor film suitable for use in a driving TFT or the like as an active layer in the same substrate, and a semiconductor film disposed in the same substrate Provides a simple method capable of selectively crystallizing and accurately producing an amorphous semiconductor film and a crystalline semiconductor film, a TFT, a semiconductor device, a display device, and a method of manufacturing the same to which the amorphous semiconductor film and the crystalline semiconductor film are applied. Is.

The method for manufacturing a display device according to the present invention is a method for manufacturing a display device including a crystalline semiconductor thin film transistor and an amorphous semiconductor thin film transistor mixed on a substrate composed of a transparent insulating substrate, the method comprising: Forming a first gate electrode constituting the crystalline semiconductor thin film transistor and a second gate electrode constituting the amorphous semiconductor thin film transistor, and on the first gate electrode and the second gate electrode. Forming a silicon oxide film on the substrate including, and forming a silicon nitride film that has an opening in a region including at least the first gate electrode and partially covers the silicon oxide film, The silicon nitride film covered with the silicon nitride film and the first region which is not covered with the silicon nitride film and the silicon oxide film becomes a surface Forming a second region to be a surface layer, at least on the silicon oxide film including on the first gate electrode in the first region and on the second gate electrode in the second region A step of forming an amorphous semiconductor film in contact with the surface of each insulating film on the silicon nitride film, and the amorphous semiconductor film formed in the first region and the second region. By irradiating an energy beam to both of the substrates continuously or uniformly under the same irradiation conditions, only the amorphous semiconductor film formed in the first region is changed into a crystalline semiconductor film. An annealing process for converting and maintaining the amorphous semiconductor film formed in the second region in an amorphous state, the crystalline semiconductor film converted in the first region, and the second region Maintained in an amorphous state Forming a source electrode and a drain electrode simultaneously with each of the crystalline semiconductor films, and forming the silicon oxide film as a first gate insulating film on the first gate electrode. And further, forming the crystalline semiconductor thin film transistor having the crystalline semiconductor film as an active layer on the second gate electrode through the first gate insulating film, and forming a second on the second gate electrode. A laminated film made of the silicon oxide film and the silicon nitride film formed on the silicon oxide film, and the amorphous semiconductor on the second gate insulating film The amorphous semiconductor thin film transistor including the amorphous semiconductor film is formed as an active layer of the thin film transistor, and the amorphous semiconductor thin film transistor is used as an image. This is used for a pixel thin film transistor for supplying a display voltage or a display current for controlling the amount of light visually recognized, and the crystalline semiconductor thin film transistor is used for a driving thin film transistor constituting a driving circuit .

According to the present invention, an amorphous semiconductor film and a microcrystalline semiconductor film are separately formed on a substrate composed of a transparent insulating substrate by a relatively simple annealing method, and an amorphous film optimized as a pixel thin film transistor It is possible to obtain a display device including a crystalline semiconductor TFT and a crystalline semiconductor TFT optimized as a driving thin film transistor at a low manufacturing cost .

FIG. 3 is a plan view showing a liquid crystal display panel in the drive circuit integrated liquid crystal display device in the first embodiment. It is sectional drawing which shows TFT used for the liquid crystal display device of Embodiment 1 of this invention. It is sectional drawing explaining the manufacturing method of TFT used for the liquid crystal display device of Embodiment 1 of this invention. It is the analysis data by the Raman analysis of the semiconductor film in the manufacturing process of TFT in Embodiment 1 of this invention. FIG. 5 is a schematic plan view showing the configuration of the mother array substrate in the manufacturing process of the liquid crystal display device in the first embodiment. It is sectional drawing which shows TFT used for the liquid crystal display device of Embodiment 2 of this invention. It is sectional drawing explaining the manufacturing method of TFT used for the liquid crystal display device of Embodiment 2 of this invention. It is sectional drawing which shows TFT used for the liquid crystal display device of Embodiment 3 of this invention. It is sectional drawing explaining the manufacturing method of TFT used for the liquid crystal display device of Embodiment 3 of this invention.

Embodiment 1 FIG.
First, as a first embodiment of the present invention, the present invention is applied to a liquid crystal display device integrated with a driving circuit, which is an example of a semiconductor device provided with a mixture of a crystalline semiconductor TFT and an amorphous semiconductor TFT on a substrate. The case of applying will be described as an example. First, FIG. 1 is a plan view showing a liquid crystal display panel constituting the liquid crystal display device according to the first embodiment. The drawings are schematic and do not reflect the exact size of the components shown. Moreover, omission of parts other than the main part of the invention and simplification of a part of the configuration are appropriately performed so that the drawings are not complicated. The same applies to the following drawings. Further, in the following drawings, the same components as those described in the previous drawings are denoted by the same reference numerals, and the description thereof is omitted.

  In the liquid crystal display panel according to the first embodiment, two substrates composed of a transparent insulating substrate such as a glass substrate are disposed to face each other, but as shown in FIG. A pixel TFT 105 serving as a switching element for controlling on / off of supply of a display voltage for applying a voltage to the liquid crystal is disposed on the substrate to be configured corresponding to the pixel 103 serving as a unit for displaying an image. Since the pixel TFTs 105 are arranged in an array for each pixel 103, the substrate on which the pixel TFTs 105 are arranged is referred to as an array substrate 100. Further, the array substrate 100 is provided with a display area 101 for displaying an image and a frame area 102 provided so as to surround the display area 101. In the display region 101, a plurality of gate lines (scanning signal lines) 108, a plurality of storage capacitor lines 110, and a plurality of source lines (display signal lines) 109 are formed.

  The plurality of gate wirings 108 and the plurality of storage capacitor wirings 110 are arranged to face each other and are provided in parallel. The gate wiring 108, the storage capacitor wiring 110, and the source wiring 109 are arranged so as to be orthogonal to each other. A region surrounded by the adjacent gate wiring 108 and the storage capacitor wiring 110 and the adjacent source wiring 109 is the pixel 103. In the array substrate 100, the pixels 103 are arranged in a matrix.

  In the pixel 103, at least one pixel TFT 105 and a storage capacitor 107 connected to the pixel TFT 105 are formed to be connected in series. The pixel TFT 105 serves as a switching element for supplying a display voltage to the pixel electrode. The gate electrode of the pixel TFT 105 is connected to the gate wiring 108, and on / off of the pixel TFT 105 is controlled by a gate signal (scanning signal) supplied from the gate wiring 108. The source electrode of the pixel TFT 105 is connected to the source wiring 109. When the pixel TFT 105 is turned on, a current flows from the source electrode side to the drain electrode side of the pixel TFT 105. Thereby, a display voltage is applied to the pixel electrode connected to the drain electrode. An electric field corresponding to the display voltage is generated between the pixel electrode and the counter electrode. Further, the storage capacitor 107 is connected in parallel with a capacitor formed between the pixel electrode and the counter electrode. Therefore, the voltage is applied to the storage capacitor 107 at the same time as the voltage is applied to the pixel electrode, and the charge can be held for a certain time.

  Further, a drive circuit 104 is provided in the frame region 102 of the array substrate 100. For example, the driving circuit includes a scanning signal driving circuit and a display signal driving circuit. A circuit is constituted by the driving TFT 106 formed simultaneously with the pixel TFT 105 in the display area 101. The gate line 108 extends from the display area 101 to the frame area 102. The gate wiring 108 is connected to a scanning signal driving circuit 104. Similarly, the source line 109 extends from the display area 101 and is connected to the display signal driving circuit 104. These drive circuits 104 are connected to external terminals via external wiring 111. A printed circuit board 112 is mounted on and electrically connected to the external terminals.

  An IC chip 113 for controlling various signals is mounted on the printed circuit board 112. As these signals, a gate signal (scanning signal) is supplied to the gate wiring 108, and the pixel TFTs 105 are sequentially selected. Similarly, a source signal (display signal) is supplied to the source wiring 109, and a display voltage corresponding to display data is supplied to each pixel 103. An alignment film is formed on the outermost surface of the array substrate 100. The array substrate 100 is configured as described above.

Hereinafter, although not shown in the drawings, the array substrate 100 is provided with a counter substrate, which is another substrate made of a transparent insulating substrate such as a glass substrate, facing the array substrate 100. The counter substrate is a color filter substrate (CF substrate), for example, and is disposed on the viewing side. In the counter substrate, for example, a color resist (color material), a black matrix (BM), a counter electrode, an alignment film, and the like are formed on a glass substrate. Incidentally, for example, IPS mode and FFS: sometimes counter electrode as the (F ringe F ield S witching FFS ) mode liquid crystal display device is disposed on the array substrate 100 side. Then, liquid crystal is injected between the array substrate 100 and the counter substrate. Polarizing plates are attached to the outside of the array substrate 100 and the counter substrate, and the liquid crystal display panel is configured as described above. Further, a backlight unit is disposed on the non-viewing side of the liquid crystal display panel configured as described above via an optical film such as a retardation plate. Further, the liquid crystal display panel and these peripheral members are appropriately accommodated in a frame made of resin or metal. The liquid crystal display device according to the first embodiment is configured as described above.

  Next, the display operation of the liquid crystal display device according to the first embodiment will be briefly described. The liquid crystal is driven by the electric field between the pixel electrode and the counter electrode. That is, the alignment direction of the liquid crystal between the substrates changes, and the amount of light passing through the liquid crystal changes. That is, the amount of light that passes through the polarizing plate on the viewing side among the transmitted light that passes through the liquid crystal display panel from the backlight unit changes. The alignment direction of the liquid crystal changes depending on the applied display voltage. Therefore, the amount of light passing through the viewing-side polarizing plate can be changed by controlling the display voltage. That is, the amount of light visually recognized as an image can be controlled. In this series of operations, the storage capacitor 107 contributes to holding the display voltage.

  Next, referring to FIG. 2, the structure of the amorphous semiconductor TFT used for the pixel TFT 105 and the microcrystalline semiconductor TFT which is an example of the crystalline semiconductor TFT used for the driving TFT 106 is arranged on the array substrate 100. Will be described. FIG. 2 is a sectional view showing a TFT used in the liquid crystal display device according to the first embodiment of the present invention. Note that the TFT used in the liquid crystal display device of Embodiment 1 is an inverted staggered TFT.

  As shown in FIG. 2, on the substrate 1 made of a transparent insulating substrate such as glass, each of the region where the pixel TFT 105 is formed and the region where the driving TFT 106 is formed (curly brackets by dotted lines). And a region corresponding to the TFT reference numeral), a gate electrode 22 as a first gate electrode constituting a microcrystalline semiconductor TFT serving as a driving TFT 106 and an amorphous semiconductor serving as a pixel TFT 105. A gate electrode 21 which is a second gate electrode constituting the TFT is formed. The substrate 1 may be only a transparent insulating substrate such as glass, or an underlying layer having some function on the surface of the transparent insulating substrate such as glass below the gate electrodes 21 and 22. And other configurations may be appropriately formed.

  Then, a first insulating film 31 is formed on the substrate 1 including the gate electrodes 21 and 22 so as to cover the gate electrodes 21 and 22. For the first insulating film 31, a silicon oxide film (SiO film) is used. In the region where the pixel TFT 105 is formed, a silicon nitride film (SiN film) is formed as the second insulating film 33 that partially covers the first insulating film 31. In other words, the second insulating film 33 made of a silicon nitride film has an opening 34 in a region including at least the gate electrode 22 in a region where the driving TFT 106 is formed. The opening 34 is not limited to the opening surrounded by the second insulating film 33, and the partially formed second insulating film 33 is not formed, that is, the opening 34 is covered by the second insulating film 33. All the areas that are not applicable fall under this category. Further, with the above configuration, the first gate insulating film 42 which is a gate insulating film constituting the microcrystalline semiconductor TFT serving as the driving TFT 106 is configured by the first insulating film 31 made of a silicon oxide film, and the pixel TFT 105 The second gate insulating film 41, which is a gate insulating film constituting the amorphous semiconductor TFT to be, is a stack of a first insulating film 31 made of a silicon oxide film and a second insulating film 33 made of a silicon nitride film. Consists of a membrane.

  Further, in the region where the pixel TFT 105 is formed, an amorphous semiconductor film 51 serving as an active layer of the TFT is formed in direct contact with the surface of the second insulating film 33 in the region covered with the second insulating film 33. . On the other hand, in the region where the driving TFT 106 is formed, the first insulating film 31 is a surface layer in the region of the opening 34 formed in the second insulating film 33 that is not covered by the second insulating film 33. A microcrystalline semiconductor film 52 serving as an active layer of the TFT is formed in direct contact with the surface of the first insulating film 31 in the region of the opening 34. This microcrystalline semiconductor film 52 is a crystalline semiconductor film obtained by heating and crystallizing an amorphous semiconductor film by excimer laser irradiation. More specifically, an amorphous silicon film and a microcrystalline silicon film are used as the amorphous semiconductor film 51 and the microcrystalline semiconductor film 52 in the first embodiment. Note that in general, a microcrystalline semiconductor film is a category of a polycrystalline semiconductor film; however, in this specification, a crystallinity formed of small crystal grains of approximately the same size of about 100 nm or less. The semiconductor film is particularly distinguished and referred to as a microcrystalline semiconductor film.

  Note that the first insulating film 31 made of a silicon oxide film formed below the microcrystalline semiconductor film 52 is formed below the second insulating film 33 to form the second gate insulating film 41, and at least It may be formed below the microcrystalline semiconductor film 52. The opening 34 formed in the second insulating film 33 made of the silicon nitride film may be formed at least in a region below the microcrystalline semiconductor film 52 where the second insulating film 33 does not exist. It may be provided in the entire driving circuit 104 or the entire region of the pixel TFT 105 except for the area under the amorphous semiconductor film 51, which is the formation region of the TFT 106. Furthermore, in other words, the second insulating film 33 made of a silicon nitride film only needs to be provided at least in the lower layer of the amorphous semiconductor film 51, and conversely, the entire display area 101 or the driving area serving as the formation area of the pixel TFT 105. The TFT 106 may be provided in all regions except under the microcrystalline semiconductor film 52.

  Further, on the amorphous semiconductor film 51 in the pixel TFT 105, an amorphous semiconductor film 61 and amorphous semiconductor films 71 s and 71 d containing two impurities formed separately from each other are stacked. A configured amorphous semiconductor layer 81 is formed. Further, on the microcrystalline semiconductor film 52 in the driving TFT 106, similarly to the pixel TFT 105, an amorphous semiconductor film 62, and an amorphous semiconductor film 72 s containing two impurities formed separately from each other, An amorphous semiconductor layer 82 formed by stacking 72d is formed. Here, the amorphous semiconductor film 51 and the amorphous semiconductor layer 81 are patterned in the same planar shape. Similarly, the microcrystalline semiconductor film 52 and the amorphous semiconductor layer 82 are patterned in the same planar shape. Yes. In the first embodiment, the impurity regions formed in the amorphous semiconductor layer 81 and the amorphous semiconductor layer 82 that are common to the pixel TFT 105 and the driving TFT 106 are amorphous in this way. The semiconductor films 71 s and 71 d and the amorphous semiconductor films 72 s and 72 d are formed on the amorphous semiconductor layer 61 and the amorphous semiconductor layer 62, but the amorphous semiconductor layer 61 and the amorphous semiconductor layer 61 are formed. Impurities may be implanted into part of the crystalline semiconductor layer 62 to form two impurity regions separated from each other.

  Further, in common with the pixel TFT 105 and the driving TFT 106, a source electrode made of a metal film is in contact with the amorphous semiconductor films 71 s and 71 d (or 72 s and 72 d) containing impurities that are formed separately from each other. 91s (or 92s) and a drain electrode 91d (or 92d) are formed. The active layer region under the source electrode 91s (or 92s) is called a source region, and the active layer region under the drain electrode 91d (or 92d) is called a drain region. The active layer region sandwiched between the source region and the drain region is called a channel region. As a result, the source electrode 91s (or 92s) and the drain electrode 91d (or 92d) pass through the amorphous semiconductor film 61 (or 72d) through the amorphous semiconductor films 71s (or 72s) and 71d (or 72d) containing impurities. 62) and the amorphous semiconductor film 51 (or the microcrystalline semiconductor film 52). The amorphous semiconductor films 71s and 71d (or 72s and 72d) containing the impurities are the source electrodes 91s (or 92s). In addition, the connection resistance with the drain electrode 91d (or 92d) is lowered to perform ohmic connection. Further, the amorphous semiconductor film 61 (or 62) is the same as or thinner than the film thickness in the source region and the drain region in the channel region. In this way, the pixel TFT 105 and the driving TFT 106 are formed.

  The operations of the pixel TFT 105 and the driving TFT 106 whose configurations have been described above will be briefly described. When a gate voltage is applied to the gate electrode 21 of the pixel TFT 105, a channel is formed mainly on the gate insulating film 41 side of the channel region in the amorphous semiconductor film 51 which is an active layer. When a signal voltage is applied from the source wiring side, a current flows from the source region to the drain region via the channel portion of the channel region via the source electrode 91s, and a current flows to the drain electrode 91d. Similarly, in the driving TFT 106, when a gate voltage is applied to the gate electrode 22, a channel is formed mainly on the gate insulating film 42 side of the channel region in the microcrystalline semiconductor film 52 that is an active layer. Then, a current flows from the source region to the drain region via the channel portion of the channel region via the source electrode 92s, and a current flows to the drain electrode 92d. Note that the source electrode 91s and the drain electrode 91d or the source electrode 92s and the drain electrode 92d in the amorphous semiconductor TFT and the microcrystalline semiconductor TFT constituting the pixel TFT 105 and the driving TFT 106 are the active layer of the amorphous semiconductor film 51 or the microscopic TFT. As the connection means for connecting to the crystalline semiconductor film 52, as described above, the amorphous semiconductor films 71s (or 72s) and 71d (or 72d) containing impurities are formed in order to lower the connection resistance and make ohmic connection. And a method of injecting impurities into part of the amorphous semiconductor layer 61 and the amorphous semiconductor layer 62. However, as long as it can function as a TFT as a minimum, the source electrode 91s (or 92s) and the drain electrode 91d (or 92d) are basically connected to the amorphous semiconductor TFT or the microcrystalline semiconductor TFT. Any configuration may be used as the specific connection means.

  Next, a method for manufacturing the liquid crystal display device according to the first embodiment will be described with reference to FIGS. 3A to 3F are schematic cross-sectional views in the middle of the manufacturing process of the TFT used in the liquid crystal display device of Embodiment 1 of the present invention.

  First, a metal film is formed on a substrate 1 made of a transparent insulating substrate by sputtering. As the substrate 1, for example, a glass substrate or a quartz substrate can be used, and further, a base layer or other configuration that has some function before forming a metal film on the surface of a transparent insulating substrate such as a glass substrate or a quartz substrate. May be formed. As the metal film, aluminum (Al) or an alloy containing the same, preferably molybdenum (Mo) or chromium (Cr) which is a high melting point metal can be used. By using a refractory metal as the metal film, damage due to thermal damage can be suppressed in later laser irradiation. Then, a photoresist, which is a photosensitive resin, is applied onto the metal film by spin coating, and a first photolithography process (photoengraving process) is performed in which the applied photoresist is exposed and developed. As a result, the photoresist is patterned into a desired planar shape. Thereafter, using the photoresist as a mask, the metal film is etched and patterned into a desired shape. Thereafter, the photoresist pattern is peeled off. Thereby, the gate electrodes 21 and 22 are formed by patterning. The end surfaces of the gate electrodes 21 and 22 are preferably tapered. By adopting the taper shape, the film property of film formation performed thereafter is improved. For example, when a silicon oxide film is subsequently formed, the film property is improved and the withstand voltage is improved. In this manner, the gate electrode is formed for each of the regions where the pixel TFT 105 is formed later and the region where the driving TFT 106 is formed (regions are indicated by reference numerals of the TFTs corresponding to the curly brackets indicated by dotted lines). 21 and 22 are formed, and subsequently, a silicon oxide film as a first insulating film 31 is formed on the substrate 1 including the formed gate electrodes 21 and 22 by a plasma CVD method, for example, a film thickness of 200 nm. The film is formed. Further, a silicon nitride film 32 is formed on the first insulating film 31 to a thickness of 100 nm, for example. Then, in the second photolithography process, a photoresist PR is formed in a region indicated by dotted brackets 105 in the drawing, that is, a region where the pixel TFT 105 is formed later. With the above process, the configuration shown in FIG.

  Subsequently, using the photoresist PR as a mask, the silicon nitride film 32 is removed by etching to form an opening 34. As a result, a second insulating film 33 having an opening 34 and partially covering the first insulating film 31 is formed. In the step of removing the silicon nitride film 32 by etching and forming the second insulating film 33, the etching speed of the silicon nitride film 32 is faster than the etching speed of the silicon oxide film. At the time of overetching, the amount of scraping of the surface layer of the first insulating film 31 generated by exposing the surface layer of the first insulating film 31 made of the lower silicon oxide film to the etching can be kept low. As a result, a high-quality silicon oxide film surface can be exposed in the region of the driving TFT 106. Through the above steps, as shown in FIG. 3B, the first gate insulating film formed of the first insulating film 31 made of the silicon oxide film is formed on the first gate electrode 22 of the driving TFT 106. 42 is formed on the second gate electrode 21 of the pixel TFT 105 by a laminated film of a first insulating film 31 made of a silicon oxide film and a second insulating film 33 made of a silicon nitride film. A gate insulating film 41 is formed respectively.

  Then, as described above, the first insulating film 31 is not covered by the second insulating film 33 that is the region of the opening 34, and the second insulating film 33 is covered by the second insulating film 33 and the second insulating film 33. An amorphous semiconductor film 5 is formed on a substrate 1 made of a transparent insulating substrate on which a base film structure having a region where the insulating film 33 is a surface layer is formed. In the first embodiment, the amorphous semiconductor film 5 is formed with a film thickness of about 40 nm over substantially the entire surface of the substrate 1 by using, for example, an amorphous silicon film. The amorphous semiconductor film 5 is in contact with the surface of the first insulating film 31 made of a silicon oxide film as a surface layer on the first gate insulating film 42, and on the second gate insulating film 41, It is formed in contact with the surface of the second insulating film 33 made of a silicon nitride film as a surface layer. The amorphous semiconductor film 5 is subjected to a dehydrogenation process of about 300 degrees for the purpose of suppressing the ablation caused by the subsequent laser irradiation. With the above process, the configuration shown in FIG.

  Since the amorphous semiconductor film 5 whose surface is exposed is easy to form a natural oxide film, a hydrofluoric acid-based solution (specifically, dilute hydrofluoric acid or buffered hydrofluoric acid having a concentration of several percent is used). A removal process of the natural oxide film on the surface of the amorphous semiconductor film 5 is performed. This removal process of the natural oxide film has an effect of removing contamination from the air on the surface of the amorphous semiconductor film 5 simultaneously with the removal of the natural oxide film. Immediately after the removal process of the natural oxide film, an annealing process is performed in which the amorphous semiconductor film 5 is irradiated with the laser beam LB by scanning from above the excimer laser beam formed into a line beam having a wider width. . Here, the entire substrate 1 was irradiated with the laser beam LB continuously under the same irradiation conditions, particularly at the same irradiation energy density. By performing the annealing process as described above, the amorphous semiconductor film 5 is converted to a microcrystalline semiconductor film 52 in a microcrystalline state in a region in contact with the surface of the first insulating film 31 made of a silicon oxide film, and is nitrided In a region in contact with the surface of the second insulating film 33 made of a silicon film, the amorphous semiconductor film 51 is maintained in an amorphous state, and the structure shown in FIG. That is, the region where the amorphous semiconductor film 5 is converted to the microcrystalline semiconductor film 52 and the amorphous state are maintained in an amorphous state despite the laser beam LB being irradiated with the same irradiation energy density. A region to be the amorphous semiconductor film 51 is separately formed. Further, the positional accuracy of the region where the amorphous semiconductor film 51 is obtained and the region where the microcrystalline semiconductor film 52 is obtained are equal to the accuracy with which the second insulating film 33 made of a silicon nitride film is partially formed. Since it depends on the PR formation accuracy and the silicon nitride film patterning accuracy, the amorphous semiconductor film 51 and the microcrystalline semiconductor film 52 can be separately formed with a high positional accuracy of about 1 μm or less.

  Here, a detailed description will be given of the annealing process by laser irradiation of the first embodiment that enables the microcrystalline semiconductor film 52 and the amorphous semiconductor film 51 to be separately formed. When the amorphous semiconductor film 5 is irradiated with laser, the laser light absorbed by the amorphous semiconductor film 5 is converted into heat. The heat is used for heating and melting the amorphous semiconductor film 5 formed at 40 nm, for example, and contributes to the conversion from the amorphous semiconductor film 5 to the microcrystalline semiconductor film 52. However, part of the heat propagates to the lower substrate 1 side and is not used for heating the amorphous semiconductor film 5. That is, a part of laser irradiation energy is lost due to propagation to the substrate 1 side. First, in the region of the driving TFT 106, as described above, the first insulating film 31 made of a silicon oxide film having a thickness of 200 nm is disposed in contact with the lower layer of the amorphous semiconductor film 5 irradiated with the laser. ing. Here, since the silicon oxide film has relatively low thermal conductivity, the first insulating film 31 prevents the heat transmitted to the lower substrate 1 side described above from being transmitted to the substrate side. It can be accumulated in the amorphous semiconductor film 5. Therefore, the laser irradiation energy density required for conversion to the microcrystalline semiconductor film 52 by laser irradiation can be suppressed. In particular, in the first embodiment, since the silicon oxide film is formed with a relatively large film thickness of 200 nm, heat transfer to the substrate side can be effectively prevented and converted into the microcrystalline semiconductor film 52. The laser irradiation energy density required for the process can be greatly suppressed. In contrast, in the region of the pixel TFT 105, a second insulating film 33 made of a 100 nm silicon nitride film is formed on the first insulating film 31 made of a silicon oxide film. The silicon nitride film has higher thermal conductivity than the silicon oxide film, and has a weak effect of preventing the propagation of heat to the lower substrate 1 described above. Therefore, the loss due to propagation to the first insulating film 31 and the substrate 1 below is large, and as a result, the energy given to the amorphous semiconductor film 5 by laser irradiation is converted into the microcrystalline semiconductor film 52. The energy efficiency used for it is bad. That is, contrary to the region of the driving TFT 106, the laser irradiation energy density required for conversion into the microcrystalline semiconductor film 52 is increased.

As described above, when the film configuration of the first insulating film 31, the second insulating film 33, and the amorphous semiconductor film 5 of the first embodiment is used, the pixel TFT 105 region and the driving TFT 106 region are used. A large difference occurs in the laser irradiation energy density required for conversion to the microcrystalline state. As a result, the first insulating film 31, the second insulating film 33, and the amorphous semiconductor film 5 of the first embodiment are converted into a microcrystalline state in the region of the driving TFT 106. When the amorphous semiconductor film 5 in the region of the pixel TFT 105 and the region of the driving TFT 106 is irradiated with laser under the same irradiation condition using an appropriate laser irradiation energy density, the amorphous semiconductor in the region of the driving TFT 106 In contrast to the conversion from the film 5 to the microcrystalline semiconductor film 52, in the region of the pixel TFT 105, the amorphous semiconductor film 51 is maintained in an amorphous state. As a specific energy density of laser irradiation, the energy density necessary for converting only the amorphous semiconductor film 5 in the driving TFT 106 region into a microcrystalline state having a crystal grain size of 100 nm or less is set to the minimum value, and the pixel Formed in contact with the surface of the second insulating film 33 made of a silicon nitride film, that is, the energy density range in which the amorphous semiconductor film 5 in the TFT 105 region becomes the amorphous semiconductor film 51 maintained in an amorphous state. By selecting a range of energy density that is lower than the energy density necessary for converting the semiconductor film 5 to be converted into a crystalline semiconductor film, the amorphous semiconductor film 51 and the fine TFT are formed in the region of the pixel TFT 105 and the driving TFT 106. The crystalline semiconductor film 52 can be formed separately. More specifically, the range of 180~240mJ / cm ² When using the film structure of the first embodiment is applicable to the above range, more preferably 200 mJ / cm ² becomes the optimum value.

Note that although the crystal grain size of the microcrystalline semiconductor film 52 is set to 100 nm or less, it is determined whether or not microcrystals are obtained by evaluating the crystal grain size by SEM observation or AFM observation after performing the seco-etching process. It can be confirmed as appropriate. More specifically, the crystallinity may be evaluated by Raman analysis as shown in FIG. FIG. 4A and FIG. 4B show Raman analysis data. As shown in the Raman analysis data of FIG. 4A, the crystallization rate obtained from the Raman scattered light intensity peak near the Raman shift of 520 cm ⁻¹ is 60 to 80%, preferably 70 to 80%. By adjusting the laser irradiation energy density, a microcrystalline semiconductor film 52 having a desired crystal grain size can be obtained. On the other hand, FIG. 4B shows that a crystallization ratio of 90% or more was obtained. At this time, the irradiation energy density was not maintained in the amorphous state of the amorphous semiconductor film 5 in the pixel TFT 105 region. Since it is crystallized, the amorphous semiconductor film 51 and the microcrystalline semiconductor film 52 cannot be made separately, which is not appropriate. As described above, the crystallinity evaluation using the Raman analysis is appropriately used to evaluate the crystal state of the semiconductor film formed in the region of the pixel TFT 105 and the region of the driving TFT 106, whereby the first of the first embodiment. In the film structures of the insulating film 31, the second insulating film 33, and the amorphous semiconductor film 5, the amorphous semiconductor film 51 and the amorphous semiconductor film 51 and An appropriate irradiation energy density capable of separately forming the microcrystalline semiconductor film 52 can be determined by trial and error.

  Next, the amorphous semiconductor film 6 and the amorphous semiconductor film 7 containing impurities are continuously formed on the amorphous semiconductor film 51 and the microcrystalline semiconductor film 52 which are separately formed as described above. Further, a metal film 9 is formed on the amorphous semiconductor film 7 containing impurities by sputtering. Subsequently, a third photolithography process is performed. In the third photolithography process, photoresists PR1 and PR2 having different film thicknesses as shown in the figure are formed using a known halftone mask (or slit mask, gray tone mask). Specifically, the thickness of the portion that becomes the channel region is relatively thin, and the thickness of the portion that becomes the source region and the drain region that are separated from each other on both sides of the portion that becomes the channel region is determined as the channel region. The film thicknesses of the photoresists PR1 and PR2 are both set so as to be thicker than the film thickness of the portion to be. The absolute value of the film thickness or the difference between the film thickness of the thick part and the thin part can be arbitrarily set according to the process condition to be selected. With the above process, the configuration shown in FIG.

Subsequently, the metal film 9 is etched using the photoresists PR1 and PR2 as a mask. Further, the amorphous semiconductor film 7 containing the impurities, the amorphous semiconductor film 6, and the amorphous semiconductor film 51 or the microcrystalline semiconductor film 52 are sequentially etched to be patterned into an island-like planar shape. A semiconductor film 51 and a microcrystalline semiconductor film 52; an amorphous semiconductor film 71 and an amorphous semiconductor film 61 containing impurities patterned in the same planar shape; and an amorphous semiconductor film 72 containing impurities An amorphous semiconductor film 62, a metal film 91, and a metal film 92 are obtained. Subsequently, by performing an ashing process by a plasma process using O ₂ gas, the photoresist in the thin part of the channel region is completely removed, and at the same time, a constant amount is left in the other thick part. Then, a thickness reduction process for removing the photoresists PR1 and PR2 is performed. As a result, new planar photoresists PR1 ′ and PR2 ′ arranged separately on both sides of the channel region are formed on the amorphous semiconductor film 71 and the amorphous semiconductor film 72 containing impurities, and further on the metal. Formed on films 91 and 92. With the above process, the configuration shown in FIG.

  Then, the metal film 91 (or 92) in the channel region and the amorphous semiconductor film 71 (or 72) containing impurities are etched by the new planar photoresists PR1 ′ and PR2 ′, as in the previous etching. By removing, the metal film 91 (or 92) and the amorphous semiconductor film 71 (or 72) are separated from each other on both sides of the channel region. In this way, in order to separate the metal film 91 (or 92) and the amorphous semiconductor film 71 (or 72) from each other on both sides of the channel region, the metal film 91 (or 92) in the channel region is, of course, non- It is necessary to completely remove the crystalline semiconductor film 71 (or 72). Since the amorphous semiconductor film 71 (or 72) can be reliably removed by etching, overetching is usually performed in consideration of a process margin when etching, and a part of the amorphous semiconductor film 61 (or 62) is obtained. Etching is performed until the film is removed. However, on the contrary, the amorphous semiconductor film 61 (or 62) functioning as a channel needs to remain, and is not etched at least completely. Since such an etching method is formed by partially etching the back side of the channel portion, it is called a back channel etch process. A TFT formed by using this method is a channel etch of an inverted staggered structure TFT, in particular. This is called a type TFT. As described above, the metal film 91 (or 92) and the amorphous semiconductor film 71 (or 72) in the channel region are removed, and the etching for removing a part of the amorphous semiconductor film 61 (or 62) is completed. Thereafter, the unnecessary photoresists PR1 ′ and PR2 ′ are removed. In this way, in common with the pixel TFT 105 and the driving TFT 106, the amorphous semiconductor film 61 (or 62) and the amorphous semiconductor film 71s containing impurities formed in two separate from each other (or 72s) and 71d (or 72d) are laminated, and an amorphous semiconductor layer 81s (or 82s) including impurities formed separately from each other. And a source electrode 91s (or 92s) and a drain electrode 91d (or 92d) formed in contact with 71d (or 72d), and a channel region sandwiched between them is formed. Thus, a structure including a mixture of an amorphous semiconductor TFT used for the pixel TFT 105 and a microcrystalline semiconductor TFT used for the driving TFT 106 shown in FIG. 2 is formed. In the first embodiment, as described above, the amorphous semiconductor film 51 and the amorphous semiconductor layer 81 are patterned in the same planar shape, and similarly, the microcrystalline semiconductor film 52 and the amorphous semiconductor layer are patterned. 82 adopts a structure patterned in the same planar shape, and in the third photolithography process, the formation of each semiconductor film and each semiconductor layer and the formation of the source electrode and the drain electrode are shared by using a half-tone mask. However, it goes without saying that the formation of each semiconductor film and each semiconductor layer, and the source electrode and the drain electrode may be performed by forming separate photoresists.

  Further, in the pixel 103 formed in the display region 101 shown in FIG. 1, for example, a silicon nitride film is formed as an insulating film, and a contact hole is formed in the insulating film on the drain electrode 91d by the fourth photolithography process. To do. Thereafter, for example, ITO is formed as a transparent conductive film on the insulating film by sputtering, and a pixel electrode is formed by a fifth photolithography process. In addition, the first to fifth photolithography processes and the etching processes described above are used to configure other than the pixel TFT 105 and the driving TFT 106 necessary for the completion of the array substrate 100, for example, the gate wiring 108 and the source wiring including the storage capacitor 107. 109, a storage capacitor wiring 110, an external wiring 111, an external terminal, and the like are formed at the same time. As described above, the array substrate 100 described with reference to FIG. 1 is formed.

  Note that in the array substrate 100 described above, the first insulating film 31 and the second insulating film 33 that contribute to the formation of the amorphous semiconductor film 51 and the microcrystalline semiconductor film 52 are the pixel TFT 105 and the driving TFT 106. The first gate insulating film 41 and the second gate insulating film 42 are configured, and the second gate insulating film 41 in the pixel TFT 105 is usually formed also as a capacitor insulating film of the storage capacitor 107. There are many. Accordingly, in order to provide an appropriate on characteristic, breakdown voltage characteristic, or appropriate capacitance value as a TFT, the thickness of the first insulating film 31 and the second insulating film 33 is adjusted as appropriate, or the first insulating film 33 You may change into the laminated structure which added the insulating film etc. separately below the film | membrane 31. FIG. It is sufficient that at least the structure of the lower layer in contact with the amorphous semiconductor film 5 is as described above. However, if such changes in the thickness of the first insulating film 31 and the second insulating film 33 or the configuration of layers below the first insulating film 31 are affected, heat propagation is affected. The appropriate laser irradiation energy density needs to be appropriately optimized in combination with the crystallinity evaluation using the Raman analysis described above. Note that these changes may narrow the range of the appropriate laser irradiation energy density as compared to the first embodiment.

  Next, a cell assembly process in the method for manufacturing a liquid crystal display device will be described with reference to FIG. FIG. 5 is a schematic plan view showing the configuration of the mother liquid crystal cell substrate 10 in the manufacturing process of the liquid crystal display device according to the first embodiment. Usually, when manufacturing a liquid crystal display device, a mother liquid crystal cell substrate in which a plurality of liquid crystal cell substrates 10a, 10b,..., 10n are partitioned and arranged in an array form as shown in FIG. 10, and the liquid crystal cell substrates 10 a, 10 b,..., 10 n are cut out from the mother liquid crystal cell substrate 10 to the size of each liquid crystal display panel unit. A liquid crystal display panel as shown in FIG. 1 is obtained. Therefore, in the method of manufacturing the array substrate 100 described above, it is possible to simultaneously manufacture a single mother array substrate 1a that is a large transparent insulating substrate in which a plurality of array substrates 100 are arranged in an array.

  In addition to the mother array substrate 1a manufactured by the method for manufacturing the array substrate 100, there is a mother counter substrate 1b arranged to face the mother array substrate 1a. The mother counter substrate 1b may be a CF substrate having a color resist (coloring material), a black matrix (BM), a counter electrode, and the like. After forming an alignment film on the surface of the mother array substrate 1a and the mother counter substrate 1b by a general method, the liquid crystal cell substrates 10a, 10b,. A seal pattern surrounding the corresponding liquid crystal sealing region is formed, and the mother array substrate 1a and the mother counter substrate 1b are bonded together. In this way, the mother liquid crystal cell substrate 10 shown in FIG. 5 is formed. In addition, the liquid crystal can be injected into the seal pattern by using a vacuum injection method in which vacuum is applied from the injection port after bonding, or liquid crystal is dropped into the seal pattern to simultaneously inject and bond the liquid crystal. A dropping method may be used. The liquid crystal cell substrate cutting step for cutting into individual liquid crystal display panel units is performed before liquid crystal injection in the case of the vacuum injection method, and is performed after liquid crystal injection in the case of the liquid crystal dropping method. In this way, the cell assembly process is completed, and individual liquid crystal cell substrates 10a, 10b,..., 10n are obtained.

  Finally, polarizing plates are attached to the outside of the individual array substrates 100 of the liquid crystal cell substrates 10a, 10b,. Further, in the external terminals of the array substrate 100, the counter substrate is cut so that the counter substrate is removed and exposed, and the IC chip 113 and the printed circuit board 112 are mounted on the exposed external terminals. As described above, the liquid crystal display panel shown in FIG. 1 is completed. Further, a backlight unit is disposed on the back side of the array substrate 100 on the opposite side of the liquid crystal display panel via an optical film such as a phase difference plate, and the liquid crystal display panel is placed in a frame made of resin or metal. And these peripheral members are stored appropriately, and the liquid crystal display device of the first embodiment is completed.

  As described above, in the liquid crystal display device according to the first embodiment, different TFTs such as the pixel TFT 105 and the driving TFT 106 can be formed on the substrate 1 at the same time. That is, the pixel TFT 105 is an amorphous semiconductor TFT in which the channel region includes the amorphous semiconductor film 51, and has optimum characteristics as a pixel TFT such that characteristic variation and leakage current are small. The driving TFT 106 is a crystalline semiconductor TFT having a microcrystalline semiconductor film 52 in the channel region, and can realize carrier mobility when the TFT is on, that is, sufficiently high field effect mobility. Furthermore, the defect level due to crystal defects is suppressed by crystallization, and the threshold voltage shift can be reduced. That is, a highly reliable TFT operation can be obtained, and since it has optimum characteristics as a driving TFT, it can be applied to a driving circuit, and the driving circuit can be integrated on the array substrate. By integrating the drive circuit and replacing it with an IC chip, it is possible to obtain effects such as reducing the amount of components, reducing the weight of the liquid crystal display device, and improving productivity during manufacturing. Further, the frame of the liquid crystal display device can be reduced (reduction in size per necessary display area). In addition, since the IC chip mounting process can be reduced, it is possible to improve productivity during manufacturing, including prevention of quality loss due to the occurrence of defective products. As described above, in the liquid crystal display device according to the first embodiment, it is possible to realize cost reduction and the like from such productivity improvement.

  Furthermore, in the liquid crystal display device and the manufacturing method thereof, or the method for crystallizing an amorphous semiconductor film in Embodiment Mode 1, the pixel TFT 105 and the driving TFT 106 have an underlayer at the time of crystallizing the semiconductor film by laser irradiation. By using a characteristic configuration for the gate insulating film of each TFT, a relatively simple laser processing method, that is, by uniformly irradiating the substrate with the same laser irradiation energy density, an amorphous state is obtained. It is possible to make the high-quality semiconductor film 51 and the microcrystalline semiconductor film 52 with high accuracy. Further, by using these as active layers of different TFTs, an amorphous semiconductor TFT and a microcrystalline semiconductor TFT can be separately formed, or a liquid crystal display device provided with a mixture of an amorphous semiconductor TFT and a microcrystalline semiconductor TFT Can be obtained. That is, a complicated laser processing method such as a method of changing conditions and positioning in the middle as in the prior art, or a method of selectively performing laser irradiation by a method through a mask that covers a part of the substrate is used. In addition, it is possible to obtain a liquid crystal display device in which an amorphous semiconductor TFT and a microcrystalline semiconductor TFT which are optimal in the pixel TFT 105 and the driving TFT 106 are mixed. As a result, it is possible to eliminate a design margin in consideration of the amount of misalignment in the distance between the pixel TFT 105 and the driving TFT 106, so that it is possible to achieve a narrow frame at the level required in recent liquid crystal display devices. Furthermore, when manufacturing a liquid crystal display device by manufacturing a plurality of array substrates from a single substrate such as the mother array substrate 1a of the first embodiment, an array substrate for each liquid crystal display device is used. On the other hand, it is not necessary to align the laser irradiation position, and the laser irradiation may be performed while moving the entire substrate. Therefore, the processing time can be shortened, that is, the productivity can be improved.

  In addition, since the microcrystalline semiconductor TFT serving as the driving TFT 106 included in the liquid crystal display device of Embodiment 1 is a TFT having an inverted stagger structure, as described above, during the crystallization process of the semiconductor film by laser irradiation. The structure of the insulating film that contributes to the formation of the amorphous semiconductor film 51 and the microcrystalline semiconductor film 52 as the underlying layer also functions as the gate insulating film 42 of the driving TFT 106. In the microcrystalline semiconductor TFT serving as the driving TFT 106, the gate insulating film 42 is constituted by the first insulating film 31 made of a silicon oxide film, and the surface layer on the microcrystalline semiconductor film 52 side is formed by a silicon oxide film. The channel region of the microcrystalline semiconductor film 52 is entirely formed of a microcrystalline silicon film. Accordingly, since the interface between the gate insulating film 42 and the crystalline semiconductor is formed by the microcrystalline silicon film and the silicon oxide film, charge accumulation at the interface is reduced, the threshold voltage is enhanced, and when a negative bias is applied. It is possible to suppress fluctuations in the threshold voltage such as shifting at. A similar effect is obtained when the crystalline semiconductor portion is formed of a crystalline silicon film at least in a portion where the gate insulating film 42 and the crystalline semiconductor portion are in contact with each other, and the gate insulating film 42 is formed of a silicon oxide film. For example, the gate insulating film 42 of the first embodiment can be obtained even if it is formed of a laminated film having another insulating film below the first insulating film 31 made of a silicon oxide film. it can.

  In addition, since the amorphous semiconductor TFT serving as the pixel TFT 105 included in the liquid crystal display device according to the first embodiment is also a TFT having an inverted stagger structure, as described above, the crystallization process of the semiconductor film by laser irradiation is performed. The structure of the insulating film that contributes to the formation of the amorphous semiconductor film 51 and the microcrystalline semiconductor film 52 as the underlying layer also functions as the gate insulating film 41 of the pixel TFT 105. In the amorphous semiconductor TFT serving as the pixel TFT 105, the gate insulating film 41 is composed of a laminated film of a first insulating film 31 made of a silicon oxide film and a second insulating film 33 made of a silicon nitride film, A surface layer on the amorphous semiconductor film 51 side is formed of a silicon nitride film, and a channel region of the amorphous semiconductor film 51 is formed of an amorphous silicon film. Therefore, since the interface between the gate insulating film 41 and the amorphous semiconductor is formed by the amorphous silicon film and the silicon nitride film, the charge accumulation at the interface is reduced and the shift to the depletion side. Variation in threshold voltage can be suppressed. A similar effect is that the amorphous semiconductor film 51 is formed of an amorphous silicon film at least in a portion where the gate insulating film 41 and the amorphous semiconductor film 51 are in contact, and the gate insulating film 41 is formed of a silicon nitride film. For example, in the gate insulating film 41 of the first embodiment, the second insulating film 33 made of a silicon nitride film or the lower layer of the first insulating film 31 made of a silicon oxide film can be obtained. Further, it can be obtained even if it is formed of a laminated film having another insulating film.

  As described above, the configuration of the gate insulating film 42 in the microcrystalline semiconductor TFT serving as the driving TFT 106 included in the liquid crystal display device of the first embodiment and the configuration of the gate insulating film 41 in the amorphous semiconductor TFT serving as the pixel TFT 105. This contributes to the formation of the amorphous semiconductor film 51 and the microcrystalline semiconductor film 52, and at the same time, is effective in terms of TFT characteristics that the fluctuation of the threshold voltage of the microcrystalline semiconductor TFT and the amorphous semiconductor TFT can be suppressed. Demonstrate.

  As described above, the configuration of the gate insulating film 41 and the gate insulating film 42 in the pixel TFT 105 and the driving TFT 106 in the first embodiment can minimize the number of photolithography processes, and further the gate insulating film 41 and the gate insulating film. Etching (processing) for forming a silicon nitride film partially on the silicon oxide film for obtaining the structure of the film 42 is facilitated, and the amorphous semiconductor film 51 and the microcrystalline semiconductor film 52 are separately formed. It contributes in a complex way to what is possible. On the other hand, a relatively thick silicon oxide film is formed under the amorphous semiconductor film in a portion where the microcrystalline semiconductor film 52 is to be formed, and the amorphous semiconductor film 51 in the portion where the amorphous semiconductor film 51 is desired to be maintained. If a silicon nitride film is formed in the lower layer, the amorphous semiconductor film 51 and the microcrystalline semiconductor film 52 can be separately formed under the same laser irradiation conditions. For example, a configuration of a silicon nitride film and a silicon oxide film On the other hand, the first insulating film 31 as a lower layer may be a silicon nitride film, and the second insulating film 33 to be partially formed may be a silicon oxide film. However, in the configuration in which the first insulating film 31 as the lower layer is a silicon nitride film and the second insulating film 33 to be partially formed is a silicon oxide film, the following various problems occur. Hereinafter, a problem that occurs will be described in detail by using a configuration in which the configurations of the silicon nitride film and the silicon oxide film are reversed as a comparative example with respect to the configuration of the first embodiment.

  First, since it is effective to make the amorphous semiconductor film 51 and the microcrystalline semiconductor film 52 relatively thicker, it is effective to make the thickness of the silicon oxide film where the microcrystalline semiconductor film 52 is to be formed relatively thick. It is assumed that the silicon oxide film as the second insulating film 33 to be formed is, for example, 100 nm or more. The etching rate of the first insulating film 31 made of the silicon nitride film as a lower layer is higher than the etching for partially removing the silicon oxide film, but the silicon oxide film formed relatively thick is used. In this case, the first insulating film 31 as the lower layer may be lost due to the etching of the silicon oxide film, and even if it can be left, it is difficult to control the remaining film thickness. Since the first insulating film 31 made of the silicon nitride film is used as the gate insulating film 41 of the pixel TFT 105 which is a single layer amorphous semiconductor TFT, it is realistic in terms of reliability and characteristic variation. It becomes difficult to adopt. Further, by making the first insulating film 31 made of a silicon nitride film much thicker than the second insulating film 33 made of a silicon oxide film, these problems caused by etching can be alleviated. However, in this method, the ON characteristic is deteriorated due to the thick gate insulating film 41 of the pixel TFT 105. Further, in the crystalline semiconductor TFT using the microcrystalline semiconductor film 52, the laminated film of the first insulating film 31 and the second insulating film 33 is used as the gate insulating film 42, and therefore, particularly on characteristics. As a result, the use of the TFT as a driving TFT is hindered.

Conversely, when the thickness of the silicon oxide film as the second insulating film 33 is reduced so as to facilitate etching, for example, when it is set to 100 nm or less, the first insulating film 31 and the second insulating film 33 are formed. The laser irradiation energy density necessary for converting the amorphous semiconductor film 5 on the insulating film into a microcrystalline state overlaps 220 to 230 mJ / cm ² , and the amorphous semiconductor film 51 and the microcrystal It becomes impossible to make the semiconductor film 52 separately. Since the above problems occur, the first insulating film 31 as a lower layer, which is a comparative example of the configuration of the first embodiment, is a silicon nitride film, and the second insulating film 33 that is partially formed is silicon oxide. Whatever method is used, the film structure is a structure obtained by forming the amorphous semiconductor film 51 and the microcrystalline semiconductor film 52 and the first insulating film 31 and the second insulating film 33. The use of the pixel TFT 105 made of an amorphous semiconductor TFT used as a gate insulating film and the driving TFT 106 made of a crystalline semiconductor TFT cannot be compatible, and is not appropriate.

Embodiment 2. FIG.
In the description of the first embodiment described above, in the microcrystalline semiconductor TFT serving as the driving TFT 106, the gate insulating film 42 is configured by the first insulating film 31 made of a silicon oxide film, and the pixel TFT 105 In the amorphous semiconductor TFT to be formed, the gate insulating film 41 is composed of a laminated film of a first insulating film 31 made of a silicon oxide film and a second insulating film 33 made of a partially formed silicon nitride film. As a comparative example, the first insulating film 31 is a silicon nitride film, and the partially formed second insulating film 33 is a silicon oxide film as a comparative example. We explained the problem that occurred in. Subsequently, as another embodiment of the present invention, a gate oxide film of a microcrystalline semiconductor TFT and an amorphous semiconductor TFT is formed of a silicon oxide film and a silicon nitride film from the liquid crystal display device of Embodiment 1, respectively. The liquid crystal display device according to the second embodiment, which is modified by a single layer film, will be described. Note that the difference from the first embodiment is that the gate insulating film of the microcrystalline semiconductor TFT and the amorphous semiconductor TFT of the structure of the array substrate, that is, the semiconductor film that becomes the active layer of each TFT is made differently. Therefore, only the structure of the underlying film of the semiconductor film, which is the main point, is the structure of the gate insulating film, which is the underlying film of the semiconductor film, the formation method thereof, and the semiconductor film which is the active layer of the TFT. The process and the effect obtained by the deformation will be described focusing on the differences from the first embodiment.

  First, the configuration of the liquid crystal display device according to Embodiment 2 of the present invention will be described. FIG. 6 is an example of an amorphous semiconductor TFT used for the pixel TFT 105a and a crystalline semiconductor TFT used for the driving TFT 106a disposed on the array substrate 100a in the liquid crystal display device according to Embodiment 2 of the present invention. It is sectional drawing which shows the structure of a microcrystal semiconductor TFT. The TFT used in the liquid crystal display device of the second embodiment is also a reverse staggered TFT as in the first embodiment. Hereinafter, the configuration of the array substrate 100a of the liquid crystal display device according to the second embodiment of the present invention will be described with reference to FIG. Constituent elements that are the same as those of the array substrate 100 according to the first embodiment described with reference to FIG. As shown in FIG. 6, in the array substrate 100a of the second embodiment, as in the array substrate 100 of the first embodiment, the pixel TFT 105a is formed on the substrate 1 made of a transparent insulating substrate such as glass. The microcrystalline semiconductor that becomes the driving TFT 106a for the region where the TFT is formed and the region where the driving TFT 106a is formed (the region is indicated by the dotted brackets and the reference numerals of the TFTs) A gate electrode 22 which is a first gate electrode constituting the TFT and a gate electrode 21 which is a second gate electrode constituting the amorphous semiconductor TFT serving as the pixel TFT 105a are formed.

  In the array substrate 100a of the second embodiment, as shown in FIG. 6, silicon nitride is formed on the substrate 1 including the gate electrode 21 so as to cover the gate electrode 21 in the region where the pixel TFT 105a is formed. A second insulating film 33 made of a film is partially formed. In other words, an opening 34 is formed in the second insulating film 33 made of a silicon nitride film in a region including at least the gate electrode 22 in a region where the driving TFT 106a is formed. On the other hand, in the region where the driving TFT 106 a is formed, a first insulating film 31 a made of a silicon oxide film is partially formed on the substrate 1 including the gate electrode 22 so as to cover the gate electrode 22. In other words, in the first insulating film 31a made of the silicon oxide film, the opening 35 is formed in a region including at least the gate electrode 21 in the region where the pixel TFT 105a is formed. As described for the opening 34 in the first embodiment, the opening 34 or the opening 35 in the second embodiment is particularly an opening surrounded by the second insulating film 33 or the first insulating film 31a. The second insulating film 33 or the first insulating film 31a that is partially formed is not formed, that is, the entire region that is not covered by the second insulating film 33 or the first insulating film 31a is not formed. Applicable. With the above configuration, in the microcrystalline semiconductor TFT serving as the driving TFT 106a, the gate insulating film 42 is configured by a single layer film of the first insulating film 31a made of a silicon oxide film, and the amorphous semiconductor serving as the pixel TFT 105a. In the TFT, the gate insulating film 43 is composed of a single layer film of the second insulating film 33 made of a silicon nitride film.

  Further, as shown in FIG. 6, an amorphous semiconductor film 51 which is an active layer of the pixel TFT 105a is formed in direct contact with the surface of the second insulating film 33 made of a silicon nitride film which is the gate insulating film 43 of the pixel TFT 105a. Then, the microcrystalline semiconductor film 52 serving as the active layer of the driving TFT 106a is in direct contact with the surface of the first insulating film 31a made of the silicon oxide film which is the gate insulating film 42 in the region where the driving TFT 106a is formed. It is formed. In other words, the amorphous semiconductor film 51 is formed in direct contact with the surface of the second insulating film 33 in the region covered with the second insulating film 33 and is not covered with the second insulating film 33. On the surface of the first insulating film 31a in the region 34, a microcrystalline semiconductor film 52 is formed in direct contact. In addition, as in the first embodiment, an amorphous semiconductor film 61 (or 62) formed on the amorphous semiconductor film 51 or the microcrystalline semiconductor film 52, respectively, and two impurities formed separately from each other The structure of the amorphous semiconductor layer 81 (or 82) formed by laminating the amorphous semiconductor film 71s (or 72s) or 71d (or 72d) including the source electrode 91s (or 92s) and the drain The pixel TFT 105a or the driving TFT 106a of Embodiment 2 is configured by the electrode 91d (or 92d) or the like.

  Next, a method for manufacturing a liquid crystal display device according to Embodiment 2 of the present invention will be described with reference to FIG. Here, first, a method of forming the first insulating film 31a made of a partially formed silicon oxide film and the second insulating film 33 made of a silicon nitride film, which is different from the first embodiment, will be described. Do. In the second embodiment, as described using the comparative example in the description of the first embodiment, when performing etching for partially removing the silicon oxide film formed on the silicon nitride film, Since the problem that the resulting silicon nitride film is scraped away or the control of the remaining film thickness becomes difficult occurs, the silicon oxide film is formed first as in the first embodiment. Thereafter, the silicon oxide film is patterned to form a first insulating film 31a partially made of a silicon oxide film in the pixel TFT 105 region, and subsequently, a silicon nitride film 32 is formed, whereby FIG. Can be obtained. Further, by patterning the silicon nitride film 32, a second insulating film 33 made of a silicon nitride film is partially formed in the driving TFT 106a region. In this manner, as compared with the first embodiment, the first insulating film 31a partially made of a silicon oxide film is formed and the number of photolithography processes is increased by one, so that the region of the pixel TFT 105a is made of a silicon oxide film. The first gate insulating film 42 is formed from the single layer film of the first insulating film 31a, and the second gate insulating film is formed in the driving TFT 106a region from the single layer film of the second insulating film 33 formed of the silicon nitride film. 43 can be formed respectively.

  Then, the region of the opening 34 formed as described above is not covered with the second insulating film 33, and the first insulating film 31a is the surface layer, and the other second insulating film 33 covers the region. As in the first embodiment, the first insulating film 31a and the second insulating film 33 are formed on the substrate 1 on which the base film structure including the region where the second insulating film 33 is a surface layer is formed. The amorphous semiconductor film 5 is formed over substantially the entire surface of the substrate 1 in contact with the surface of each insulating film, whereby the structure shown in FIG. Subsequently, after performing pre-processing such as dehydrogenation processing and natural oxide film removal processing similar to those of the first embodiment on the amorphous semiconductor film 5, the amorphous semiconductor film 5 is irradiated with the laser beam LB. An annealing process is performed. By this annealing step, the amorphous semiconductor film 5 is converted into a microcrystalline semiconductor film 52 in a region in contact with the surface of the first insulating film 31a made of a silicon oxide film, and the second insulating film 33 made of a silicon nitride film. In the region in contact with the surface, the amorphous semiconductor film 51 is maintained in an amorphous state, and the structure shown in FIG. That is, in the same manner as in the first embodiment, the laser beam LB is continuously irradiated to the entire substrate 1 under the same irradiation conditions, particularly at the same irradiation energy density, and from the amorphous semiconductor film 5. A region to be converted into the microcrystalline semiconductor film 52 and a region to be the amorphous semiconductor film 51 maintained in an amorphous state can be separately formed. Note that the amorphous semiconductor film 5 in contact with the surface of the first insulating film 31a made of a silicon oxide film and the region in contact with the surface of the second insulating film 33 made of a silicon nitride film are microcrystalline. Since there is a large difference in the laser irradiation energy density required for the conversion to the state, the operation of making different use of the microcrystalline semiconductor film 52 and the amorphous semiconductor film 51 is the same as in the first embodiment. Then, detailed description is abbreviate | omitted. Further, the subsequent steps may be the same as those in the first embodiment, and thus the description thereof will be omitted. However, by using the same manufacturing method as that in the first embodiment, the array substrate according to the second embodiment in FIG. The configuration of 100a and the liquid crystal display device of the second embodiment can be obtained.

  As described above, the configuration of the gate insulating film 42 in the microcrystalline semiconductor TFT serving as the driving TFT 106a included in the liquid crystal display device of the second embodiment and the configuration of the gate insulating film 43 in the amorphous semiconductor TFT serving as the pixel TFT 105a. As in the first embodiment, in the microcrystalline semiconductor TFT, the microcrystalline semiconductor film 52 serving as the active layer of the TFT is formed on the surface of the first insulating film 31a made of the silicon oxide film in direct contact with the first insulating film 31a. In the crystalline semiconductor TFT, since the amorphous semiconductor film 51 serving as an active layer of the TFT is formed in direct contact with the surface of the second insulating film 33 made of a silicon nitride film, the liquid crystal according to the first embodiment. Similar to the display device, it contributes to the formation of the amorphous semiconductor film 51 and the microcrystalline semiconductor film 52, and at the same time, changes in the threshold voltage of the microcrystalline semiconductor TFT and the amorphous semiconductor TFT. Also effective in TFT characteristics aspect of being able to suppress.

  Further, by using the manufacturing method of the second embodiment described above, the gate insulating film 43 made of a single layer film of the second insulating film 33 made of a silicon nitride film is shaved and thinned, and the film thickness varies. In addition, the gate insulating film 42 made of a single layer film of the first insulating film 31a made of a silicon oxide film is thickened to a thickness optimized for the formation of the amorphous semiconductor film 51 and the microcrystalline semiconductor film 52. In the same manner as in the first embodiment, the structure obtained by forming the amorphous semiconductor film 51 and the microcrystalline semiconductor film 52 and the first insulating film 31a and the second insulating film 33 is the same as the gate insulating film. The pixel TFT 105a made of an amorphous semiconductor TFT and the driving TFT 106a made of a crystalline semiconductor TFT can be used at the same time. Furthermore, in the liquid crystal display device according to the second embodiment of the present invention, the gate insulating film 43 in the pixel TFT 105a region is configured by a single layer film of the second insulating film 33 made of a silicon nitride film, so that the pixel TFT 105a region, The transmittance can be increased in the display area 101 (not shown). That is, a suitable configuration can be obtained for a semiconductor device such as a transmissive liquid crystal display device that generally requires high transmittance.

Embodiment 3 FIG.
Next, a liquid crystal display device according to a third embodiment will be described as another embodiment of the present invention. The difference between the liquid crystal display device according to the third embodiment and the first embodiment is that, in the first embodiment, the opening formed in the second insulating film 33 made of a silicon nitride film in the region where the driving TFT 106 is formed. The portion 34 is changed to the opening 36 formed only in the channel region of the driving TFT 106b in the configuration of the driving TFT 106b of the third embodiment, and the semiconductor film that becomes the active layer of the driving TFT 106b is replaced with the crystalline portion. This is a microcrystalline semiconductor TFT formed with two different regions of an amorphous part. Therefore, this gate insulating film, which is the base film of the semiconductor film, the structure of the semiconductor film having two different regions, the crystalline part and the amorphous part, and the structure of these parts are formed. The formation method and the effects obtained by the deformation will be described with a focus on differences from the first embodiment.

  First, the configuration of the liquid crystal display device according to the third embodiment of the present invention will be described. FIG. 8 is an example of an amorphous semiconductor TFT used for the pixel TFT 105b and a crystalline semiconductor TFT used for the driving TFT 106b disposed on the array substrate 100b in the liquid crystal display device according to Embodiment 3 of the present invention. It is sectional drawing which shows the structure of a microcrystal semiconductor TFT. The TFT used in the liquid crystal display device of the third embodiment is also a reverse staggered TFT as in the first embodiment. Hereinafter, the configuration of the array substrate 100b of the liquid crystal display device according to Embodiment 3 of the present invention will be described with reference to FIG. Constituent elements that are the same as those of the array substrate 100 according to the first embodiment described with reference to FIG. As shown in FIG. 8, in the array substrate 100b according to the third embodiment, like the array substrate 100 according to the first embodiment, the pixel TFT 105b is formed on the substrate 1 made of a transparent insulating substrate such as glass. The microcrystalline semiconductor to be the driving TFT 106b for the region where the TFT is formed and the region where the driving TFT 106b is formed (the region is indicated by the reference numerals of the TFTs corresponding to the curly brackets indicated by dotted lines) A gate electrode 22 that is a first gate electrode constituting the TFT and a gate electrode 21 that is a second gate electrode constituting the amorphous semiconductor TFT serving as the pixel TFT 105b are formed.

  As shown in FIG. 8, in the array substrate 100b of the third embodiment, the first substrate made of a silicon oxide film is formed on the substrate 1 including the gate electrodes 21, 22 so as to cover the gate electrodes 21, 22. An insulating film 31 is formed. Further, a silicon nitride film is formed as the second insulating film 33 that partially covers the first insulating film 31. In other words, the opening 36 is formed in the second insulating film 33 made of a silicon nitride film. Further, the opening 36 formed in the second insulating film 33 is formed in a region including at least the gate electrode 22 in a region where the driving TFT 106b is formed, that is, in a channel region of the driving TFT 106b. With the above structure, the first gate insulating film 44 which is a gate insulating film constituting the microcrystalline semiconductor TFT serving as the driving TFT 106b includes the first insulating film 31 made of a silicon oxide film and the gate electrode 22. A second gate insulating film 41, which is a gate insulating film that is formed of a laminated film of the first insulating film 31 and the second insulating film 33 in the portion covering the end face and constitutes the amorphous semiconductor TFT serving as the pixel TFT 105b, The first insulating film 31 is made of a silicon oxide film and the second insulating film 33 is made of a silicon nitride film.

  Further, in the region where the pixel TFT 105 b is formed, the amorphous semiconductor film 51 is formed in direct contact with the surface of the second insulating film 33 in the region covered with the second insulating film 33. On the other hand, in the region where the driving TFT 106b is formed, the first insulating film 31 is a surface layer in the region of the opening 36 formed in the second insulating film 33 that is not covered by the second insulating film 33. On the surface of the first insulating film 31 in the region of the opening 36, that is, the channel region of the driving TFT 106b, a microcrystalline semiconductor film 52 serving as an active layer of the TFT is formed in direct contact. Further, in the region covered with the second insulating film 33 other than the opening 36, the second insulating film 33 becomes the surface layer similarly to the region where the pixel TFT 105b is formed. An amorphous semiconductor film 51 is formed in direct contact with the surface of the insulating film 33. As described above, the semiconductor film 53 which is an active layer of the driving TFT 106b has a structure in which the amorphous semiconductor film 51 and the microcrystalline semiconductor film 52 each including the microcrystalline semiconductor film 52 are mixed only in the channel region. In addition, as in the first embodiment, the amorphous semiconductor film 51 (or 62) formed on the amorphous semiconductor film 51 or the semiconductor film 53 and the impurity formed separately from each other are included. The structure of the amorphous semiconductor layer 81 (or 82) configured by laminating the amorphous semiconductor films 71s (or 72s) and 71d (or 72d), the source electrode 91s (or 92s), and the drain electrode 91d. (Or 92d) or the like constitutes the pixel TFT 105b or the driving TFT 106b of the third embodiment.

  As described above, the configuration of the amorphous semiconductor TFT serving as the pixel TFT 105b is not different from the configuration of the amorphous semiconductor TFT serving as the pixel TFT 105 of Embodiment 1, but the configuration of the microcrystalline semiconductor TFT serving as the driving TFT 106b. The semiconductor film 53 which is an active layer is in contact with the surface of the first insulating film 31 through the opening 36 of the second insulating film 33 only in the channel region, and a microcrystalline semiconductor film 52 made of a crystalline portion is formed. In the source region and the drain region, an amorphous semiconductor film 51 made of an amorphous portion is formed in contact with the surface of the second insulating film, and has two different regions of a crystalline portion and an amorphous portion. Is formed. That is, the microcrystalline semiconductor TFT has the microcrystalline semiconductor film 52 only in the channel region and the amorphous semiconductor film 51 in the source region and the drain region. Further, the semiconductor film 53 as an active layer and the amorphous semiconductor layer 82 are patterned in the same planar shape. Further, a source electrode 92s and a drain electrode 92d are formed in contact with the amorphous semiconductor films 72s and 72d containing impurities. As a result, the source electrode 92s and the drain electrode 92d are formed in contact with the semiconductor film 53 at the end face of the semiconductor film 53, and at least the semiconductor film 53 in the region having the end face in contact with the source electrode 92s or the drain electrode 92d is amorphous. The amorphous semiconductor film 51 is made of a material portion.

  Next, a method for manufacturing a liquid crystal display device according to Embodiment 3 of the present invention will be described with reference to FIG. Here, first, the first insulating film 31 made of a silicon oxide film and the second insulating film 33 made of a silicon nitride film and partially covering the first insulating film 31 are different from the first embodiment. The formation method will be described. In the third embodiment, the first made of a silicon oxide film is formed on the substrate 1 including the gate electrodes 21 and 22 formed on the substrate 1 made of a transparent insulating substrate, as in the first embodiment. The second insulating film 33 made of a silicon nitride film having an opening 36 and partially covering the first insulating film 31 is formed. As described above, the opening 36 formed in the second insulating film 33 made of the silicon nitride film of the third embodiment is formed in a portion where the channel region of the driving TFT 106b on the gate electrode 22 is formed. ing. On the other hand, the second insulating film 33 is formed in a region excluding a portion where the channel region of the driving TFT 106b on the gate electrode 22 is formed. Note that the opening 36 is different from the opening 34 described in Embodiment 1 only in the region where the opening 36 is formed, and this silicon nitride film is etched to form the second insulating film 33 having the opening. Since the process may be the same as in the first embodiment, detailed description thereof is omitted. Through the above steps, as shown in FIG. 9A, the first insulating film 31 made of a silicon oxide film and the first insulating film 31 made of a silicon oxide film are covered on the gate electrode 22 of the driving TFT 106b. A first gate insulating film 44 composed of a laminated film of the insulating film 31 and the second insulating film 33 is formed on the second gate electrode 21 of the pixel TFT 105b. And a second gate insulating film 41 composed of a laminated film of a silicon nitride film and a second insulating film 33 are formed.

  As described above, the second insulating film 33 that is not covered by the second insulating film 33 that is the region of the opening 36 and the first insulating film 31 that is the surface layer and the other second insulating film 33 that is covered by the second insulating film 33. As in the first embodiment, the first insulating film 31 and the second insulating film 33 are formed on the substrate 1 formed of the transparent insulating substrate on which the base film having the region where the insulating film 33 is the surface layer is formed. An amorphous semiconductor film 5 (not shown) is formed over substantially the entire surface of the substrate 1 in contact with the surface of each of the insulating films 33. Subsequently, after pre-processing such as dehydrogenation processing and natural oxide film removal processing similar to those of the first embodiment is performed on the amorphous semiconductor film 5, the amorphous semiconductor film 5 is irradiated with the laser beam LB. An annealing process is performed. By this annealing process, the amorphous semiconductor film 5 is converted into the microcrystalline semiconductor film 52 in the region of the opening 36 in contact with the surface of the first insulating film 31 made of a silicon oxide film, and from other silicon nitride films. In the region to be the surface of the second insulating film 33, the amorphous semiconductor film 51 is maintained in an amorphous state, and the structure shown in FIG. 9B is obtained. That is, in the same manner as in the first embodiment, the laser beam LB is continuously irradiated to the entire substrate 1 under the same irradiation conditions, particularly at the same irradiation energy density, and from the amorphous semiconductor film 5. A region to be converted into the microcrystalline semiconductor film 52 and a region to be the amorphous semiconductor film 51 maintained in an amorphous state can be separately formed. Note that the amorphous semiconductor film 5 in contact with the surface of the first insulating film 31 made of a silicon oxide film and the region in contact with the surface of the second insulating film 33 made of a silicon nitride film are microcrystalline. Since there is a large difference in the laser irradiation energy density required for the conversion to the state, the operation of making different use of the microcrystalline semiconductor film 52 and the amorphous semiconductor film 51 is the same as in the first embodiment. Then, detailed description is abbreviate | omitted. Further, the subsequent steps may be the same as those in the first embodiment, and thus the description thereof will be omitted. However, by using the same manufacturing method as that in the first embodiment, the array substrate of the third embodiment in FIG. The configuration of 100b and the liquid crystal display device of the third embodiment can be obtained.

  As described above, the configuration of the gate insulating film 44 in the microcrystalline semiconductor TFT serving as the driving TFT 106b included in the liquid crystal display device of Embodiment 3 and the configuration of the gate insulating film 41 in the amorphous semiconductor TFT serving as the pixel TFT 105b. As in the first embodiment, in the microcrystalline semiconductor TFT, the microcrystalline semiconductor film 52 serving as the active layer of the TFT is formed on the surface of the first insulating film 31 made of the silicon oxide film in direct contact with the non-crystalline semiconductor TFT. In the crystalline semiconductor TFT, since the amorphous semiconductor film 51 serving as an active layer of the TFT is formed in direct contact with the surface of the second insulating film 33 made of a silicon nitride film, the liquid crystal according to the first embodiment. Similar to the display device, it contributes to the formation of the amorphous semiconductor film 51 and the microcrystalline semiconductor film 52 at the same time, and at the same time, the threshold voltage variation of the microcrystalline semiconductor TFT and the amorphous semiconductor TFT. Also effective in TFT characteristics surfaces that can be suppressed.

  In addition, the microcrystalline semiconductor TFT constituting the driving TFT 106b of the third embodiment described above is formed by forming the microcrystalline semiconductor film 52 only in the channel region of the semiconductor film 53, thereby forming an amorphous semiconductor composed of an amorphous portion. A TFT in which the film 51 and the microcrystalline semiconductor film 52 including a crystalline portion are mixed in one semiconductor layer is realized. Further, the channel region in the semiconductor film 53 to be an active layer, that is, the region including at least a part between the region under the source electrode 92s and the region under the drain electrode 92d is constituted by the microcrystalline semiconductor film 52 which is a crystalline portion. This region is composed of an amorphous semiconductor film 51 made of an amorphous portion. With such a structure, in at least a part of a path through which an on-current flows as a TFT, a current is generated by a semiconductor film having higher mobility than the amorphous semiconductor film or lower on-resistance than the amorphous semiconductor film. As a result, a TFT having better on-characteristics than a general amorphous semiconductor TFT in which the semiconductor film 53 as an active layer is entirely made of an amorphous semiconductor film 51 can be obtained.

  In addition, the microcrystalline semiconductor TFT constituting the driving TFT 106b of the third embodiment employs a structure in which the semiconductor film 53 and the amorphous semiconductor layer 82 are patterned in the same planar shape. This is a low-cost structure that is advantageous for simplifying the photoresist formation process using tones. On the other hand, the structure in which the semiconductor film 53 and the amorphous semiconductor layer 82 are patterned in the same planar shape cannot avoid the semiconductor film 53 being in contact with the source electrode 92s and the drain electrode 92d. In this manner, when all of the semiconductor film 53 serving as an active layer is formed of the microcrystalline semiconductor film 52, the leakage current through the semiconductor film 53 including the microcrystalline semiconductor film 52 is likely to increase. However, in the present third embodiment, the semiconductor film 53 is changed to the amorphous semiconductor film 51 made of an amorphous part in the region having end faces in contact with the source electrode 92s and the drain electrode 92d, so that the source electrode 92s and The drain electrode 92d is formed without being in contact with the microcrystalline semiconductor film 52. As a result, a leakage current generated by movement of holes in the semiconductor film 53 generated when a negative voltage that is reverse biased is applied to the gate electrode 22 or when backlight light is irradiated during image display. On the other hand, the amorphous semiconductor film 51 in contact with the source electrode 92s and the drain electrode 92d serves as a barrier for hole movement between the source electrode 92s and the drain electrode 92d, and the occurrence of a leakage current can be prevented. As a result, in the microcrystalline semiconductor TFT constituting the driving TFT 106b of the third embodiment, it is possible to realize both a TFT having a good on characteristic and a TFT having a low off current at a low manufacturing cost.

  Note that the opening 36 formed in the second insulating film 33 only needs to have the opening 36 in at least the channel region, that is, the region including the gate electrode 22, and is in contact with the source electrode 92s or the drain electrode 92d. The opening 36 is preferably formed inside the end surface of the semiconductor film 53 so that the semiconductor film 53 in the region having the end surface becomes the amorphous semiconductor film 51. However, as in the third embodiment, the opening 36 is formed on the inner side of the end surface of the gate electrode 22, that is, the first insulating film 31 and the second insulating film are formed in a portion covering the end surface of the gate electrode 22. When the driving TFT 106b is configured by the stacked film of the film 33, the gate insulating film 44 is configured by the single-layer film of the first insulating film 31 having a small thickness in the channel region, so that the ON characteristic is enhanced. At the same time, since the gate insulating film 44 is formed of the laminated film at the stepped portion of the end face of the gate electrode 22 that is relatively susceptible to dielectric breakdown, a configuration that is strong against dielectric breakdown and has a high breakdown voltage can be obtained. .

  In the third embodiment, an application example to a configuration including a mixture of amorphous semiconductor TFTs and microcrystalline semiconductor TFTs as in the first and second embodiments has been described. The structure of the microcrystalline semiconductor TFT in which the semiconductor film 53 which is an active layer described here is formed with two different regions of a crystalline portion and an amorphous portion has a high on characteristic, a low leakage current, Furthermore, since it is an excellent TFT capable of obtaining various effects such as cost reduction, it can be used alone and can be applied to various semiconductor devices and display devices. Further, as described above, since an effect of obtaining a high on-state characteristic and a low leakage current is obtained, when applied to a liquid crystal display device as in the third embodiment, not only the driving TFT 106b, The present invention may be applied in common to both the driving TFT 106b and the pixel TFT 105b. In addition, since a leakage current due to backlight light during image display can be effectively reduced, it is particularly effective as a TFT for a transmissive liquid crystal display device using a backlight.

In addition, the structure including the amorphous semiconductor TFT and the crystalline semiconductor TFT described in Embodiment Mode 1, Embodiment Mode 2, and Embodiment Mode 3 is combined with this configuration as a basic configuration. by varying the structure appropriately, not limited to the liquid crystal display device, an organic EL (E lectro L uminescence) display device, other display devices, and can be applied to a semiconductor device such as an imaging device, the first embodiment and, The same effects as those obtained by the configuration including the mixed amorphous semiconductor TFT and crystalline semiconductor TFT described in the suggested modification can be obtained. In these cases, the crystalline semiconductor TFT can be applied to a drive circuit that drives various elements as long as it is a TFT constituting a drive circuit, and can also be applied to a TFT that constitutes a digitally operated logic circuit. . When applied to any circuit, it can operate at high speed without increasing the circuit area, and can prevent the increase in the size and cost of the display device or semiconductor device such as the need for a new IC chip. The effect similar to the form 1 and its modification can be obtained.

  When the structure including the amorphous semiconductor TFT and the crystalline semiconductor TFT of the present invention mixed as described above is applied to an organic EL display device, the pixel TFT 105 formed of the amorphous semiconductor TFT is used. , 105a, and 105b function as switching elements for controlling on / off of supply of a display voltage for controlling the amount of light that is viewed as an image by driving the liquid crystal in the liquid crystal display device. In the case of an organic EL display device, for example, in the case of an organic EL display device, the amount of light that is supplied to the organic light emitting layer and is visually recognized as an image is controlled. A transistor provided for each pixel that supplies display current to be used as a pixel TFT may be formed of an amorphous semiconductor TFT. . In any case, by supplying a display voltage or display current that directly contributes to the amount of light visually recognized as an image by the amorphous semiconductor TFT, variations in TFT characteristics can be easily reduced, and display unevenness can be suppressed. Become.

  In the first embodiment, the second embodiment, and the third embodiment, the entire substrate 1 is continuously irradiated with the laser beam LB to the amorphous semiconductor film 5 at the same irradiation energy density. The microcrystalline semiconductor film 52 formed by heating and melting is selectively formed using the difference in the heat propagation due to the difference in the structure of the insulating film below the amorphous semiconductor film 5, and the amorphous semiconductor film 5 is amorphous. A method capable of separately forming the crystalline semiconductor film 51 and the microcrystalline semiconductor film 52 has been described. If the entire substrate 1 can be irradiated under the same irradiation conditions, particularly at the same irradiation energy density, the degree of heating using the difference in heat propagation due to the difference in the structure of the insulating film below the amorphous semiconductor film 5 And the amorphous semiconductor film 51 and the microcrystalline semiconductor film 52 can be formed separately. Therefore, the energy beam is not limited to laser light, and may be any energy beam that is absorbed by at least the amorphous semiconductor film 51 or the silicon oxide film and heated, and such an energy beam is used under the same irradiation conditions, particularly the same irradiation energy density. Irradiation may be performed by continuously scanning with. Note that “continuous under the same irradiation conditions” here does not consider irradiation conditions due to in-plane distribution, temporal fluctuations on the irradiation apparatus side, or variations in irradiation energy density when scanning the inside of the substrate. is there. In particular, it means continuous irradiation without making intended changes to conditions such as settings on the device side and distance to the substrate, and the effect of reducing work and processing time such as condition changes can be obtained. The effect can be obtained without causing the problem of alignment accuracy as in the case of selective irradiation by changing the laser irradiation position.

  Further, as another method capable of irradiating the entire substrate 1 with the same irradiation energy density, the beam region can be expanded over the entire substrate 1 other than the method of continuously scanning the energy beam under the same conditions. If present, the entire substrate 1 may be irradiated with an energy beam uniformly. For example, you may use the RTA method which can irradiate the said substrate 1 whole with the energy beam which consists of optical energy uniformly. Even when the RTA method is used, the energy of the lamp light applied to the entire substrate 1 can be absorbed by the amorphous semiconductor film 51 or the silicon oxide film, and the heating can be performed. Since it is controlled by the difference in the structure of the insulating film under the film 5, the amorphous semiconductor film 51 and the microcrystalline semiconductor film 52 can be separately formed as in the case of scanning the energy beam. In addition, when using a method of irradiating an energy beam other than these lasers, the optimum energy density condition at the time of laser irradiation described in Embodiment 1 is independent of the type of energy beam irradiated. This is a common condition, and the same effect as in the case of using a laser can be obtained by replacing the energy density in each energy beam and using the same energy density range.

  Note that although the case where the driving TFTs 106, 106a, and 106b are formed using microcrystalline semiconductor TFTs has been described as an example in Embodiment Modes 1, 2, and 3, the present invention is not limited thereto. The range is not limited to this. For example, in the crystallization process of an amorphous semiconductor film, it is possible to create an amorphous semiconductor film and a crystalline semiconductor film by controlling irradiation conditions such as laser irradiation energy, atmosphere during irradiation, and substrate temperature. If it is within this range, larger crystal grains may be formed. That is, the semiconductor film formed by the crystallization step is not limited to the microcrystalline semiconductor film, and may be a polycrystalline semiconductor film including relatively large crystal grains. If it is a crystalline semiconductor film, the same effects as those of the first embodiment, the second embodiment, and the third embodiment described above can be obtained. However, the microcrystalline semiconductor film is a microcrystalline semiconductor film because the range of appropriate conditions is wide and easy to manufacture, and the characteristic variation of the TFT using the obtained crystalline semiconductor film can be reduced. It is preferable. The semiconductor type is described using silicon as an example, but other semiconductors may be used as long as they can be converted from an amorphous semiconductor to a microcrystalline or crystalline semiconductor by laser irradiation. Not too long.

  In Embodiments 1, 2, and 3, the example in which the present invention is applied to an inverted staggered TFT has been described, but the scope of the present invention is not limited thereto. By uniformly irradiating the substrate with the same laser irradiation energy density, the amorphous semiconductor film 51 and the microcrystalline semiconductor film 52 can be produced separately. By using as an active layer, an amorphous semiconductor TFT and a microcrystalline semiconductor TFT are separately formed, and a TFT in which an amorphous semiconductor film 51 and a microcrystalline semiconductor film 52 are mixed as an active layer of the TFT is obtained. Alternatively, the effect of obtaining a semiconductor device such as a liquid crystal display device including a mixture of an amorphous semiconductor TFT and a microcrystalline semiconductor TFT is not limited to a TFT having an inverted stagger structure. That is, as a substrate formed of a transparent insulating substrate that is irradiated with an energy beam and separately forms an amorphous semiconductor film and a microcrystalline semiconductor film, the first embodiment, the second embodiment, and the third embodiment. Like the reverse staggered TFT, the substrate is not limited to the substrate after the gate electrode is formed. At least a first insulating film made of a silicon oxide film on a substrate composed of a transparent insulating substrate, a second insulating film made of a silicon nitride film partially covering the substrate, and a first insulating film For the configuration in which the amorphous semiconductor film formed in contact with the surface of each insulating film is provided in the region that becomes the surface layer and the region in which the second insulating film becomes the surface layer, By using the method for crystallizing an amorphous semiconductor film that is irradiated with an energy beam in the same manner as the annealing method described in Embodiment 2 and Embodiment 3 or modifications thereof, an amorphous semiconductor film and a microcrystal It is possible to make different semiconductor films. Further, an amorphous semiconductor TFT and a microcrystalline semiconductor TFT are formed by forming an amorphous semiconductor TFT and a microcrystalline semiconductor TFT using the amorphous semiconductor film and the microcrystalline semiconductor film as active layers of different TFTs. It can be made separately.

  As an application example other than the configuration in which both the amorphous semiconductor TFT and the microcrystalline semiconductor TFT are inverted staggered TFTs as in the first embodiment, the second embodiment, and the third embodiment, there is a microcrystalline semiconductor TFT. Only a first insulating film 31 made of a silicon oxide film is used as a base film, and a gate insulating film made of a silicon oxide film and a gate electrode are formed on the microcrystalline semiconductor film to form a microcrystalline semiconductor TFT having a coplanar structure. . The amorphous semiconductor TFT may have an inverted staggered structure, or may be formed by separating an amorphous semiconductor film containing a source electrode and a drain electrode and further an impurity into a lower layer of the amorphous semiconductor film. A positive staggered amorphous semiconductor TFT may be formed by forming a gate insulating film made of a silicon nitride film and a gate electrode on the porous semiconductor film. In other words, the amorphous semiconductor film and the microcrystalline semiconductor film obtained by making the amorphous semiconductor film have any structure as long as the amorphous semiconductor film and the microcrystalline semiconductor film can be made without any problem. You may utilize for formation of TFT and microcrystal semiconductor TFT. Further, the amorphous semiconductor film obtained by separately forming the amorphous semiconductor film and the microcrystalline semiconductor film is not necessarily amorphous as it is used in a part of the structure of the microcrystalline semiconductor TFT of Embodiment 3. It is not necessary to use it for the active layer of the semiconductor TFT, and it may be used for the configuration of the photoelectric conversion element and other configurations using an amorphous semiconductor film. In any case, by using the method for crystallizing an amorphous semiconductor film of the present invention, it is possible to separately produce an amorphous semiconductor film and a microcrystalline semiconductor film. By using a crystalline semiconductor film as an active layer of different TFTs or an amorphous semiconductor film constituting a semiconductor device, a microcrystalline semiconductor TFT and an amorphous semiconductor constituting an amorphous semiconductor TFT or other semiconductor device A semiconductor device including a liquid crystal display device in which films are mixed can be obtained.

  As described above, each embodiment should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, and includes meanings equivalent to the terms of the claims and all modifications within the scope.

1 substrate, 1a mother array substrate, 1b mother counter substrate,
10 mother liquid crystal cell substrate, 10a, 10b, 10x to 10n liquid crystal cell substrate,
21, 22 Gate electrode,
31, 31a first insulating film, 32 silicon nitride film, 33 second insulating film,
34, 35, 36 opening,
41, 43 Second gate insulating film, 42, 42b, 44 First gate insulating film,
5, 51 Amorphous semiconductor film, 52 Microcrystalline semiconductor film, 53 Semiconductor film,
6, 61, 62 amorphous semiconductor film,
7, 71, 72, 71s, 71d, 72s, 72d amorphous semiconductor film containing impurities,
81, 82 amorphous semiconductor layer,
91s, 92s source electrode, 91d, 92d drain electrode,
100, 100a, 100b array substrate, 101 display area,
102 frame region, 103 pixels, 104 drive circuit,
105, 105a, 105b pixel TFT,
106, 106a, 106b Driving TFT,
107 storage capacitor, 108 gate wiring, 109 source wiring,
110 storage capacitor wiring, 111 external wiring, 112 printed circuit board,
113 IC chip,
LB laser light, PR, PR1, PR2, PR1 ′, PR2 ′ photoresist.

Claims (2)

A method for manufacturing a display device comprising a mixture of a crystalline semiconductor thin film transistor and an amorphous semiconductor thin film transistor on a substrate composed of a transparent insulating substrate ,
Forming a first gate electrode constituting the crystalline semiconductor thin film transistor and a second gate electrode constituting the amorphous semiconductor thin film transistor on the substrate;
Forming a silicon oxide film on the substrate including the first gate electrode and the second gate electrode;
A silicon nitride film having an opening at least in a region including on the first gate electrode and partially covering the silicon oxide film is formed, and the silicon oxide film is not covered with the silicon nitride film and the surface layer Forming a first region and a second region covered with the silicon nitride film and the silicon nitride film serving as a surface layer;
At least on the silicon oxide film including the first gate electrode in the first region and on the silicon nitride film including the second gate electrode in the second region,
Forming an amorphous semiconductor film in contact with the surface of each insulating film;
By irradiating an energy beam to both the first region and the amorphous semiconductor film formed in the second region continuously under the same irradiation conditions or uniformly over the entire substrate, An annealing step of converting only the amorphous semiconductor film formed in the first region into a crystalline semiconductor film and maintaining the amorphous semiconductor film formed in the second region in an amorphous state;
The source electrode and the drain electrode are simultaneously connected to the crystalline semiconductor film converted in the first region and the amorphous semiconductor film maintained in an amorphous state in the second region, respectively. Forming, and
By providing
On the first gate electrode, the silicon oxide film is provided as a first gate insulating film, and further, the crystalline semiconductor film is provided as an active layer on the first gate insulating film. Forming the crystalline semiconductor thin film transistor,
On the second gate electrode, the silicon oxide film as a second gate insulating film and a laminated film made of the silicon nitride film formed thereon are provided, and further, the second gate insulating film is interposed therebetween. Then, as the active layer of the amorphous semiconductor thin film transistor, the amorphous semiconductor thin film transistor including the amorphous semiconductor film is formed,
The amorphous semiconductor thin film transistor is used as a pixel thin film transistor for supplying a display voltage or a display current for controlling a light amount visually recognized as an image,
A method for manufacturing a display device, characterized in that the crystalline semiconductor thin film transistor is used as a driving thin film transistor constituting a driving circuit. Energy required for converting the amorphous semiconductor film formed on the silicon oxide film in the first region into a crystalline semiconductor film having a microcrystalline state of 100 nm or less in the energy region irradiated in the annealing step The density is higher than the density and lower than the energy density required to convert the amorphous semiconductor film formed on the silicon nitride film in the second region into a crystalline semiconductor film. The manufacturing method of the display apparatus of Claim 1 .

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